Memory device with controllable backgate electrode and shield bit line

Abstract

A memory device includes a plurality of memory blocks and a voltage generator. Each of the plurality of memory blocks may include: a plurality of word lines extending in a first direction of the memory device; a plurality of back gate lines, wherein the plurality of back gate lines are adjacent to corresponding word lines in the plurality of word lines; a plurality of bit lines extending in a second direction perpendicular to the first direction; and a shield bit line disposed between the plurality of bit lines and below the plurality of bit lines. The back gate line is electrically connected to the shield bit line. The voltage generator may be configured to drive the shield bit lines and the plurality of back gate lines of each of the plurality of memory blocks at the same voltage level.

Description

Technical Field

[0001] Aspects of the inventive concept relate to a memory device, and more particularly, to a memory device in which a shield bit line and a back gate electrode of a memory cell are controlled. Background Art

[0002] According to the recent trend of multi-functionalization of information and communication devices, there is a desire for a memory device with a larger capacity and higher integration. As the size of memory cells for higher integration decreases, the operation circuits and / or wiring structures for the operation and electrical connection of the memory device included in the memory device have become complex. There is a need for a memory device having excellent electrical characteristics and increased integration. To increase the storage capacity and integration of the memory device, vertical channel transistors vertically formed on a semiconductor substrate have been introduced to replace planar channel transistors formed on the semiconductor substrate in a planar manner.

[0003] A memory device (e.g., a dynamic random access memory (DRAM)) may include a plurality of memory cells including vertical channel transistors and capacitors, and may operate by writing and reading data by charges stored in the capacitors. The memory cells may be connected to word lines and bit lines. According to the miniaturization of the vertical channel transistors, the threshold voltage of the vertical channel transistors may decrease, which results in the generation of leakage current. In addition, the coupling noise between the bit lines may increase. To control the threshold voltage of the vertical channel transistors, a back gate electrode may be formed in the vertical channel transistors, and to reduce the coupling noise between the bit lines, shield bit lines may be formed in the memory cell array.

[0004] During the operation of the DRAM, to activate a word line connected to a selected memory cell, for example, a high voltage may be applied thereto. When the word line voltage increases, the voltage of the back gate electrode coupled to the word line may change. According to the change in the voltage level of the back gate electrode, the threshold voltage of the vertical channel transistors may also change, which may lead to the degradation of the memory cell characteristics. Therefore, a method for improving the stability of the memory cells by controlling the back gate electrode is needed. Summary of the Invention

[0005] Aspects of the inventive concept provide a memory device including a plurality of memory cells including vertical channel transistors and configured to control a back gate electrode and a shield bit line of the plurality of memory cells.

[0006] According to an aspect of the inventive concept, a memory device includes a plurality of memory blocks and a voltage generator. Each of the plurality of memory blocks includes: a plurality of word lines extending in a first direction of the memory device; a plurality of back gate lines, each of the plurality of back gate lines being adjacent to a corresponding one of the plurality of word lines; a plurality of bit lines extending in a second direction perpendicular to the first direction; and a shield bit line disposed between adjacent ones of the plurality of bit lines and below the plurality of bit lines. Each of the plurality of memory blocks includes a mesh structure in which the plurality of back gate lines are electrically connected to the shield bit line. The voltage generator is connected to the shield bit line of each of the plurality of memory blocks, and the voltage generator is configured to drive the shield bit line and the plurality of back gate lines of each of the plurality of memory blocks at the same voltage level.

[0007] According to another aspect of the inventive concept, a memory device includes: a core-peripheral circuit structure including a first bonding metal pad; and a cell array structure overlapping the core-peripheral circuit structure in a vertical direction and including a second bonding metal pad respectively contacting the first bonding metal pad. The cell array structure includes a memory cell region including a plurality of memory blocks. Each of the plurality of memory blocks includes: a plurality of word lines extending in a first direction of the memory device; a plurality of back gate lines, each of the plurality of back gate lines being adjacent to a corresponding one of the plurality of word lines; a plurality of bit lines extending in a second direction perpendicular to the first direction; and a shield bit line disposed between adjacent ones of the plurality of bit lines and below the plurality of bit lines. In each of the plurality of memory blocks, the plurality of back gate lines are electrically connected to the shield bit line, and the shield bit line contacts the second bonding metal pad. The core-peripheral circuit structure includes a voltage generator electrically connected to the first bonding metal pad, and the voltage generator is configured to drive the shield bit line and the plurality of back gate lines of each of the plurality of memory blocks at the same voltage level.

[0008] According to another aspect of the inventive concept, a memory device includes a plurality of memory blocks and a voltage generator. Each of the plurality of memory blocks includes: a plurality of word lines extending in a first direction of the memory device; a plurality of back gate lines, each of the plurality of back gate lines being adjacent to a corresponding one of the plurality of word lines; a plurality of bit lines extending in a second direction perpendicular to the first direction; and a shield bit line disposed between adjacent ones of the plurality of bit lines and below the plurality of bit lines. The voltage generator is configured to drive the shield bit line and the plurality of back gate lines of each of the plurality of memory blocks at the same voltage level. Wherein, the voltage generator includes: a voltage generation circuit configured to generate an internal power voltage having a voltage level the same as that of the power voltage of the memory device, a bit line precharge voltage having a voltage level lower than the voltage level of the power voltage, and a negative voltage having a voltage level lower than the voltage level of the ground voltage of the memory device by using the power voltage of the memory device; a first driver configured to supply the internal power voltage transmitted through a first switch connected to the voltage generation circuit to an internal power voltage line; a second driver configured to supply the bit line precharge voltage transmitted through a second switch connected to the voltage generation circuit to a bit line precharge voltage line; and a third driver configured to supply the negative voltage transmitted through a third switch connected to the voltage generation circuit to a negative voltage line. The voltage generator is configured to supply the ground voltage of the memory device to a ground voltage line, and each of the internal power voltage line, the bit line precharge voltage line, the negative voltage line, and the ground voltage line is electrically connected to the shield bit line and the plurality of back gate lines of each of the plurality of memory blocks. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a conceptual diagram of a memory device according to some embodiments;

[0011] Figure 2 shows Figure 1 the configuration of the memory device;

[0012] Figure 3 , Figure 4 , Figure 5 and Figure 6 are each a diagram showing the structure of a memory device according to some embodiments;

[0013] Figure 7 is a diagram of a voltage generator according to some embodiments;

[0014] Figure 8 is a diagram showing a part of a memory cell array according to some embodiments;

[0015] Figure 9 is a diagram showing the architecture of a voltage generator arranged in a memory device according to some embodiments;

[0016] Figure 10 is a diagram showing the characteristics of a memory device according to some embodiments; and

[0017] Figure 11 is a block diagram of a system for showing an electronic device including a memory device according to some embodiments. Detailed Description

[0018] Figure 1 is a conceptual diagram of a memory device according to some embodiments. Figure 2 is showing Figure 1 the configuration of the memory device 10.

[0019] Referring to Figure 1 and Figure 2 , the memory device 10 may include a core peripheral circuit 21 and a memory cell array 22, and the core peripheral circuit 21 may include a control logic circuit 24, a voltage generator 27, a sense amplifier 28, a row decoder 25, and a column decoder 26. The core peripheral circuit 21 may further include an address buffer 23, an input / output (I / O) gating circuit 2090, a data I / O circuit 2095, etc. In an embodiment of the inventive concept, the memory device 10 may be a dynamic random access memory (DRAM) including a plurality of memory cells, the plurality of memory cells including vertical channel transistors and capacitors, and hereinafter, the "memory device" may refer to a DRAM.

[0020] The memory cell array 22 may be connected to the row decoder 25 through word lines WL and may be connected to the sense amplifier 28 through bit lines BL. The memory cell array 22 may include a first bank array 2080a, a second bank array 2080b, a third bank array 2080c, and a fourth bank array 2080d. Each of the first to fourth bank arrays 2080a, 2080b, 2080c, and 2080d may include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells formed at intersections of the plurality of word lines WL and the plurality of bit lines BL, and may be divided into a plurality of memory blocks (BLK1 to BLKi), where i is an integer of 2 or greater (see, for example Figure 9 ).

[0021] The voltage generator 27 can generate various internal voltages for driving the circuits of the memory device 10. The voltage generator 27 can generate an internal power supply voltage VINT, a bit line precharge voltage VBL, a negative voltage VBB, a high voltage, a reference voltage, a body bias voltage, etc. by using the power supply voltage of the memory device (e.g., the main power supply voltage VDD) applied from outside the memory device 10.

[0022] For example, the high voltage can be supplied to the row decoder 25, can have a voltage level higher than the power supply voltage VDD, and can be used in the main word line drive signal generation circuit and the sub word line drive signal generation circuit to turn on the N-type metal oxide semiconductor (NMOS) cell transistors connected to the word line WL. The internal power supply voltage VINT can have the same voltage level as the power supply voltage VDD and can be used as the sense drive voltage of the sense amplifier 28. The sense amplifier 28 can sense and amplify the voltage difference between the bit line BL and the complementary bit line by using the sense drive voltage. The bit line precharge voltage VBL can have a voltage level corresponding to half of the level of the internal power supply voltage VINT and can be used to equalize the bit line BL and the complementary bit line before the sense amplifier 28 senses the voltage difference between the bit line BL and the complementary bit line. The negative voltage VBB can have a negative (-) voltage level lower than the power supply voltage VDD and can be used to increase the data retention time by raising the threshold voltage Vth of the NMOS transistor. The negative voltage VBB can be applied to the well region forming the NMOS transistor and is generally referred to as the body bias voltage or the reverse bias voltage. The reference voltage can be used to compare with the voltage of the signal received from the command / address bus to determine the logical value of the signal received from the memory controller.

[0023] In some embodiments, the internal power supply voltage VINT, the bit line precharge voltage VBL, and / or the negative voltage VBB generated by the voltage generator 27 can be commonly supplied to the back gate line BG (or back gate electrode, e.g., Figure 5 and 6 ) and the shield bit line SBL of the memory cell array 22. This is to prevent the voltage change of the back gate line BG by using the large capacitance of the shield bit line SBL (see, for example, Figure 5 and Figure 6 ) arranged between and under the bit lines BL of the memory cell array 22.

[0024] The row decoder 25 may include a first bank row decoder 2060a, a second bank row decoder 2060b, a third bank row decoder 2060c, and a fourth bank row decoder 2060d respectively connected to the first to fourth bank arrays 2080a, 2080b, 2080c, and 2080d, and the column decoder 26 may include a first bank column decoder 2070a, a second bank column decoder 2070b, a third bank column decoder 2070c, and a fourth bank column decoder 2070d respectively connected to the first to fourth bank arrays 2080a, 2080b, 2080c, and 2080d. The sense amplifiers 28 may include a first sense amplifier 2082a, a second sense amplifier 2082b, a third sense amplifier 2082c, and a fourth sense amplifier 2082d respectively connected to the first to fourth bank arrays 2080a, 2080b, 2080c, and 2080d.

[0025] The first to fourth bank arrays 2080a, 2080b, 2080c, and 2080d, the first to fourth bank row decoders 2060a, 2060b, 2060c, and 2060d, the first to fourth bank column decoders 2070a, 2070b, 2070c, and 2070d, and the first to fourth sense amplifiers 2082a, 2082b, 2082c, and 2082d may form the first to fourth banks. The first to fourth bank row decoders 2060a, 2060b, 2060c, and 2060d, the first to fourth bank column decoders 2070a, 2070b, 2070c, and 2070d, and the first to fourth sense amplifiers 2082a, 2082b, 2082c, and 2082d may be referred to as the core circuits of the first to fourth bank BANK1 to BANK4. Although the embodiments describe an example in which the storage device 10 includes four banks, in some embodiments, the storage device 10 may include various numbers of banks.

[0026] The address buffer 23 may receive an address ADDR including a row address and a column address from a memory controller connected to the storage device 10. Additionally, the address buffer 23 may receive a bank address and provide it to the bank control logic, provide the received row address to the row decoder 25, and provide the received column address to the column decoder 26. The bank control logic may generate bank control signals in response to the bank address. In response to the bank control signals, among the first to fourth bank row decoders 2060a, 2060b, 2060c, and 2060d, the bank row decoder corresponding to the bank address may be activated, and among the first to fourth bank column decoders 2070a, 2070b, 2070c, and 2070d, the bank column decoder corresponding to the bank address may be activated.

[0027] The control logic circuit 24 can control the overall operation of the memory device 10. The control logic circuit 24 can generate control signals to perform write operations and / or read operations of the memory device 10. The control logic circuit 24 can include a mode register for setting multiple operation options of the memory device 10 and a command decoder for decoding a command CMD received from a memory controller.

[0028] The sense amplifier 28 can sense data stored in the memory cells and send the sensed data to the data I / O circuit 2095 to output it to the memory controller through the data pads. The data I / O circuit 2095 can receive data to be written to the memory cells from the memory controller through the data pads and send it to the memory cell array 22. The I / O gating circuit 2090 can output the read data by using a data line amplifier configured to receive and amplify the data sensed by the sense amplifier 28. The read data can be output to the memory controller through the data pads. In addition to the circuit for gating the I / O data DQ, the I / O gating circuit 2090 can further include a column selection circuit, an input data mask logic, a read data latch for storing the read data output from the first to fourth bank arrays 2080a, 2080b, 2080c, and 2080d, and a write driver for writing data to the first to fourth bank arrays 2080a, 2080b, 2080c, and 2080d.

[0029] The read data output from a bank array among the first to fourth bank arrays 2080a, 2080b, 2080c, and 2080d can be sensed by a sense amplifier 2082 corresponding to the bank array and stored in the read data latch. The write data to be written to the memory cell array of a bank array among the first to fourth bank arrays 2080a, 2080b, 2080c, and 2080d can be provided from the memory controller to the data I / O circuit 2095. The data provided to the data I / O circuit 2095 can be written to the bank array through the write driver.

[0030] Figure 3 , Figure 4 , Figure 5 and Figure 6 Each is a diagram showing the structure of a memory device according to some embodiments. Figure 4 is Figure 3 a perspective view of the cell array structure CAS of the memory device 10. Figure 5 is a cross-sectional view showing a cross-section taken along a direction corresponding to the second direction D2 in the perspective view of the memory device 10 shown in Figure 4 , Figure 6is a cross-section taken along a direction corresponding to the first direction D1. For ease of understanding, portions shown using terms such as "upper surface / lower surface", "upper part / lower part", "above / below", etc. are described based on the directions indicated in the drawings. Thus, depending on the directions indicated in the drawings, a surface can be referred to as both an upper surface and a lower surface.

[0031] Reference Figure 2 and Figure 3 , the memory device 10 may include a cell array structure CAS and a core peripheral circuit structure CPS that overlap each other in the third direction (D3 direction). The cell array structure CAS may include a memory cell array 22. The core peripheral circuit structure CPS may include a core peripheral circuit that includes an address buffer 23, a control logic circuit 24, a row decoder 25, a column decoder 26, a sense amplifier 28, an I / O gating circuit 2090, and a data I / O circuit 2095. For the sake of simplicity of the drawings, the circuit arrangement constituting the voltage generator 27 is shown in the core peripheral circuit structure CPS in the drawings. The memory device 10 may have a structure in which the memory cell array 22 is arranged on the core peripheral circuit, that is, a cell-on-periphery (COP) structure.

[0032] The cell array structure CAS may include a plurality of memory cells, and the plurality of memory cells may include vertical channel transistors VCT. In the cell array structure CAS, a plurality of word lines WL may extend in the first direction (D1 direction), and a plurality of bit lines BL may extend in the second direction (D2 direction). A plurality of back gate lines BG may be arranged adjacent to the plurality of word lines WL, and a plurality of shield bit lines SBL may be arranged adjacent to the plurality of bit lines BL. For example, each word line WL may be arranged adjacent to a corresponding back gate line BG among the plurality of back gate lines BG. For example, the plurality of bit lines BL and the plurality of shield bit lines SBL may be arranged in an alternating manner such that each bit line BL is located between two shield bit lines SBL, and each shield bit line SBL is located between two bit lines BL. See, for example Figure 4 .

[0033] The core peripheral circuit structure CPS may include a semiconductor substrate, and the core peripheral circuit may be formed by forming semiconductor elements such as transistors and patterns for wiring the elements on the semiconductor substrate. After forming the core peripheral circuit in the core peripheral circuit structure CPS, a cell array structure CAS including the memory cell array 22 may be formed, and patterns (e.g., Figure 5bonding metal pads 301 and 302). For ease of explanation, the terms "back gate line BG" and "back gate electrode BG" may be used throughout the specification.

[0034] Reference Figure 4 、 Figure 5 and Figure 6 , the core peripheral circuit structure CPS may include a lower substrate 310, an interlayer insulating layer 315, a plurality of circuit elements 312a and 312b formed on the lower substrate 310, first metal layers 314a and 314b connected to each of the plurality of circuit elements 312a and 312b, second metal layers 316a and 316b formed on the first metal layers 314a and 314b, and a bonding metal pad 301 formed on the uppermost metal layer of the core peripheral circuit structure CPS. In an embodiment, the first metal layers 314a and 314b may be formed of or include tungsten having a relatively high resistance, the second metal layers 316a and 316b may be formed of or include copper having a relatively low resistance, and the bonding metal pad 301 may be formed of or include copper. In another embodiment, the bonding metal pad 301 may be formed of or include aluminum (Al) or tungsten (W).

[0035] Although this specification only describes and shows the first metal layers 314a and 314b and the second metal layers 316a and 316b, the inventive concept is not limited thereto, and at least one metal layer may also be formed on the second metal layers 316a and 316b. Some of the at least one metal layer formed on the second metal layers 316a and 316b may be formed of or include aluminum or the like having a lower resistance than the copper forming the second metal layers 316a and 316b. The interlayer insulating layer 315 may be disposed on the lower substrate 310 to cover the plurality of circuit elements 312a and 312b, the first metal layers 314a and 314b, and the second metal layers 316a and 316b, and may be formed of or include an insulating material such as silicon oxide, silicon nitride, etc.

[0036] The plurality of circuit elements 312a and 312b may be connected to at least one circuit element constituting the peripheral circuit. For ease of explanation, the first circuit element 312a may represent a transistor constituting the row decoder 25, and the second circuit element 312b may represent a transistor constituting the voltage generator 27.

[0037] In the memory device 10, bit lines BL may be arranged separately from each other along a first direction D1 on an upper substrate 320. The upper substrate 320 may be formed of the same material as that of the lower substrate 310. According to an embodiment, the upper substrate 320 may be referred to as a plate or a conductive plate. The bit lines BL may be arranged separately from each other in the first direction D1 and may extend in a second direction D2 intersecting the first direction D1. Active patterns AP may be alternately arranged along the second direction D2 on each bit line BL. The active patterns AP may be arranged separately from each other in the first direction D1. That is, the active patterns AP may be arranged in a two-dimensional (2D) manner in the first direction D1 and the second direction D2 intersecting each other. In some embodiments, a plurality of word lines WL, a plurality of bit lines BL, and a plurality of active patterns AP may constitute a plurality of vertical channel transistors.

[0038] Each active pattern AP may have a length in the first direction D1, a width in the second direction D2, and a height in a third direction D3 perpendicular to the surface of the upper substrate 320. The active pattern AP may have a substantially uniform width. Each active pattern AP may have an upper surface and a lower surface facing each other in the third direction D3. For example, the lower surface of the active pattern AP may be in contact with the bit line BL. Each active pattern AP may include a source region adjacent to the bit line BL, a drain region adjacent to a contact pattern BC, and a channel region between the source region and the drain region. During operation of the memory device 10, the channel region of the active pattern AP may be controlled by the word line WL and the back gate electrode BG. The active pattern AP may be formed of or include single crystal silicon (Si) to improve leakage current characteristics during operation of the memory device 10.

[0039] The back gate electrodes BG may be arranged separately from each other along the second direction D2 on the bit lines BL. The back gate electrodes BG may extend in the first direction D1, crossing the bit lines BL. Each back gate electrode BG may be arranged between adjacent active patterns AP in the second direction D2. A first active pattern 191 may be arranged on one side of each back gate electrode BG, and a second active pattern 192 may be arranged on the other side. The height of the back gate electrode BG in the vertical direction may be less than the height of the active pattern AP. During operation of the memory device 10, a negative voltage may be applied to the back gate electrode BG, and the back gate electrode BG may increase the threshold voltage of the vertical channel transistor. This means that deterioration of leakage current characteristics due to a threshold voltage reduction resulting from miniaturization of the vertical channel transistor can be prevented.

[0040] A first insulating pattern 111 may be disposed between active patterns AP adjacent to each other along a second direction D2. The first insulating pattern 111 may extend parallel to the back gate electrode BG in a first direction D1. A back gate insulating film 113 may be disposed between the back gate electrode BG and the active pattern AP and between the back gate electrode BG and the first insulating pattern 111. The back gate insulating film 113 may include vertical portions covering both sides of the back gate electrode BG and a horizontal portion connecting the vertical portions to each other. The horizontal portion of the back gate insulating film 113 may be closer to the contact pattern BC than the bit line BL and may cover the upper surface of the back gate electrode BG, as Figure 5 and Figure 6 shown. A back gate covering pattern 115 may be disposed between the bit line BL and the back gate electrode BG. The back gate covering pattern 115 may be formed of an insulating material or include an insulating material, and the lower surface of the back gate covering pattern 115 may be in contact with the bit line BL. The back gate covering pattern 115 may be disposed between the vertical portions of the back gate insulating film 113.

[0041] The word line WL may extend on the bit line BL along the first direction D1 and may be alternately disposed in the second direction D2. A first word line 181 among the word lines WL may be disposed on one side of the first active pattern 191, and a second word line 182 among the word lines WL may be disposed on the other side of the second active pattern 192. A part of the first word line 181 may be disposed between the first active patterns 191 adjacent to each other along the first direction D1, and a part of the second word line 182 may be disposed between the second active patterns 192 adjacent to each other along the first direction D1.

[0042] The word line WL may be vertically and separately disposed from the bit line BL and the contact pattern BC. Viewed from a vertical angle (e.g., in a plan view), the word line WL may be disposed between the bit line BL and the contact pattern BC. Adjacent word lines WL may have sidewalls facing each other. The height of the word line WL in the vertical direction may be less than the height of the active pattern AP. The height of the word line WL in a third direction D3 may be greater than or equal to the height of the back gate electrode BG.

[0043] A gate insulating film 160 may be disposed between the word line WL and the active pattern AP. The gate insulating film 160 may extend parallel to the word line WL in the first direction D1. The gate insulating film 160 may cover one side of the first active pattern 191 and the other side of the second active pattern 192. The gate insulating film 160 may have a substantially uniform thickness. A second insulating pattern 141 may be disposed between the gate insulating film 160 and the contact pattern BC. For example, the second insulating pattern 141 may be formed of silicon oxide or include silicon oxide. A first etch stop film 131 and a second etch stop film 133 may be disposed between the active pattern AP and the second insulating pattern 141.

[0044] On the gate insulating film 160, the word lines WL can be separated from each other by the third insulating pattern 151. The third insulating pattern 151 can extend between the word lines WL along the first direction D1. A first covering film 153 can be disposed between the third insulating pattern 151 and the word lines WL. The first covering film 153 can have a substantially uniform thickness. The third insulating pattern 151 can include a third vertical pattern 151A and a third horizontal pattern 151B.

[0045] The contact pattern BC can pass through the third etch stop film 210 and the interlayer insulating film 220, and can be connected to each active pattern AP. In other words, the contact pattern BC can be connected to each of the drain regions of the active pattern AP. The contact pattern BC can have a lower width greater than the upper width. The contact patterns BC adjacent to each other can be separated from each other by the isolation insulating pattern 230. From a planar perspective, each contact pattern BC can have various shapes, such as circular, oval, rectangular, square, diamond, hexagonal, etc. A landing pad LP can be disposed on the contact pattern BC.

[0046] The isolation insulating pattern 230 can be disposed between the landing pads LP. From a planar perspective, the landing pads LP can be arranged in a matrix in the first direction D1 and the second direction D2. The upper surface of the landing pad LP can be substantially coplanar with the upper surface of the isolation insulating pattern 230. A fourth etch stop film 240 can be formed on the isolation insulating pattern 230.

[0047] A data storage pattern DSP can be disposed on the landing pad LP. The data storage pattern DSP can be electrically connected to the active pattern AP. The data storage pattern DSP can be arranged in a matrix in the first direction D1 and the second direction D2. The data storage pattern DSP can completely or partially overlap with the landing pad LP. The data storage pattern DSP can contact all or part of the upper surface of the landing pad LP. An upper insulating film 260 can be disposed on the data storage pattern DSP, and the cell contact plug PLG can pass through the upper insulating film 260 and can be connected to the plate electrode 255.

[0048] In some embodiments, the data storage pattern DSP can be a capacitor, and can include a capacitor dielectric film 253 disposed between the plate electrode 255 and the storage electrode 251. In this case, the storage electrode 251 can be in direct contact with the landing pad LP, and from a planar perspective, the storage electrode 251 can have various shapes, such as circular, oval, rectangular, square, diamond, hexagonal, etc.

[0049] In some embodiments, the data storage pattern DSP may be a variable resistance pattern that can be switched between two resistance states by an electrical pulse applied to a storage element. For example, the data storage pattern DSP may be formed of or include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, an antiferromagnetic material, etc., whose crystalline state changes according to the amount of current. However, the inventive concept is not limited thereto. Depending on the material film of the data storage pattern DSP, the storage device 10 may be implemented as a resistive memory, such as a phase change random access memory (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), etc.

[0050] The shield bit line SBL may be disposed between and below the bit lines BL. The shield bit line SBL may reduce the coupling noise between adjacent bit lines BL. For example, the shield bit line SBL may be a shield structure formed of or including a conductive material. The first line insulating layer 173 may be disposed separately from each other in the first direction D1 and may extend in the second direction D2. The first line insulating layer 173 may contact the facing sidewalls of the adjacent bit lines BL and may be separated from each other in the first direction D1. For example, as Figure 6 shown, each first line insulating layer 173 may contact two sidewalls and the bottom surface of the corresponding bit line BL. The second line insulating layer 325 may cover the lower surface and the side surfaces of the shield bit line SBL and may fill the space between the shield bit lines SBL. The shield bit line SBL may pass through the back gate covering pattern 115 and may be connected to each back gate electrode BG.

[0051] The via electrode 322 may pass through the upper substrate 320 and contact the metal layer 318b, and may extend in the third direction (D3 direction) to the bonding metal pad 302 formed on the uppermost metal layer of the core peripheral circuit structure CPS. Although the embodiment describes and shows one metal layer (318a and 318b), the inventive concept is not limited thereto, and at least one metal layer may also be formed on the metal layer (318a and 318b). The shield bit line SBL may be electrically connected to the element 312b of the voltage generator 27 through the bonding metal pad 302 of the cell array structure CAS and the bonding metal pad 301 of the core peripheral circuit structure CPS. The shield bit line SBL may be connected to the voltage generator 27 and may be controlled by the control logic circuit.

[0052] In some embodiments, the bonding metal pad 302 of the cell array structure CAS and the bonding metal pad 301 of the core peripheral circuit structure CPS can be connected to each other by an electrical bonding or physical bonding method. When the bonding metal pads 301 and 302 include copper (Cu), the bonding method can be a Cu-Cu bonding method. In another embodiment, the bonding metal pads 301 and 302 can be formed of or include aluminum (Al) or tungsten (W).

[0053] The metal layer 318a of the cell array structure CAS can be electrically or physically connected to each word line WL and can be in contact with the bonding metal pad 301. Each word line WL can be electrically connected to the element 312a of the row decoder 25 through the bonding metal pad 302 of the cell array structure CAS and the bonding metal pad 301 of the core peripheral circuit structure CPS. Hereinafter, the components and operations of the voltage generator 27 connected to the back gate line BG and the shield bit line SBL will be described in detail with respect to various embodiments.

[0054] Figure 7 is a diagram of a voltage generator according to some embodiments.

[0055] Reference Figure 7 FIG. , the voltage generator 27 can include a voltage generation circuit 70, a plurality of switches SW1, SW2, SW3, and SW4, and a plurality of driver circuits 71, 72, 73, 74, 75, and 76. The voltage generation circuit 70 can generate an internal power supply voltage VINT, a bit line precharge voltage VBL, and a negative voltage VBB by using the power supply voltage (e.g., VDD) of the storage device 10. The internal power supply voltage VINT can be provided to the first driver circuit 71 and the second driver circuit 72 through the first switch SW1. The first driver circuit 71 and the second driver circuit 72 can be commonly connected to the back gate line BG and the shield bit line SBL. The back gate line BG and the shield bit line SBL can have the level of the internal power supply voltage VINT. Although the back gate line BG and the shield bit line SBL of the storage cell array 22 are described as being driven at the level of the internal power supply voltage VINT according to the configuration of the two driver circuits 71 and 72, the inventive concept is not limited thereto and can include various numbers of driver circuits.

[0056] The bit line precharge voltage VBL can be supplied to the third driver circuit 73 and the fourth driver circuit 74 through the second switch SW2. The third driver circuit 73 and the fourth driver circuit 74 can be commonly connected to the back gate line BG and the shielded bit line SBL. The back gate line BG and the shielded bit line SBL can have the level of the bit line precharge voltage VBL. Although the back gate line BG and the shielded bit line SBL of the memory cell array 22 are described as being driven at the level of the bit line precharge voltage VBL according to the configuration of the two driver circuits 73 and 74, the inventive concept is not limited thereto, and can include various numbers of driver circuits.

[0057] The negative voltage VBB can be supplied to the fifth driver circuit 75 and the sixth driver circuit 76 through the third switch SW3. The fifth driver circuit 75 and the sixth driver circuit 76 can be commonly connected to the back gate line BG and the shielded bit line SBL. The back gate line BG and the shielded bit line SBL can have the level of the negative voltage VBB. Although the back gate line BG and the shielded bit line SBL of the memory cell array 22 are described as being driven at the level of the negative voltage VBB according to the configuration of the two driver circuits 75 and 76, the inventive concept is not limited thereto, and can include various numbers of driver circuits.

[0058] The voltage generator 27 can supply the ground voltage VSS to the back gate line BG and the shielded bit line SBL together through the fourth switch SW4.

[0059] In some embodiments, the control logic circuit 24 can control the plurality of switches SW1, SW2, SW3, and SW4 to turn on one of these switches, and through the turned-on switch, the voltage generated in the voltage generation circuit 70 can be supplied to the back gate line BG and the shielded bit line SBL.

[0060] Figure 8 is a diagram showing a part of the memory cell array 22 according to some embodiments.

[0061] Figure 7 and Figure 8 shows the vertical channel transistor VCT of each memory cell formed at the intersection of the plurality of word lines WL0 to WL4 and the plurality of bit lines BL0 to BL3 in the memory cell array 22, and the mesh structure in which the back gate line BG and the shielded bit line SBL are connected to each other. The first driver circuit 71, the third driver circuit 73, and the fifth driver circuit 75 can be arranged on one side of the memory cell array 22 in the first direction (D1 direction) in which the plurality of word lines WL0 to WL4 extend. The second driver circuit 72, the fourth driver circuit 74, and the sixth driver circuit 76 can be arranged on the other side of the memory cell array 22 in the second direction (D2 direction) in which the plurality of bit lines BL0 to BL3 extend.

[0062] This embodiment describes a configuration in which a plurality of driver circuits 71 to 76 are arranged on multiple sides of a memory cell array 22 in a first direction (D1 direction) and a second direction (D2 direction). However, this is only an example provided for ease of understanding and is not intended to limit the inventive concept. The plurality of driver circuits 71 to 76 may be arranged on any one or more sides of the memory cell array 22 in the first direction (D1 direction) and the second direction (D2 direction), and the voltages output from each of the plurality of driver circuits 71 to 76 may be supplied to shield bit lines SBL and back gate lines BG having a mesh structure. Since the plurality of driver circuits 71 to 76 arranged on both sides of the memory cell array 22 in the first direction (D1 direction) and the second direction (D2 direction) have a large driving ability, the voltage levels of the shield bit lines SBL and back gate lines BG having a mesh structure can be more stable.

[0063] The first driver circuit 71 and the second driver circuit 72 may supply an internal power supply voltage VINT to the back gate line BG and the shield bit line SBL. The third driver circuit 73 and the fourth driver circuit 74 may supply a bit line precharge voltage VBL to the back gate line BG and the shield bit line SBL. The fifth driver circuit 75 and the sixth driver circuit 76 may supply a negative voltage VBB to the back gate line BG and the shield bit line SBL.

[0064] In some embodiments, in the memory cell array 22, a fourth switch SW4 may be arranged on one side of the memory cell array 22 in a first direction (D1 direction) in which a plurality of word lines WL0 to WL4 extend, and the fourth switch SW4 may also be arranged on the other side of the memory cell array 22 in a second direction (D2 direction) in which a plurality of bit lines BL0 to BL3 extend. Through the fourth switch SW4, a ground voltage VSS may be supplied to the shield bit lines SBL and back gate lines BG having a mesh structure.

[0065] Figure 9 is a diagram showing an architecture of a voltage generator arranged in a memory device according to some embodiments. Figure 10 is a diagram showing characteristics of a memory device. For simplicity of the drawings, Figure 9 shows Figure 2The first memory block BLK1 and the second memory block BLK2 among the multiple memory blocks BLK1 to BLKi included in the first to fourth memory banks BANK1, BANK2, BANK3, and BANK4. The back gate line BG and the shield bit line SBL of the first memory block BLK1 (hereinafter, represented by "BG1" and "SBL1", respectively) are described as being electrically connected to each other, and the back gate line BG and the shield bit line SBL of the second memory block BLK2 (hereinafter, represented by "BG2" and "SBL2", respectively) are described as being electrically connected to each other (the connection points in the corresponding memory blocks BLK1 and BLK2 are marked with dots).

[0066] Refer to the Figure 5 、 Figure 6 、 Figure 7 and Figure 8 of Figure 9 , the memory device 10 may include a cell array structure CAS and a core peripheral circuit structure CPS that overlap each other in the third direction (D3 direction). The cell array structure CAS may include a first memory block BLK1 region and a second memory block BLK2 region. The core peripheral circuit structure CPS may include a voltage generator 27 region commonly connected to the first memory block BLK1 and the second memory block BLK2 and a bonding metal pad 301. The voltage generator 27 region may include driver circuits (71, 73, and 75) that respectively output an internal power supply voltage VINT, a bit line precharge voltage VBL, and a negative voltage VBB. Each of the ground voltage VSS line and the negative voltage VBB line, the bit line precharge voltage VBL line, and the internal power supply voltage VINT line respectively connected to the driver circuits (71, 73, and 75) may be selectively connected to the bonding metal pad 301.

[0067] The bonding metal pad 301 of the core peripheral circuit structure CPS may be in contact with the bonding metal pad 302 of the cell array structure CAS. The bonding metal pad 302 of the cell array structure CAS may be electrically connected to the first shield bit line SBL1 of the first memory block BLK1 and the second shield bit line SBL2 of the second memory block BLK2. The first shield bit line SBL1 of the first memory block BLK1 may be electrically or physically connected to the first back gate line BG1, and the second shield bit line SBL2 of the second memory block BLK2 may be electrically or physically connected to the second back gate line BG2.

[0068] In some embodiments, the first shield bit line SBL1 and the first back gate line BG1 of the first memory block BLK1 may be formed by Figure 2The control logic circuit 24 is driven at the same voltage level as the second shield bit line SBL2 and the second back gate line BG2 of the second memory block BLK2. For example, the first and second back gate lines BG1 and BG2 and the first and second shield bit lines SBL1 and SBL2 can all be driven at the internal power supply voltage VINT level, the bit line precharge voltage VBL level, the negative voltage VBB level, or the ground voltage VSS level.

[0069] In some embodiments, the first shield bit line SBL1 and the first back gate line BG1 of the first memory block BLK1 can be Figure 2 driven by the control logic circuit 24 at a voltage level different from the voltage levels of the second shield bit line SBL2 and the second back gate line BG2 of the second memory block BLK2. For example, the first shield bit line SBL1 and the first back gate line BG1 of the first memory block BLK1 can be driven at the internal power supply voltage VINT level, while the second shield bit line SBL2 and the second back gate line BG2 of the second memory block BLK2 can be driven at at least one of the bit line precharge voltage VBL level, the negative voltage VBB level, and the ground voltage VSS level. As another example, the first shield bit line SBL1 and the first back gate line BG1 of the first memory block BLK1 can be driven at the bit line precharge voltage VBL level, and at the same time, the second shield bit line SBL2 and the second back gate line BG2 of the second memory block BLK2 can be driven at at least one of the internal power supply voltage VINT level, the negative voltage VBB level, and the ground voltage VSS level. As another example, the first shield bit line SBL1 and the first back gate line BG1 of the first memory block BLK1 can be driven at the negative voltage VBB level, and at the same time, the second shield bit line SBL2 and the second back gate line BG2 of the second memory block BLK2 can be driven at at least one of the internal power supply voltage VINT level, the bit line precharge voltage VBL level, and the ground voltage VSS level. As another example, the first shield bit line SBL1 and the first back gate line BG1 of the first memory block BLK1 can be driven at the ground voltage VSS level, and at the same time, the second shield bit line SBL2 and the second back gate line BG2 of the second memory block BLK2 can be driven at at least one of the internal power supply voltage VINT level, the bit line precharge voltage VBL level, and the negative voltage VBB level.

[0070] Figure 8 and Figure 10Shows the voltage level of the back gate line BG adjacent to the selected word line WL1 of the memory cell array 22 when the selected word line WL1 is activated to a high voltage level at time point Ta. Waveform A represents the voltage level of the back gate line BG when the back gate line BG is not electrically connected to the shield bit line SBL, and waveform B represents the voltage level of the back gate line BG when the back gate line BG is electrically connected to the shield bit line SBL. Waveform A shows the change in the voltage level of the back gate line BG coupled to the high voltage level of the selected word line WL1. Waveform B shows a negligible voltage change in the back gate line BG that is not yet coupled to the high voltage level of the selected word line WL1. This means that, due to the back gate line BG being coupled to a large-capacitance capacitor of the shield bit line SBL disposed between and below the bit lines BL of the memory cell array 22 (see Figure 5 and Figure 6 ), and being maintained at a specific voltage level provided by the voltage generator 27 (e.g., the internal power supply voltage VINT level, the bit line precharge voltage VBL level, or the ground voltage VSS level), the voltage level of the back gate line BG can be stable. Therefore, a change in the threshold voltage of the vertical channel transistor VCT can be prevented, thereby improving the stability of the memory cell and enhancing the performance of the DRAM.

[0071] Figure 11 is a block diagram of a system 2000 for showing an electronic device including a memory device according to some embodiments.

[0072] Referring to Figure 11 , the system 2000 may include a camera 2100, a display 2200, an audio processor 2300, a modem 2400, DRAMs 2500a and 2500b, flash memories 2600a and 2600b, I / O devices 2700a and 2700b, and an application processor (AP) 2800. The system 2000 may be implemented as a laptop computer, a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a health care device, an Internet of Things (IoT) device, etc. The system 2000 may also be implemented as a server or a personal computer.

[0073] The camera 2100 can take still pictures or record videos according to user control, and can store the captured images or the captured video data or send them to the display 2200. The audio processor 2300 can process the audio data included in the flash memories 2600a and 2600b or the content of the network. The modem 2400 can modulate and send signals to transmit / receive wired / wireless data, and can demodulate the modulated signals to restore them to the original signals on the receiving side. The I / O devices 2700a and 2700b can include devices that provide digital input and / or output functions, such as a universal serial bus (USB), a storage device, a digital camera, a secure digital (SD) card, a digital versatile disc (DVD), a network adapter, a touch screen, etc.

[0074] The AP 2800 can control the overall operation of the system 2000. The AP 2800 can include blocks such as a control block (e.g., the controller 2810), an accelerator block or an accelerator chip 2820, and an interface 2830. The AP 2800 can control the display 2200 such that some of the content stored in the flash memories 2600a and 2600b is displayed on the display 2200. When a user input is received through the I / O devices 2700a and 2700b, the AP 2800 can perform a control operation corresponding to the user input. The AP 2800 can include an accelerator block, which is a dedicated circuit for artificial intelligence (AI) data operations, or can include an accelerator chip 2820 separate from the AP 2800. The DRAM 2500b can be additionally installed in the accelerator block or the accelerator chip 2820. The accelerator is a functional block that professionally executes specific functions of the AP 2800, and the accelerator can include a GPU (which is a functional block that professionally executes graphic data processing), a neural processing unit (NPU) (which is a block that professionally executes AI calculations and inferences), and a data processing unit (DPU) (which is a block that professionally executes data transmission).

[0075] The system 2000 can include multiple DRAMs 2500a and 2500b. The AP 2800 can control the DRAMs 2500a and 2500b through commands and mode register (MRS) settings that conform to the standards of the Joint Electron Device Engineering Council (JEDEC), or can set the DRAM interface protocol and perform communication to use company-specific functions, such as low voltage / high speed / reliability and cyclic redundancy check (CRC) or error correction code (ECC) functions. For example, the AP 2800 can communicate with the DRAM 2500a through an interface that conforms to JEDEC standards (such as LPDDR4, LPDDR5, etc.), and the accelerator block or the accelerator chip 2820 can establish a new DRAM interface protocol and perform communication to control the DRAM 2500b for the accelerator, which has a higher bandwidth than the DRAM 2500a.

[0076] In Figure 11 this, only DRAMs 2500a and 2500b are shown, but the inventive concept is not limited thereto, and any memory such as PRAM, SRAM, MRAM, RRAM, FRAM, or hybrid RAM memory may be used when the bandwidth, response speed, and voltage conditions of the AP 2800 or the accelerator chip 2820 are satisfied. The DRAMs 2500a and 2500b may have relatively smaller latency and bandwidth than the I / O devices 2700a and 2700b or the flash memories 2600a and 2600b. The DRAMs 2500a and 2500b may be initialized when the system 2000 is powered on. When the operating system and application data are loaded, the DRAMs 2500a and 2500b may be used as temporary storage for the operating system and application data, or may be used as an execution space for various software codes.

[0077] In the DRAMs 2500a and 2500b, four basic arithmetic operations, namely addition / subtraction / multiplication / division operations, vector operations, address operations, or fast Fourier transform (FFT) operations may be performed. In addition, functions for performing inference may be executed in the DRAMs 2500a and 2500b. Here, an artificial neural network may be used to perform inference in a deep learning algorithm. The deep learning algorithm may include a training operation of learning a model through various data and an inference operation of discriminating data using the trained model. According to an embodiment, an image captured by the user using the camera 2100 may be signal-processed and stored in the DRAM 2500b, and the accelerator block or the accelerator chip 2820 may perform AI data operations to discriminate data by using the data stored in the DRAM 2500b and the functions for inference.

[0078] The system 2000 may include a plurality of storage devices or a plurality of flash memories 2600a and 2600b having a larger capacity than the DRAMs 2500a and 2500b. The accelerator block or the accelerator chip 2820 may perform training operations and AI data operations by using the flash memories 2600a and 2600b. According to an embodiment, the flash memories 2600a and 2600b may include a memory controller 2610 and flash memory devices 2620, and may efficiently perform the training operations and the inference AI data operations performed by the AP 2800 and / or the accelerator chip 2820 by using an operator included in the memory controller 2610. The flash memories 2600a and 2600b may store pictures captured by using the camera 2100 or data transmitted through a data network. For example, the flash memories 2600a and 2600b may store augmented reality / virtual reality, high definition (HD), or ultra-high definition (UHD) content.

[0079] In system 2000, DRAMs 2500a and 2500b can each be the memory devices described with respect to Figures 1 to 10 The memory device may include a core-peripheral circuit formed on a semiconductor substrate and a cell array structure overlapping the core-peripheral circuit structure in a vertical direction on the core-peripheral circuit structure. The cell array structure may include a plurality of memory blocks in a memory cell region, in which a plurality of vertical channel transistor structures and a plurality of capacitor structures respectively connected to the plurality of vertical channel transistor structures are formed. Each of the plurality of memory blocks may include a plurality of word lines extending in a first direction of the memory device, a plurality of back gate lines adjacent to the plurality of word lines, a plurality of bit lines extending in a second direction perpendicular to the first direction, and shield bit lines disposed between and below the plurality of bit lines. Each of the plurality of memory blocks may include a mesh structure in which the back gate lines are electrically connected to the shield bit lines. The core-peripheral circuit structure may include a voltage generator connected to the shield bit lines of each of the plurality of memory blocks. Bonding metal pads in electrical contact with the core-peripheral circuit structure and the cell array structure may be electrically connected to the shield bit lines and the back gate lines of the cell array structure, and may be electrically connected to the voltage generator of the core-peripheral circuit structure. A plurality of driver circuits of the voltage generator may drive the shield bit lines and the plurality of back gate lines of each of the plurality of memory blocks at the same voltage level. Since the back gate electrodes and the shield bit lines are commonly controlled at a specific voltage level provided by the voltage generator, the voltage level of the back gate lines can be kept constant. Accordingly, a change in the threshold voltage of the vertical channel transistors can be prevented, thereby improving the stability of the memory cells and improving the performance of the DRAM.

[0080] Although the inventive concept has been particularly shown and described with reference to its embodiments, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A storage device, comprising: A plurality of memory blocks, each of the plurality of memory blocks comprising: a plurality of word lines extending in a first direction of the memory device; a plurality of back gate lines, each of the plurality of back gate lines being adjacent to a corresponding word line of the plurality of word lines; a plurality of bit lines extending in a second direction perpendicular to the first direction; and a shielding bit line arranged between adjacent bit lines of the plurality of bit lines and located below the plurality of bit lines, wherein each of the plurality of memory blocks comprises a mesh structure in which the plurality of back gate lines are electrically connected to the shielding bit lines; and a voltage generator connected to the shielded bit line of each of the plurality of memory blocks, The voltage generator is configured to drive the shielding bit line and the plurality of back gate lines of each memory block in the plurality of memory blocks at the same voltage level.

2. The memory device according to claim 1, wherein: The voltage generator is configured to generate an internal power supply voltage by using a power supply voltage of the memory device, and includes a plurality of driver circuits configured to provide the internal power supply voltage to the plurality of back gate lines and the shielding bit lines.

3. The memory device according to claim 2, wherein: The internal power supply voltage has the same voltage level as that of the power supply voltage and is a voltage for sensing data of memory cells of the plurality of memory blocks.

4. The memory device according to claim 1, wherein: The voltage generator is configured to generate a bit line precharge voltage by using a power supply voltage of the memory device, and includes a plurality of driver circuits configured to provide the bit line precharge voltage to the plurality of back gate lines and the shielding bit lines.

5. The memory device according to claim 4, wherein: The voltage level of the bit line precharge voltage is lower than the voltage level of the power supply voltage, and The voltage generator is configured to provide the bit line precharge voltage to the plurality of bit lines before memory cells of the plurality of memory blocks are sensed.

6. The memory device according to claim 1, wherein: The voltage generator is configured to generate a negative voltage having a negative voltage level lower than a ground voltage level of the memory device, and includes a plurality of driver circuits configured to provide the negative voltage to the plurality of back gate lines and the shielding bit lines.

7. The memory device according to claim 1, wherein: The plurality of storage blocks include a first storage block and a second storage block, The voltage generator is commonly connected to the first memory block and the second memory block, and The memory device further includes a control logic circuit configured to control the voltage generator.

8. The memory device according to claim 7, wherein: The control logic circuit is configured to independently control a first voltage level of the shielded bit line and the plurality of back gate lines of the first memory block and a second voltage level of the shielded bit line and the plurality of back gate lines of the second memory block.

9. A storage device, comprising: a core peripheral circuit structure, the core peripheral circuit structure comprising a first bonding metal pad; as well as a cell array structure, the cell array structure overlapping the core peripheral circuit structure in a vertical direction and comprising second bonding metal pads respectively contacting the first bonding metal pads, wherein the cell array structure comprises a memory cell region, the memory cell region comprises a plurality of memory blocks, each of the plurality of memory blocks comprises: a plurality of word lines extending in a first direction of the memory device; a plurality of back gate lines, each of the plurality of back gate lines being adjacent to a corresponding word line of the plurality of word lines; a plurality of bit lines extending in a second direction perpendicular to the first direction; and a shielding bit line arranged between adjacent bit lines of the plurality of bit lines and located below the plurality of bit lines, wherein, in each of the plurality of memory blocks, the plurality of back gate lines are electrically connected to the shielding bit lines, and the shielding bit lines are in contact with the second bonding metal pad, wherein the core peripheral circuit structure includes a voltage generator electrically connected to the first bonding metal pad, and The voltage generator is configured to drive the shielding bit line and the plurality of back gate lines of each memory block in the plurality of memory blocks at the same voltage level.

10. The memory device according to claim 9, wherein: The voltage generator comprises: a voltage generating circuit configured to generate an internal power supply voltage, a bit line precharge voltage, and a negative voltage by using a power supply voltage of the memory device; a first driver configured to provide the internal power supply voltage transmitted through a first switch connected to the voltage generating circuit to an internal power supply voltage line; a second driver configured to provide the bit line precharge voltage transmitted through a second switch connected to the voltage generating circuit to a bit line precharge voltage line; and a third driver configured to provide the negative voltage transmitted through a third switch connected to the voltage generating circuit to a negative voltage line, wherein the voltage generator is configured to provide a ground voltage of the memory device to the ground voltage line, and Wherein, each of the internal power supply voltage line, the bit line precharge line, the negative voltage line, and the ground voltage line is electrically connected to the first bonding metal pad.

11. The memory device according to claim 10, wherein: The first driver includes a plurality of first driver circuits configured to drive the internal power supply voltage line, the second driver includes a plurality of second driver circuits configured to drive the bit line precharge line, and the third driver includes a plurality of third driver circuits configured to drive the negative voltage line.

12. The memory device according to claim 10, wherein: A voltage level of the internal power voltage is the same as a voltage level of the power voltage, and the internal power voltage is a voltage for sensing data of memory cells of the plurality of memory blocks.

13. The memory device according to claim 10, wherein: The voltage level of the bit line precharge voltage is lower than the voltage level of the power supply voltage, and The second driver is configured to provide the bit line precharge voltage to the plurality of bit lines before memory cells of the plurality of memory blocks are sensed.

14. The memory device according to claim 10, wherein: The negative voltage has a negative voltage level lower than a voltage level of the ground voltage, and The third driver is configured to provide the negative voltage as a body bias voltage or a reverse bias voltage applied to a well region of an NMOS transistor in which the first driver, the second driver, and the third driver are formed.

15. The memory device according to claim 9, wherein: The plurality of storage blocks include a first storage block and a second storage block, The voltage generator is commonly connected to the first memory block and the second memory block, and The memory device also includes a control logic circuit configured to control the voltage generator.

16. The memory device according to claim 15, wherein: The control logic circuit is configured to independently control a first voltage level of the shielded bit line and the plurality of back gate lines of the first memory block and a second voltage level of the shielded bit line and the plurality of back gate lines of the second memory block.

17. A storage device, comprising: A plurality of memory blocks, each of the plurality of memory blocks comprising: a plurality of word lines extending in a first direction of the memory device; a plurality of back gate lines, each of the plurality of back gate lines being adjacent to a corresponding word line of the plurality of word lines; a plurality of bit lines extending in a second direction perpendicular to the first direction; and a shielding bit line arranged between adjacent bit lines of the plurality of bit lines and located below the plurality of bit lines; and a voltage generator configured to drive the shielding bit line and the plurality of back gate lines of each of the plurality of memory blocks at the same voltage level, The voltage generator includes: a voltage generating circuit configured to generate an internal power supply voltage, a bit line precharge voltage, and a negative voltage by using a power supply voltage of the memory device, the internal power supply voltage having a voltage level the same as that of the power supply voltage, the bit line precharge voltage having a voltage level lower than that of the power supply voltage, and the negative voltage having a voltage level lower than that of a ground voltage of the memory device; a first driver configured to provide the internal power supply voltage transmitted through a first switch connected to the voltage generating circuit to an internal power supply voltage line; a second driver configured to provide the bit line precharge voltage transmitted through a second switch connected to the voltage generating circuit to a bit line precharge voltage line; and a third driver configured to provide the negative voltage transmitted through a third switch connected to the voltage generating circuit to a negative voltage line. wherein the voltage generator is configured to provide the ground voltage of the memory device to a ground voltage line, and Wherein, each of the internal power supply voltage line, the bit line precharge voltage line, the negative voltage line and the ground voltage line is electrically connected to the shielding bit line and the plurality of back gate lines of each of the plurality of memory blocks.

18. The memory device according to claim 17, wherein: The first driver includes a plurality of first driver circuits configured to drive the internal power supply voltage line, the second driver includes a plurality of second driver circuits configured to drive the bit line precharge line, and the third driver includes a plurality of third driver circuits configured to drive the negative voltage line.

19. The memory device according to claim 17, wherein: The plurality of storage blocks include a first storage block and a second storage block, The voltage generator is commonly connected to the first memory block and the second memory block, and The memory device also includes a control logic circuit configured to control the voltage generator.

20. The memory device according to claim 19, wherein: The control logic circuit is configured to independently control a first voltage level of the shielded bit line and the plurality of back gate lines of the first memory block and a second voltage level of the shielded bit line and the plurality of back gate lines of the second memory block.

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