Lower tube coupling opening suppression circuit and half-bridge ground division driving chip

Abstract

The invention provides a lower tube coupling opening suppression circuit and a half-bridge ground division driving chip, and relates to the technical field of electronic circuits. A coupling suppression tube and a suppression tube driving circuit are introduced on the basis of the design of a traditional half-bridge ground division driving chip, so that the upper power tube is switched on, the lower power tube is switched off, and meanwhile, the grid potential of the lower power tube is raised due to the power ground ringing phenomenon or the coupling influence of the potential change of the driving output end; the suppression tube driving circuit drives the coupling suppression tube to be opened, so that the grid potential of the lower power tube is pulled down to a low state, and the phenomenon that the lower power tube is opened by mistake under the coupling influence of the power ground ringing phenomenon or the potential change of the driving output end is avoided. Therefore, when the upper power tube is turned on and the lower power tube is turned off, the upper power tube and the lower power tube are effectively prevented from penetrating and even burning.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and more particularly, to a lower transistor coupling turn-on suppression circuit and a half-bridge split-ground drive chip. Background Art

[0002] With the continuous development of science and technology, the half-bridge driver technology is widely used in circuit scenarios such as motor drive, power conversion, and inverter because it can drive the upper power transistor and the lower power transistor to alternately turn on or off to control the current and voltage of the load. In the implementation of traditional half-bridge driver technology, the half-bridge driver chip often generates huge current changes when switching the power transistors, and the huge current changes will cause serious voltage ringing phenomena at the parasitic inductance and parasitic capacitance of the power loop, thus seriously interfering with the internal logic signals of the chip used for switching the power transistors.

[0003] To improve this situation, a split-ground design is usually adopted to divide the internal reference ground of the half-bridge driver chip into a power ground (PGND) and an analog ground (AGND) and then connect them to the circuit board power ground respectively (refer to Figure 1 and Figure 2 the traditional half-bridge split-ground drive chip circuit topology diagram shown), so as to isolate the half-bridge drive logic circuit and the half-bridge drive power circuit, and prevent the power ground ringing phenomenon in the half-bridge drive power circuit (i.e., Figure 1 or Figure 2 the ringing phenomenon at the parasitic inductance Lpar2 in

[0004] from affecting the normal operation of the lower transistor logic circuit in the half-bridge drive logic circuit, and ensuring that the lower transistor logic circuit can operate in a stable power supply domain based on the analog ground (i.e., the analog signal power supply VCC~analog ground AGND). Summary of the Invention

[0005] In view of this, the purpose of the present application is to provide a lower transistor coupled turn-on suppression circuit and a half-bridge split-ground drive chip, which can introduce a coupled suppression transistor and a suppression transistor drive circuit on the basis of the traditional half-bridge split-ground drive chip design. When the upper power transistor is turned on and the lower power transistor is turned off, and at the same time the gate potential of the lower power transistor is raised due to the coupled influence of the power ground ringing phenomenon or the potential change at the drive output end, the suppression transistor drive circuit drives the coupled suppression transistor to turn on, so as to pull down the gate potential of the lower power transistor to a lower state, avoiding the mis-turn-on phenomenon of the lower power transistor under the coupled influence of the power ground ringing phenomenon or the potential change at the drive output end, thereby effectively avoiding the problem of through conduction or even chip burning of the upper and lower power transistors when the upper power transistor is turned on and the lower power transistor is turned off.

[0006] To achieve the above object, the technical solutions adopted in the embodiments of the present application are as follows:

[0007] In a first aspect, the present application provides a lower transistor coupled turn-on suppression circuit, which is applied to a half-bridge split-ground drive chip. The drive output end of the half-bridge split-ground drive chip is formed by connecting the source of the upper power transistor and the drain of the lower power transistor. The lower transistor logic circuit in the half-bridge split-ground drive chip is connected to the gate of the lower power transistor through a lower transistor drive circuit. The source of the lower power transistor is connected to the power ground. The power supply terminals of the lower transistor logic circuit and the lower transistor drive circuit are connected to the analog signal power supply, and the ground terminal of the lower transistor logic circuit is connected to the analog ground; wherein, the lower transistor coupled turn-on suppression circuit includes a coupled suppression transistor and a suppression transistor drive circuit;

[0008] The logic input terminal of the suppression transistor drive circuit is connected to the logic output terminal of the lower transistor logic circuit. The gate voltage output terminal of the suppression transistor drive circuit is connected to the gate of the coupled suppression transistor. The drain of the coupled suppression transistor is connected to the analog ground. The source of the coupled suppression transistor is connected to the gate of the lower power transistor. The power supply terminal of the suppression transistor drive circuit is connected to the analog signal power supply, and the ground terminal of the suppression transistor drive circuit is connected to the analog ground; wherein, the gate voltage output terminal of the lower transistor drive circuit is connected to the gate of the lower power transistor. The lower power transistor is an N-channel MOS transistor, and the coupled suppression transistor is a P-channel MOS transistor.

[0009] In an optional embodiment, when the ground terminal of the lower transistor drive circuit is connected to the power ground, the lower transistor coupled turn-on suppression circuit further includes a logic level shift circuit, where the logic level shift circuit is disposed between the lower transistor logic circuit and the lower transistor drive circuit;

[0010] The power supply terminal of the logic level shift circuit is connected to the analog signal power supply. The first ground terminal of the logic level shift circuit is connected to the analog ground, and the second ground terminal of the logic level shift circuit is connected to the power ground;

[0011] The logic input terminal of the logic level shift circuit is connected to the logic output terminal of the lower transistor logic circuit, and the logic output terminal of the logic level shift circuit is connected to the logic input terminal of the lower transistor drive circuit, for performing a power domain conversion on the original lower transistor control logic signal output by the lower transistor logic circuit and transmitting a target lower transistor control logic signal adapted to the power domain to the lower transistor drive circuit.

[0012] In a second aspect, the present application provides a half-bridge split-ground drive chip, which includes an upper power transistor, a lower power transistor, an upper transistor control circuit, a lower transistor control circuit, and the lower transistor coupling turn-on suppression circuit described in the foregoing embodiment, wherein the lower transistor control circuit includes a lower transistor logic circuit and a lower transistor drive circuit;

[0013] The upper transistor control circuit is connected to the gate of the upper power transistor, and the drain of the upper power transistor is connected to an external power supply of the chip. Wherein the upper transistor control circuit is used to control the on-off state of the upper power transistor, and the drive output terminal of the half-bridge split-ground drive chip is formed by connecting the source of the upper power transistor and the drain of the lower power transistor, and the source of the lower power transistor is connected to a power ground;

[0014] The logic output terminal of the lower transistor logic circuit is connected to the logic input terminal of the lower transistor drive circuit, the gate voltage output terminal of the lower transistor drive circuit is connected to the gate of the lower power transistor, the power supply terminals of the lower transistor logic circuit and the lower transistor drive circuit are connected to an analog signal power supply, and the ground terminals of the lower transistor logic circuit and the lower transistor drive circuit are connected to an analog ground.

[0015] In an optional embodiment, the upper transistor control circuit includes an upper transistor logic circuit and an upper transistor drive circuit;

[0016] The logic output terminal of the upper transistor logic circuit is connected to the logic input terminal of the upper transistor drive circuit, and the gate voltage output terminal of the upper transistor drive circuit is connected to the gate of the upper power transistor;

[0017] The power supply terminals of the upper transistor logic circuit and the upper transistor drive circuit are connected to a bootstrap floating power supply based on the external power supply of the chip, and the ground terminals of the upper transistor logic circuit and the upper transistor drive circuit are connected to the source of the upper power transistor.

[0018] In an optional embodiment, the half-bridge split-ground drive chip further includes a differential pressure maintaining circuit;

[0019] The power supply terminal of the differential pressure maintaining circuit is connected to the analog signal power supply, and the ground terminal of the differential pressure maintaining circuit is connected to the power ground, for continuously maintaining the relative differential pressure between the analog signal power supply and the analog ground potential.

[0020] In an alternative embodiment, the differential pressure maintaining circuit is implemented by a capacitor. One end of the capacitor serves as the power supply terminal of the differential pressure maintaining circuit, and the other end of the capacitor serves as the ground terminal of the differential pressure maintaining circuit.

[0021] In a third aspect, the present application provides a half-bridge split-ground driving chip, which includes an upper power transistor, a lower power transistor, an upper transistor control circuit, a lower transistor control circuit, and the lower transistor coupling turn-on suppression circuit described in the foregoing embodiments. The lower transistor control circuit includes a lower transistor logic circuit and a lower transistor driving circuit.

[0022] The upper transistor control circuit is connected to the gate of the upper power transistor. The drain of the upper power transistor is connected to an external power supply of the chip. The upper transistor control circuit is used to control the on / off state of the upper power transistor. The driving output terminal of the half-bridge split-ground driving chip is formed by connecting the source of the upper power transistor and the drain of the lower power transistor. The source of the lower power transistor is connected to the power ground.

[0023] The logic output terminal of the lower transistor logic circuit is connected to the logic input terminal of the lower transistor driving circuit. The gate voltage output terminal of the lower transistor driving circuit is connected to the gate of the lower power transistor. The power supply terminals of the lower transistor logic circuit and the lower transistor driving circuit are connected to an analog signal power supply. The ground terminal of the lower transistor logic circuit is connected to the analog ground. The ground terminal of the lower transistor driving circuit is connected to the power ground.

[0024] In an alternative embodiment, the upper transistor control circuit includes an upper transistor logic circuit and an upper transistor driving circuit.

[0025] The logic output terminal of the upper transistor logic circuit is connected to the logic input terminal of the upper transistor driving circuit. The gate voltage output terminal of the upper transistor driving circuit is connected to the gate of the upper power transistor.

[0026] The power supply terminals of the upper transistor logic circuit and the upper transistor driving circuit are connected to a bootstrap floating power supply based on the external power supply of the chip. The ground terminals of the upper transistor logic circuit and the upper transistor driving circuit are connected to the source of the upper power transistor.

[0027] In an alternative embodiment, the half-bridge split-ground driving chip further includes a differential pressure maintaining circuit.

[0028] The power supply terminal of the differential pressure maintaining circuit is connected to the analog signal power supply. The ground terminal of the differential pressure maintaining circuit is connected to the power ground, and is used to continuously maintain the relative differential pressure between the analog signal power supply and the analog ground potential.

[0029] In an alternative embodiment, the differential pressure maintaining circuit is implemented by a capacitor. One end of the capacitor serves as the power supply terminal of the differential pressure maintaining circuit, and the other end of the capacitor serves as the ground terminal of the differential pressure maintaining circuit.

[0030] In this case, the beneficial effects of the embodiments of the present application may include the following:

[0031] Based on the design of the traditional half-bridge split-ground drive chip, the present application introduces a suppressor drive circuit and a P-channel coupled suppressor. The logic input terminal of the suppressor drive circuit is connected to the logic output terminal of the lower transistor logic circuit, the gate voltage output terminal of the suppressor drive circuit is connected to the gate of the coupled suppressor, and at the same time, the source of the coupled suppressor is connected to the gate of the N-channel lower power transistor. The ground terminal of the suppressor drive circuit and the drain of the coupled suppressor are respectively connected to the analog ground, and the power supply terminals of the lower transistor logic circuit, the lower transistor drive circuit, and the suppressor drive circuit are respectively connected to the analog signal power supply. Thus, when the upper power transistor is turned on and the lower power transistor is turned off, and at the same time, the gate potential of the lower power transistor is raised due to the coupling effect of the power ground ringing phenomenon or the potential change of the drive output terminal, it is ensured that the suppressor drive circuit can drive the coupled suppressor to turn on, making the gate of the lower power transistor directly equivalent to being connected to the analog ground, so as to pull down the gate potential of the lower power transistor to a lower state, avoiding the mis-turn-on phenomenon of the lower power transistor under the coupling effect of the power ground ringing phenomenon or the potential change of the drive output terminal, and effectively avoiding the problem of the upper and lower power transistors punching through or even burning the chip when the upper power transistor is turned on and the lower power transistor is turned off.

[0032] To make the above objects, features, and advantages of the present application more obvious and understandable, the following specific preferred embodiments are given below and are described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0034] Figure 1 One of the chip circuit topologies of the traditional half-bridge split-ground drive chip;

[0035] Figure 2 Another chip circuit topology of the traditional half-bridge split-ground drive chip;

[0036] Figure 3 The chip circuit topology of the first half-bridge split-ground drive chip provided by the embodiments of the present application;

[0037] Figure 4 The chip circuit topology of the second half-bridge split-ground drive chip provided by the embodiments of the present application;

[0038] Figure 5 This is the chip circuit topology diagram of the third half-bridge split-ground drive chip provided by the embodiments of the present application.

[0039] Icons: 10 - Half-bridge split-ground drive chip; 11 - Upper power transistor; 12 - Upper transistor control circuit; 13 - Lower power transistor; 14 - Lower transistor control circuit; 121 - Upper transistor logic circuit; 122 - Upper transistor drive circuit; 141 - Lower transistor logic circuit; 142 - Lower transistor drive circuit; 100 - Lower transistor coupling turn-on suppression circuit; 110 - Coupling suppression transistor; 120 - Suppression transistor drive circuit; 130 - Logic level shift circuit; 15 - Pressure difference maintenance circuit. Specific embodiments

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Components of the embodiments of the present application usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0041] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.

[0042] It should be noted that like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0043] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship when the product of this application is normally placed, or the orientation or positional relationship commonly understood by those skilled in the art. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application.

[0044] In the description of the present application, it should also be noted that unless otherwise clearly specified and defined, the terms "arranged", "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0045] In addition, in the description of the present application, it can be understood that relative terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0046] The following will describe in detail some embodiments of the present application with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0047] Please refer to Figure 1 and Figure 3 , where Figure 1 is one of the chip circuit topologies of the traditional half-bridge split-ground drive chip, Figure 3 is the chip circuit topology of the first half-bridge split-ground drive chip 10 provided by the embodiment of the present application. In the embodiment of the present application, compared with the traditional half-bridge split-ground drive chip shown in Figure 1 , Figure 3 the first half-bridge split-ground drive chip 10 shown additionally introduces a lower transistor coupled turn-on suppression circuit 100, so as to avoid the phenomenon of the lower transistor being coupled and turned on by using the lower transistor coupled turn-on suppression circuit 100 when the upper power transistor is turned on and the lower power transistor is turned off, and prevent the problem of the upper and lower power transistors being punched through or even the chip being burned.

[0048] Specifically, in the embodiment of the present application, Figure 3The first half-bridge split-drive chip 10 shown at least includes an upper power transistor 11, an upper transistor control circuit 12, a lower power transistor 13, a lower transistor control circuit 14, and a lower transistor coupling turn-on suppression circuit 100. Among them, the upper transistor control circuit 12 is used to control the on / off state of the upper power transistor 11, the lower transistor control circuit 14 is used to control the on / off state of the lower power transistor 13, and the upper power transistor 11 and the lower power transistor 13 switch on or off during normal operation (that is, when the upper power transistor 11 is required to be turned on, the lower power transistor 13 needs to be turned off, and when the lower power transistor 13 is required to be turned on, the upper power transistor 11 needs to be turned off).

[0049] In the embodiment of the present application, the upper transistor control circuit 12 is connected to the gate of the upper power transistor 11 (that is, Figure 3 the G port of the upper power transistor 11 in the above), the drain of the upper power transistor 11 (that is, Figure 3 the D port of the upper power transistor 11 in the above) is connected to the external power supply VIN of the chip with a high potential, the source of the upper power transistor 11 (that is, Figure 3 the S port of the upper power transistor 11 in the above) is connected to the drain of the lower power transistor 13 (that is, Figure 3 the D port of the lower power transistor 13 in the below), the source of the lower power transistor 13 (that is, Figure 3 the S port of the lower power transistor 13 in the below) is connected to the power ground PGND, and the lower transistor control circuit 14 is connected to the gate of the lower power transistor 13 (that is, Figure 3 the G port of the lower power transistor 13 in the below). Among them, the gate potential of the upper power transistor 11 can be regulated by the upper transistor control circuit 12, and the gate potential of the lower power transistor 13 can be regulated by the lower transistor control circuit 14 to achieve the switching-on function or switching-off function between the upper power transistor 11 and the lower power transistor 13; the upper power transistor 11 can be implemented by an N-channel MOS (Metal-Oxide-Semiconductor) transistor or a P-channel MOS transistor, so as to utilize the device on / off characteristics of the N-channel MOS transistor or the P-channel MOS transistor to achieve the switching control effect of the upper power transistor 11; the lower power transistor 13 is implemented by an N-channel MOS transistor, so as to utilize the device on / off characteristics of the N-channel MOS transistor to achieve the switching control effect of the lower power transistor 13; for Figure 3 the parasitic inductance Lpar1 in it, it belongs to the set of the drain parasitic inductance of the upper power transistor 11 and the parasitic inductance of the circuit board trace; for Figure 3 the parasitic inductance Lpar2 in it, it belongs to the set of the source parasitic inductance of the lower power transistor 13 and the parasitic inductance of the circuit board trace (including the parasitic inductance from the power ground PGND to the circuit board power ground).

[0050] In the embodiment of the present application, the upper transistor control circuit 12 may include an upper transistor logic circuit 121 and an upper transistor driving circuit 122, wherein the logical output terminal of the upper transistor logic circuit 121 (i.e., Figure 3 the LO port of the upper transistor logic circuit 121 in Figure 3 is connected to the logical input terminal of the upper transistor driving circuit 122 (i.e., Figure 3 the LI port of the upper transistor driving circuit 122 in Figure 3 The GO port of the upper transistor driving circuit 122 is connected to the gate of the upper power transistor 11. Among them, the upper transistor logic circuit 121 is configured to receive an upper transistor switch control instruction from outside the chip (i.e., Figure 3 the instruction HCO in

[0051] and generate an adapted upper transistor control logic signal according to the upper transistor switch control instruction, and then send the generated upper transistor control logic signal to the upper transistor driving circuit 122. The upper transistor driving circuit 122 provides a gate voltage signal with a corresponding potential matching the upper transistor control logic signal to the upper power transistor 11 to drive the upper power transistor 11 to turn on or off. During this process, the power supply terminals of the upper transistor logic circuit 121 and the upper transistor driving circuit 122 (i.e., Figure 3 the DY port of the upper transistor logic circuit 121 and the DY port of the upper transistor driving circuit 122 in Figure 3 are connected to the bootstrap floating power supply BOOT based on an external power supply of the chip. The grounding terminals of the upper transistor logic circuit 121 and the upper transistor driving circuit 122 (i.e., Figure 3 the JD port of the upper transistor logic circuit 121 and the JD port of the upper transistor driving circuit 122 in

[0052] In the embodiment of the present application, the lower transistor control circuit 14 may include a lower transistor logic circuit 141 and a lower transistor driving circuit 142, wherein the logical output terminal of the lower transistor logic circuit 141 (i.e., Figure 3 the LO port of the lower transistor logic circuit 141 in Figure 3 is connected to the logical input terminal of the lower transistor driving circuit 142 (i.e., Figure 3 the LI port of the lower transistor driving circuit 142 in Figure 3 The GO port of the lower transistor driving circuit 142 is connected to the gate of the lower power transistor 13. Among them, the lower transistor logic circuit 141 is configured to receive a lower transistor switch control instruction from outside the chip (i.e., Figure 3The instruction LCO) therein, and generate an adapted lower transistor control logic signal according to the lower transistor switch control instruction, and then send the generated lower transistor control logic signal to the lower transistor drive circuit 142. The lower transistor drive circuit 142 provides a gate voltage signal corresponding to the potential and matching the lower transistor control logic signal to the lower power transistor 13 to drive the lower power transistor 13 to turn on or off.

[0053] In this process, the power supply terminals of the lower transistor logic circuit 141 and the lower transistor drive circuit 142 (i.e., Figure 3 the DY port of the lower transistor logic circuit 141 in, and the DY port of the lower transistor drive circuit 142) are connected to the analog signal power supply VCC. The ground terminals of the lower transistor logic circuit 141 and the lower transistor drive circuit 142 (i.e., Figure 3 the JD port of the lower transistor logic circuit 141 in, and the JD port of the lower transistor drive circuit 142) are connected to the analog ground AGND, so as to ensure that both the lower transistor logic circuit 141 and the lower transistor drive circuit 142 can work in a relatively stable power supply domain (i.e., analog signal power supply VCC~analog ground AGND); for Figure 3 the parasitic inductance Lpar3 in, it belongs to the parasitic inductance set from the analog ground AGND to the circuit board power ground.

[0054] When it is necessary to control the lower power transistor 13 to turn on, the lower transistor control logic signal generated by the lower transistor logic circuit 141 is used to drive the lower transistor drive circuit 142 to generate a high-potential gate voltage signal, so that the gate-source voltage of the lower power transistor 13 (i.e., VGSL = VGL - VPGND, where VGSL is used to represent the gate-source voltage of the lower power transistor 13, VGL is used to represent the gate potential of the lower power transistor 13, and VPGND is used to represent the source potential of the lower power transistor 13 (i.e., the power ground potential)) exceeds its threshold voltage (i.e., VTHL) to turn on the lower power transistor 13. And when it is necessary to control the lower power transistor 13 to turn off, the lower transistor control logic signal generated by the lower transistor logic circuit 141 is used to drive the lower transistor drive circuit 142 to generate a low-potential gate voltage signal, so that the gate-source voltage of the lower power transistor 13 is lower than its threshold voltage to turn off the lower power transistor 13.

[0055] In the embodiment of the present application, the lower transistor coupled turn-on suppression circuit 100 may include a coupling suppression transistor 110 and a suppression transistor drive circuit 120, wherein the coupling suppression transistor 110 is implemented by a P-channel MOS transistor. The logic input terminal of the suppression transistor drive circuit 120 (i.e., Figure 3 the LI port of the suppression transistor drive circuit 120 in) is connected to the logic output terminal of the lower transistor logic circuit 141. The gate voltage output terminal of the suppression transistor drive circuit 120 (i.e., Figure 3The GO port of the suppression transistor driving circuit 120) is connected to the gate of the coupled suppression transistor 110 (i.e., Figure 3 The G port of the coupled suppression transistor 110 in), and the drain of the coupled suppression transistor 110 (i.e., Figure 3 The D port of the coupled suppression transistor 110 in) is connected to the analog ground AGND, and the source of the coupled suppression transistor 110 (i.e., Figure 3 The S port of the coupled suppression transistor 110 in) is connected to the gate of the lower power transistor 13. Wherein, the power supply terminal of the suppression transistor driving circuit 120 (i.e., Figure 3 The DY port of the suppression transistor driving circuit 120 in) is connected to the analog signal power supply VCC, and the ground terminal of the suppression transistor driving circuit 120 (i.e., Figure 3 The JD port of the suppression transistor driving circuit 120 in) is connected to the analog ground AGND, so that the suppression transistor driving circuit 120 and the lower transistor logic circuit 141 operate in the same power supply domain (i.e., the analog signal power supply VCC to the analog ground AGND), ensuring that the suppression transistor driving circuit 120 can also generate a lower transistor control logic signal according to the lower transistor logic circuit 141 for the lower power transistor 13, and synchronously provide a gate voltage signal corresponding to the potential matching the lower transistor control logic signal to the coupled suppression transistor 110 to drive the coupled suppression transistor 110 to turn on or off.

[0056] Wherein, when it is necessary to control the lower power transistor 13 to turn on, the lower transistor control logic signal generated by the lower transistor logic circuit 141 will synchronously drive the suppression transistor driving circuit 120 to generate a high-potential gate voltage signal. At this time, the gate-source voltage of the coupled suppression transistor 110 (i.e., VGSF = VGF - VGL, where VGSF is used to represent the gate-source voltage of the coupled suppression transistor 110, VGF is used to represent the gate potential of the coupled suppression transistor 110, and VGL is used to represent the source potential of the coupled suppression transistor 110 (i.e., the gate potential of the lower power transistor 13)) is basically equal to 0, but greater than its threshold voltage (i.e., VTHF), and the coupled suppression transistor 110 cannot conduct (turn on) and will not generate additional power consumption.

[0057] When the lower power tube 13 needs to be controlled to be turned off, the gate-source voltage of the coupling suppression tube 110 should be 0 in an ideal state (that is, the coupling suppression tube 110 is not turned on). However, since the upper power tube 11 will be turned on synchronously when the lower power tube 13 is turned off, the potential of the driving output terminal OUT jumps from the power ground potential (PGND potential is lower) to the chip external power supply potential (VIN potential is higher), and there is an obvious power ground ringing phenomenon or a change in the potential of the driving output terminal. At this time, the parasitic inductance at the lower power tube 13 will produce a voltage drop under the coupling effect of the power ground ringing phenomenon or the change in the potential of the driving output terminal, causing the power ground potential to be coupled and raised to a state far greater than the analog ground potential, VCC The voltage difference between the lower power tube 13 and the PGND will be reduced under the coupling effect (at this time, the power domain of the low-potential gate voltage signal generated by the lower tube driving circuit 142 (i.e., the analog signal power supply VCC~analog ground AGND) cannot be adapted to the working power domain of the lower power tube 13 (i.e., the analog signal power supply VCC~power ground PGND), and the lower tube driving circuit 142 has insufficient ability to drive the lower power tube 13 to maintain the off state, and it is very easy for the lower power tube 13 to fail to be turned off). At the same time, the parasitic capacitance at the lower power tube 13 will also raise the gate potential of the lower power tube 13 under the coupling effect, so that the gate-source voltage of the lower power tube 13 may be greater than its threshold voltage and a coupling-on phenomenon occurs.

[0058] In this case, since the suppression transistor driving circuit 120 shares the same lower transistor control logic signal with the lower transistor driving circuit 142, the suppression transistor driving circuit 120 will generate a low-potential gate voltage signal according to the lower transistor control logic signal. The gate-source voltage of the coupling suppression transistor 110 will actually be pulled down to a state less than its threshold voltage, causing the coupling suppression transistor 110 to turn on (conduct), making the gate of the lower power transistor 13 directly equivalent to being connected to the analog ground, generating a pull-down current for the gate potential of the lower power transistor 13 to clamp the gate potential of the lower power transistor 13 at the state of the analog ground potential (i.e., VAGND) + VSGF (i.e., the source-gate voltage of the coupling suppression transistor 110). At this time, as long as the MOS transistor size of the coupling suppression transistor 110 is set to be large enough to ensure that "VAGND + VSGF < VPGND + VTHL", the lower power transistor 13 can be effectively prevented from being coupled and turned on. In other words, the body size of the coupling suppression transistor 110 in the present application can meet the constraint condition of "VAGND + VSGF < VPGND + VTHL" when the upper power transistor 11 needs to be turned on and the lower power transistor 13 needs to be turned off, so as to prevent the lower power transistor 13 from being mis-opened under the coupling influence of the power ground ringing phenomenon or the potential change at the drive output end. Among them, the coupling suppression transistor 110 can adaptively adjust its own pull-down ability for the gate potential of the lower power transistor 13 according to the degree of coupling elevation of the gate potential of the lower power transistor 13 by using the device on-off characteristics of the P-channel MOS transistor, so as to improve the driving reliability of the first half-bridge split-ground driving chip 10 for the lower power transistor 13; among them, the greater the degree of coupling elevation of the gate potential of the lower power transistor 13, the stronger the pull-down ability of the coupling suppression transistor 110 for the gate potential of the lower power transistor 13.

[0059] Therefore, the present application introduces a suppression transistor driving circuit 120 and a P-channel coupling suppression transistor 110 on the basis of the design of the traditional half-bridge split-ground driving chip as shown in Figure 1 so that when the upper power transistor 11 is turned on and the lower power transistor 13 is turned off, and at the same time the gate potential of the lower power transistor 13 is elevated due to the coupling influence of the power ground ringing phenomenon or the potential change at the drive output end, the suppression transistor driving circuit 120 drives the coupling suppression transistor 110 to turn on, making the gate of the lower power transistor 13 directly equivalent to being connected to the analog ground, so as to pull down the gate potential of the lower power transistor 13 to a lower state, avoiding the lower power transistor 13 from being mis-opened under the coupling influence of the power ground ringing phenomenon or the potential change at the drive output end, so as to effectively avoid the problem of through conduction or even chip burning of the upper and lower power transistors when the upper power transistor 11 is turned on and the lower power transistor 13 is turned off.

[0060] Optionally, please refer to again Figure 3, in the embodiment of the present application, the first half-bridge split-ground drive chip 10 may further include a differential pressure maintaining circuit 15, and the differential pressure maintaining circuit 15 is used to continuously maintain the relative differential pressure between the analog signal power supply VCC and the analog ground potential (i.e., VAGND), so as to ensure that the lower transistor logic circuit 141, the lower transistor drive circuit 142, and the suppression transistor drive circuit 120 can work in a relatively stable power supply domain (i.e., the analog signal power supply VCC~analog ground AGND) as much as possible, and improve the reliability of the lower transistor drive of the first half-bridge split-ground drive chip 10.

[0061] Among them, the differential pressure maintaining circuit 15 can be implemented by a capacitor, and one end of the capacitor is used as the power supply terminal of the differential pressure maintaining circuit 15 (i.e., Figure 3 the DY port of the differential pressure maintaining circuit 15 in Figure 3 to connect to the analog signal power supply, and the other end of the capacitor is used as the grounding terminal of the differential pressure maintaining circuit 15 (i.e.,

[0062] Optionally, please refer to Figure 1 , Figure 3 and Figure 4 , where Figure 4 is the chip circuit topology diagram of the second half-bridge split-ground drive chip 10 provided in the embodiment of the present application. In the embodiment of the present application, compared with the first half-bridge split-ground drive chip 10 shown in Figure 3 , the main difference between the second half-bridge split-ground drive chip 10 shown in Figure 4 and the first half-bridge split-ground drive chip 10 is that: Figure 4 the grounding terminal of the lower transistor drive circuit 142 in Figure 4 (i.e., the JD port of the lower transistor drive circuit 142 in

[0063] is connected to the power ground PGND instead of the analog ground AGND, so as to ensure that the lower transistor drive circuit 142 can work in the same working power supply domain as the lower power transistor 13 (i.e., the analog signal power supply VCC~power ground PGND), so that the low-potential gate voltage signal generated when the power ground potential is coupled and raised (when the upper power transistor 11 is turned on and the lower power transistor 13 needs to be maintained in the off state) by the lower transistor drive circuit 142 can be adapted to the power supply domain of the lower power transistor 13, so as to improve the ability of the lower transistor drive circuit 142 to drive the lower power transistor 13 to maintain the off state, thereby effectively improving the reliability of the lower transistor drive of the half-bridge split-ground drive chip. Figure 1 or Figure 3 in the stable power supply domain (i.e., the analog signal power supply VCC~analog ground AGND) to Figure 4The working power supply domain therein (i.e., the analog signal power supply VCC to the power ground PGND), Figure 4 In Figure 4 , the lower transistor driving circuit 142 and the lower transistor logic circuit 141 therein will operate in different power supply domains respectively. The lower transistor control logic signal (corresponding power supply domain is the analog signal power supply VCC to the analog ground AGND) generated by the lower transistor logic circuit 141 when the upper power transistor 11 is turned on and the lower power transistor 13 is turned off cannot be adapted to the power supply domain of the lower transistor driving circuit 142, resulting in the gate voltage signal generated by the lower transistor driving circuit 142 in the corresponding working power supply domain often being unable to reach the desired gate potential state due to the transient voltage difference between the analog ground AGND and the power ground PGND (i.e., the actual potential state of the gate voltage signal generated by the lower transistor driving circuit 142 in the stable power supply domain), affecting the driving reliability of the lower transistor of the half-bridge split-ground driving chip.

[0064] To further improve Figure 4 the defect of the lower transistor gate potential regulation ability existing in the lower transistor driving circuit 142 in Figure 4 , the present application further expands the specific composition of the lower transistor coupling turn-on suppression circuit 100 on the basis of the second half-bridge split-ground driving chip design shown in Figure 4 to obtain the third half-bridge split-ground driving chip design, so as to further improve the Figure 4 precision regulation ability of the lower transistor gate potential of the lower transistor driving circuit 142 in Figure 4 . Specifically, please refer to Figure 5 , Figure 4 Figure 5 Figure 5 , Figure 5 Figure 5 is the chip circuit topology diagram of the third half-bridge split-ground driving chip 10 provided by the embodiment of the present application. In the embodiment of the present application, compared with the second half-bridge split-ground driving chip 10 shown in Figure 4 , Figure 4 Figure 4 Figure 5 the main difference between the third half-bridge split-ground driving chip 10 shown in Figure 5 and the second half-bridge split-ground driving chip 10 is that: Figure 5 The lower transistor coupling turn-on suppression circuit 100 in Figure 5 further includes a logic level shift circuit 130. The logic level shift circuit 130 is arranged between the lower transistor logic circuit 141 and the lower transistor driving circuit 142, and is used to ensure that the gate voltage signals generated by the lower transistor driving circuit 142 in the working power supply domain and the stable power supply domain respectively for the same original lower transistor control logic signal maintain the same potential state as much as possible, so as to effectively improve the precision regulation ability of the lower transistor gate potential of the lower transistor driving circuit 142 and enhance the driving reliability of the lower transistor of the half-bridge split-ground driving chip, wherein the original lower transistor control logic signal is directly generated by the lower transistor logic circuit 141.

[0065] In the embodiment of the present application, the power supply terminal of the logic level shift circuit 130 (i.e., Figure 5The DY port of the logic level shifter circuit 130 is connected to the analog signal power supply VCC, and the first ground terminal of the logic level shifter circuit 130 (i.e., Figure 5 the JD1 port of the logic level shifter circuit 130) is connected to the analog ground AGND, and the second ground terminal of the logic level shifter circuit 130 (i.e., Figure 5 the JD2 port of the logic level shifter circuit 130) is connected to the power ground PGND. Among them, the logic input terminal of the logic level shifter circuit 130 (i.e., Figure 5 the LI port of the logic level shifter circuit 130) is associated with the first ground terminal, and the logic output terminal of the logic level shifter circuit 130 (i.e., Figure 5 the LO port of the logic level shifter circuit 130) is associated with the second ground terminal.

[0066] In the embodiment of the present application, the logic input terminal of the logic level shifter circuit 130 is connected to the logic output terminal of the lower transistor logic circuit 141 to receive the original lower transistor control logic signal generated by the lower transistor logic circuit 141 for the lower power transistor 13 (wherein, the original lower transistor control logic signal will be synchronously transmitted to the suppression transistor driving circuit 120); the logic output terminal of the logic level shifter circuit 130 is connected to the logic input terminal of the lower transistor driving circuit 142, and the logic level shifter circuit 130 performs a power domain conversion on the original lower transistor control logic signal output by the lower transistor logic circuit 141 to change the power domain of the original lower transistor control logic signal from the stable power domain (i.e., the analog signal power supply VCC~the analog ground AGND) to the working power domain (i.e., the analog signal power supply VCC~the power ground PGND), so as to obtain a target lower transistor control logic signal adapted to the power domain of the lower transistor driving circuit 142, and then the logic level shifter circuit 130 transmits the target lower transistor control logic signal to the lower transistor driving circuit 142, so that the gate voltage signal that can be correspondingly generated by the lower transistor driving circuit 142 in the working power domain can reach the desired gate potential state of the original lower transistor control logic signal in the stable power domain.

[0067] Thus, the third half-bridge split-ground driving chip 10 provided by the present application can enhance the reliability of the lower transistor driving of the half-bridge split-ground driving chip by expanding the specific composition of the lower transistor coupling turn-on suppression circuit 100 and improving the precise regulation ability of the lower transistor gate potential of the lower transistor driving circuit 142.

[0068] The above is only various embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present application, and all should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A lower tube coupling turn-on suppression circuit, characterized in that: Applicable to a half-bridge ground-sharing driver chip, wherein the driving output end of the half-bridge ground-sharing driver chip is formed by connecting the source of the upper power tube and the drain of the lower power tube, the lower tube logic circuit in the half-bridge ground-sharing driver chip is connected to the gate of the lower power tube via the lower tube driving circuit, the source of the lower power tube is connected to the power ground, the power supply ends of the lower tube logic circuit and the lower tube driving circuit are respectively connected to the analog signal power supply, and the ground end of the lower tube logic circuit is connected to the analog ground; wherein the lower tube coupling start-up inhibition circuit includes a coupling inhibition tube and an inhibition tube driving circuit; The logic input end of the suppression tube driving circuit is connected to the logic output end of the lower tube logic circuit, the gate voltage output end of the suppression tube driving circuit is connected to the gate of the coupling suppression tube, the drain of the coupling suppression tube is connected to the analog ground, the source of the coupling suppression tube is connected to the gate of the lower power tube, the power supply end of the suppression tube driving circuit is connected to the analog signal power supply, and the ground end of the suppression tube driving circuit is connected to the analog ground; wherein, the gate voltage output end of the lower tube driving circuit is connected to the gate of the lower power tube, the lower power tube is an N-channel MOS tube, and the coupling suppression tube is a P-channel MOS tube.

2. The bottom tube coupling turn-on suppression circuit according to claim 1, characterized in that: In the case where the ground terminal of the lower tube driving circuit is connected to the power ground, the lower tube coupling start-up suppression circuit further includes a logic level shift circuit, wherein the logic level shift circuit is arranged between the lower tube logic circuit and the lower tube driving circuit; The power supply terminal of the logic level shift circuit is connected to the analog signal power supply, the first ground terminal of the logic level shift circuit is connected to the analog ground, and the second ground terminal of the logic level shift circuit is connected to the power ground; The logic input end of the logic level shift circuit is connected to the logic output end of the lower tube logic circuit, and the logic output end of the logic level shift circuit is connected to the logic input end of the lower tube driving circuit, so as to perform power domain conversion on the original lower tube control logic signal output by the lower tube logic circuit, and transmit the target lower tube control logic signal adapted by the power domain to the lower tube driving circuit.

3. A half-bridge ground-sharing driver chip, characterized in that: The half-bridge ground-dividing driving chip comprises an upper power tube, a lower power tube, an upper tube control circuit, a lower tube control circuit and the lower tube coupling start-up suppression circuit according to claim 1, wherein the lower tube control circuit comprises a lower tube logic circuit and a lower tube driving circuit; The upper tube control circuit is connected to the gate of the upper power tube, and the drain of the upper power tube is connected to the chip external power supply, wherein the upper tube control circuit is used to control the on-off state of the upper power tube, and the driving output end of the half-bridge ground-sharing driving chip is formed by connecting the source of the upper power tube and the drain of the lower power tube, and the source of the lower power tube is connected to the power ground; The logic output end of the lower tube logic circuit is connected to the logic input end of the lower tube driving circuit, the gate voltage output end of the lower tube driving circuit is connected to the gate of the lower power tube, the power supply ends of the lower tube logic circuit and the lower tube driving circuit are respectively connected to the analog signal power supply, and the ground ends of the lower tube logic circuit and the lower tube driving circuit are respectively connected to the analog ground.

4. The half-bridge ground-dividing driver chip according to claim 3, characterized in that: The upper tube control circuit includes an upper tube logic circuit and an upper tube driving circuit; The logic output terminal of the upper tube logic circuit is connected to the logic input terminal of the upper tube driving circuit, and the gate voltage output terminal of the upper tube driving circuit is connected to the gate of the upper power tube; The power supply terminals of the upper tube logic circuit and the upper tube driving circuit are respectively connected to a bootstrap floating power supply based on a chip external power supply, and the ground terminals of the upper tube logic circuit and the upper tube driving circuit are respectively connected to the source of the upper power tube.

5. The half-bridge ground-dividing driver chip according to claim 3 or 4, characterized in that: The half-bridge ground-sharing driver chip also includes a voltage difference maintaining circuit; The power supply end of the voltage difference maintaining circuit is connected to the analog signal power supply, and the ground end of the voltage difference maintaining circuit is connected to the power ground, so as to continuously maintain the relative voltage difference between the analog signal power supply and the analog ground potential.

6. The half-bridge ground-dividing driver chip according to claim 5, characterized in that: The voltage difference maintaining circuit is implemented by a capacitor, one end of the capacitor serves as a power supply end of the voltage difference maintaining circuit, and the other end of the capacitor serves as a ground end of the voltage difference maintaining circuit.

7. A half-bridge ground-dividing driver chip, characterized in that: The half-bridge ground-dividing driving chip comprises an upper power tube, a lower power tube, an upper tube control circuit, a lower tube control circuit and a lower tube coupling start-up suppression circuit as claimed in claim 1 or 2, wherein the lower tube control circuit comprises a lower tube logic circuit and a lower tube driving circuit; The upper tube control circuit is connected to the gate of the upper power tube, and the drain of the upper power tube is connected to the chip external power supply, wherein the upper tube control circuit is used to control the on-off state of the upper power tube, and the driving output end of the half-bridge ground-sharing driving chip is formed by connecting the source of the upper power tube and the drain of the lower power tube, and the source of the lower power tube is connected to the power ground; The logic output end of the lower tube logic circuit is connected to the logic input end of the lower tube driving circuit, the gate voltage output end of the lower tube driving circuit is connected to the gate of the lower power tube, the power supply ends of the lower tube logic circuit and the lower tube driving circuit are respectively connected to the analog signal power supply, the ground end of the lower tube logic circuit is connected to the analog ground, and the ground end of the lower tube driving circuit is connected to the power ground.

8. The half-bridge ground-dividing driver chip according to claim 7, characterized in that: The upper tube control circuit includes an upper tube logic circuit and an upper tube driving circuit; The logic output terminal of the upper tube logic circuit is connected to the logic input terminal of the upper tube driving circuit, and the gate voltage output terminal of the upper tube driving circuit is connected to the gate of the upper power tube; The power supply terminals of the upper tube logic circuit and the upper tube driving circuit are respectively connected to a bootstrap floating power supply based on a chip external power supply, and the ground terminals of the upper tube logic circuit and the upper tube driving circuit are respectively connected to the source of the upper power tube.

9. The half-bridge ground-dividing driver chip according to claim 7 or 8, characterized in that: The half-bridge ground-sharing driver chip also includes a voltage difference maintaining circuit; The power supply end of the voltage difference maintaining circuit is connected to the analog signal power supply, and the ground end of the voltage difference maintaining circuit is connected to the power ground, so as to continuously maintain the relative voltage difference between the analog signal power supply and the analog ground potential.

10. The half-bridge ground-dividing driver chip according to claim 9, characterized in that: The voltage difference maintaining circuit is implemented by a capacitor, one end of the capacitor serves as a power supply end of the voltage difference maintaining circuit, and the other end of the capacitor serves as a ground end of the voltage difference maintaining circuit.

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