Signal-to-noise ratio adjustment

Abstract

The invention discloses signal-to-noise ratio adjustment. Devices, systems, and techniques for adjusting one or more signal-to-noise ratios are disclosed. In at least one embodiment, a processor includes one or more circuits to cause one or more signal-to-noise ratios to be adjusted by a variable based at least in part on a number of indications received by the processor indicating whether a signal is successfully interpreted.

Description

Technical Field

[0001] At least one embodiment relates to processing resources for performing wireless packet transmissions. For example, at least one embodiment relates to a processor and / or computing system for adjusting a variable amount of one or more signal-to-noise ratios based at least in part on a number of indications of whether a received indication signal has been successfully interpreted according to various new techniques described herein. Background Art

[0002] Wireless packet transmissions consume a large amount of computing resources and time. Methods of wireless packet transmissions can be improved. Brief Description of the Drawings

[0003] Figure 1 is a block diagram showing a system according to at least one embodiment;

[0004] Figure 2 is a block diagram showing signal-to-interference-plus-noise ratio (SINR) adjustment according to at least one embodiment;

[0005] Figure 3 shows a flowchart of a technique for adjusting signal-to-noise ratio and selecting a modulation and coding scheme according to at least one embodiment;

[0006] Figure 4 is a block diagram showing an example of a processor according to at least one embodiment;

[0007] Figure 5 is a block diagram showing a driver and / or runtime environment according to at least one embodiment;

[0008] Figure 6 shows a graph comparing the performance of harmonic outer loop link adaptation (OLLA) and linear OLLA according to at least one embodiment;

[0009] Figure 7 shows an example data center system according to at least one embodiment;

[0010] Fig. 8A shows an example of an autonomous vehicle according to at least one embodiment;

[0011] Figure 8B shows according to at least one embodiment Fig. 8A of the camera positions and fields of view of an autonomous vehicle;

[0012] Figure 8C is according to at least one embodiment showing Fig. 8A of an example system architecture of an autonomous vehicle;

[0013] Fig.8D is a diagram showing a system for communication between one or more cloud-based servers and Fig. 8A autonomous vehicles according to at least one embodiment;

[0014] Fig. 9 is a block diagram showing a computer system according to at least one embodiment;

[0015] Fig.10 is a block diagram showing a computer system according to at least one embodiment;

[0016] Fig.11 shows a computer system according to at least one embodiment;

[0017] Fig.12 shows a computer system according to at least one embodiment;

[0018] Fig.13A shows a computer system according to at least one embodiment;

[0019] Fig. 13B shows a computer system according to at least one embodiment;

[0020] Fig. 13C shows a computer system according to at least one embodiment;

[0021] Fig.13D shows a computer system according to at least one embodiment;

[0022] Fig.13E and Fig.13F shows a shared programming model according to at least one embodiment;

[0023] Fig.14 shows an exemplary integrated circuit and associated graphics processor according to at least one embodiment;

[0024] Fig.15A and Fig. 15B shows an exemplary integrated circuit and associated graphics processor according to at least one embodiment;

[0025] Fig.16A and Fig. 16B shows additional exemplary graphics processor logic according to at least one embodiment;

[0026] Fig.17 shows a computer system according to at least one embodiment;

[0027] Fig.18A shows a parallel processor according to at least one embodiment;

[0028] Fig.18BShows a partition unit according to at least one embodiment;

[0029] Fig.18C Shows a processing cluster according to at least one embodiment;

[0030] Fig.18D Shows a graphics multiprocessor according to at least one embodiment;

[0031] Fig.19 Shows a multi-graphics processing unit (GPU) system according to at least one embodiment;

[0032] Fig. 20 Shows a graphics processor according to at least one embodiment;

[0033] Fig.21 Is a block diagram showing a processor microarchitecture for a processor according to at least one embodiment;

[0034] Fig. 22 Shows at least a portion of a graphics processor according to one or more embodiments;

[0035] Fig.23 Shows at least a portion of a graphics processor according to one or more embodiments;

[0036] Fig.24 Shows at least a portion of a graphics processor according to one or more embodiments;

[0037] Fig.25 Is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0038] Fig.26 Is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0039] Fig.27A And Fig.27B Shows thread execution logic according to at least one embodiment, which includes an array of processing elements of a graphics processor core;

[0040] Fig.28 Shows a parallel processing unit ("PPU") according to at least one embodiment;

[0041] Fig.29 Shows a general processing cluster ("GPC") according to at least one embodiment;

[0042] Fig.30 Shows a memory partition unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0043] Fig.31Shows a streaming multi-processor according to at least one embodiment;

[0044] Fig.32 Shows a network for communicating data within a 5G wireless communication network according to at least one embodiment;

[0045] Fig.33 Shows a network architecture for a 5G LTE wireless network according to at least one embodiment;

[0046] Fig.34 Is a diagram showing some basic functions of a mobile telecommunications network / system operating according to LTE and 5G principles according to at least one embodiment;

[0047] Fig.35 Shows a radio access network that can be part of a 5G network architecture according to at least one embodiment;

[0048] Fig.36 Provides an example illustration of a 5G mobile communication system in which multiple different types of devices are used according to at least one embodiment;

[0049] Fig.37 Shows an example advanced system according to at least one embodiment;

[0050] Fig.38 Shows the architecture of a network system according to at least one embodiment;

[0051] Fig.39 Shows example components of a device according to at least one embodiment;

[0052] Fig.40 Shows an example interface of a baseband circuit according to at least one embodiment;

[0053] Fig.41 Shows an example of an uplink channel according to at least one embodiment;

[0054] Fig.42 Shows the architecture of a network system according to at least one embodiment;

[0055] Fig.43 Shows a control plane protocol stack according to at least one embodiment;

[0056] Fig.44 Shows a user plane protocol stack according to at least one embodiment;

[0057] Fig.45 Shows the components of a core network according to at least one embodiment;

[0058] Fig.46shows components of a system supporting network function virtualization (NFV) according to at least one embodiment; and

[0059] Fig.47 shows components of a system for accessing a large language model according to at least one embodiment. DETAILED DESCRIPTION

[0060] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one of ordinary skill in the art that the concepts of the present invention may be practiced without one or more of these specific details.

[0061] Figure 1 FIG. 13 shows a block diagram of a system 100 according to at least one embodiment. In at least one embodiment, system 100 includes a base station 102 that communicates with a group of user equipment devices (UE) 104 via wireless radio signals. In at least one embodiment, the UE is a mobile communication device (e.g., a smart phone, a cell phone, a tablet device supporting cellular wireless, and / or any other suitable wireless mobile communication device). In at least one embodiment, the base station 102 is a gNodeB (gNB). In at least one embodiment, the base station 102 and the UE in the group of UEs 104 communicate according to one or more 3rd Generation Partnership Project (3GPP) protocols (e.g., 5th Generation (5G) New Radio (NR), 6G, and / or some other suitable protocol and / or standard). In at least one embodiment, the base station 102 adjusts the signal-to-noise ratio by a variable amount based at least in part on the number of consecutive indications of whether an indication signal received from the UE was successfully interpreted. In at least one embodiment, successful interpretation includes being successfully decoded without errors. In at least one embodiment, the base station 102 generates an offset value based on the number of consecutive acknowledgments (ACKs), applies the generated offset to a signal-to-interference-plus-noise (SINR) value to generate an adjusted SINR value, and selects a modulation and coding scheme (MCS) based at least in part on the adjusted SINR value.

[0062] In at least one embodiment, UE 104 includes a first UE 106 and a second UE 108. In at least one embodiment, base station 102 includes an antenna 110 that is used to receive signals from UEs in the set of UEs 104. In at least one embodiment, antenna 110 is further used to transmit signals to UEs in the set of UEs 104. In at least one embodiment, antenna 110 is a multi-element antenna. In at least one embodiment, antenna 110 includes a set of antenna elements 112. In at least one embodiment, the antenna elements in the set of antenna elements 112 are referred to as antennas. In at least one embodiment, the set of antenna elements 112 includes a first antenna 114 and a second antenna 116. In at least one embodiment, the set of antenna elements 112 includes an antenna number that is a power of 2 (e.g., two, four, eight, or sixteen antennas), or some other suitable number of antennas. In at least one embodiment, signals transmitted by UEs in the set of UEs 104 will be received using multiple antennas in the set of antenna elements 112. In at least one embodiment, signals transmitted to UEs in the set of UEs 104 are transmitted using multiple antennas in the set of antenna elements 112. In at least one embodiment, base station 102 includes a beamformer 152. In at least one embodiment, base station 102 is used to transmit and / or receive signals using the antennas in the set of antenna elements 112 by using beamforming (e.g., using beamformer 152).

[0063] In at least one embodiment, base station 102 includes a processor 118. In at least one embodiment, base station 102 includes a memory 120. In at least one embodiment, base station 102 includes an accelerator 122. In at least one embodiment, accelerator 122 includes one or more graphics processing units (GPUs). In at least one embodiment, accelerator 122 includes one or more parallel processing units (PPUs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and / or some other suitable accelerator. In at least one embodiment, base station 102 includes different numbers of processors (e.g., more than one processor 118), different numbers of memories (e.g., more than one memory 120), and / or different numbers of accelerators (e.g., more than one accelerator 122). In at least one embodiment, processor 118 is a central processing unit (CPU). In at least one embodiment, at least one component of base station 102 is included in a virtual radio access network (vRAN). In at least one embodiment, base station 102 uses multiple input multiple output (MIMO) (e.g., digital massive MIMO) to form beams and transmit data to multiple UEs using the same set of time and frequency resources.

[0064] In at least one embodiment, the UE 106 includes a processor 124. In at least one embodiment, the UE 106 includes a memory 126. In at least one embodiment, the UE 106 includes a different number of processors (e.g., more than one processor 124), a different number of memories (e.g., more than one memory 126), one or more accelerators, and / or one or more other suitable components (e.g., one or more user interface components, one or more antennas, and / or one or more other components), which are not shown for clarity. In at least one embodiment, other UEs in the group of UEs 104 (e.g., UE 108) include components not shown for clarity, such as the components shown and / or described with respect to UE 106.

[0065] In at least one embodiment, as used in any implementation described herein, unless the context clearly dictates otherwise or is clearly contrary, terms such as "module" and nominalized verbs (e.g., signal-to-noise ratio regulator, MCS selector, channel estimator, beamformer, signal-to-noise ratio regulation module, MCS selection module, controller, and / or other terms) refer to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functions described herein. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions, and "hardware" as used in any implementation described herein may include, for example, hardwired circuitry, programmable circuitry, state machine circuitry, fixed function circuitry, execution unit circuitry, and / or firmware storing instructions executed by the programmable circuitry, either alone or in any combination. In at least one embodiment, a module may be embodied, jointly or separately, as circuitry that forms part of a larger system (e.g., an integrated circuit (IC), a system on a chip (SoC), etc.).

[0066] In at least one embodiment, the UE 106 includes a channel quality information (CQI) generator 128. In at least one embodiment, the CQI generator 128 generates a CQI 130. In at least one embodiment, the CQI 130 includes information that can be used to generate an SNR. In at least one embodiment, the SNR is a signal-to-interference plus noise ratio (SINR). In at least one embodiment, the CQI 130 includes information indicating the SNR. In at least one embodiment, the UE 106 sends the CQI 130 to the base station 102. In at least one embodiment, the base station 102 generates one or more indications of an SNR 132 based at least in part on the CQI 130. In at least one embodiment, when the CQI 130 includes information indicating the SNR, the base station 102 stores one or more aspects of the CQI 130 as one or more indications of the SNR 132. In at least one embodiment, one or more indications of the SNR 132 are one or more SINR indications.

[0067] In at least one embodiment, base station 102 includes a signal-to-noise ratio (SNR) regulator 134. In at least one embodiment, SNR regulator 134 generates one or more offsets 136 to apply to one or more SNRs. In at least one embodiment, SNR regulator 134 generates one or more effective SNRs 138 at least in part based on one or more indications to apply offset 136 to SNR 132. In at least one embodiment, SNR regulator 134 adjusts one or more SNRs during outer loop link adaptation (OLLA). In at least one embodiment, SNR regulator 134 adjusts the SNR in a non-linear manner. In at least one embodiment, the SNR regulator adjusts the SINR. In at least one embodiment, the SNR regulator adjusts the SNR by a variable amount at least in part based on the number of indications (e.g., the number of consecutive ACKs) indicating whether a signal has been successfully interpreted.

[0068] In at least one embodiment, base station 102 includes a modulation and coding scheme (MCS) selector 140. In at least one embodiment, MCS selector 140 selects a modulation and coding scheme (e.g., identified using an MCS index) to be used for transmission to one or more UEs at least in part based on one or more effective SNRs 138. In at least one embodiment, MCS selector 140 stores one or more identifiers of the selected MCS 142. In at least one embodiment, base station 102 transmits to one or more UEs using the selected MCS. In at least one embodiment, base station 102 transmits the identifier of the selected MCS to one or more UEs. In at least one embodiment, MCS selector 138 stores the selected MCS for each packet to be transmitted as packet MCS information 144. In at least one embodiment, the MCS level determines the relative portion of the radio transmission resources used for transmitting bits and error correction information. In at least one embodiment, a higher MCS level has a higher code rate than a lower MCS level. In at least one embodiment, a modulation order (e.g., 2, 4, 6, 8, or some other suitable value) is associated with each MCS level, and some MCS levels have the same modulation order. In at least one embodiment, a particular MCS level defines the number of useful bits to be transmitted per symbol (e.g., not used as error correction information).

[0069] In at least one embodiment, one or more base stations in a 5G NR network (e.g., a gNodeB, such as base station 102) use multiple antenna elements (e.g., elements of antenna 110). In at least one embodiment, one or more base stations operate at least partially in a lower frequency band (e.g., sub-6GHz (below 6GHz) regime and / or millimeter wave (mmWave) band). In at least one embodiment, one or more base stations (e.g., base station 102) and a UE (e.g., a UE in the group of UEs 104) operate using one or more of enhanced mobile broadband (eMBB), ultra-reliable low-latency communication (URLLC), and / or massive machine type communication (mMTC). In at least one embodiment, to achieve high downlink user throughput, a base station (BS) performs beamforming based on channel estimation. In at least one embodiment, when downlink-uplink channel reciprocity is available, the BS performs channel estimation through channel measurement and / or using an uplink signal (e.g., a sounding reference signal) to obtain channel state information (CSI). In at least one embodiment, one or more techniques use a mini-slot as a scheduling unit (e.g., when performing URLLC communication). In at least one embodiment, each mini-slot includes a predefined number of orthogonal frequency division multiplexing (OFDM) symbols per mini-slot (e.g., 2, 3, 5, or 7 according to system configuration).

[0070] In at least one embodiment, base station 102 includes a channel estimator 150 that performs channel estimation and equalization of wireless signals received at base station 102. In at least one embodiment, channel estimator 150 is used to perform channel estimation at least partially based on a reference signal received from a UE (e.g., a sounding reference signal (SRS)). In at least one embodiment, beamformer 152 is used to calculate and / or identify one or more beam directions for transmitting one or more downlink signals at least partially based on the channel estimation (e.g., performed by channel estimator 150).

[0071] Figure 2 is a block diagram illustrating SNR adjustment 200 according to at least one embodiment. In at least one embodiment, base station 202 communicates with a group of UEs 204. In at least one embodiment, the group of UEs 204 includes UE 206. In at least one embodiment, base station 202 is a gNodeB (gNB). In at least one embodiment, base station 202 performs link adaptation 208 for the UEs in the group of UEs 204. In at least one embodiment, link adaptation 210 corresponds to UE 206 (e.g., for performing link adaptation for a wireless transmission to UE 206). In at least one embodiment, base station 202 is Figure 1 the base station 102 in Figure 1 a group of UEs 104 and / or UEs 206 in Figure 1 the UE 106 in

[0072] In at least one embodiment, the UE sends one or more channel quality indicators (CQIs) to the base station 202. In at least one embodiment, the CQI processor 212 generates an estimated SINR using the CQI from the UE 206. In at least one embodiment, the CQI processor 212 generates an estimated SNR. In at least one embodiment, the UEs in the group of UEs 204 generate and send an acknowledgement (ACK) indicating that the signal was successfully decoded and a negative acknowledgement (NACK) indicating that the signal was not successfully decoded. In at least one embodiment, the ACK and / or NACK are generated, sent, and received as part of a protocol, such as a hybrid automatic repeat request (HARQ) protocol or some other suitable protocol. In at least one embodiment, the outer loop link adaptation (OLLA) 214 compensates for SINR estimation errors by applying an offset. In at least one embodiment, the OLLA adaptively updates the offset based on the received ACK / NACK. In at least one embodiment, the inner loop link adaptation (ILLA) 216 selects a suitable MCS based on the corrected SINR. In at least one embodiment, Figure 1 the SNR regulator 134 in Figure 1 the MCS selector 140 in

[0073] In at least one embodiment, OLLA 214 uses a non - linear algorithm. In at least one embodiment, OLLA 214 is used for ultra - reliable low - latency communication (URLLC) services in 5G NR. In at least one embodiment, OLLA 214 is used for a low block error rate (BLER) target (e.g., 1e - 4, 1e - 5, or some other suitable value). In at least one embodiment, OLLA 214 uses an algorithm called harmonic OLLA. In at least one embodiment, this algorithm uses the harmonic series to generate an offset. In at least one embodiment, the offset drops faster at the beginning (e.g., when the first ACK in a series of consecutive ACKs is received), and then drops more slowly. In at least one embodiment, harmonic OLLA converges faster than traditional methods and gives a better estimate. In at least one embodiment, the faster convergence and better estimate of OLLA 216 enable meeting the more stringent requirements (e.g., low latency and low BLER) of wireless packet transmission for URLLC at a higher coding rate than traditional (e.g., linear OLLA) methods.

[0074] In at least one embodiment, the offset for SINR estimation is called Δ OLLA . In at least one embodiment, the initial Δ OLLA is called Δ ini . In at least one embodiment, Δ ini is a predetermined and / or predefined value. In at least one embodiment, Δ OLLA is up - regulated when a NACK is received and down - regulated when an ACK is received. In at least one embodiment, when a NACK is received, Δ OLLA =Δ OLLA +Δ up is used to adjust the offset. In at least one embodiment, when an ACK is received, Δ OLLA =Δ OLLA -Δ down / n is used to adjust the offset, where n is the number of consecutive ACKs. In at least one embodiment, for the first ACK, Δ OLLA =Δ OLLA -Δ down ; for the second consecutive ACK, Δ OLLA =Δ OLLA -Δ down / 2, for the third consecutive ACK, Δ OLLA =Δ OLLA -Δ down / 3, and so on. In at least one embodiment, as consecutive ACKs are received, Δ OLLAIt drops rapidly at the beginning and then more and more slowly. In at least one embodiment, dropping in this way results in much faster convergence than traditional methods, especially when the target block error rate BLER tar is small. In at least one embodiment, the adjusted SINR is referred to as the calibrated SINR. In at least one embodiment, the adjusted SINR is referred to as the effective SINR. In at least one embodiment, the adjusted SINR is denoted as Yeff. In at least one embodiment, the UE measures the channel quality and periodically sends CQI to the base station. In at least one embodiment, the base station estimates the SINR using the CQI from the UE. In at least one embodiment, the estimated SINR before being adjusted by OLLA is denoted as In at least one embodiment, OLLA 214 generates the adjusted SINR according to where n refers to the nth time slot or the nth transmission time interval (TTI). In at least one embodiment, if two or more consecutive NACKs are received, the offset is also adjusted at least in part based on the number of consecutive NACKs received. In at least one embodiment, the offset is adjusted at least in part based on the number of consecutive ACKs received, but not based on the number of consecutive NACKs received.

[0075] In at least one embodiment, the value of Δ up is a predetermined and / or predefined value (e.g., established using numerical simulation). In at least one embodiment, the value of Δ down is set using Δ up and the target BLER (BLER tar ). In at least one embodiment, Δ up and BLER tar are very small, and in each mini-slot, the probability of NACK is p = BLER tar . In at least one embodiment, after convergence, the increase and decrease of Δ OLLA reach equilibrium. In at least one embodiment, between two NACKs, the expected decrease is equal to Δ up . In at least one embodiment, between two NACKs, the probability of zero decrease is p, the probability of Δ down decrease is p(1 - p), the probability of (1 + 1 / 2)Δ down decrease is p(1 - p) 2 , and so on. In at least one embodiment, the expected decrease is and so on. In at least one embodiment, this is equal to which uses the property of the polylogarithm: of In at least one embodiment, to achieve balance, ln(1 / BLER tar ) * Δ down = Δ up . In at least one embodiment, when Δ up →0 and Δ down = Δ up / ln(1 / BLER tar ), the BLER of the harmonic OLLA approaches BLER tar . In at least one embodiment, when Δ up is not close to 0, Δ down is set using (α > 0) to ensure that the BLER is lower than BLER tar . In at least one embodiment, α is set to ensure that the BLER is lower than the target BLER (e.g., by setting α to 0.5 or some other suitable value when Δ up is a predefined value of 1 decibel (dB)).

[0076] Figure 3 is a flowchart of technique 300 for adjusting SNR and selecting MCS according to at least one embodiment. In at least one embodiment, one or more aspects of technique 300 are performed by one or more aspects shown or described with respect to Figure 1 (e.g., processor 118, accelerator 122, SNR regulator 134, and / or MCS selector 140), one or more aspects shown or described with respect to Figure 2 (e.g., CQI processor 212, OLLA 214, and / or ILLA 216), and / or one or more components, techniques, and / or other aspects shown or described with respect to other figures herein.

[0077] In at least one embodiment, at block 302, technique 300 includes: receiving channel quality information (CQI). In at least one embodiment, a base station (e.g., Figure 1 base station 102 and / or Figure 2 base station 202) receives CQI from a UE (e.g., Figure 1 UE 106 and / or Figure 2 UE 206). In at least one embodiment, receiving CQI includes: identifying the CQI in one or more wireless signals received from one or more UEs.

[0078] In at least one embodiment, at block 304, technique 300 includes: generating an estimated signal-to-noise ratio. In at least one embodiment, a base station (e.g., Figure 1 base station 102 and / or Figure 2 The base station 202) generates an estimated SNR. In at least one embodiment, the estimated SNR is at least partially based on one or more measurements of the channel quality (e.g., indicated by the CQI received at block 302). In at least one embodiment, Figure 2 The CQI processor 212 generates an estimated SNR. In at least one embodiment, the estimated SNR is an estimated SINR. In at least one embodiment, instead of transmitting the CQI and / or in addition to transmitting the CQI, one or more UEs also estimate the SNR and provide an indication of the estimated SNR to the base station.

[0079] In at least one embodiment, at block 306, technique 300 includes: adjusting the signal-to-noise ratio. In at least one embodiment, the base station (e.g., Figure 1 the base station 102 and / or Figure 2 the base station 202) adjusts the SNR. In at least one embodiment, Figure 1 the SNR regulator 134 adjusts the SNR. In at least one embodiment, Figure 2 the OLLA 214 adjusts the SNR. In at least one embodiment, adjusting the SNR is at least partially based on the number of consecutive ACKs received. In at least one embodiment, adjusting the SNR includes: generating an effective SNR and / or an effective SINR.

[0080] In at least one embodiment, at block 308, technique 300 includes: selecting a modulation and coding scheme (MCS). In at least one embodiment, the base station (e.g., Figure 1 the base station 102 and / or Figure 2 the base station 202) selects the MCS. In at least one embodiment, Figure 1 the MCS selector 140 selects the MCS. In at least one embodiment, Figure 2 the ILLA 216 selects the MCS. In at least one embodiment, selecting the MCS is at least partially based on the adjusted SNR.

[0081] In at least one embodiment, at block 310, technique 300 includes performing other actions. In at least one embodiment, performing other actions includes: returning to block 302 to receive additional CQI and / or returning to block 304 to perform one or more additional adjustments to the SNR (e.g., at least partially based on one or more received ACKs and / or NACKs). In at least one embodiment, performing other actions includes: transmitting one or more wireless packets using the selected MCS. In at least one embodiment, performing other actions includes: sending an identifier of the selected MCS to the UE.

[0082] In at least one embodiment, Figure 3One or more aspects of the technique 300 include: adjusting one or more signal-to-noise ratios (e.g., using Figure 1 the SNR regulator 134 and / or Figure 2 the OLLA 214) a variable amount, at least in part based on the number of indications indicating whether an indication signal received by a processor has been successfully interpreted. In at least one embodiment, the number of indications is the number of consecutive acknowledgments (ACKs) sent by one or more UE devices (e.g., UE devices in the set of UEs 104 and / or the set of UEs 204). In at least one embodiment, the technique includes: selecting a fifth-generation (5G) new radio (NR) modulation and coding scheme (MCS) at least in part based on the adjusted signal-to-noise ratio. In at least one embodiment, one or more signal-to-noise ratios are signal-to-interference-plus-noise ratios that are at least in part based on channel quality information (CQI) received from one or more UE devices. In at least one embodiment, the number of indications is the number of consecutive ACKs, and the variable amount decreases with each consecutive ACK. In at least one embodiment, the number of indications includes the number of consecutive ACKs received from UE devices at a radio network base station (e.g., Figure 1 the base station 102 and / or Figure 2 the base station 202), and the technique includes: generating an offset value that decreases with each consecutive ACK, adjusting the SINR value at least in part based on the offset value, selecting a 5G NR MCS at least in part based on the adjusted SINR value, and sending an indication of the selected MCS to the UE device. In at least one embodiment, a non-transitory computer-readable medium stores a set of instructions that, if executed by one or more processors (e.g., Figure 1 the processor 118 and / or the accelerator 122, and / or Figure 4 the processor 402), cause the one or more processors to at least perform Figure 3 one or more aspects of the technique 300.

[0083] Figure 4FIG. 0 is a block diagram illustrating an example of a processor 400 according to at least one embodiment. In at least one embodiment, processor 402 executes one or more processes (such as the processes described herein) to adjust the signal SNR by a variable amount based at least in part on the number of indications indicating whether an indication signal received by processor 400 has been successfully interpreted. In at least one embodiment, processor 402 executes one or more processes such as those described herein to select an MCS for transmitting one or more packets based at least in part on the adjusted SNR. In at least one embodiment, it should be understood that adjusting the SNR includes adjusting the SINR. In at least one embodiment, processor 402 executes one or more processes such as those described herein to non-linearly adjust the SINR based on the number of consecutive ACKs received from one or more UE devices.

[0084] In at least one embodiment, processor 402 executes with respect to Figure 1 processor 118, accelerator 122, SNR regulator 134, and / or MCS selector 140, Figure 2 OLLA 214 and / or ILLA 216 of Figure 3 techniques 300 of and / or Figure 5 one or more aspects described by one or more APIs 510 of. In at least one embodiment, processor 402 executes one or more processes, such as those combined with Figure 1-3 described processes.

[0085] In at least one embodiment, processor 402 includes one or more processors, such as the processors shown and / or described in conjunction with Figure 1 and / or one or more of the figures described below. In at least one embodiment, processor 402 is any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof. In at least one embodiment, processor 402 includes a signal-to-noise ratio (SNR) adjustment module 404 and a modulation and coding scheme (MCS) selection module 406. In at least one embodiment, SNR adjustment module 404 and / or MCS selection module 406 are part of processor 402 and / or one or more other processors. In at least one embodiment, SNR adjustment module 404 and / or MCS selection module 406 are distributed among multiple processors that communicate via a bus, network, write to shared memory, and / or any suitable communication process (such as the communication processes described herein). In at least one embodiment, SNR adjustment module 404 is referred to as a SINR adjustment module and / or some other suitable name. In at least one embodiment, MCS selection module 406 is referred to as an MCS identification module and / or some other suitable name.

[0086] In at least one embodiment, as used in any implementation described herein, unless the context clearly dictates otherwise or is clearly contrary, a module refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functions described herein. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions, and "hardware" as used in any implementation described herein may include, for example, hardwired circuitry, programmable circuitry, state machine circuitry, fixed function circuitry, execution unit circuitry, and / or firmware storing instructions executed and / or implemented by the programmable circuitry, either individually or in any combination. In at least one embodiment, a module may be embodied, jointly or individually, as circuitry forming part of a larger system (such as an integrated circuit (IC), system on a chip (SoC), etc.). In at least one embodiment, a module, in combination with any suitable processing unit and / or combination of processing units (such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof), performs one or more processes.

[0087] In at least one embodiment, the SNR adjustment module 404 is a module that adjusts the SNR by a variable amount based at least in part on the number of indications indicating whether an indication signal received by the processor has been successfully interpreted (e.g., the number of consecutive ACKs received from a UE device). In at least one embodiment, the SNR adjustment module 404 performs one or more aspects shown or described regarding the SNR adjuster 134 of Figure 1 and the OLLA 214 of Figure 2 and / or the adjustment of the SNR at block 306 of the technique 300 of Figure 3 . In at least one embodiment, the MCS selection module 406 is a module that selects and / or identifies one or more MCSs (e.g., the packet MCS information 144 of Figure 1 ) for transmitting one or more packets (e.g., URLLC packets). In at least one embodiment, the MCS selection module 406 performs one or more aspects shown or described regarding the MCS selector 140 of Figure 1 , the ILLA 216 of Figure 2 and / or the selection of the MCS at block 308 of the technique 300 of Figure 3 .

[0088] In at least one embodiment, the processor (e.g., the processor 402 in Figure 4 and / or Figure 1The processor 118 and / or the accelerator 122) includes one or more circuits that are configured to adjust one or more signal-to-noise ratios by a variable amount based at least in part on the number of indications indicating whether an indication signal received by the processor has been successfully interpreted. In at least one embodiment, the indication is an acknowledgement (ACK). In at least one embodiment, the number of indications is the number of consecutive indications, where each indication indicates that the corresponding signal has been decoded without error. In at least one embodiment, the number of indications is the number of consecutive acknowledgements (ACKs) sent by one or more UE devices. In at least one embodiment, one or more circuits are configured to cause a modulation and coding scheme (MCS) to be selected based at least in part on the adjusted SNR. In at least one embodiment, the processor is a processor of a radio network base station, the one or more signal-to-noise ratios are signal-to-interference-plus-noise (SINR) ratios, and the indication is sent by one or more UE devices. In at least one embodiment, the number of indications is the number of consecutive acknowledgements (ACKs), and one or more circuits are configured to generate an offset value that decreases with each consecutive ACK.

[0089] In at least one embodiment, the system (e.g., Figure 1 the system 100) includes one or more processors (e.g., Figure 4 the processor 402 and / or Figure 1 the processor 118 and / or the accelerator 122), the one or more processors being configured to adjust one or more signal-to-noise ratios by a variable amount based at least in part on the number of indications indicating whether an indication signal received by the processor has been successfully interpreted. In at least one embodiment, the one or more processors are one or more processors of a radio network base station. In at least one embodiment, the number of indications is the number of consecutive indications. In at least one embodiment, the number of indications is the number of consecutive acknowledgements (ACKs) sent by one or more UE devices. In at least one embodiment, the number of indications is the number of consecutive acknowledgements (ACKs) sent by one or more UE devices, and the one or more processors are configured to cause a modulation and coding scheme (MCS) to be selected based at least in part on the adjusted SNR. In at least one embodiment, the number of indications is the number of consecutive indications, and the one or more processors are configured to generate an offset value to be applied to link adaptation based at least in part on the number of consecutive indications.

[0090] Figure 5is a block diagram showing a driver and / or runtime environment 500 that includes one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment. In at least one embodiment, the software program 502 is a software module. In at least one embodiment, the software program 502 includes one or more software modules, which include but are not limited to the software modules described herein at least in conjunction with Figure 4 as described. In at least one embodiment, the software module is further non-exclusively described as in Figure 4 . In at least one embodiment, one or more APIs 510 are a set of software instructions that, if executed, cause one or more processors to perform one or more computing operations. In at least one embodiment, executing software instructions includes implementing the software instructions. In at least one embodiment, one or more aspects of one or more software modules shown or described in conjunction with Figure 4 are partially included in the software program 502 (e.g., instructions and / or code that call a function when executed by a processor), and are partially included in one or more APIs 510 and / or functions 512 (e.g., instructions and / or code that implement the called function when executed by a processor).

[0091] In at least one embodiment, one or more APIs 510 are distributed or otherwise provided as part of one or more libraries 506, drivers, and / or runtimes 504 and / or any other software grouping, non-transitory computer-readable instructions, and / or executable code further described herein. In at least one embodiment, one or more APIs 510 perform one or more computing operations in response to a call from the software program 502. In at least one embodiment, the software program 502 is a collection of software code, commands, instructions, or other text sequences that are used to direct a computing device to perform one or more computing operations and / or call one or more other instruction sets to be executed (e.g., API 510 or API function 512). In at least one embodiment, the functions provided by one or more APIs 510 include software functions 512, e.g., software functions 512 that can be used to accelerate one or more parts of the software program 502 using one or more parallel processing units (PPUs) (e.g., graphics processing units (GPUs)). In at least one embodiment, the API 510 and / or API function 512 include an SNR regulator 134 and / or an MCS selector 140 for performing operations related to Figure 1 , an OLLA 214 and / or an ILLA 216 for Figure 2 , and / or APIs and / or functions for one or more aspects shown or described by the technique 300 for Figure 3 .

[0092] In at least one embodiment, the API 510 is a hardware interface of one or more circuits for performing one or more computing operations. In at least one embodiment, one or more of the software APIs 510 described herein are implemented as one or more circuits for performing one or more of the techniques described in conjunction with Figure 1-4 In at least one embodiment, one or more software programs 502 include instructions that, if executed, cause one or more hardware devices and / or circuits to perform one or more of the techniques described in conjunction with Figure 1-4 In at least one embodiment, one or more software programs 502 utilize one or more APIs 510 provided by the driver and / or runtime 504 to manage virtual memory and / or allocate or otherwise reserve one or more blocks of the memory 514 of one or more PPUs (e.g., GPUs). In at least one embodiment, one or more software programs 502 utilize one or more APIs 510 provided by the driver and / or runtime 504 to manage virtual memory and / or allocate or otherwise reserve memory blocks.

[0093] In at least one embodiment, the software program 502 (e.g., a user-implemented software program) utilizes one or more application programming interfaces (APIs) 510 to perform various computing operations, such as memory reservation, matrix multiplication, arithmetic operations, or any computing operation performed by a parallel processing unit (PPU) (e.g., a graphics processing unit (GPU)), as further described herein. In at least one embodiment, one or more APIs 510 provide a set of callable functions 512 (referred to herein as APIs, API functions, and / or functions) that perform one or more computing operations, such as computing operations related to parallel computing. In at least one embodiment, the processor uses an API that includes an SNR adjustment function 516. In at least one embodiment, the SNR adjustment function 516 performs Figure 1 the SNR regulator 134 of Figure 2 the OLLA 214 of Figure 3 adjusting the SNR by a variable amount at block 306 of the technique 300 of Figure 4 and / or one or more aspects of the SNR adjustment module 404 of Figure 1 the MCS selector 140 of Figure 2 the ILLA 216 of Figure 3 selecting the MCS at block 308 of the technique 300 of Figure 4One or more aspects of the MCS selection module 406. In at least one embodiment, the set of callable functions 512 includes a different number of functions (e.g., separate functions for performing one or more other aspects of the technique 300). Figure 3 of the technique 300).

[0094] In at least one embodiment, one or more software programs 502 interact with or otherwise communicate with one or more APIs 510 to perform one or more computational operations using one or more PPUs (e.g., GPUs). In at least one embodiment, one or more computational operations using one or more PPUs include at least one or more sets of computational operations that are accelerated by being performed at least in part by the one or more PPUs. In at least one embodiment, one or more software programs 502 interact with one or more APIs 510 to facilitate parallel computing using a remote or local interface.

[0095] In at least one embodiment, the interface is a software instruction that, if executed, provides access to one or more functions 512 provided by one or more APIs 510. In at least one embodiment, the software program 502 uses a local interface when a software developer compiles one or more software programs 502 in conjunction with one or more libraries 506, where the libraries 506 include one or more APIs 510 or otherwise provide access to one or more APIs 510. In at least one embodiment, one or more software programs 502 are statically compiled in conjunction with pre-compiled libraries 506 or uncompiled source code that includes instructions for performing one or more APIs 510. In at least one embodiment, one or more software programs 502 are dynamically compiled and the one or more software programs are linked using a linker to one or more pre-compiled libraries 506 that include one or more APIs 510.

[0096] In at least one embodiment, the software program 502 uses a remote interface when the software program communicates with or otherwise uses a library 506 that includes one or more APIs 510 via a network or other remote communication medium. In at least one embodiment, one or more libraries 506 that include one or more APIs 510 will be executed by a remote computing service (e.g., a computing resource service provider). In another embodiment, one or more libraries 506 that include one or more APIs 510 will be executed by any other computing host that provides the one or more APIs 510 to one or more software programs 502.

[0097] In at least one embodiment, a processor that executes or uses one or more software programs 502 invokes, uses, executes, or otherwise implements one or more APIs 510 to allocate and otherwise manage the memory to be used by the software program 502. In at least one embodiment, one or more software programs 502 utilize one or more APIs 510 to allocate and otherwise manage the memory to be used by one or more portions of the software program 502 to be accelerated using one or more PPUs (such as a GPU or any other accelerator or processor further described herein).

[0098] In at least one embodiment, the API in one or more APIs 510 is an API for facilitating parallel computing. In at least one embodiment, one or more APIs 510 include any other APIs further described herein. In at least one embodiment, one or more APIs 510 are provided by a driver and / or runtime 504. In at least one embodiment, the API in one or more APIs 510 is provided by a CUDA user mode driver. In at least one embodiment, the API in one or more APIs 510 is provided by a CUDA runtime. In at least one embodiment, the driver 504 is data values and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 512 of the API 510 during the loading and execution of one or more portions of the software program 502. In at least one embodiment, the driver and / or runtime 504 is data values and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 512 of the API 510 during the execution of the software program 502. In at least one embodiment, one or more software programs 502 utilize one or more APIs 510 implemented or otherwise provided by the driver and / or runtime 504 to perform combined arithmetic operations by one or more software programs 502 during execution by one or more PPUs (such as a GPU).

[0099] Figure 6 is an example comparison 600 showing a comparison of the performance of harmonic OLLA and linear OLLA according to at least one embodiment. In at least one embodiment, harmonic OLLA is by Figure 1 the SNR regulator 134 of Figure 2 the OLLA 214 of Figure 3 block 306 of the technique 300 of Figure 4 the SNR adjustment module 404 of Figure 5The adjusted SNR function 516 is executed. In at least one embodiment, the graph 602 shows that the performance of the harmonic OLLA is significantly better than that of the linear OLLA shown in graph 604. In at least one embodiment, graph 602 and graph 604 have time in mini - slots along the x - axis and Δ along the y - axis OLLA . In at least one embodiment, the target BLER for generating the two graphs is 1e - 4, and the Δ up for generating the two graphs is 1 dB. In at least one embodiment, the Δ down for generating graph 602 is where α = 0.5, while the Δ down for generating graph 604 is 0.0001 dB. In at least one embodiment, it can be seen that the harmonic OLLA Δ OLLA 606 initially decreases faster than the linear OLLA Δ OLLA 608 (e.g., because an ACK is received after a NACK, which causes Δ OLLA to increase). In at least one embodiment, it can also be seen that the harmonic OLLA Δ OLLA 606 remains between the upper limit 610 and the lower limit 612 for a longer duration than the linear OLLA Δ OLLA 608 remains between the upper limit 614 and the lower limit 616, where the upper limit corresponds to Δ opt +0.2Δ up , the lower limit corresponds to Δ opt -0.2Δ up , and Δ opt is the predefined value 0.86 shown by the dashed line. In at least one embodiment, in URLLC where low latency and low BLER are required, the harmonic OLLA converges faster than traditional methods (such as linear OLLA) and gives a better estimate. In at least one embodiment, the harmonic OLLA results in a BLER of 8.7e - 5, and the linear OLLA results in a BLER of 1.0e - 4, where the lower BLER achieved by the harmonic OLLA is better. In at least one embodiment, the harmonic OLLA results in an average coding rate of 0.728, and the linear OLLA results in an average coding rate of 0.681, where the higher coding rate achieved by the harmonic OLLA is better. In at least one embodiment, regarding the percentage of time for a good estimate, as defined by (|Δ OLLA -Δ opt |<0.2Δ up)Defined, the percentage of time for the harmonic OLLA implementation is 87.9%, and the percentage of time for the linear OLLA implementation is 34.2%, where a higher percentage for the harmonic OLLA is better. In at least one embodiment, the average convergence time for the harmonic OLLA implementation is 1397 mini-slots, and the average convergence time for the linear OLLA implementation is 6245 mini-slots, where a lower time for the harmonic OLLA is better.

[0100] Data center

[0101] Figure 7 Illustrates an example data center 700 that may use at least one embodiment. In at least one embodiment, data center 700 includes a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0102] In at least one embodiment, as Figure 7 shown, the data center infrastructure layer 710 may include a resource coordinator 712, grouped computing resources 714, and node computing resources (“node C.R.”) 716(1)-716(N), where “N” represents any integer, positive integer. In at least one embodiment, node C.R. 716(1)-716(N) may include, but is not limited to, any number of central processing units (“CPU”) or other processors (including accelerators, field programmable gate arrays (FPGA), graphics processors, etc.), memory devices (such as dynamic read-only memory), storage devices (such as solid state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VM”), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node C.R. 716(1)-716(N) may be a server having one or more of the above computing resources.

[0103] In at least one embodiment, the grouped computing resources 714 may include separate groupings (not shown) of node C.R.s housed within one or more racks, or many racks (also not shown) housed within data centers at various geographical locations. In at least one embodiment, the separate groupings of node C.R.s within the grouped computing resources 714 may include grouped computing, network, memory, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R.s including CPUs or processors may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0104] In at least one embodiment, the resource coordinator 712 may configure or otherwise control one or more node C.R.s 716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, the resource coordinator 712 may include a software design infrastructure (“SDI”) management entity for the data center 700. In at least one embodiment, the resource coordinator may include hardware, software, or some combination thereof.

[0105] In at least one embodiment, as Figure 7 shown, the framework layer 720 includes a job scheduler 732, a configuration manager 734, a resource manager 736, and a distributed file system 738. In at least one embodiment, the framework layer 720 may include a framework for software 732 of the support software layer 730 and / or one or more applications 742 of the application layer 740. In at least one embodiment, the software 732 or the application 742 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 720 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark that may utilize the distributed file system 738 for large-scale data processing (e.g., “big data”) TM (hereinafter referred to as “Spark”). In at least one embodiment, the job scheduler 732 may include a Spark driver to facilitate scheduling of workloads supported by the various layers of the data center 700. In at least one embodiment, the configuration manager 734 may be able to configure different layers, such as the support software layer 730 and the framework layer 720 including Spark and the distributed file system 738 for supporting large-scale data processing. In at least one embodiment, the resource manager 736 is capable of managing the clusters or grouped computing resources mapped to or allocated for supporting the distributed file system 738 and the job scheduler 732. In at least one embodiment, the clusters or grouped computing resources may include grouped computing resources 714 on the data center infrastructure layer 710. In at least one embodiment, the resource manager 736 may coordinate with the resource coordinator 712 to manage these mapped or allocated computing resources.

[0106] In at least one embodiment, the software 732 included in the software layer 730 may include software used by at least a portion of nodes C.R. 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 738 of the framework layer 720. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web search software, email virus scanning software, database software, and streaming video content software.

[0107] In at least one embodiment, one or more applications 742 included in the application layer 740 may include one or more types of applications used by at least a portion of nodes C.R. 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 738 of the framework layer 720. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, and machine learning applications, including training or inference software, machine learning framework software (such as PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0108] In at least one embodiment, any one of the configuration manager 734, the resource manager 736, and the resource coordinator 712 may implement any number and type of self-modifying actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modifying actions may relieve the data center operator of the data center 700 from making potentially bad configuration decisions and may avoid underutilization and / or poorly performing parts of the data center.

[0109] In at least one embodiment, the data center 700 may include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by computing weight parameters according to a neural network architecture by using the software and computing resources described above with respect to the data center 700. In at least one embodiment, by using the weight parameters calculated by one or more training techniques described herein, the resources described above with respect to the data center 700 may be used to infer or predict information using the trained machine learning model corresponding to one or more neural networks.

[0110] In at least one embodiment, data center 700 may use a CPU, an application specific integrated circuit (ASIC), a GPU, an FPGA, or other hardware to perform training and / or inference using the above resources. Additionally, one or more of the above software and / or hardware resources may be configured as a service to allow users to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0111] In at least one embodiment, at least one component shown or described with respect to Figure 7 is used to implement the techniques and / or functions described in connection with Figure 1-5 In at least one embodiment, in at least one embodiment, at least one component shown or described with respect to Figure 7 one or more components shown or described includes logic or otherwise is used to adjust one or more SNRs and / or SINRs by a variable amount based at least in part on the number of indications (e.g., consecutive ACKs) indicating whether a signal has been successfully interpreted, recognized, and / or selected MCS and / or otherwise perform operations described in connection with Figure 1-5 In at least one embodiment, at least one of grouped computing resources 714 and node C.R. 716 is used to perform generation of one or more offsets 136, generation of one or more effective SNRs 138, selection of grouped MCS information 144, generation of one or more indications of SNR 132, and / or one or more other aspects shown and / or described with respect to Figure 1-5 In at least one embodiment, at least one of grouped computing resources 714 and node C.R. 716 performs at least one aspect described with respect to Figure 1 processor 118, accelerator 122, processor 124, SNR regulator 134, and / or MCS selector 140 of Figure 2 SNR regulation 200 of Figure 3 technique 300 of Figure 4 processor 402 of Figure 5 and / or one or more APIs 510 of

[0112] Fig. 8A FIG. shows an example of an autonomous vehicle 800 according to at least one embodiment. In at least one embodiment, autonomous vehicle 800 (alternatively referred to herein as "vehicle 800") may be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle that can accommodate one or more passengers. In at least one embodiment, vehicle 800 may be a semi-trailer truck for hauling cargo. In at least one embodiment, vehicle 800 may be an aircraft, a robotic vehicle, or another type of vehicle.

[0113] Autonomous vehicles can be described according to the automation levels defined by the National Highway Traffic Safety Administration (“NHTSA”) under the United States Department of Transportation and the Society of Automotive Engineers (“SAE”) in “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016 - 201806 issued on June 15, 2018, Standard No. J3016 - 201609 issued on September 30, 2016, and previous and future versions of this standard). In one or more embodiments, vehicle 800 may be capable of functioning according to one or more of automation levels Level 1 - Level 5. For example, in at least one embodiment, according to the embodiment, vehicle 800 may be capable of conditional automation (Level 3), highly automated (Level 4), and / or fully automated (Level 5).

[0114] In at least one embodiment, vehicle 800 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, vehicle 800 may include, but is not limited to, a propulsion system 850, such as an internal combustion engine, a hybrid device, a fully electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 850 may be connected to the driveline of vehicle 800, which may include, but is not limited to, a transmission, to enable propulsion of vehicle 800. In at least one embodiment, a signal may be received from throttle / accelerator 852 to control propulsion system 850.

[0115] In at least one embodiment, when propulsion system 850 is operating (e.g., when the vehicle is moving), a steering system 854 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 800 (e.g., along a desired path or route). In at least one embodiment, steering system 854 may receive a signal from a steering actuator 856. In at least one embodiment, the steering wheel may be optional for fully automated (Level 5) functions. In at least one embodiment, a brake sensor system 846 may be used to operate vehicle brakes in response to signals received from a brake actuator 848 and / or a brake sensor.

[0116] In at least one embodiment, controller 836 may include, but is not limited to, one or more system - on - chips (“SoC”)( Fig. 8A(not shown) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 800. For example, in at least one embodiment, controller 836 may send signals to operate vehicle brakes via brake actuator 848, operate steering system 854 via one or more steering actuators 856, and operate propulsion system 850 via one or more throttles / accelerators 852. In at least one embodiment, one or more controllers 836 may include one or more on-board (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operation commands (e.g., signals representing commands) to enable autonomous driving and / or assist a driver in driving vehicle 800. In at least one embodiment, one or more controllers 836 may include a first controller 836 for autonomous driving functions, a second controller 836 for functional safety functions, a third controller 836 for artificial intelligence functions (e.g., computer vision), a fourth controller 836 for infotainment functions, a fifth controller 836 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 836 may handle two or more of the above functions, and two or more controllers 836 may handle a single function and / or any combination thereof.

[0117] In at least one embodiment, one or more controllers 836 provide signals for controlling one or more components and / or systems of vehicle 800 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be received from sensors, and sensor types include but are not limited to one or more global navigation satellite system (“GNSS”) sensors 858 (e.g., one or more global positioning system sensors), one or more RADAR sensors 860, one or more ultrasonic sensors 862, one or more LIDAR sensors 864, one or more inertial measurement unit (IMU) sensors 866 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 896, one or more stereo cameras 868, one or more wide-angle cameras 870 (e.g., fisheye cameras), one or more infrared cameras 872, one or more surround cameras 874 (e.g., 360-degree cameras), remote cameras ( Fig. 8A (not shown), mid-range cameras ( Fig. 8A(not shown), one or more speed sensors 844 (e.g., for measuring the speed of vehicle 800), one or more vibration sensors 842, one or more steering sensors 840, one or more braking sensors (e.g., as part of a braking sensor system 846), and / or other sensor types receive.

[0118] In at least one embodiment, one or more controllers 836 may receive inputs (e.g., represented by input data) from the instrument panel 832 of vehicle 800 and provide outputs (e.g., represented by output data, display data, etc.) through a human-machine interface (“HMI”) display 834, a sound annunciator, a speaker, and / or other components of vehicle 800. In at least one embodiment, the output may include information such as vehicle speed, speed, time, map data (e.g., high-definition map ( Fig. 8A (not shown), location data (e.g., the location of vehicle 800, e.g., on a map), direction, the locations of other vehicles (e.g., occupancy grids), information about objects, and the status of objects sensed by one or more controllers 836, etc. For example, in at least one embodiment, the HMI display 834 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic signal changes, etc.) and / or information about driving operations that the vehicle has made, is making, or will make (e.g., changing lanes now, exiting at Exit 34B within two miles, etc.).

[0119] In at least one embodiment, vehicle 800 further includes a network interface 824, which may communicate through one or more networks using one or more wireless antennas 826 and / or one or more modems. For example, in at least one embodiment, the network interface 824 may be capable of communicating through Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multi-Carrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 826 may also use one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (hereinafter referred to as “LPWAN”) (e.g., LoRaWAN, SigFox, etc. protocols) to enable communication between objects in the environment (e.g., vehicles, mobile devices).

[0120] In at least one embodiment, regarding Fig. 8A at least one component shown or described is used to implement in connection with Figure 1-5The described technology and / or functionality. In at least one embodiment, in combination with Figure 1-5 The described technology and / or functionality may receive signals from vehicle 800 for its autonomous operation and / or may be used to provide the ability to remotely control vehicle 800 to a remote operator. In at least one embodiment, in combination with Figure 1-5 The described technology and / or functionality may perform one or more operations related to transmitting information to vehicle 800 (e.g., transmitted in a URLLC packet) (e.g., adjusting SNR using CQI estimation from vehicle 800 and / or selecting MCS). In at least one embodiment, vehicle 800 is used to perform the technology and / or functionality described for one or more UEs (e.g., UE 106) in a set of UEs 104 in combination with Figure 1 .

[0121] Figure 8B Shows an example of the camera positions and fields of view of Fig. 8A The autonomous vehicle 800 according to at least one embodiment. In at least one embodiment, the cameras and their respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on vehicle 800.

[0122] In at least one embodiment, the camera types for the cameras may include, but are not limited to, digital cameras that may be suitable for use with the components and / or systems of vehicle 800. In at least one embodiment, one or more cameras may operate at an automotive safety integrity level (“ASIL”) B and / or other ASIL. In at least one embodiment, according to the embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 120 fps, 240 fps, etc. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red clear clear (“RCCC”) color filter array, a red clear clear blue (“RCCB”) color filter array, a red blue green clear (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer (RGGB) sensor color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, transparent pixel cameras, such as cameras with RCCC, RCCB, and / or RBGC color filter arrays, may be used to attempt to improve photosensitivity.

[0123] In at least one embodiment, one or more cameras can be used to perform Advanced Driver Assistance System (“ADAS”) functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-functional monocular camera can be installed to provide functions including lane departure warning, traffic sign assistance, and smart headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can record and provide image data (e.g., video) simultaneously.

[0124] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom-designed (three-dimensional (“3D”) printed) assembly, to cut out stray light and reflections from within the vehicle (e.g., reflections from the dashboard reflected in the windshield mirror), which may interfere with the camera's image data capture ability. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side cameras, one or more cameras can also be integrated within the four pillars at each corner of the vehicle.

[0125] In at least one embodiment, a camera having a field of view including a portion of the environment in front of vehicle 800 (e.g., a forward camera) can be used for surround view and to help identify forward paths and obstacles with the help of one or more controllers 836 and / or a control SoC, thereby providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward camera can be used to perform many of the same ADAS functions as LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions (e.g., traffic sign recognition).

[0126] In at least one embodiment, various cameras can be used in a forward configuration, including for example a monocular camera platform including a CMOS (“Complementary Metal Oxide Semiconductor”) color imager. In at least one embodiment, a wide-angle camera 870 can be used to sense objects entering from the periphery (e.g., pedestrians, crossing the road, or bicycles). Although in Figure 8BOnly one wide - angle camera 870 is shown, but in other embodiments, there can be any number (including zero) of wide - angle cameras on vehicle 800. In at least one embodiment, any number of long - range cameras 898 (e.g., long - range stereo camera pairs) can be used for depth - based object detection, especially for objects for which a neural network has not been trained. In at least one embodiment, the long - range cameras 898 can also be used for object detection and classification and basic object tracking.

[0127] In at least one embodiment, any number of stereo cameras 868 can also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 868 can include an integrated control unit that includes a scalable processing unit that can provide programmable logic (“FPGA”) and a multi - core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit can be used to generate a 3D map of the environment of vehicle 800, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 868 can include, but are not limited to, a compact stereo vision sensor that can include, but is not limited to, two camera lenses (one on the left and one on the right) and an image - processing chip that can measure the distance from vehicle 800 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane - departure warning functions. In at least one embodiment, other types of stereo cameras 868 can be used in addition to those described herein.

[0128] In at least one embodiment, a camera with a field of view that includes a portion of the environment on the side of vehicle 800 (e.g., a side - view camera) can be used for surround - view, thereby providing information for creating and updating an occupancy grid, and generating side - collision warnings. For example, in at least one embodiment, surround cameras 874 (e.g., four surround cameras 874 as Figure 8B shown) can be positioned on vehicle 800. In at least one embodiment, one or more surround cameras 874 can include, but are not limited to, any number and combination of wide - angle cameras 870, one or more fisheye lenses, one or more 360 - degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye - lens cameras can be located at the front, rear, and sides of vehicle 800. In at least one embodiment, vehicle 800 can use three surround cameras 874 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward camera) as the fourth surround - view camera.

[0129] In at least one embodiment, a camera (e.g., a rear-view camera) having a field of view that includes a portion of the environment behind vehicle 800 can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy grids. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward cameras (e.g., long-range camera 898 and / or one or more mid-range cameras 876, one or more stereo cameras 868, one or more infrared cameras 872, etc.), as described herein.

[0130] In at least one embodiment, with respect to Figure 8B at least one component shown or described is used to implement the techniques and / or functions associated with Figure 1-5 described. In at least one embodiment, the techniques and / or functions associated with Figure 1-5 described can receive signals from vehicle 800 for its autonomous operation and / or can be used to provide the ability to remotely control vehicle 800 to a remote operator. In at least one embodiment, the techniques and / or functions associated with Figure 1-5 described can perform one or more operations related to transmitting information to vehicle 800 (e.g., transmitted in a URLLC packet) (e.g., adjusting SNR using CQI estimates from vehicle 800 and / or selecting MCS). In at least one embodiment, vehicle 800 is used to perform the techniques and / or functions described for one or more UEs (e.g., UE 106) in a set of UEs 104 associated with Figure 1 .

[0131] Figure 8C FIG. shows a block diagram of an example system architecture of an autonomous vehicle 800 according to at least one embodiment. In at least one embodiment, Fig. 8A each of one or more components, one or more features, and one or more systems of vehicle 800 in Figure 8C is shown connected via a bus 802. In at least one embodiment, bus 802 can include but is not limited to a CAN data interface (which may alternatively be referred to herein as the "CAN bus"). In at least one embodiment, CAN can be a network within vehicle 800 that helps control various features and functions of vehicle 800, such as actuation of brakes, acceleration, braking, steering, windshield wipers, etc. In one embodiment, bus 802 can be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 802 can be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle state indicators. In at least one embodiment, bus 802 can be an ASIL B compliant CAN bus.

[0132] In at least one embodiment, in addition to or from CAN, FlexRay and / or Ethernet may be used. In at least one embodiment, there may be any number of buses 802, which may include but are not limited to zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 802 may be used to perform different functions and / or may be used for redundancy. For example, a first bus 802 may be used for a collision avoidance function, and a second bus 802 may be used for actuation control. In at least one embodiment, each bus 802 may communicate with any component of the vehicle 800, and two or more of the buses 802 may communicate with the same component. In at least one embodiment, each of any number of system-on-chips (“SoC”) 804, each of one or more controllers 836, and / or each computer in the vehicle may access the same input data (e.g., input from sensors of the vehicle 800) and may be connected to a common bus, such as a CAN bus.

[0133] In at least one embodiment, the vehicle 800 may include one or more controllers 836, such as those described herein with respect to Fig. 8A In at least one embodiment, the controller 836 may be used for a variety of functions. In at least one embodiment, the controller 836 may be coupled to any of the various other components and systems of the vehicle 800 and may be used to control the vehicle 800, the artificial intelligence of the vehicle 800, the infotainment of the vehicle 800, and / or other functions.

[0134] In at least one embodiment, the vehicle 800 may include any number of SoCs 804. Each of the SoCs 804 may include but is not limited to a central processing unit (“one or more CPUs”) 806, a graphics processing unit (“one or more GPUs”) 808, one or more processors 810, one or more caches 812, one or more accelerators 814, one or more data stores 816, and / or other components and features not shown. In at least one embodiment, one or more SoCs 804 may be used to control the vehicle 800 in various platforms and systems. For example, in at least one embodiment, one or more SoCs 804 may be combined with a high-definition (“HD”) map 822 in a system (e.g., the system of the vehicle 800), and the high-definition map 822 may obtain map refresh and / or update from one or more servers ( Figure 8C not shown in the figure) via the network interface 824.

[0135] In at least one embodiment, one or more CPUs 806 may include a CPU cluster or a CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, one or more CPUs 806 may include multiple cores and / or a secondary ("L2") cache. For example, in at least one embodiment, one or more CPUs 806 may include eight cores in a multi-processor configuration that are coupled to each other. In at least one embodiment, one or more CPUs 806 may include four dual-core clusters, each of which has a dedicated L2 cache (e.g., a 2MB L2 cache). In at least one embodiment, one or more CPUs 806 (e.g., a CCPLEX) may be configured to support simultaneous cluster operations such that any combination of the clusters of one or more CPUs 806 can be active at any given time.

[0136] In at least one embodiment, one or more CPUs 806 may implement power management functions that include, but are not limited to, one or more of the following features: individual hardware modules can be automatically clock-gated when idle to save dynamic power; each core clock can be gated when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core can be powered independently; each core cluster can be independently clock-gated when all cores are clock-gated or power-gated; and / or each core cluster can be independently power-gated when all cores are power-gated. In at least one embodiment, one or more CPUs 806 may further implement enhanced algorithms for managing power states, where allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state for core, cluster, and CCPLEX inputs. In at least one embodiment, the processing core may support a simplified power state input sequence in software, where the work is shared with the microcode. In at least one embodiment, the processing core is referred to as a computing unit or an arithmetic unit.

[0137] In at least one embodiment, one or more GPUs 808 may include an integrated GPU (referred to herein as an "iGPU"). In at least one embodiment, one or more GPUs 808 may be programmable and may be effective for parallel workloads. In at least one embodiment, one or more GPUs 808 may use an enhanced tensor instruction set. In one embodiment, one or more GPUs 808 may include one or more streaming microprocessors, where each streaming microprocessor may include a level 1 ("L1") cache (e.g., an L1 cache having a storage capacity of at least 96 KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having a 512 KB storage capacity). In at least one embodiment, one or more GPUs 808 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 808 may use a compute application programming interface (API). In at least one embodiment, one or more GPUs 808 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA).

[0138] In at least one embodiment, one or more GPUs 808 may be power-optimized to achieve optimal performance in automotive and embedded use cases. For example, in one embodiment, one or more GPUs 808 may be fabricated on fin field-effect transistors ("FinFETs"). In at least one embodiment, each streaming microprocessor may contain multiple mixed-precision processing cores divided into multiple blocks. For example but not limited to, 64 PF32 cores and 32 PF64 cores may be divided into four processing blocks. In at least one embodiment, 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA tensor cores for deep learning matrix arithmetic, a level zero ("L0") instruction cache, a warp scheduler, a dispatch unit, and / or a 64 KB register file may be allocated to each processing block. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix computational and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0139] In at least one embodiment, one or more GPUs 808 may include High Bandwidth Memory (“HBM”) and / or a 16GB HBM2 memory subsystem to provide a peak memory bandwidth of approximately 900GB / second in some examples. In at least one embodiment, Synchronous Graphics Random Access Memory (“SGRAM”), such as Graphics Double Data Rate type five Synchronous Random Access Memory (“GDDR5”), may be used in addition to or in place of HBM memory.

[0140] In at least one embodiment, one or more GPUs 808 may include unified memory technology. In at least one embodiment, Address Translation Service (“ATS”) support may be used to allow one or more GPUs 808 to directly access the page tables of one or more CPUs 806. In at least one embodiment, when the memory management unit (“MMU”) of one or more GPUs 808 experiences a miss, an address translation request may be sent to one or more CPUs 806. In response, in at least one embodiment, one or more CPUs 806 may look up the virtual-physical mapping of the address in their page tables and transmit the translation back to one or more GPUs 808. In at least one embodiment, unified memory technology may allow a single unified virtual address space for the memory of both one or more CPUs 806 and one or more GPUs 808, thus simplifying the programming of one or more GPUs 808 and porting applications to one or more GPUs 808.

[0141] In at least one embodiment, one or more GPUs 808 may include any number of access counters that may track the frequency of access by one or more GPUs 808 to the memory of other processors. In at least one embodiment, one or more access counters may help ensure that memory pages are moved into the physical memory of the processor that most frequently accesses the pages, thereby improving the efficiency of the memory range shared among the processors.

[0142] In at least one embodiment, one or more SoCs 804 may include any number of caches 812, including those described herein. For example, in at least one embodiment, one or more caches 812 may include a level three (“L3”) cache that may be available to one or more CPUs 806 and one or more GPUs 808 (e.g., connected to the CPU 806 and GPU 808). In at least one embodiment, one or more caches 812 may include a write-back cache that may track the state of lines, for example, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although smaller cache sizes may be used, according to an embodiment, the L3 cache may include 4MB or more.

[0143] In at least one embodiment, one or more SoCs 804 may include one or more accelerators 814 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 804 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memories. In at least one embodiment, a large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 808 and offload some tasks of one or more GPUs 808 (e.g., free up more cycles of one or more GPUs 808 to perform other tasks). In at least one embodiment, one or more accelerators 814 may be used for target workloads that are stable enough to withstand acceleration testing (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, a CNN may include a region-based or region convolutional neural network (“RCNN”) and Fast RCNN (e.g., as used for object detection) or other types of CNNs.

[0144] In at least one embodiment, one or more accelerators 814 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). One or more DLAs may include, but are not limited to, one or more Tensor Processing Units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNNs, RCNNs, etc.). One or more DLAs may be further optimized for a particular set of neural network types and floating-point operations, as well as inference. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU and generally far exceed the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including supporting, for example, INT8, INT16, and FP16 data types for single-instance convolution functions of features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs may execute neural networks, especially CNNs, quickly and efficiently on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: CNNs for object recognition and detection using data from a camera sensor; CNNs for distance estimation using data from a camera sensor; CNNs for emergency vehicle detection, as well as identification and detection, using data from a microphone 896; CNNs for face recognition and vehicle owner identification using data from a camera sensor; and / or CNNs for security and / or safety-related events.

[0145] In at least one embodiment, a DLA may perform any function of one or more GPUs 808, and by using an inference accelerator, for example, a designer may target one or more DLAs or one or more GPUs 808 for any function. For example, in at least one embodiment, a designer may concentrate the processing and floating-point operations of a CNN on one or more DLAs and leave other functions to one or more GPUs 808 and / or one or more other accelerators 814.

[0146] In at least one embodiment, one or more accelerators 814 (e.g., a hardware acceleration cluster) can include a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, one or more PVAs can be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 838, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, one or more PVAs can strike a balance between performance and flexibility. For example, in at least one embodiment, each of one or more PVAs can include, for example but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0147] In at least one embodiment, the RISC cores can interact with an image sensor (e.g., the image sensor of any of the cameras described herein), an image signal processor, etc. In at least one embodiment, each RISC core can include any number of memories. In at least one embodiment, according to an embodiment, the RISC cores can use any one of a variety of protocols. In at least one embodiment, the RISC cores can execute a real-time operating system (“RTOS”). In at least one embodiment, one or more integrated circuit devices, application-specific integrated circuits (“ASICs”), and / or storage devices can be used to implement the RISC cores. For example, in at least one embodiment, the RISC cores can include an instruction cache and / or tightly coupled RAM.

[0148] In at least one embodiment, the DMA can enable components of the PVA to access system memory independently of one or more CPUs 806. In at least one embodiment, the DMA can support any number of features for optimizing the delivery to the PVA, including but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA can support up to six or more dimensions of addressing, which can include but are not limited to block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0149] In at least one embodiment, the vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can serve as the main processing engine of the PVA and can include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core can include a digital signal processor, e.g., a single instruction multiple data (“SIMD”), very long instruction word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0150] In at least one embodiment, each vector processor can include an instruction cache and can be coupled to a dedicated memory. As a result, in at least one embodiment, each vector processor can be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA can be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA can execute the same computer vision algorithm, except on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA can execute different computer vision algorithms simultaneously on the same image, or even different algorithms on sequential images or partial images. In at least one embodiment, among other things, any number of PVAs can be included in a hardware acceleration cluster, and any number of vector processors can be included in each PVA. In at least one embodiment, the PVA can include additional error correction code (“ECC”) memory to enhance overall system security.

[0151] In at least one embodiment, one or more accelerators 814 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the one or more accelerators 814. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, which includes, for example but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an Advanced Peripheral Bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone network that provides high-speed access to the memory for the PVA and the DLA. In at least one embodiment, the backbone network may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using the APB).

[0152] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and the DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-type communication for continuous data transfer. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard.

[0153] In at least one embodiment, one or more SoCs 804 may include a real-time line-of-sight tracking hardware accelerator. In at least one embodiment, the real-time line-of-sight tracking hardware accelerator may be used to quickly and efficiently determine the position and extent of an object (e.g., within a world model) to generate a real-time visualization simulation for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for SONAR system simulation, for general wave propagation simulation, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0154] In at least one embodiment, one or more accelerators 814 (e.g., a hardware acceleration cluster) have a wide range of uses for autonomous driving. In at least one embodiment, the PVA can be a programmable vision accelerator that is used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of the PVA at low power and low latency are well matched to algorithmic domains that require predictable processing. In other words, the PVA excels in semi-dense or dense general-purpose computing, even on small data sets that may require predictable runtimes with low latency and low power. In at least one embodiment, autonomous vehicles, such as in vehicle 800, the PVA may be designed to run classical computer vision algorithms because they can be effective in object detection and integer math operations.

[0155] For example, according to at least one embodiment of the technology, the PVA is used to perform computer stereo vision. In at least one embodiment, algorithms based on semi-global matching may be used in some examples, although this is not meant to be limiting. In at least one embodiment, applications for level 3 - 5 autonomous driving use dynamic estimation / stereo matching in operation (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, the PVA can perform computer stereo vision functions on inputs from two monocular cameras.

[0156] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using 4D fast Fourier transform) to provide processed RADAR data. In at least one embodiment, for example, by processing raw time-of-flight data to provide processed time-of-flight data, the PVA is used for time-of-flight depth processing.

[0157] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including for example but not limited to neural networks, the output of which provides a confidence level for each object detection. In at least one embodiment, the confidence level can be represented or interpreted as a probability, or as providing a relative "weight" of each detection relative to other detections. In at least one embodiment, the confidence level enables the system to make further decisions, namely, regarding which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence level and consider only detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, false positive detections would cause the vehicle to automatically perform emergency braking, which is clearly undesirable. In at least one embodiment, highly confident detections can be considered as triggers for AEB. In at least one embodiment, the DLA can run a neural network for regressing confidence values. In at least one embodiment, the neural network can take as its input at least some subset of parameters, such as bounding box dimensions, a obtained ground plane estimate (e.g., from another subsystem), the output of one or more IMU sensors 866 related to the vehicle 800 direction, distance, 3D position estimate of an object obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 864 or one or more RADAR sensors 860), etc.

[0158] In at least one embodiment, one or more SoCs 804 (e.g., a hardware acceleration cluster) can include one or more data storage devices 816 (e.g., a memory). In at least one embodiment, one or more data storages 816 can be on-chip memories of one or more SoCs 804, which can store neural networks to be executed on one or more GPUs 808 and / or DLA. In at least one embodiment, one or more data storages 816 can have a large enough capacity to store multiple instances of neural networks for redundancy and safety. In at least one embodiment, one or more data storages 812 can include L2 or L3 caches.

[0159] In at least one embodiment, one or more SoCs 804 may include any number of processors 810 (e.g., embedded processors). In at least one embodiment, one or more processors 810 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions as well as associated security implementations. In at least one embodiment, the boot and power management processor may be part of the one or more SoC804 boot sequences and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low power state transitions, manage one or more SoC 804 thermal and temperature sensors, and / or manage the power state of one or more SoC 804. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoC804 may use the ring oscillator to detect the temperature of one or more CPUs 806, one or more GPUs 808, and / or one or more accelerators 814. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the boot and power management processor may enter a temperature fault routine and place one or more SoC 804 in a lower power state and / or place the vehicle 800 in a safe parking pattern for the driver (e.g., safely park the vehicle 800).

[0160] In at least one embodiment, one or more processors 810 may further include a set of embedded processors, which may be used as an audio processing engine. In at least one embodiment, the audio processing engine may be an audio subsystem that can provide full hardware support for multi-channel audio to the hardware through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0161] In at least one embodiment, one or more processors 810 may further include an always-on processor engine. In at least one embodiment, the always-on processing engine may provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processors on the always-on processor engine may include, but are not limited to, processor cores, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0162] In at least one embodiment, one or more processors 810 may further include a security cluster engine, which includes but is not limited to a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the security cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (such as timers, interrupt controllers, etc.) and / or routing logic. In a security mode, in at least one embodiment, two or more cores may operate in a lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 810 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 810 may further include a high-dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine that is part of a camera processing pipeline.

[0163] In at least one embodiment, one or more processors 810 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required for a video playback application to produce a final video to generate a final image for a player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 870, one or more surround cameras 874, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, preferably, the in-cabin monitoring camera sensors are monitored by a neural network running on another instance of the SoC 804, which is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform but is not limited to lip reading to activate cellular services and make phone calls, indicate emails, change the destination of the vehicle, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode and are otherwise disabled.

[0164] In at least one embodiment, the video image synthesizer may include enhanced temporal noise reduction for simultaneous spatial and temporal noise reduction. For example, in at least one embodiment, in the case where motion occurs in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of the information provided by adjacent frames. In at least one embodiment, in the case where an image or a part of the image does not include motion, the temporal noise reduction performed by the video image synthesizer may use information from a previous image to reduce the noise in the current image.

[0165] In at least one embodiment, the video image synthesizer may also be configured to perform stereo correction on the input stereoscopic lens frames. In at least one embodiment, when using an operating system desktop, the video image synthesizer may also be used for user interface synthesis and does not require one or more GPUs 808 to continuously render new surfaces. In at least one embodiment, when powering one or more GPUs 808 and making them actively perform 3D rendering, the video image synthesizer may be used to offload one or more GPUs 808 to improve performance and responsiveness.

[0166] In at least one embodiment, one or more of the SoCs 804 may further include a Mobile Industry Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block for receiving video and inputs from cameras and may be used for camera and related pixel input functions. In at least one embodiment, one or more of the SoCs 804 may further include an input / output controller that may be software-controlled and may be used to receive I / O signals that are not committed to a specific role.

[0167] In at least one embodiment, one or more of the SoCs 804 may further include a wide range of peripheral interfaces to enable communication with peripheral devices, audio encoder / decoders (“codecs”), power management, and / or other devices. One or more of the SoCs 804 may be used to process data from cameras (e.g., via Gigabit Multimedia Serial Link and Ethernet connections), sensors (e.g., one or more LIDAR sensors 864, one or more RADAR sensors 860, etc., which may be connected via Ethernet), data from the bus 802 (e.g., the speed of the vehicle 800, the steering wheel position, etc.), data from one or more GNSS sensors 858 (e.g., via an Ethernet bus or CAN bus connection), etc. In at least one embodiment, one or more of the SoCs 804 may further include a dedicated high-performance mass storage controller that may include its own DMA engine and may be used to free one or more CPUs 806 from conventional data management tasks.

[0168] In at least one embodiment, one or more SoCs 804 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thus providing an integrated functional safety architecture that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, and that provides a platform for a flexible and reliable driving software stack as well as deep learning tools. In at least one embodiment, one or more SoCs 804 can be faster and more reliable than conventional systems, and even more energy and space efficient. For example, in at least one embodiment, one or more accelerators 814 can provide a fast and efficient platform for level 3-5 autonomous vehicles when combined with one or more CPUs 806, one or more GPUs 808, and one or more data storage devices 816.

[0169] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured in a high-level programming language (e.g., the C programming language) to execute a variety of processing algorithms on a variety of visual data. However, in at least one embodiment, a CPU generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual level 3-5 autonomous vehicles.

[0170] The embodiments described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and allow the results to be combined to achieve level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPUs 820) can include text and word recognition, thus allowing a supercomputer to read and understand traffic signs, including signs that the neural network has not been specifically trained for. In at least one embodiment, the DLA can also include a neural network that is capable of recognizing, interpreting, and providing semantic understanding of symbols, and passing that semantic understanding to a path planning module running on a CPU Complex.

[0171] In at least one embodiment, for a level 3, 4, or 5 drive, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign consisting of, among other things, a connected electric light with the text "Caution: flashing lights indicate icy conditions" can be interpreted independently or jointly by multiple neural networks. In at least one embodiment, the sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the text "flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executed on the CPU Complex) that when flashing lights are detected, there is an icy condition. In at least one embodiment, a third deployed neural network can operate on multiple frames to identify the flashing lights and notify the vehicle's path planning software of the presence (or absence) of the flashing lights. In at least one embodiment, all three neural networks can run simultaneously, e.g., within the DLA and / or on one or more GPUs 808.

[0172] In at least one embodiment, a CNN for face recognition and vehicle owner recognition can use data from a camera sensor to identify the presence of an authorized driver and / or the owner of the vehicle 800. In at least one embodiment, a normally open sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in a security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 804 provide protection against theft and / or carjacking.

[0173] In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphone 896 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 804 use the CNN to classify ambient and urban sounds, as well as to classify visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative approach speed of an emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles for the area in which the vehicle is operating, as identified by one or more GNSS sensors 858. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while in the United States, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 862, to perform emergency vehicle safety routines, decelerate the vehicle, drive the vehicle to the side of the road, park, and / or idle the vehicle until the emergency vehicle has passed.

[0174] In at least one embodiment, vehicle 800 can include one or more CPUs 818 (e.g., one or more discrete CPUs or one or more dCPUs), which can be coupled to one or more SoCs 804 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, one or more CPUs 818 can include X86 processors, e.g., one or more CPUs 818 can be used to perform any of a variety of functions, such as including potentially arbitrating inconsistent results between ADAS sensors and one or more SoCs 804, and / or monitoring the status and health of one or more monitoring controllers 836 and / or the on-chip information system (“Info SoC”) 830.

[0175] In at least one embodiment, vehicle 800 can include one or more GPUs 820 (e.g., one or more discrete GPUs or one or more dGPUs), which can be coupled to one or more SoCs 804 via a high-speed interconnect (e.g., NVIDIA's NVLINK). In at least one embodiment, one or more GPUs 820 can provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and can be used for training and / or updating neural networks at least in part based on inputs from sensors of vehicle 800 (e.g., sensor data).

[0176] In at least one embodiment, vehicle 800 may further include a network interface 824, which may include, but is not limited to, one or more wireless antennas 826 (e.g., one or more wireless antennas 826 for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 824 may be used to enable a wireless connection with other vehicles and / or computing devices (e.g., a passenger's client device) via the Internet with a cloud (e.g., using a server and / or other network devices). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 800 and other vehicles and / or an indirect link (e.g., via a network and the Internet) may be established. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 800 with information about vehicles in the vicinity of vehicle 800 (e.g., vehicles in front of, to the side of, and / or behind vehicle 800). In at least one embodiment, the foregoing function may be part of the cooperative adaptive cruise control function of vehicle 800.

[0177] In at least one embodiment, network interface 824 may include a SoC that provides modulation and demodulation functions and enables one or more controllers 836 to communicate via a wireless network. In at least one embodiment, network interface 824 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by well-known processes and / or using a superheterodyne process. In at least one embodiment, the radio frequency front end functions may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functions for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0178] In at least one embodiment, vehicle 800 may further include one or more data stores 828, which may include, but is not limited to, off-chip (e.g., one or more SoCs 804) storage. In at least one embodiment, one or more data stores 828 may include, but is not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disks, and / or other components and / or devices that can store at least one bit of data.

[0179] In at least one embodiment, vehicle 800 may further include one or more GNSS sensors 858 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 858 may be used, including, for example but not limited to, a GPS connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0180] In at least one embodiment, vehicle 800 may further include one or more RADAR sensors 860. The one or more RADAR sensors 860 may be used by vehicle 800 for remote vehicle detection, even in dark and / or adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. The one or more RADAR sensors 860 may use a CAN bus and / or bus 802 (e.g., to transmit data generated by the one or more RADAR sensors 860) for control and access to object tracking data, and in some examples may access an Ethernet channel to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example but not limited to, one or more of the RADAR sensors 860 may be suitable for front, rear, and side RADAR use. In at least one embodiment, the one or more RADAR sensors 860 are pulsed Doppler RADAR sensors.

[0181] In at least one embodiment, the one or more RADAR sensors 860 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR may be used for adaptive cruise control functions. In at least one embodiment, a long-range RADAR system may provide a wide field of view achieved through two or more independent scans (e.g., within 250 m). In at least one embodiment, the one or more RADAR sensors 860 may assist in differentiating between static and moving objects and may be used by ADAS system 838 for emergency braking assistance and forward collision warning. In at least one embodiment, the one or more sensors 860 included in the long-range RADAR system may include, for example but not limited to, a monostatic multimode RADAR having multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, with six antennas, the central four antennas may create a focused beam pattern designed to record the surrounding environment of vehicle 800 at a higher speed with minimal traffic interference in adjacent lanes. In at least one embodiment, the other two antennas may expand the field of view so that vehicles entering or leaving the lane of vehicle 800 can be quickly detected.

[0182] In at least one embodiment, by way of example, a mid-range RADAR system may include, for example, a range of up to 160 m (front) or 80 m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 860 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the blind spots at the rear and in the vicinity of the vehicle. In at least one embodiment, the short-range RADAR system may be used in the ADAS system 838 for blind spot detection and / or lane change assistance.

[0183] In at least one embodiment, the vehicle 800 may further include one or more ultrasonic sensors 862. In at least one embodiment, one or more ultrasonic sensors 862 that may be positioned at the front, rear, and / or sides of the vehicle 800 may be used for parking assistance and / or creating and updating an occupancy grid. In at least one embodiment, a variety of ultrasonic sensors 862 may be used, and different ultrasonic sensors 862 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 862 may operate at a functional safety level of ASIL B.

[0184] In at least one embodiment, the vehicle 800 may include one or more LIDAR sensors 864. One or more LIDAR sensors 864 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LIDAR sensors 864 may be of functional safety level ASIL B. In at least one embodiment, the vehicle 800 may include multiple (e.g., two, four, six, etc.) LIDAR sensors 864 (e.g., providing data to a gigabit Ethernet switch) that may use Ethernet.

[0185] In at least one embodiment, one or more LIDAR sensors 864 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 864 may, for example, have an advertised range of approximately 100 m, an accuracy of 2 cm - 3 cm, and support an Ethernet connection of 100 Mbps. In at least one embodiment, one or more non-protruding LIDAR sensors 864 may be used. In such an embodiment, one or more LIDAR sensors 864 may be implemented as small devices embedded in the front, rear, sides, and / or corners of the vehicle 800. In at least one embodiment, one or more LIDAR sensors 864, in such an embodiment, may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for low-reflectivity objects, and have a range of 200 m. In at least one embodiment, the forward one or more LIDAR sensors 864 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0186] In at least one embodiment, LIDAR technologies such as 3D flash LIDAR may also be used. 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200 m around the vehicle 800. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light on each pixel, which in turn corresponds to the range from the vehicle 800 to the object. In at least one embodiment, flash LIDAR may allow for the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, with one sensor on each side of the vehicle 800. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera that has no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device may use class I (eye-safe) laser pulses of 5 nanoseconds per frame and may capture the reflected laser in the form of a 3D ranging point cloud and co-registered intensity data.

[0187] In at least one embodiment, vehicle 800 may further include one or more IMU sensors 866. In at least one embodiment, one or more IMU sensors 866 may be located at the center of the rear axle of vehicle 800. In at least one embodiment, one or more IMU sensors 866 may include, for example but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, one or more IMU sensors 866 may include but not limited to accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, one or more IMU sensors 866 may include but not limited to accelerometers, gyroscopes, and magnetometers.

[0188] In at least one embodiment, one or more IMU sensors 866 may be implemented as a miniature high-performance GPS-aided inertial navigation system (“GPS / INS”) that combines microelectromechanical system (“MEMS”) inertial sensors, high-sensitivity GPS receivers, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude; in at least one embodiment, one or more IMU sensors 866 may enable vehicle 800 to estimate heading without input from a magnetic sensor by directly observing and correlating speed changes from GPS to one or more IMU sensors 866. In at least one embodiment, one or more IMU sensors 866 and one or more GNSS sensors 858 may be combined in a single integrated unit.

[0189] In at least one embodiment, vehicle 800 may include one or more microphones 896 placed inside and / or around vehicle 800. In at least one embodiment, in addition, one or more microphones 896 may be used for emergency vehicle detection and identification.

[0190] In at least one embodiment, vehicle 800 may further include any number of camera types, including one or more stereo cameras 868, one or more wide-angle cameras 870, one or more infrared cameras 872, one or more surround cameras 874, one or more long-range cameras 898, one or more mid-range cameras 876, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of vehicle 800. In at least one embodiment, the type of cameras used depends on vehicle 800. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around vehicle 800. In at least one embodiment, the number of cameras deployed may vary according to the embodiment. For example, in at least one embodiment, vehicle 800 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras may support, by way of example and not limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet. In at least one embodiment, each camera may be described in more detail with reference to Fig. 8A and Figure 8B which may be described in more detail.

[0191] In at least one embodiment, vehicle 800 may further include one or more vibration sensors 842. In at least one embodiment, one or more vibration sensors 842 may measure the vibration of components of vehicle 800 (e.g., an axle). For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 842 are used, the difference between the vibrations may be used to determine road surface friction or slippage (e.g., when there is a vibration difference between a powered drive axle and a free-rotating axle).

[0192] In at least one embodiment, vehicle 800 may include an ADAS system 838. The ADAS system 838 may include, but is not limited to, a SoC. In at least one embodiment, the ADAS system 838 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions and combinations thereof.

[0193] In at least one embodiment, the ACC system may use one or more RADAR sensors 860, one or more LIDAR sensors 864, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to the vehicle in front of the adjacent vehicle 800 and automatically adjusts the speed of the vehicle 800 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that the vehicle 800 change lanes when necessary. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0194] In at least one embodiment, the CACC system uses information from other vehicles, which may be received via a network interface 824 and / or one or more wireless antennas 826 from other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Generally, the V2V communication concept provides information about the vehicle immediately in front (e.g., the vehicle immediately in front of and in the same lane as the vehicle 800), while the I2V communication concept provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, in the case of information about the vehicle in front of a given vehicle 800, the CACC system may be more reliable and has the potential to improve the smoothness of traffic flow and reduce road congestion.

[0195] In at least one embodiment, the FCW system is designed to warn the driver of a hazard so that the driver can take corrective measures. In at least one embodiment, the FCW system uses a forward camera and / or one or more RADAR sensors 860, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system may provide warnings, such as in the form of audible, visual warnings, vibration, and / or rapid braking pulses.

[0196] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can use one or more forward cameras and / or one or more RADAR sensors 860 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes in an attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or braking for impending collision.

[0197] In at least one embodiment, when vehicle 800 crosses a lane marking, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibration, to alert the driver. In at least one embodiment, the LDW system is inactive when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system can use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variant of the LDW system. If vehicle 800 begins to leave the lane, the LKA system provides steering input or braking to correct vehicle 800.

[0198] In at least one embodiment, the BSW system detects and warns the driver of a vehicle in the blind spot of an automobile. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide an additional warning when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 860 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0199] In at least one embodiment, when an object is detected outside the rear camera range while the vehicle 800 is reversing, the RCTW system can provide visual, auditory, and / or tactile notifications. In at least one embodiment, the RCTW system includes an AEB system to ensure that the vehicle brakes are applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 860, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0200] In at least one embodiment, conventional ADAS systems may be prone to producing false positive results, which may annoy and distract the driver, but are generally not catastrophic because conventional ADAS systems will warn the driver and allow the driver to decide whether a safety situation truly exists and take appropriate action. In at least one embodiment, in the case of conflicting results, the vehicle 800 itself decides whether to follow the result of the primary computer or the secondary computer (e.g., the first controller 836 or the second controller 836). For example, in at least one embodiment, the ADAS system 838 can be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run various software redundantly on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 838 can be provided to the monitoring MCU. In at least one embodiment, if the outputs from the primary computer and the auxiliary computer conflict, the supervisory MCU decides how to reconcile the conflict to ensure safe operation.

[0201] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU to indicate the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the instructions of the primary computer regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, in the case where the confidence score does not meet the threshold and the primary computer and the auxiliary computer indicate different results (e.g., conflict), the supervisory MCU can arbitrate between the computers to determine an appropriate result.

[0202] In at least one embodiment, the supervisory MCU may be configured to run a neural network that is trained and configured to determine conditions under which the auxiliary computer provides an error alert based at least in part on outputs from a host computer and an auxiliary computer. In at least one embodiment, the neural network in the supervisory MCU may learn when the output of the auxiliary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, the neural network in the supervisory MCU may learn when the FCW system identifies a metallic object that is not actually dangerous, such as a drain grate or manhole cover that would trigger an alert. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override the LDW when there is a bicyclist or pedestrian present and when lane departure is actually the safest course of action. In at least one embodiment, the supervisory MCU may include at least one of a DLA or a GPU suitable for running a neural network with an associated memory. In at least one embodiment, the supervisory MCU may be included as and / or be a component of one or more SoCs 804.

[0203] In at least one embodiment, the ADAS system 838 may include an auxiliary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of the neural network in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the overall system more fault-tolerant, especially for faults caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or error in the software running on the host computer and the different software code running on the auxiliary computer provides the same overall result, the supervisory MCU can be more confident that the overall result is correct and that the vulnerability in the software or hardware on the host computer will not cause a major error.

[0204] In at least one embodiment, the output of the ADAS system 838 may be input into the perception module of the host computer and / or the dynamic driving task module of the host computer. For example, in at least one embodiment, if the ADAS system 838 indicates a forward collision warning due to an object directly ahead, the perception block may use that information when identifying the object. In at least one embodiment, as described herein, the auxiliary computer may have its own neural network that is trained to reduce the risk of false alarms.

[0205] In at least one embodiment, vehicle 800 may further include an infotainment SoC 830 (e.g., in-vehicle infotainment (IVI)). Although shown and described as an SoC, in at least one embodiment, infotainment system 830 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, infotainment SoC 830 may include, but is not limited to, a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation systems, rear parking assist, radio data system, vehicle-related information such as fuel level, total covered distance, brake fuel level, oil level, door open / closed, air filter information, etc.) to vehicle 800. For example, infotainment SoC 830 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, car, in-vehicle entertainment system, WiFi, steering wheel audio control, hands-free voice control, heads-up display (“HUD”), HMI display 834, telematics device, control panel (e.g., for controlling various components, features, and / or systems and / or interacting therewith), and / or other components. In at least one embodiment, infotainment SoC 830 may further be used to provide information (e.g., visual and / or auditory) to a user of the vehicle, such as information from ADAS system 838, autonomous driving information (such as planned vehicle maneuvers), trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0206] In at least one embodiment, infotainment SoC 830 may include any number and type of GPU functionality. In at least one embodiment, infotainment SoC 830 may communicate with other devices, systems, and / or components of vehicle 800 via bus 802 (e.g., CAN bus, Ethernet, etc.). In at least one embodiment, infotainment SoC 830 may be coupled to a monitoring MCU such that the GPU of the infotainment system may perform some autonomous driving functions in the event of a failure of the main controller 836 (e.g., the main computer and / or standby computer of vehicle 800). In at least one embodiment, infotainment SoC 830 may cause vehicle 800 to enter the driver-to-safe stop mode as described herein.

[0207] In at least one embodiment, vehicle 800 may further include a dashboard 832 (e.g., a digital dashboard, an electronic dashboard, a digital instrument cluster, etc.). In at least one embodiment, the dashboard 832 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the dashboard 832 may include, but is not limited to, any number and combination of a set of gauges, such as a speedometer, a fuel level, an oil pressure, a tachometer, an odometer, a turn indicator, a shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine fault lights, airbag (e.g., an auxiliary restraint system) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 830 and the dashboard 832. In at least one embodiment, the dashboard 832 may be included as part of the infotainment SoC 830, and vice versa.

[0208] In at least one embodiment, at least one component shown or described with respect to Figure 8C is used to implement the techniques and / or functions described in connection with Figure 1-5 In at least one embodiment, the techniques and / or functions described in connection with Figure 1-5 may receive signals from vehicle 800 for its autonomous operation and / or may be used to provide a remote operator with the ability to remotely control vehicle 800. In at least one embodiment, the techniques and / or functions described in connection with Figure 1-5 may perform one or more operations related to transmitting information to vehicle 800 (e.g., transmitting in a URLLC packet) (e.g., adjusting the SNR using the CQI estimate from vehicle 800 and / or selecting an MCS). In at least one embodiment, vehicle 800 is used to perform the techniques and / or functions described in connection with Figure 1 one or more UEs (e.g., UE 106) of a set of UEs 104 described with respect to

[0209] Fig.8D is, according to at least one embodiment, between a cloud-based server and Fig. 8AA diagram of a system 877 for communication between an autonomous vehicle 800 and other entities. In at least one embodiment, system 877 may include, but is not limited to, one or more servers 878, one or more networks 890, and any number and type of vehicles, including vehicle 800. One or more servers 878 may include, but are not limited to, multiple GPUs 884(A)-884(H) (collectively referred to herein as GPUs 884), PCIe switches 882(A)-882(D) (collectively referred to herein as PCIe switches 882), and / or CPUs 880(A)-880(B) (collectively referred to herein as CPUs 880). GPUs 884, CPUs 880, and PCIe switches 882 may be interconnected by high-speed connection lines, such as, but not limited to, the NVLink interface 888 developed by NVIDIA and / or PCIe connections 886. GPUs 884 are connected via NVLink and / or NVSwitchSoC, and GPUs 884 and PCIe switches 882 are interconnected via PCIe. In at least one embodiment, although eight GPUs 884, two CPUs 880, and four PCIe switches 882 are shown, this is not intended to be limiting. In at least one embodiment, each of one or more servers 878 may include, but is not limited to, any combination of any number of GPUs 884, CPUs 880, and / or PCIe switches 882. For example, in at least one embodiment, one or more servers 878 may each include eight, sixteen, thirty-two, and / or more GPUs 884.

[0210] In at least one embodiment, one or more servers 878 may receive image data representing an image from a vehicle via one or more networks 890, where the image shows an unexpected or changed road condition, such as recently started roadwork. In at least one embodiment, one or more servers 878 may transmit a neural network 892, an updated neural network 892, and / or map information 894, including but not limited to information about traffic and road conditions, to a vehicle via one or more networks 890. In at least one embodiment, an update to map information 894 may include, but is not limited to, an update to the HD map 822, such as information about construction sites, potholes, detours, floods, and / or other obstacles. In at least one embodiment, neural network 892, updated neural network 892, and / or map information 894 may be generated from new training and / or experiences represented in data received from any number of vehicles in the environment, and / or at least based on training performed in a data center (e.g., using one or more servers 878 and / or other servers).

[0211] In at least one embodiment, one or more servers 878 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by the vehicle and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., in cases where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., in cases where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 890), and / or the machine learning model may be used by one or more servers 878 to remotely monitor the vehicle.

[0212] In at least one embodiment, one or more servers 878 may receive data from the vehicle and apply the data to a state-of-the-art real-time neural network for real-time intelligent inference. In at least one embodiment, one or more servers 878 may include a deep learning supercomputer powered by one or more GPUs 884 and / or a dedicated AI computer, such as DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 878 may include a deep learning infrastructure of a data center powered by CPUs.

[0213] In at least one embodiment, the deep learning infrastructure of one or more servers 878 may be capable of performing fast, real-time inference and may use this ability to evaluate and verify the health of the processors, software, and / or associated hardware in vehicle 800. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 800, such as an image sequence and / or objects located in that image sequence by vehicle 800 (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them with the objects identified by vehicle 800, and if the results do not match and the deep learning infrastructure determines that the AI in vehicle 800 is malfunctioning, one or more servers 878 may send a signal to vehicle 800 to instruct the fail-safe computer in vehicle 800 to take control, notify the passengers, and complete a safe parking operation.

[0214] In at least one embodiment, one or more servers 878 may include one or more GPUs 884 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time responses. In at least one embodiment, for example, in cases where performance is less critical, servers driven by CPUs, FPGAs, and other processors can be used for inference.

[0215] Computer system

[0216] Fig. 9 is a block diagram showing an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system with interconnected devices and components, a system-on-chip (SOC), or some combination thereof formed with a processor that may include execution units to execute instructions. In at least one embodiment, according to the present disclosure, for example, the embodiments described herein, computer system 900 may include, but is not limited to, components such as a processor 902, whose execution units include logic to execute algorithms for processing data. In at least one embodiment, computer system 900 may include a processor, such as those available from Intel Corporation of Santa Clara, California processor family, Xeon TM 、 XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessors, although other systems (including PCs, engineering workstations, set-top boxes, etc. with other microprocessors) may also be used. In at least one embodiment, computer system 900 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0217] Embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, an embedded application can include a microcontroller, a digital signal processor (“DSP”), a system-on-chip, a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0218] In at least one embodiment, computer system 900 can include, but is not limited to, a processor 902, which can include, but is not limited to, one or more execution units 908 to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, system 900 is a single-processor desktop or server system, but in another embodiment, system 900 can be a multi-processor system. In at least one embodiment, processor 902 can include, but is not limited to, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 902 can be coupled to a processor bus 910, which can transfer data signals between processor 902 and other components in computer system 900.

[0219] In at least one embodiment, processor 902 can include, but is not limited to, a level 1 (“L1”) internal cache memory (“cache”) 904. In at least one embodiment, processor 902 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory can reside external to processor 902. Other embodiments can also include a combination of internal and external caches, depending on the particular implementation and requirements. In at least one embodiment, register file 906 can store different types of data in various registers, including, but not limited to, integer registers, floating-point registers, status registers, and instruction pointer registers.

[0220] In at least one embodiment, an execution unit 908, including but not limited to logic for performing integer and floating point operations, is also located in the processor 902. In at least one embodiment, the processor 902 may further include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 908 may include logic for processing a packed instruction set 909. In at least one embodiment, by including the packed instruction set 909 in the instruction set of a general-purpose processor, and the associated circuitry for the instructions to be executed, operations used by many multimedia applications can be performed using the packed data in the general-purpose processor 902. In one or more embodiments, operations can be performed on the packed data by using the full width of the data bus of the processor to accelerate and more efficiently execute many multimedia applications, which may not require transmitting smaller data units on the data bus of the processor to perform one or more operations on one data element at a time.

[0221] In at least one embodiment, the execution unit 908 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, the computer system 900 may include but not be limited to a memory 920. In at least one embodiment, the memory 920 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other storage devices. In at least one embodiment, the memory 920 may store instructions 919 and / or data 921 represented by data signals that can be executed by the processor 902.

[0222] In at least one embodiment, the system logic chip may be coupled to the processor bus 910 and the memory 920. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 916, and the processor 902 may communicate with the MCH 916 via the processor bus 910. In at least one embodiment, the MCH 916 may provide a high-bandwidth memory path 918 to the memory 920 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 916 may initiate data signals among the processor 902, the memory 920, and other components in the computer system 900, and bridge data signals among the processor bus 910, the memory 920, and the system I / O 922. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 916 may be coupled to the memory 920 via the high-bandwidth memory path 918, and the graphics / video card 912 may be coupled to the MCH 916 via an Accelerated Graphics Port (“AGP”) interconnect 914.

[0223] In at least one embodiment, the computer system 900 may use the system I / O 922, which is a proprietary hub interface bus, to couple the MCH 916 to an I / O controller hub (“ICH”) 930. In at least one embodiment, the ICH 930 may provide a direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 920, the chipset, and the processor 902. Examples may include, but are not limited to, an audio controller 929, a firmware hub (“Flash BIOS”) 928, a wireless transceiver 926, a data storage 924, a legacy I / O controller 923 that includes a user input and a keyboard interface, a serial expansion port 927 (such as a Universal Serial Bus (USB)), and a network controller 934. In at least one embodiment, the data storage 924 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash device, or other mass storage devices.

[0224] In at least one embodiment, Fig. 9 a system including interconnected hardware devices or “chips” is shown, while in other embodiments, Fig. 9 a system-on-chip (SoC) may be shown. In at least one embodiment, Fig. 9The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 900 are interconnected using Compute Express Link (CXL) interconnects.

[0225] In at least one embodiment, regarding Fig. 9 at least one of the components shown or described is used to implement the techniques and / or functions described in connection with Figure 1-5 In at least one embodiment, in at least one embodiment, regarding Fig. 9 one or more of the components shown or described include logic or otherwise operate to adjust one or more SNRs and / or SINRs by a variable amount based at least in part on an indication (e.g., consecutive ACKs) indicating whether a signal has been successfully interpreted, identifying and / or selecting an MCS and / or otherwise performing operations described in connection with Figure 1-5 In at least one embodiment, at least one of processor 902 and graphics card 912 is used to perform the generation of one or more offsets 136, the generation of one or more effective SNRs 138, the selection of packet MCS information 144, the generation of one or more indications of SNR 132, and / or one or more other aspects shown and / or described in connection with Figure 1-5 In at least one embodiment, at least one of processor 902 and graphics card 912 performs at least one aspect described regarding Figure 1 processor 118, accelerator 122, processor 124, SNR regulator 134, and / or MCS selector 140 of Figure 2 SNR regulation 200 of Figure 3 technique 300 of Figure 4 processor 402 of Figure 5 and / or at least one aspect described regarding one or more APIs 510 of

[0226] Fig.10 is a block diagram showing an electronic device 1000 for utilizing a processor 1010 according to at least one embodiment. In at least one embodiment, the electronic device 1000 can be, for example but not limited to, a laptop, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0227] In at least one embodiment, system 1000 may include, but is not limited to, a processor 1010 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1010 is coupled using a bus or interface, such as an I℃ bus, a system management bus (“SMBus”), a low pin count (LPC) bus, a serial peripheral interface (“SPI”), a high definition audio (“HDA”) bus, a serial advanced technology attachment (“SATA”) bus, a universal serial bus (“USB”) (versions 1, 2, 3, etc.), or a universal asynchronous receiver / transmitter (“UART”) bus. In at least one embodiment, Fig.10 a system is shown that includes interconnected hardware devices or “chips,” while in other embodiments, Fig.10 an exemplary system-on-chip (SoC) may be shown. In at least one embodiment, Fig.10 the devices shown therein may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Fig.10 one or more of the components of are interconnected using Compute Express Link (CXL) interconnects.

[0228] In at least one embodiment, Fig.10 it may include a display 1024, a touch screen 1025, a touch pad 1030, a near field communication unit (“NFC”) 1045, a sensor hub 1040, a thermal sensor 1039, an embedded controller (“EC”) 1035, a trusted platform module (“TPM”) 1038, a BIOS / firmware / flash (“BIOS, FW Flash”) 1022, a DSP 1060, a drive “SSD or HDD” 1020 (e.g., a solid state disk (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1050, a Bluetooth unit 1052, a wireless wide area network unit (“WWAN”) 1056, a global positioning system (GPS) 1055, a camera (“USB 3.0 camera”) 1054 (e.g., a USB 3.0 camera), or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1015 implemented in accordance with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0229] In at least one embodiment, other components may be communicatively coupled to the processor 1010 via the components described above. In at least one embodiment, the accelerometer 1041, the ambient light sensor ("ALS") 1042, the compass 1043, and the gyroscope 1044 may be communicatively coupled to the sensor hub 1040. In at least one embodiment, the thermal sensor 1039, the fan 1037, the keyboard 1036, and the touchpad 1030 may be communicatively coupled to the EC 1035. In at least one embodiment, the speaker 1063, the earphone 1064, and the microphone ("mic") 1065 may be communicatively coupled to the audio unit ("audio codec and class-D amplifier") 1064, which in turn may be communicatively coupled to the DSP 1060. In at least one embodiment, the audio unit 1064 may include, for example but not limited to, an audio encoder / decoder ("codec") and a class-D amplifier. In at least one embodiment, the SIM card ("SIM") 1057 may be communicatively coupled to the WWAN unit 1056. In at least one embodiment, components such as the WLAN unit 1050, the Bluetooth unit 1052, and the WWAN unit 1056 may be implemented in a next-generation form factor (NGFF).

[0230] In at least one embodiment, regarding Fig.10 at least one of the components shown or described is used to implement the techniques and / or functions associated with Figure 1-5 described. In at least one embodiment, in at least one embodiment, regarding Fig.10 one or more of the components shown or described include logic or otherwise are used to adjust one or more SNRs and / or SINRs by a variable amount based at least in part on the number of indications (e.g., consecutive ACKs) indicating whether a signal has been successfully interpreted, identifying and / or selecting an MCS and / or otherwise performing the operations associated with Figure 1-5 described. In at least one embodiment, the processor 1010 is used to perform the generation of one or more offsets 136, the generation of one or more effective SNRs 138, the selection of packet MCS information 144, the generation of one or more indications of SNR 132, and / or one or more other aspects shown and / or described in Figure 1-5 In at least one embodiment, the processor 1010 performs at least one aspect described regarding Figure 1 the processor 118, the accelerator 122, the processor 124, the SNR regulator 134, and / or the MCS selector 140 of Figure 2 the SNR adjustment 200 of Figure 3 the technique 300 of Figure 4 the processor 402 of Figure 5 and / or one or more APIs 510 of

[0231] Fig.11 FIG. 1100 illustrates a computer system 1100 according to at least one embodiment. In at least one embodiment, the computer system 1100 is configured to implement the various processes and methods described throughout this disclosure.

[0232] In at least one embodiment, the computer system 1100 includes, but is not limited to, at least one central processing unit (“CPU”) 1102 that is connected to a communication bus 1110 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1100 includes, but is not limited to, a main memory 1104 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data may be stored in the main memory 1104 in the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1122 provides an interface to other computing devices and networks for receiving data from and transmitting data to the computer system 1100.

[0233] In at least one embodiment, the computer system 1100 includes, but is not limited to, an input device 1108, a parallel processing system 1112, and a display device 1106, which may be implemented using a conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light emitting diode (“LED”), plasma display, or other suitable display technology. In at least one embodiment, user input is received from the input device 1108 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the foregoing modules may be located on a single semiconductor platform to form a processing system.

[0234] In at least one embodiment, with respect to Fig.11 at least one of the components shown or described is used to implement the techniques and / or functions described in connection with Figure 1-5 In at least one embodiment, in at least one embodiment, with respect to Fig.11 one or more of the components shown or described include logic or otherwise operate at least in part based on whether an indication signal has been successfully interpreted, recognized, and / or selected MCS and / or otherwise perform the operations described in connection with Figure 1-5The number of indications (e.g., continuous ACKs) of the described operations will adjust one or more SNRs and / or SINRs by a variable amount. In at least one embodiment, at least one of the parallel processing system 1112 and the CPU 1102 is used to perform the generation of one or more offsets 136, the generation of one or more effective SNRs 138, the selection of packet MCS information 144, the generation of one or more indications of SNR 132, and / or with respect to Figure 1-5 one or more of the other aspects shown and / or described in Figure 1 processor 118, accelerator 122, processor 124, SNR regulator 134, and / or MCS selector 140 of Figure 2 SNR adjustment 200 of Figure 3 technique 300 of Figure 4 processor 402 of Figure 5 and / or at least one aspect described by one or more APIs 510 of

[0235] Fig.12 FIG. 16 shows a computer system 1200 according to at least one embodiment. In at least one embodiment, the computer system 1200 includes, but is not limited to, a computer 1210 and a USB stick 1220. In at least one embodiment, the computer 1210 may include, but is not limited to, any number and type of processors (not shown) and memories (not shown). In at least one embodiment, the computer 1210 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0236] In at least one embodiment, the USB stick 1220 includes, but is not limited to, a processing unit 1230, a USB interface 1240, and USB interface logic 1250. In at least one embodiment, the processing unit 1230 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1230 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing core 1230 includes an application specific integrated circuit (“ASIC”) that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 1230 is a tensor processing unit (“TPC”) that is optimized to perform machine learning inference operations. In at least one embodiment, the processing core 1230 is a vision processing unit (“VPU”) that is optimized to perform machine vision and machine learning inference operations.

[0237] In at least one embodiment, the USB interface 1240 can be any type of USB connector or USB socket. For example, in at least one embodiment, the USB interface 1240 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, the USB interface 1240 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1250 can include any number and type of logic that enables the processing unit 1230 to connect to a device (such as computer 1210) via the USB connector 1240.

[0238] In at least one embodiment, regarding Fig.12 at least one of the components shown or described is used to implement the techniques and / or functions associated with Figure 1-5 the description. In at least one embodiment, in at least one embodiment, regarding Fig.12 one or more of the components shown or described include logic or otherwise are used to adjust one or more SNRs and / or SINRs by a variable amount based at least in part on the number of indications (such as consecutive ACKs) indicating whether a signal has been successfully interpreted, recognized, and / or selected for MCS and / or otherwise perform operations associated with Figure 1-5 the description. In at least one embodiment, computer 1210 is used to perform the generation of one or more offsets 136, the generation of one or more effective SNRs 138, the selection of packet MCS information 144, the generation of one or more indications of SNR 132, and / or one or more other aspects shown and / or described in Figure 1-5 In at least one embodiment, computer 1210 performs at least one aspect described regarding Figure 1 processor 118, accelerator 122, processor 124, SNR regulator 134, and / or MCS selector 140 of Figure 2 SNR regulation 200 of Figure 3 technique 300 of Figure 4 processor 402 of Figure 5 and / or one or more APIs 510 of

[0239] Fig.13A FIG. shows an exemplary architecture in which multiple GPUs 1310 - 1313 are communicatively coupled to multiple multi-core processors 1305 - 1306 via high-speed links 1340 - 1343 (such as buses / peer-to-peer interconnections, etc.). In one embodiment, the high-speed links 1340 - 1343 support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher. Various interconnection protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0240] In addition, in one embodiment, two or more GPUs 1310-1313 are interconnected by high-speed links 1329-1330, which may be implemented using the same or different protocols / links as those used for high-speed links 1340-1343. Similarly, two or more multi-core processors 1305-1306 may be connected by a high-speed link 1328, which may be a symmetric multi-processor (SMP) bus operating at a speed of 20 GB / s, 30 GB / s, 120 GB / s or higher. Alternatively, the same protocol / link (e.g., via a common interconnect structure) may be used to accomplish Fig.13A all communications between the various system components shown in

[0241] In one embodiment, each multi-core processor 1305-1306 is communicatively coupled to a processor memory 1301-1302 via a memory interconnect 1326-1327, respectively, and each GPU 1310-1313 is communicatively coupled to a GPU memory 1320-1323 via a GPU memory interconnect 1350-1353, respectively. The memory interconnects 1326-1327 and 1350-1353 may utilize the same or different memory access technologies. By way of example and not limitation, the processor memories 1301-1302 and the GPU memories 1320-1323 may be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories such as 3D XPoint or Nano-Ram. In one embodiment, some portions of the processor memories 1301-1302 may be volatile memories while other portions may be non-volatile memories (e.g., using a two-level memory (2LM) hierarchy).

[0242] As described herein, although the various processors 1305-1306 and GPUs 1310-1313 may be physically coupled to specific memories 1301-1302, 1320-1323, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as the "effective address" space) is distributed among the various physical memories. For example, each of the processor memories 1301-1302 may contain 64 GB of the system memory address space, and each of the GPU memories 1320-1323 may contain 32 GB of the system memory address space (resulting in a total addressable memory size of 256 GB in this example).

[0243] Fig. 13BAdditional details of the interconnection between the multi-core processor 1307 and the graphics acceleration module 1346 are shown according to an exemplary embodiment. The graphics acceleration module 1346 may include one or more GPU chips integrated on a line card that is coupled to the processor 1307 via a high-speed link 1340. Optionally, the graphics acceleration module 1346 may be integrated on the same package or chip as the processor 1307.

[0244] In at least one embodiment, the illustrated processor 1307 includes a plurality of cores 1360A - 1360D, each core having a translation lookaside buffer 1361A - 1361D and one or more caches 1362A - 1362D. In at least one embodiment, the cores 1360A - 1360D may include various other components (not shown) for executing instructions and processing data. In at least one embodiment, the caches 1362A - 1362D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1356 may be included in the caches 1362A - 1362D and shared by groups of cores 1360A - 1360D. For example, one embodiment of the processor 1307 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. The processor 1307 and the graphics acceleration module 1346 are connected to the system memory 1314, which may include Fig.13A processor memories 1301 - 1302 therein.

[0245] Coherence is maintained for data and instructions stored in the respective caches 1362A - 1362D, 1356, and the system memory 1314 through inter-core communication via the coherence bus 1364. For example, each cache may have cache coherence logic / circuit associated therewith to communicate via the coherence bus 1364 in response to detecting a read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via the coherence bus 1364 to snoop on cache accesses.

[0246] In one embodiment, the proxy circuit 1325 communicatively couples the graphics acceleration module 1346 to the coherence bus 1364, thereby allowing the graphics acceleration module 1346 to participate in the cache coherence protocol as a peer of the cores 1360A - 1360D. The interface 1335 provides a connection to the proxy circuit 1325 via the high-speed link 1340 (e.g., PCIe bus, NVLink, etc.), and the interface 1337 connects the graphics acceleration module 1346 to the link 1340.

[0247] In one implementation, the accelerator integrated circuit 1336 represents multiple graphics processing engines 1331, 1332, N of a graphics acceleration module and provides cache management, memory access, context management, and interrupt management services. The graphics processing engines 1331, 1332, N may each include a separate graphics processing unit (GPU). Optionally, the graphics processing engines 1331, 1332, N may alternatively include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1346 may be a GPU having multiple graphics processing engines 1331 - 1332, N, or the graphics processing engines 1331 - 1332, N may be individual GPUs integrated on a common package, line card, or chip.

[0248] In one embodiment, the accelerator integrated circuit 1336 includes a memory management unit (MMU) 1339 for performing various memory management functions, such as virtual - to - physical memory translation (also known as effective - to - real memory translation), and also includes a memory access protocol for accessing system memory 1314. The MMU 1339 may also include a translation lookaside buffer (“TLB”) (not shown) for caching virtual / effective - to - physical / real address translations. In one implementation, the cache 1338 may store commands and data for efficient access by the graphics processing engines 1331 - 1332, N. In at least one embodiment, the data stored in the cache 1338 and the graphics memories 1333 - 1334, M are kept consistent with the core caches 1362A - 1362D, 1356, and the system memory 1314. As previously described, this task may be accomplished via the proxy circuit 1325 representing the cache 1338 and the graphics memories 1333 - 1334, M (e.g., sending updates related to modifications / accesses of cache lines on the processor caches 1362A - 1362D, 1356 to the cache 1338 and receiving updates from the cache 1338).

[0249] A set of registers 1345 stores context data of threads executed by the graphics processing engines 1331, 1332, N, and a context management circuit 1348 manages thread contexts. For example, the context management circuit 1348 can perform save and restore operations to save and restore the contexts of individual threads during a context switch (e.g., where the first thread is saved and the second thread is stored so that the second thread can be executed by the graphics processing engine). For example, the context management circuit 1348 can store the current register values to a specified area in memory (e.g., identified by a context pointer) during a context switch. Then, the register values can be restored when the context is returned. In one embodiment, an interrupt management circuit 1347 receives and processes interrupts received from system devices.

[0250] In one implementation, the MMU 1339 converts virtual / valid addresses from the graphics processing engine 1331 to real / physical addresses in the system memory 1314. One embodiment of the accelerator integrated circuit 1336 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1346 and / or other accelerator devices. The graphics accelerator module 1346 can be dedicated to a single application executed on the processor 1307, or can be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented where the resources of the graphics processing engines 1331 - 1332, N are shared among multiple applications or virtual machines (VMs). In at least one embodiment, resources can be subdivided into "slices" based on processing requirements and priorities associated with the VMs and / or applications, and these slices are allocated to different VMs and / or applications.

[0251] In at least one embodiment, the accelerator integrated circuit 1336 acts as a bridge for the system of the graphics accelerator modules 1346 and provides address translation and system memory cache services. Additionally, the accelerator integrated circuit 1336 can provide virtualization facilities for the host processor to manage the virtualization, interrupts, and memory management of the graphics processing engines 1331 - 1332.

[0252] Since the hardware resources of the graphics processing engines 1331 - 1332, N are explicitly mapped to the real address space seen by the host processor 1307, any host processor can directly address these resources using valid address values. In at least one embodiment, one function of the accelerator integrated circuit 1336 is to physically isolate the graphics processing engines 1331 - 1332, N such that they appear as independent units to the system.

[0253] In at least one embodiment, one or more graphics memories 1333 - 1334,M are respectively coupled to each graphics processing engine 1331 - 1332,N. The graphics memories 1333 - 1334,M store instructions and data that are processed by each graphics processing engine 1331 - 1332,N. The graphics memories 1333 - 1334,M can be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6) or HBM, and / or can be non - volatile memories such as 3D XPoint or Nano - Ram.

[0254] In one embodiment, to reduce data traffic on the link 1340, a biasing technique can be used to ensure that the data stored in the graphics memories 1333 - 1334,M is the data most frequently used by the graphics processing engines 1331 - 1332,N and preferably not used (or at least not frequently used) by the cores 1360A - 1360D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep the data required by the cores (and preferably not the graphics processing engines 1331 - 1332,N) in the caches 1362A - 1362D, 1356 of the cores and the system memory 1314.

[0255] Fig. 13C Another exemplary embodiment is shown where the accelerator integrated circuit 1336 is integrated within the processor 1307. In this embodiment, the graphics processing engines 1331 - 1332,N communicate directly with the accelerator integrated circuit 1336 via the interface 1337 and the interface 1335 (which can also utilize any form of bus or interface protocol) over the high - speed link 1340. The accelerator integrated circuit 1336 can perform the same operations as described with respect to Fig. 13B However, due to its close proximity to the coherence bus 1364 and the caches 1362A - 1362D, 1356, it may have higher throughput. One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which can include a programming model controlled by the accelerator integrated circuit 1336 and a programming model controlled by the graphics acceleration module 1346.

[0256] In at least one embodiment, the graphics processing engines 1331 - 1332,N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel requests from other applications to the graphics processing engines 1331 - 1332,N, thereby providing virtualization within a VM / partition.

[0257] In at least one embodiment, the graphics processing engines 1331-1332,N can be shared by multiple VM / application partitions. In at least one embodiment, a shared model can use a hypervisor to virtualize the graphics processing engines 1331-1332,N to allow each operating system to access them. For a single partition system without a hypervisor, the operating system owns the graphics processing engines 1331-1332,N. In at least one embodiment, the operating system can virtualize the graphics processing engines 1331-1332,N to provide access to each process or application.

[0258] In at least one embodiment, the graphics acceleration module 1346 or individual graphics processing engines 1331-1332,N use a process handle to select process elements. In one embodiment, the process elements are stored in the system memory 1314 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engines 1331-1332,N (i.e., calling system software to add a process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the process element linked list.

[0259] Fig.13D An exemplary accelerator integration slice 1390 is shown. As used herein, "slice" includes a designated portion of the processing resources of the accelerator integrated circuit 1336. An application is an effective address space 1382 in the system memory 1314 that stores process elements 1383. In one embodiment, the process elements 1383 are stored in response to a GPU call 1381 from an application 1380 executing on the processor 1307. The process element 1383 contains the process state of the corresponding application 1380. The work descriptor (WD) 1384 contained in the process element 1383 can be a single job requested by the application or can contain a pointer to a job queue. In at least one embodiment, the WD 1384 is a pointer to a job request queue in the address space 1382 of the application.

[0260] The graphics acceleration module 1346 and / or individual graphics processing engines 1331-1332,N can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure can be included for setting the process state and sending the WD 1384 to the graphics acceleration module 1346 to start a job in a virtualized environment.

[0261] In at least one embodiment, the dedicated process programming model is implementation - specific. In this model, a single process owns the graphics acceleration module 1346 or an individual graphics processing engine 1331. Since when the graphics acceleration module 1346 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, when the graphics acceleration module 1346 is assigned, the operating system initializes the accelerator integrated circuit 1336 for the owned process.

[0262] In operation, the WD fetch unit 1391 in the accelerator integration slice 1390 fetches the next WD 1384, which includes an indication of work to be completed by one or more graphics processing engines of the graphics acceleration module 1346. Data from the WD 1384 can be stored in the register 1345 and used by the MMU 1339, the interrupt management circuit 1347, and / or the context management circuit 1348, as shown. For example, one embodiment of the MMU 1339 includes a segment / page walk circuit for accessing the segment / page table 1386 within the OS virtual address space 1385. The interrupt management circuit 1347 can process the interrupt event 1392 received from the graphics acceleration module 1346. When performing a graphics operation, the effective address 1393 generated by the graphics processing engines 1331 - 1332,N is translated to a real address by the MMU1339.

[0263] In one embodiment, the same set of registers 1345 is replicated for each graphics processing engine 1331 - 1332,N and / or the graphics acceleration module 1346, and the registers 1345 can be initialized by the hypervisor or the operating system. Each of these replicated registers can be included in the accelerator integration slice 1390. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0264]

[0265] Exemplary registers that can be initialized by the operating system are shown in Table 2.

[0266]

[0267] In one embodiment, each WD 1384 is specific to a particular graphics acceleration module 1346 and / or graphics processing engine 1331 - 1332,N. It contains all the information required for the graphics processing engines 1331 - 1332,N to complete the work, or it can be a pointer to a memory location where the application has set up a command queue of work to be completed.

[0268] Fig.13EAdditional details of an exemplary embodiment of the shared model are shown. The embodiment includes a hypervisor real address space 1398 in which a list of process elements 1399 is stored. The hypervisor real address space 1398 can be accessed via a hypervisor 1396 that virtualizes a graphics acceleration module engine for an operating system 1395.

[0269] In at least one embodiment, the shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 1346. There are two programming models in which the graphics acceleration module 1346 is shared by multiple processes and partitions: time slice sharing and graphics directed sharing.

[0270] In this model, the system hypervisor 1396 owns the graphics acceleration module 1346 and makes its functionality available to all operating systems 1395. For the graphics acceleration module 1346 to support virtualization through the system hypervisor 1396, the graphics acceleration module 1346 can comply with the following: (1) the job requests of the application must be autonomous (i.e., do not need to maintain state between jobs), or the graphics acceleration module 1346 must provide a context save and restore mechanism, (2) the graphics acceleration module 1346 guarantees that the job requests of the application are completed within a specified amount of time, including any translation errors, or the graphics acceleration module 1346 provides the ability to preempt job processing, (3) fairness between the processes of the graphics acceleration module 1346 must be ensured when operating in the directed sharing programming model.

[0271] In at least one embodiment, the application 1380 is required to use the type of the graphics acceleration module 1346, a work descriptor (WD), a privilege mask register (AMR) value, and a context save / restore area pointer (CSRP) for making system calls to the operating system 1395. In at least one embodiment, the type of the graphics acceleration module 1346 describes the target acceleration function for the system call. In at least one embodiment, the type of the graphics acceleration module 1346 can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1346 and can take the form of a graphics acceleration module 1346 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure that describes the work to be done by the graphics acceleration module 1346. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that sets the AMR. If the implementation of the accelerator integrated circuit 1336 and the graphics acceleration module 1346 does not support the user privilege mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 1396 can selectively apply the current privilege mask override register (AMOR) value before placing the AMR in the process element 1383. In at least one embodiment, the CSRP is one of the registers 1345 that contains the valid address of a region in the address space 1382 of the application for the graphics acceleration module 1346 to save and restore the context state. This pointer is optional if it is not necessary to save the state between jobs or when the job is preempted. In at least one embodiment, the context save / restore area can be a fixed system memory.

[0272] Upon receiving a system call, the operating system 1395 can verify that the application 1380 has been registered and is granted the privilege to use the graphics acceleration module 1346. Then, the operating system 1395 uses

[0273] the information shown in Table 3 to call the hypervisor 1396.

[0274]

[0275]

[0276] Upon receiving a hypervisor call, the hypervisor 1396 verifies that the operating system 1395 has been registered and is granted the privilege to use the graphics acceleration module 1346. Then, the hypervisor 1396 places the process element 1383 into the process element linked list of the corresponding type of the graphics acceleration module 1346. The process element can include the information shown in Table 4.

[0277]

[0278] In at least one embodiment, the hypervisor initializes multiple accelerator integrated slice 1390 registers 1345.

[0279] As Fig.13F shown, in at least one embodiment, a unified memory is used, and the unified memory can be addressed via a common virtual memory address space for accessing the physical processor memories 1301-1302 and the GPU memories 1320-1323. In this implementation, operations executed on the GPUs 1310-1313 utilize the same virtual / effective memory address space to access the processor memories 1301-1302, and vice versa, thus simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to the processor memory 1301, a second portion is allocated to the second processor memory 1302, a third portion is allocated to the GPU memory 1320, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of the processor memories 1301-1302 and the GPU memories 1320-1323, thereby allowing any processor or GPU to access the memory using a virtual address mapped to any physical memory.

[0280] In one embodiment, the bias / coherency management circuits 1394A-1394E within one or more MMUs 1339A-1339E ensure cache coherency between one or more host processors (e.g., 1305) and the caches of the GPUs 1310-1313, and implement a bias technique for the physical memory indicating where certain types of data should be stored. Although multiple instances of the bias / coherency management circuits 1394A-1394E are shown Fig.13F in, the bias / coherency circuits can be implemented within the MMU of one or more host processors 1305 and / or within the accelerator integrated circuit 1336.

[0281] One embodiment allows the GPU-attached memories 1320 - 1323 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) techniques without suffering the performance penalties associated with full system cache coherence. In at least one embodiment, the ability to access the GPU-attached memories 1320 - 1323 as system memory without heavy cache coherence overhead provides a favorable operating environment for GPU offloading. This arrangement allows the software of the host processor 1305 to set operands and access computed results without the overhead of traditional I / O DMA data copies. Such traditional copies include driver calls, interrupts, and memory mapped I / O (MMIO) accesses, which are all less efficient than simple memory accesses. In at least one embodiment, the ability to access the GPU-attached memories 1320 - 1323 without cache coherence overhead can be critical to the execution time of offloaded computations. For example, in the presence of a large amount of streaming write memory traffic, the cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPUs 1310 - 1313. In at least one embodiment, the efficiency of operand setting, result access, and GPU computation can play a role in determining the effectiveness of GPU offloading.

[0282] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page granularity structure (e.g., controlled at the granularity of memory pages), and this page granularity structure includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, with or without a bias cache in the GPUs 1310 - 1313 (e.g., for caching frequently / recently used entries of the bias table), the bias table can be implemented in the stolen memory ranges of one or more of the GPU-attached memories 1320 - 1323. Alternatively, the entire bias table can be maintained within the GPU.

[0283] In at least one embodiment, before actually accessing the GPU memory, the bias table entry associated with each access to the GPU attached memories 1320-1323 is accessed, thereby causing the following operations. First, local requests from the GPUs 1310-1313 that find their pages in the GPU bias are directly forwarded to the corresponding GPU memories 1320-1323. Local requests from the GPUs that find their pages in the host bias are forwarded to the processor 1305 (e.g., via the high-speed link as described above). In one embodiment, requests from the processor 1305 that find the requested page in the host processor bias complete requests similar to normal memory reads. Alternatively, requests that point to GPU bias pages can be forwarded to the GPUs 1310-1313. In at least one embodiment, if the GPU is not currently using a page, the GPU can subsequently migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed by a software-based mechanism, a software mechanism with hardware assistance, or in limited cases by a purely hardware-based mechanism.

[0284] A mechanism for changing the bias state employs an API call (e.g., OpenCL), which subsequently calls the device driver of the GPU. The device driver then sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and perform a cache flush operation in the host in certain migrations. In at least one embodiment, the cache flush operation is used for migrations from the host processor 1305 bias to the GPU bias, but not for the reverse migration.

[0285] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that cannot be cached by the host processor 1305. To access these pages, the processor 1305 can request access from the GPU 1310, and the GPU 1310 may or may not immediately grant access. Therefore, to reduce the communication between the processor 1305 and the GPU 1310, it is beneficial to ensure that the GPU bias pages are pages required by the GPU rather than the host processor 1305, and vice versa.

[0286] Fig.14 An exemplary integrated circuit and associated graphics processor in accordance with various embodiments described herein are shown, which can be fabricated using one or more IP cores. In addition to the illustration, in at least one embodiment, other logic and circuitry can be included, including additional graphics processors / cores, peripheral interface controllers, or general processor cores.

[0287] Fig.14is a block diagram showing an exemplary system on a chip integrated circuit 1400 that can be fabricated using one or more IP cores. In at least one embodiment, integrated circuit 1400 includes one or more application processors 1405 (e.g., CPUs), at least one graphics processor 1410, and may additionally include an image processor 1415 and / or a video processor 1420, any of which may be a modular IP core. In at least one embodiment, integrated circuit 1400 includes peripheral or bus logic, which includes a USB controller 1425, a UART controller 1430, an SPI / SDIO controller 1435, and an I²S / I²C controller 1440. In at least one embodiment, integrated circuit 1400 may include a display device 1445 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1450 and a mobile industry processor interface (MIPI) display interface 1455. In at least one embodiment, storage may be provided by a flash memory subsystem 1460, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1465 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1470.

[0288] In at least one embodiment, regarding Fig.14 at least one of the components shown or described is used to implement the techniques and / or functions associated with Figure 1-5 described. In at least one embodiment, in at least one embodiment, regarding Fig.14 one or more of the components shown or described includes logic or otherwise is used to at least partially adjust one or more SNRs and / or SINRs by a variable amount based on the number of indications (e.g., consecutive ACKs) indicating whether a signal has been successfully interpreted, recognized, and / or selected for MCS and / or otherwise perform the operations associated with Figure 1-5 described. In at least one embodiment, the graphics processor 1410 is used to perform the generation of one or more offsets 136, the generation of one or more effective SNRs 138, the selection of packet MCS information 144, the generation of one or more indications of SNR 132, and / or one or more other aspects shown and / or described in Figure 1-5 In at least one embodiment, the graphics processor 1410 regarding Figure 1 processor 118, accelerator 122, processor 124, SNR regulator 134, and / or MCS selector 140 of Figure 2 SNR adjustment 200 of Figure 3 technique 300 of Figure 4 processor 402 of Figure 5 at least one aspect described by one or more of the APIs 510.

[0289] Figure 15A-15B An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which may be fabricated using one or more IP cores. In addition to the illustration, in at least one embodiment, other logic and circuitry may be included, including additional graphics processor(s) / core(s), peripheral interface controllers, or general-purpose processor cores.

[0290] Figure 15A-15B is a block diagram showing an exemplary graphics processor used within a SoC according to an embodiment described herein. Fig.15A An exemplary graphics processor 1510 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores is shown according to at least one embodiment. Fig. 15B Another exemplary graphics processor 1540 of a system-on-chip integrated circuit is shown according to at least one embodiment, which may be fabricated using one or more IP cores. In at least one embodiment, Fig.15A the graphics processor 1510 is a low-power graphics processor core. In at least one embodiment, Fig. 15B the graphics processor 1540 is a higher-performance graphics processor core. In at least one embodiment, each of the graphics processors 1510, 1540 may be Fig.14 a variant of the graphics processor 1410.

[0291] In at least one embodiment, the graphics processor 1510 includes a vertex processor 1505 and one or more fragment processors 1515A - 1515N (e.g., 1515A, 1515B, 1515C, 1515D to 1515N - 1, and 1515N). In at least one embodiment, the graphics processor 1510 may execute different shader programs via separate logic such that the vertex processor 1505 is optimized to execute operations for vertex shader programs, while the one or more fragment processors 1515A - 1515N perform fragment (e.g., pixel) shading operations for fragment or pixel or shader programs. In at least one embodiment, the vertex processor 1505 executes the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1515A - 1515N generate a frame buffer for display on a display device using the primitives and vertex data generated by the vertex processor 1505. In at least one embodiment, the one or more fragment processors 1515A - 1515N are optimized to execute fragment shader programs as provided in the OpenGL API, which may be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0292] In at least one embodiment, the graphics processor 1510 additionally includes one or more memory management units (MMUs) 1520A-1520B, one or more caches 1525A-1525B, and one or more circuit interconnects 1530A-1530B. In at least one embodiment, one or more MMUs 1520A-1520B provide virtual-to-physical address mapping for the graphics processor 1510, including for the vertex processor 1505 and / or fragment processors 1515A-1515N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1525A-1525B. In at least one embodiment, one or more MMUs 1520A-1520B may be synchronized with other MMUs within the system, including one or more MMUs associated with one or more application processors 1405, image processors 1415, and / or video processors 1420 of Fig.14 such that each processor 1405-1420 may participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1530A-1530B enable the graphics processor 1510 to connect to other IP cores within the SoC via the internal bus of the SoC or via a direct connection.

[0293] In at least one embodiment, the graphics processor 1540 includes Fig.15A one or more MMUs 1520A-1520B, caches 1525A-1525B, and circuit interconnects 1530A-1530B of the graphics processor 1510 of

[0294] In at least one embodiment, with respect to Fig.15A and Fig. 15B at least one of the components shown or described is used to implement the techniques and / or functions associated with Figure 1-5 described. In at least one embodiment, in at least one embodiment, with respect to Fig.15A and / or Fig. 15B one or more of the components shown or described include logic or otherwise are used to adjust one or more SNRs and / or SINRs by a variable amount based at least in part on the number of indications (e.g., consecutive ACKs) indicating whether a signal is successfully interpreted, identifying and / or selecting an MCS and / or otherwise performing the operations associated with Figure 1-5 described. In at least one embodiment, the graphics processor 1510 is used to perform the generation of one or more offsets 136, the generation of one or more effective SNRs 138, the selection of packet MCS information 144, the generation of one or more indications of SNR 132, and / or one or more other aspects shown and / or described with respect to Figure 1-5 . In at least one embodiment, the graphics processor 1510 performs at least one aspect described with respect to Figure 1 processor 118, accelerator 122, processor 124, SNR regulator 134, and / or MCS selector 140 of Figure 2 SNR regulation 200 of Figure 3 technique 300 of Figure 4 processor 402 of Figure 5 and / or one or more APIs 510 of

[0295] Figure 16A-16B shows additional exemplary graphics processor logic according to embodiments described herein. In at least one embodiment, Fig.16A shows a graphics core 1600 that may be included within Fig.14 graphics processor 1410, and in at least one embodiment, it may be a unified shader core 1555A - 1555N as shown in Fig. 15B . Fig. 16B shows a highly parallel general - purpose graphics processing unit 1630 suitable for deployment on a multi - chip module in at least one embodiment.

[0296] In at least one embodiment, the graphics core 1600 includes a shared instruction cache 1602, texture units 1618, and cache / shared memory 1620, which are common to the execution resources within the graphics core 1600. In at least one embodiment, the graphics core 1600 may include multiple slices 1601A - 1601N or partitions per core, and the graphics processor may include multiple instances of the graphics core 1600. The slices 1601A - 1601N may include support logic, which includes local instruction caches 1604A - 1604N, thread schedulers 1606A - 1606N, thread dispatchers 1608A - 1608N, and a set of registers 1610A - 1610N. In at least one embodiment, the slices 1601A - 1601N may include a set of additional functional units (AFU 1612A - 1612N), floating - point units (FPU 1614A - 1614N), integer arithmetic logic units (ALU 1616A - 1616N), address calculation units (ACU 1613A - 1613N), double - precision floating - point units (DPFPU 1615A - 1615N), and matrix processing units (MPU 1617A - 1617N).

[0297] In at least one embodiment, the FPU 1614A - 1614N can perform single - precision (32 - bit) and half - precision (16 - bit) floating - point operations, while the DPFPU 1615A - 1615N performs double - precision (64 - bit) floating - point operations. In at least one embodiment, the ALU 1616A - 1616N can perform variable - precision integer operations at 8 - bit, 16 - bit, and 32 - bit precisions and can be configured for mixed - precision operations. In at least one embodiment, the MPU 1617A - 1617N can also be configured for mixed - precision matrix operations, including half - precision floating - point operations and 8 - bit integer operations. In at least one embodiment, the MPU 1617 - 1617N can perform various matrix operations to accelerate machine - learning application frameworks, including enabling support for accelerated general matrix - to - matrix multiplication (GEMM). In at least one embodiment, the AFU 1612A - 1612N can perform additional logical operations not supported by the floating - point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0298] Regarding Fig.16A at least one of the components shown or described is used to implement the techniques and / or functions associated with Figure 1-5 described. In at least one embodiment, in at least one embodiment, regarding Fig.16A one or more of the components shown or described include logic or otherwise operate at least in part based on whether an indication signal is successfully interpreted, identify, and / or select MCS and / or otherwise perform operations associated with Figure 1-5The number of indications of the described operations (e.g., consecutive ACKs) will adjust one or more SNRs and / or SINRs by a variable amount. In at least one embodiment, at least one graphics processor 1600 is used to perform the generation of one or more offsets 136, the generation of one or more effective SNRs 138, the selection of packet MCS information 144, the generation of one or more indications of SNR 132, and / or with respect to Figure 1-5 one or more of the other aspects shown and / or described in Figure 1 processor 118, accelerator 122, processor 124, SNR regulator 134, and / or MCS selector 140 of Figure 2 SNR adjustment 200 of Figure 3 technique 300 of Figure 4 processor 402 of Figure 5 and / or at least one aspect described by one or more APIs 510 of

[0299] Fig. 16B Figure 16 shows a general purpose graphics processing unit (GPGPU) 1630 in at least one embodiment, which can be configured to enable highly parallel computing operations to be performed by a set of graphics processing units. In at least one embodiment, GPGPU 1630 can be directly linked to other instances of GPGPU 1630 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 1630 includes a host interface 1632 to enable connection to a host processor. In at least one embodiment, host interface 1632 is a PCI Express interface. In at least one embodiment, host interface 1632 can be a vendor-specific communication interface or communication fabric. In at least one embodiment, GPGPU 1630 receives commands from the host processor and uses a global scheduler 1634 to assign execution threads associated with those commands to a set of compute clusters 1636A-1636H. In at least one embodiment, compute clusters 1636A-1636H share a cache memory 1638. In at least one embodiment, cache memory 1638 can be used as a higher-level cache for the cache memories within compute clusters 1636A-1636H.

[0300] In at least one embodiment, the GPGPU 1630 includes memories 1644A - 1644B, which are coupled to the compute clusters 1636A - 1636H via a set of memory controllers 1642A - 1642B. In at least one embodiment, the memories 1644A - 1644B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0301] In at least one embodiment, each of the compute clusters 1636A - 1636H includes a set of graphics cores, such as Fig.16A the graphics core 1600, which may include various types of integer and floating - point logic units that can perform computational operations across various precision ranges of a computer, including precisions suitable for machine - learning computations. For example, in at least one embodiment, at least one subset of the floating - point units in each of the compute clusters 1636A - 1636H may be configured to perform 16 - bit or 32 - bit floating - point operations, while different subsets of the floating - point units may be configured to perform 64 - bit floating - point operations.

[0302] In at least one embodiment, multiple instances of the GPGPU 1630 may be configured to act as compute clusters. In at least one embodiment, the communication for synchronization and data exchange among the compute clusters 1636A - 1636H varies between embodiments. In at least one embodiment, multiple instances of the GPGPU 1630 communicate via the host interface 1632. In at least one embodiment, the GPGPU 1630 includes an I / O hub 1639 that couples the GPGPU 1630 to the GPU link 1640, enabling direct connection to other instances of the GPGPU 1630. In at least one embodiment, the GPU link 1640 is coupled to a dedicated GPU - to - GPU bridge that enables communication and synchronization among multiple instances of the GPGPU 1630. In at least one embodiment, the GPU link 1640 is coupled to a high - speed interconnect to send and receive data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of the GPGPU 1630 are located in separate data - processing systems and communicate via network devices accessible through the host interface 1632. In at least one embodiment, the GPU link 1640 may be configured to enable connection to a processor other than or in place of the host interface 1632.

[0303] In at least one embodiment, the GPGPU 1630 can be configured to train a neural network. In at least one embodiment, the GPGPU 1630 can be used within an inference platform. In at least one embodiment, in the case where the GPGPU 1630 is used for inference, the GPGPU can include fewer compute clusters 1636A - 1636H as compared to when using the GPGPU to train a neural network. In at least one embodiment, the memory technology associated with memories 1644A - 1644B can differ between inference and training configurations, with higher bandwidth memory technology dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1630 can support inference - specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8 - bit integer dot - product instructions that can be used during the inference operation of a deployed neural network.

[0304] In at least one embodiment, regarding Fig. 16B at least one of the components shown or described is used to implement the techniques and / or functions associated with Figure 1-5 described. In at least one embodiment, in at least one embodiment, regarding Fig. 16B one or more of the components shown or described include logic or otherwise are used to at least partially regulate one or more SNRs and / or SINRs by a variable amount based on the number of indications (e.g., consecutive ACKs) indicating whether a signal has been successfully interpreted, identified, and / or selected MCS and / or otherwise perform operations associated with Figure 1-5 described. In at least one embodiment, at least one GPGPU 1630 is used to perform the generation of one or more offsets 136, the generation of one or more valid SNRs 138, the selection of packet MCS information 144, the generation of one or more indications of SNR 132, and / or one or more other aspects shown and / or described in Figure 1-5 . In at least one embodiment, at least one GPGPU1630 performs at least one aspect described regarding Figure 1 processor 118, accelerator 122, processor 124, SNR regulator 134, and / or MCS selector 140 of Figure 2 SNR regulation 200 of Figure 3 technique 300 of Figure 4 processor 402 of Figure 5 and / or one or more APIs 510 of

[0305] Fig.17FIG. shows a block diagram of a computer system 1700 in accordance with at least one embodiment. In at least one embodiment, the computer system 1700 includes a processing subsystem 1701 having one or more processors 1702 and a system memory 1704, and the system memory 1704 communicates via an interconnect path that may include a memory hub 1705. In at least one embodiment, the memory hub 1705 may be a separate component within a chipset component or may be integrated within one or more processors 1702. In at least one embodiment, the memory hub 1705 is coupled to an I / O subsystem 1711 via a communication link 1706. In one embodiment, the I / O subsystem 1711 includes an I / O hub 1707, and the I / O hub may enable the computer system 1700 to receive input from one or more input devices 1708. In at least one embodiment, the I / O hub 1707 may enable a display controller to provide output to one or more display devices 1710A, and the display controller may be included within one or more processors 1702. In at least one embodiment, one or more display devices 1710A coupled to the I / O hub 1707 may include a local, internal, or embedded display device.

[0306] In at least one embodiment, the processing subsystem 1701 includes one or more parallel processors 1712 coupled to the memory hub 1705 via a bus or other communication link 1713. In at least one embodiment, the communication link 1713 may be any one of a number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or communication fabric. In at least one embodiment, one or more parallel processors 1712 form a parallel or vector processing system in a computing concentration, and the system may include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, one or more parallel processors 1712 form a graphics processing subsystem, and the graphics processing subsystem may output pixels to one of one or more display devices 1710A coupled via the I / O hub 1707. In at least one embodiment, one or more parallel processors 1712 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1710B.

[0307] In at least one embodiment, the system storage unit 1714 may be connected to the I / O hub 1707 to provide a storage mechanism for the computer system 1700. In at least one embodiment, the I / O switch 1716 may be used to provide an interface mechanism to enable connections between the I / O hub 1707 and other components, such as a network adapter 1718 and / or a wireless network adapter 1717 that may be integrated into the platform, and various other devices that may be added via one or more additional devices 1720. In at least one embodiment, the network adapter 1718 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1719 may include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more radio devices.

[0308] In at least one embodiment, the computer system 1700 may include other components not explicitly shown, such as USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 1707. In at least one embodiment, any suitable protocol (such as a PCI (Peripheral Component Interconnect)-based protocol (such as PCI-Express) or other bus or point-to-point communication interface and / or protocol) may be used to implement the communication paths between the various components, such as NV-Link high-speed interconnect or interconnect protocol. Fig.17 among the various components.

[0309] In at least one embodiment, one or more parallel processors 1712 include circuitry optimized for graphics and video processing, which includes, for example, video output circuitry and constitutes a Graphics Processing Unit (GPU). In at least one embodiment, one or more parallel processors 1712 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of the computer system 1700 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1712, the memory hub 1705, the processor 1702, and the I / O hub 1707 may be integrated into a System-on-Chip (SoC) integrated circuit. In at least one embodiment, the components of the computer system 1700 may be integrated into a single package to form a System-in-Package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computer system 1700 may be integrated into a Multi-Chip Module (MCM), which may be interconnected with other multi-chip modules into a modular computer system.

[0310] In at least one embodiment, with respect to Fig.17 at least one of the components shown or described is used to implement in connection with Figure 1-5 The described techniques and / or functions. In at least one embodiment, in at least one embodiment, regarding Fig.17 One or more components shown or described include logic or otherwise for at least partially based on whether an indication signal is successfully interpreted, identifying and / or selecting MCS and / or otherwise performing operations in connection with Figure 1-5 The number of indications (e.g., consecutive ACKs) described will adjust one or more SNR and / or SINR by a variable amount. In at least one embodiment, at least one of processor 1702 and parallel processor 1712 is used to perform the generation of one or more offsets 136, the generation of one or more effective SNR 138, the selection of packet MCS information 144, the generation of one or more indications of SNR 132, and / or regarding Figure 1-5 One or more other aspects shown and / or described in Figure 1 Processor 118, accelerator 122, processor 124, SNR regulator 134, and / or MCS selector 140 of Figure 2 SNR adjustment 200 of Figure 3 Technique 300 of Figure 4 Processor 402 of Figure 5 At least one aspect described by one or more APIs 510 of

[0311] Processor

[0312] Fig.18A Shows a parallel processor 1800 according to at least one embodiment. In at least one embodiment, various components of the parallel processor 1800 can be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). In at least one embodiment, the shown parallel processor 1800 is a variant of Fig.17 One or more of the shown parallel processors 1712 according to an exemplary embodiment.

[0313] In at least one embodiment, the parallel processor 1800 includes a parallel processing unit 1802. In at least one embodiment, the parallel processing unit 1802 includes an I / O unit 1804 that enables communication with other devices, including other instances of the parallel processing unit 1802. In at least one embodiment, the I / O unit 1804 can be directly connected to other devices. In at least one embodiment, the I / O unit 1804 is connected to other devices by using a hub or switch interface (e.g., memory hub 1805). In at least one embodiment, the connection between the memory hub 1805 and the I / O unit 1804 forms a communication link. In at least one embodiment, the I / O unit 1804 is connected to a host interface 1806 and a memory crossbar 1816, where the host interface 1806 receives commands for performing processing operations and the memory crossbar 1816 receives commands for performing memory operations.

[0314] In at least one embodiment, when the host interface 1806 receives a command buffer via the I / O unit 1804, the host interface 1806 can direct the work operations to execute those commands to the front end 1808. In at least one embodiment, the front end 1808 is coupled to a scheduler 1810 configured to allocate commands or other work items to an array of processing clusters 1812. In at least one embodiment, the scheduler 1810 ensures that the array of processing clusters 1812 is properly configured and in an active state before tasks are assigned to it. In at least one embodiment, the scheduler 1810 is implemented by firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1810 can be configured to perform complex scheduling and work distribution operations at both coarse-grained and fine-grained levels, enabling fast preemption and context switching of threads executing on the processing array 1812. In at least one embodiment, the host software can attest to the workload for scheduling on the processing array 1812 via one of a plurality of graphics processing doorbells. In at least one embodiment, the workload can then be automatically allocated on the processing array 1812 by the scheduler 1810 logic within the microcontroller including the scheduler 1810.

[0315] In at least one embodiment, the processing cluster array 1812 may include up to "N" processing clusters (e.g., cluster 1814A, cluster 1814B to cluster 1814N). In at least one embodiment, each of the clusters 1814A - 1814N of the processing cluster array 1812 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 1810 may use various scheduling and / or work assignment algorithms to assign work to the clusters 1814A - 1814N of the processing cluster array 1812, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, the scheduling may be handled dynamically by the scheduler 1810, or may be assisted in part by compiler logic during the compilation of the program logic configured to be executed by the processing cluster array 1812. In at least one embodiment, different ones of the clusters 1814A - 1814N of the processing cluster array 1812 may be assigned to process different types of programs or to perform different types of computations.

[0316] In at least one embodiment, the processing cluster array 1812 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 1812 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 1812 may include logic for performing processing tasks that include filtering of video and / or audio data, performing modeling operations, including physics operations, and performing data transformation.

[0317] In at least one embodiment, the processing cluster array 1812 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 1812 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 1812 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 1802 may transfer data from the system memory via the I / O unit 1804 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1822) during processing and then written back to the system memory.

[0318] In at least one embodiment, when the parallel processing unit 1802 is used to perform graphics processing, the scheduler 1810 can be configured to divide the processing workload into tasks of approximately equal size to better distribute the graphics processing operations to the multiple clusters 1814A - 1814N of the processing cluster array 1812. In at least one embodiment, portions of the processing cluster array 1812 can be configured to perform different types of processing. For example, in at least one embodiment, the first portion can be configured to perform vertex shading and topology generation, the second portion can be configured to perform tessellation and geometry shading, and the third portion can be configured to perform pixel shading or other screen space operations to generate a rendered image for display. In at least one embodiment, the intermediate data generated by one or more of the clusters 1814A - 1814N can be stored in a buffer to allow the transfer of the intermediate data between the clusters 1814A - 1814N for further processing.

[0319] In at least one embodiment, the processing cluster array 1812 can receive the processing tasks to be executed via the scheduler 1810, which receives commands defining the processing tasks from the front end 1808. In at least one embodiment, the processing tasks can include indices of the data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as status parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 1810 can be configured to obtain the indices corresponding to the tasks, or can receive the indices from the front end 1808. In at least one embodiment, the front end 1808 can be configured to ensure that the processing cluster array 1812 is configured in a valid state before starting the workload specified by the incoming command buffer (e.g., batch - buffer, push - buffer, etc.).

[0320] In at least one embodiment, each of one or more instances of the parallel processing unit 1802 can be coupled to the parallel processor memory 1822. In at least one embodiment, the parallel processor memory 1822 can be accessed via the memory crossbar 1816, which can receive memory requests from the processing cluster array 1812 as well as the I / O unit 1804. In at least one embodiment, the memory crossbar 1816 can access the parallel processor memory 1822 via the memory interface 1818. In at least one embodiment, the memory interface 1818 can include a plurality of partitioning units (e.g., partitioning unit 1820A, partitioning unit 1820B to partitioning unit 1820N), each of which can be coupled to a portion (e.g., a memory unit) of the parallel processor memory 1822. In at least one embodiment, the plurality of partitioning units 1820A - 1820N are configured to be equal to the number of memory units, such that the first partitioning unit 1820A has a corresponding first memory unit 1824A, the second partitioning unit 1820B has a corresponding memory unit 1824B, and the Nth partitioning unit 1820N has a corresponding Nth memory unit 1824N. In at least one embodiment, the number of partitioning units 1820A - 1820N may not be equal to the number of memory devices.

[0321] In at least one embodiment, the memory units 1824A - 1824N can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, the memory units 1824A - 1824N can also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps can be stored across the memory units 1824A - 1824N, allowing the partitioning units 1820A - 1820N to write portions of each rendering target in parallel to effectively utilize the available bandwidth of the parallel processor memory 1822. In at least one embodiment, local instances of the parallel processor memory 1822 can be excluded in favor of a unified memory design that utilizes system memory in combination with local cache memory.

[0322] In at least one embodiment, any one of clusters 1814A - 1814N of processing cluster array 1812 can process data to be written into any of memory cells 1824A - 1824N within parallel processor memory 1822. In at least one embodiment, memory crossbar 1816 can be configured to transfer the output of each of clusters 1814A - 1814N to any of partition units 1820A - 1820N or to another one of clusters 1814A - 1814N, where clusters 1814A - 1814N can perform other processing operations on the output. In at least one embodiment, each of clusters 1814A - 1814N can communicate with memory interface 1818 through memory crossbar 1816 to read from or write to various external storage devices. In at least one embodiment, memory crossbar 1816 has a connection to memory interface 1818 to communicate with I / O unit 1804, and a connection to a local instance of parallel processor memory 1822, enabling processing units within different processing clusters 1814A - 1814N to communicate with system memory or other memory that is not local to parallel processing unit 1802. In at least one embodiment, memory crossbar 1816 can use virtual channels to separate the traffic flow between clusters 1814A - 1814N and partition units 1820A - 1820N.

[0323] In at least one embodiment, multiple instances of parallel processing unit 1802 can be provided on a single insertion card, or multiple insertion cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 1802 can be configured to operate with each other even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 1802 can include floating - point units with higher precision relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 1802 or parallel processor 1800 can be implemented in various configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, gaming consoles, and / or embedded systems.

[0324] Fig.18B is a block diagram of partition unit 1820 according to at least one embodiment. In at least one embodiment, partition unit 1820 is Fig.18AAn example of one of the partition units 1820A - 1820N. In at least one embodiment, the partition unit 1820 includes an L2 cache 1821, a frame buffer interface 1825, and a ROP 1826 (raster operation unit). The L2 cache 1821 is a read / write cache configured to perform load and store operations received from the memory crossbar 1816 and the ROP 1826. In at least one embodiment, the L2 cache 1821 outputs read misses and urgent writeback requests to the frame buffer interface 1825 for processing. In at least one embodiment, updates can also be sent to the frame buffer via the frame buffer interface 1825 for processing. In at least one embodiment, the frame buffer interface 1825 interacts with one of the memory units (such as Fig.18A the memory units 1824A - 1824N (e.g., within the parallel processor memory 1822)).

[0325] In at least one embodiment, the ROP 1826 is a processing unit that performs raster operations such as stencil, z - test, blending, etc. In at least one embodiment, the ROP 1826 then outputs the processed graphics data stored in the graphics memory. In at least one embodiment, the ROP 1826 includes compression logic to compress depth or color data written to the memory and decompress depth or color data read from the memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by the ROP 1826 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per - tile basis.

[0326] In at least one embodiment, the ROP 1826 is included within each processing cluster (e.g., Fig.18A the clusters 1814A - 1814N), rather than within the partition unit 1820. In at least one embodiment, read and write requests for pixel data are made via the memory crossbar 1816 rather than pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device (such as Fig.17 one of the one or more display devices 1710), routed by the processor 1702 for further processing, or routed by Fig.18A one of the processing entities within the parallel processor 1800 for further processing.

[0327] Fig.18C is a block diagram of a processing cluster 1814 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is Fig.18AAn instance of one of the processing clusters 1814A - 1814N. In at least one embodiment, the processing cluster 1814 may be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issue techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0328] In at least one embodiment, the operation of the processing cluster 1814 can be controlled by assigning processing tasks to the pipeline manager 1832 of the SIMT parallel processor. In at least one embodiment, the pipeline manager 1832 receives instructions from Fig.18A the scheduler 1810, and manages the execution of these instructions through the graphics multiprocessor 1834 and / or the texture unit 1836. In at least one embodiment, the graphics multiprocessor 1834 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within the processing cluster 1814. In at least one embodiment, one or more instances of the graphics multiprocessor 1834 may be included within the processing cluster 1814. In at least one embodiment, the graphics multiprocessor 1834 may process data, and the data crossbar 1840 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 1832 may facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 1840.

[0329] In at least one embodiment, each graphics multiprocessor 1834 within the processing cluster 1814 may include the same set of functional execution logic (e.g., arithmetic logic unit, load store unit, etc.). In at least one embodiment, the functional execution logic may be configured in a pipeline manner, where new instructions may be issued before the completion of previous instructions. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating - point arithmetic, comparison operations, boolean operations, shifts, and the calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0330] In at least one embodiment, the instructions transmitted to processing cluster 1814 constitute threads. In at least one embodiment, a set of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes a program on different input data. In at least one embodiment, each thread within the thread group can be assigned to a different processing engine within graphics multiprocessor 1834. In at least one embodiment, the thread group can include fewer threads than the number of processing engines within graphics multiprocessor 1834. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during the cycle in which the thread group is being processed. In at least one embodiment, the thread group can also include more threads than the number of processing engines within graphics multiprocessor 1834. In at least one embodiment, when the thread group includes more threads than the number of processing engines within graphics multiprocessor 1834, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 1834.

[0331] In at least one embodiment, graphics multiprocessor 1834 includes an internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor 1834 can forgo the internal cache and use the cache memory (e.g., L1 cache 1848) within processing cluster 1814. In at least one embodiment, each graphics multiprocessor 1834 can also access the L2 cache within the partition units (e.g., Fig.18A partition units 1820A - 1820N) of, which are shared among all processing clusters 1814 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 1834 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 1802 can be used as global memory. In at least one embodiment, processing cluster 1814 includes multiple instances of graphics multiprocessor 1834, which can share common instructions and data that can be stored in L1 cache 1848.

[0332] In at least one embodiment, each processing cluster 1814 can include a memory management unit (“MMU”) 1845 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 1845 can reside in Fig.18Awithin the memory interface 1818. In at least one embodiment, the MMU 1845 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 1845 may include a translation lookaside buffer (TLB) or a cache that may reside within the graphics multiprocessor 1834 or the L1 cache or the processing cluster 1814. In at least one embodiment, the physical address is processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request to a cache line is a hit or a miss.

[0333] In at least one embodiment, the processing cluster 1814 may be configured such that each graphics multiprocessor 1834 is coupled to a texture unit 1836 to perform texture mapping operations that determine texture sample positions, read texture data, and filter texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from the L1 cache within the graphics multiprocessor 1834 as needed and texture data is fetched from the L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 1834 outputs the processed task to the data crossbar 1840 to provide the processed task to another processing cluster 1814 for further processing or to store the processed task in the L2 cache, local parallel processor memory, or system memory via the memory crossbar 1816. In at least one embodiment, the PreROP 1842 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 1834 and direct the data to a ROP unit that may be located with the partition units (e.g., Fig.18A the partition units 1820A - 1820N) described herein. In at least one embodiment, the PreROP 1842 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0334] Regarding Fig.18A at least one of the components shown or described with respect to Figure 1-5 is used to implement the techniques and / or functions described in connection with Fig.18A at least one of the components shown or described with respect to Figure 1-5The number of indications (e.g., consecutive ACKs) of the described operation will adjust one or more SNRs and / or SINRs by a variable amount. In at least one embodiment, at least one parallel processor 1800 is used to perform the generation of one or more offsets 136, the generation of one or more effective SNRs 138, the selection of packet MCS information 144, the generation of one or more indications of SNR 132, and / or with respect to Figure 1-5 one or more other aspects shown and / or described in Figure 1 processor 118, accelerator 122, processor 124, SNR regulator 134, and / or MCS selector 140 of Figure 2 SNR adjustment 200 of Figure 3 technique 300 of Figure 4 processor 402 of Figure 5 and / or at least one aspect described by one or more APIs 510 of

[0335] Fig.18D FIG. shows a graphics multiprocessor 1834 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 1834 is coupled to a pipeline manager 1832 of a processing cluster 1814. In at least one embodiment, the graphics multiprocessor 1834 has an execution pipeline that includes, but is not limited to, an instruction cache 1852, an instruction unit 1854, an address mapping unit 1856, a register file 1858, one or more general-purpose graphics processing unit (GPGPU) cores 1862, and one or more load / store units 1866. The GPGPU cores 1862 and the load / store units 1866 are coupled to a cache memory 1872 and a shared memory 1870 via a memory and cache interconnect 1868.

[0336] In at least one embodiment, the instruction cache 1852 receives a stream of instructions to be executed from the pipeline manager 1832. In at least one embodiment, the instructions are cached in the instruction cache 1852 and dispatched for execution by the instruction unit 1854. In one embodiment, the instruction unit 1854 may dispatch instructions as a thread group (e.g., a warp), and each thread of the thread group is assigned to a different execution unit within the GPGPU core 1862. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, the address mapping unit 1856 may be used to convert an address in the unified address space into a different memory address that can be accessed by the load / store unit 1866.

[0337] In at least one embodiment, register file 1858 provides a set of registers for the functional units of graphics multiprocessor 1834. In at least one embodiment, register file 1858 provides temporary storage for the operands of the data paths of the functional units (e.g., GPGPU cores 1862, load / store units 1866) connected to graphics multiprocessor 1834. In at least one embodiment, register file 1858 is partitioned among each of the functional units such that a dedicated portion of register file 1858 is allocated to each functional unit. In at least one embodiment, register file 1858 is partitioned among different warps being executed by graphics multiprocessor 1834.

[0338] In at least one embodiment, GPGPU cores 1862 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing the instructions of graphics multiprocessor 1834. GPGPU cores 1862 may be architecturally similar or may have different architectures. In at least one embodiment, a first portion of GPGPU core 1862 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point algorithms or enable variable-precision floating-point algorithms. In at least one embodiment, graphics multiprocessor 1834 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copy rectangle or pixel blend operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0339] In at least one embodiment, GPGPU cores 1862 include SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, GPGPU cores 1862 may physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU cores may be generated by a shader compiler at compile time or automatically generated when executing a program written and compiled for a single-program multiple-data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel by a single SIMD8 logic unit.

[0340] In at least one embodiment, the memory and cache interconnect 1868 is an interconnect network that connects each functional unit of the graphics multiprocessor 1834 to the register file 1858 and the shared memory 1870. In at least one embodiment, the memory and cache interconnect 1868 is a crossbar interconnect that allows the load / store unit 1866 to perform load and store operations between the shared memory 1870 and the register file 1858. In at least one embodiment, the register file 1858 can operate at the same frequency as the GPGPU core 1862, resulting in very low latency for data transfer between the GPGPU core 1862 and the register file 1858. In at least one embodiment, the shared memory 1870 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 1834. In at least one embodiment, the cache memory 1872 can be used as, for example, a data cache to cache texture data communicated between the functional units and the texture unit 1836. In at least one embodiment, the shared memory 1870 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in the cache memory 1872, threads executing on the GPGPU core 1862 can also programmatically store data in the shared memory.

[0341] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core can allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0342] In at least one embodiment, at least one component shown or described with respect to Fig.18D is used to implement the techniques and / or functions described in connection with Figure 1-5 In at least one embodiment, in at least one embodiment, at least one component shown or described with respect to Fig.18D includes logic or otherwise is used to at least partially based on whether an indication signal is successfully interpreted, recognized, and / or selected MCS and / or otherwise perform in connection with Figure 1-5The number of indications (e.g., consecutive ACKs) of the described operations will adjust one or more SNRs and / or SINRs by a variable amount. In at least one embodiment, at least one graphics multiprocessor 1834 is used to perform the generation of one or more offsets 136, the generation of one or more effective SNRs 138, the selection of packet MCS information 144, the generation of one or more indications of SNR 132, and / or with respect to Figure 1-5 one or more other aspects shown and / or described in Figure 1 processor 118, accelerator 122, processor 124, SNR regulator 134, and / or MCS selector 140 of Figure 2 SNR adjustment 200 of Figure 3 technique 300 of Figure 4 processor 402 of Figure 5 and / or at least one aspect described by one or more APIs 510 of

[0343] Fig.19Shows a multi - GPU computing system 1900 according to at least one embodiment. In at least one embodiment, the multi - GPU computing system 1900 may include a processor 1902 coupled to a plurality of general - purpose graphics processing units (GPGPUs) 1906A - D via a host interface switch 1904. In at least one embodiment, the host interface switch 1904 is a PCI Express switch device that couples the processor 1902 to a PCI Express bus, and the processor 1902 can communicate with the GPGPUs 1906A - D via the PCI Express bus. The GPGPUs 1906A - D may be interconnected via a set of high - speed P2P GPU - to - GPU links 1916. In at least one embodiment, the GPU - to - GPU link 1916 is connected to each of the GPGPUs 1906A - D via a dedicated GPU link. In at least one embodiment, the P2P GPU link 1916 enables direct communication between each of the GPGPUs 1906A - D without communicating through the host interface bus 1904 to which the processor 1902 is connected. In at least one embodiment, when GPU - to - GPU traffic is directed to the P2P GPU link 1916, the host interface bus 1904 remains available for system memory access or communication with other instances of the multi - GPU computing system 1900 via, for example, one or more network devices. Although in at least one embodiment the GPGPUs 1906A - D are connected to the processor 1902 via the host interface switch 1904, in at least one embodiment the processor 1902 includes direct support for the P2P GPU link 1916 and can be directly connected to the GPGPUs 1906A - D.

[0344] In at least one embodiment, with respect to Fig.19 at least one of the components shown or described is used to implement the techniques and / or functions associated with Figure 1-5 described. In at least one embodiment, in at least one embodiment, with respect to Fig.19 one or more of the components shown or described include logic or otherwise operate to at least partially adjust one or more SNRs and / or SINRs by a variable amount based on the number of indications (e.g., consecutive ACKs) indicating whether a signal has been successfully interpreted, recognized, and / or selected for MCS and / or otherwise perform the operations associated with Figure 1-5 described. In at least one embodiment, at least one GPGPU 1906 is used to perform the generation of one or more offsets 136, the generation of one or more valid SNRs 138, the selection of packet MCS information 144, the generation of one or more indications of SNR 132, and / or with respect to Figure 1-5one or more other aspects shown and / or described therein. In at least one embodiment, at least one GPGPU 1906 performs with respect to Figure 1 processor 118, accelerator 122, processor 124, SNR regulator 134, and / or MCS selector 140 of Figure 2 SNR regulation 200 of Figure 3 technique 300 of Figure 4 processor 402 of Figure 5 and / or at least one aspect described by one or more APIs 510 of

[0345] Fig. 20 is a block diagram of a graphics processor 2000 according to at least one embodiment. In at least one embodiment, the graphics processor 2000 includes a ring interconnect 2002, a pipeline front end 2004, a media engine 2037, and graphics cores 2080A - 2080N. In at least one embodiment, the ring interconnect 2002 couples the graphics processor 2000 to other processing units, the processing units including other graphics processors or one or more general - purpose processor cores. In at least one embodiment, the graphics processor 2000 is one of many processors integrated within a multi - core processing system.

[0346] In at least one embodiment, the graphics processor 2000 receives multiple batches of commands via the ring interconnect 2002. In at least one embodiment, the input commands are interpreted by a command streamer 2003 in the pipeline front end 2004. In at least one embodiment, the graphics processor 2000 includes scalable execution logic for performing 3D geometry processing and media processing via the graphics cores 2080A - 2080N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2003 provides the commands to a geometry pipeline 2036. In at least one embodiment, for at least some media processing commands, the command streamer 2003 provides the commands to a video front end 2034, which is coupled to the media engine 2037. In at least one embodiment, the media engine 2037 includes a video quality engine (VQE) 2030 for video and image post - processing, and a multi - format encoding / decoding (MFX) 2033 engine for providing hardware - accelerated encoding and decoding of media data. In at least one embodiment, the geometry pipeline 2036 and the media engine 2037 each generate execution threads for thread execution resources provided by at least one of the graphics cores 2080A.

[0347] In at least one embodiment, the graphics processor 2000 includes scalable thread execution resources having modular cores 2080A - 2080N (sometimes referred to as core slices), with each graphics core having multiple sub - cores 2050A - 2050N, 2060A - 2060N (sometimes referred to as core sub - slices). In at least one embodiment, the graphics processor 2000 can have any number of graphics cores 2080A through 2080N. In at least one embodiment, the graphics processor 2000 includes a graphics core 2080A having at least a first sub - core 2050A and a second sub - core 2060A. In at least one embodiment, the graphics processor 2000 is a low - power processor having a single sub - core (e.g., 2050A). In at least one embodiment, the graphics processor 2000 includes multiple graphics cores 2080A - 2080N, each graphics core including a set of first sub - cores 2050A - 2050N and a set of second sub - cores 2060A - 2060N. In at least one embodiment, each of the first sub - cores 2050A - 2050N includes at least a first set of execution units 2052A - 2052N and media / texture samplers 2054A - 2054N. In at least one embodiment, each of the second sub - cores 2060A - 2060N includes at least a second set of execution units 2062A - 2062N and samplers 2064A - 2064N. In at least one embodiment, each sub - core 2050A - 2050N, 2060A - 2060N shares a set of shared resources 2070A - 2070N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0348] In at least one embodiment, regarding Fig. 20 at least one of the components shown or described is used to implement the techniques and / or functions associated with Figure 1-5 the description. In at least one embodiment, in at least one embodiment, regarding Fig. 20 one or more of the components shown or described include logic or otherwise are used to at least partially regulate one or more SNRs and / or SINRs by a variable amount based on the number of indications (e.g., consecutive ACKs) indicating whether a signal is successfully interpreted, identified, and / or selected for MCS and / or otherwise perform the operations associated with Figure 1-5 the description. In at least one embodiment, at least one graphics processor 2000 is used to perform the generation of one or more offsets 136, the generation of one or more effective SNRs 138, the selection of packet MCS information 144, the generation of one or more indications of SNR 132, and / or regarding Figure 1-5one or more other aspects shown and / or described therein. In at least one embodiment, at least one graphics processor 2000 performs with respect to Figure 1 processor 118, accelerator 122, processor 124, SNR regulator 134, and / or MCS selector 140 of Figure 2 SNR adjustment 200 of Figure 3 technique 300 of Figure 4 processor 402 of Figure 5 at least one aspect described by one or more APIs 510 of

[0349] Fig.21 is a block diagram illustrating a microarchitecture for a processor 2100 according to at least one embodiment, the processor 2100 may include logic circuitry for executing instructions. In at least one embodiment, the processor 2100 may execute instructions including x86 instructions, ARM instructions, special instructions for application specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 2100 may include registers for storing packed data, such as the 64-bit wide MMX TM registers in a microprocessor enabled with MMX technology by Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers available in integer and floating-point forms may operate with packed data elements, the packed data elements accompanying single instruction multiple data (“SIMD”) and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or later versions (generally referred to as “SSEx” technology) may hold such packed data operands. In at least one embodiment, the processor 2110 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0350] In at least one embodiment, the processor 2100 includes an in-order front end (“front end”) 2101 to fetch instructions to be executed and prepare the instructions for later use in the processor pipeline. In at least one embodiment, the front end 2101 may include several units. In at least one embodiment, the instruction prefetcher 2126 fetches instructions from memory and provides the instructions to the instruction decoder 2128, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2128 decodes the received instructions into one or more operations of so-called “microinstructions” or “micro-operations” (also referred to as “uops” or “microinstructions”) that are machine-executable. In at least one embodiment, the instruction decoder 2128 parses the instructions into an opcode and corresponding data and control fields, which can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, the trace cache 2130 may assemble the decoded microinstructions into a program-ordered sequence or trace in the microinstruction queue 2134 for execution. In at least one embodiment, when the trace cache 2130 encounters a complex instruction, the microcode ROM 2132 provides the microinstructions required to complete the operation.

[0351] In at least one embodiment, some instructions can be converted into a single micro-operation, while other instructions require several micro-operations to complete the entire operation. In at least one embodiment, if more than four microinstructions are required to complete an instruction, the instruction decoder 2128 may access the microcode ROM 2132 to execute the instruction. In at least one embodiment, instructions can be decoded into a small number of microinstructions for processing at the instruction decoder 2128. In at least one embodiment, if multiple microinstructions are required to complete the operation, the instructions can be stored in the microcode ROM 2132. In at least one embodiment, the trace cache 2130 refers to an entry point programmable logic array (“PLA”) to determine the correct microinstruction pointer for reading a microcode sequence from the microcode ROM 2132 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2132 finishes sequencing the micro-operations of an instruction, the front end 2101 of the machine can resume fetching micro-operations from the trace cache 2130.

[0352] In at least one embodiment, an out-of-order execution engine (“out-of-order engine”) 2103 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction stream to optimize performance as the instructions descend along the pipeline and are scheduled for execution. The out-of-order execution engine 2103 includes, but is not limited to, an allocator / register renamer 2140, a memory micro-instruction queue 2142, an integer / floating-point micro-instruction queue 2144, a memory scheduler 2146, a fast scheduler 2102, a slow / general floating-point scheduler (“slow / general FP scheduler”) 2104, and a simple floating-point scheduler (“simple FP scheduler”) 2106. In at least one embodiment, the fast scheduler 2102, the slow / general floating-point scheduler 2104, and the simple floating-point scheduler 2106 are also collectively referred to as “micro-instruction schedulers 2102, 2104, 2106”. In at least one embodiment, the allocator / register renamer 2140 allocates the machine buffers and resources required for each micro-instruction to execute in sequence. In at least one embodiment, the allocator / register renamer 2140 renames logical registers to entries in the register file. In at least one embodiment, the allocator / register renamer 2140 also allocates entries for each micro-instruction in one of the two micro-instruction queues, the memory micro-instruction queue 2142 for memory operations and the integer / floating-point micro-instruction queue 2144 for non-memory operations, in front of the memory scheduler 2146 and the micro-instruction schedulers 2102, 2104, 2106. In at least one embodiment, the micro-instruction schedulers 2102, 2104, 2106 determine when a micro-instruction is ready for execution based on the readiness of their dependent input register operand sources and the availability of execution resources micro-instructions that need to be completed. The fast scheduler 2102 of at least one embodiment may be scheduled on each half of the main clock cycle, while the slow / general floating-point scheduler 2104 and the simple floating-point scheduler 2106 may be scheduled once per main processor clock cycle. In at least one embodiment, the micro-instruction schedulers 2102, 2104, 2106 arbitrate the scheduling ports to schedule micro-instructions for execution.

[0353] In at least one embodiment, execution block 2111 includes, but is not limited to, integer register file / branch network 2108, floating-point register file / branch network (“FP register file / branch network”) 2110, address generation units (“AGUs”) 2112 and 2114, fast arithmetic logic units (“fast ALUs”) 2116 and 2118, slow arithmetic logic unit (“slow ALU”) 2120, floating-point ALU (“FP”) 2122, and floating-point move unit (“FP move”) 2124. In at least one embodiment, integer register file / branch network 2108 and floating-point register file / bypass network 2110 are also referred to herein as “register files 2108, 2110”. In at least one embodiment, AGUs 2112 and 2114, fast ALUs 2116 and 2118, slow ALU 2120, floating-point ALU 2122, and floating-point move unit 2124 are also referred to herein as “execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124”. In at least one embodiment, execution block 2111 can include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0354] In at least one embodiment, register files 2108, 2110 can be arranged between microinstruction schedulers 2102, 2104, 2106 and execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124. In at least one embodiment, integer register file / branch network 2108 performs integer operations. In at least one embodiment, floating-point register file / branch network 2110 performs floating-point operations. In at least one embodiment, each of register files 2108, 2110 can include, but is not limited to, a branch network that can bypass or forward a just-completed result that has not yet been written to the register file to a new dependent. In at least one embodiment, register files 2108, 2110 can communicate data with each other. In at least one embodiment, integer register file / branch network 2108 can include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, floating-point register file / branch network 2110 can include, but is not limited to, 128-bit wide entries because floating-point instructions typically have operands with widths of 64 to 128 bits.

[0355] In at least one embodiment, execution units 2112, 2114, 2116, 2118, 2120, 2122, 2124 may execute instructions. In at least one embodiment, register files 2108, 2110 store integer and floating-point data operand values that the microinstructions need to execute. In at least one embodiment, the processor 2100 may include, but is not limited to, any number of execution units 2112, 2114, 2116, 2118, 2120, 2122, 2124 and their combinations. In at least one embodiment, the floating-point ALU 2122 and the floating-point move unit 2124 may execute floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, the floating-point ALU 2122 may include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, instructions involving floating-point values may be processed with floating-point hardware. In at least one embodiment, ALU operations may be passed to the fast ALUs 2116, 2118. In at least one embodiment, the fast ALUs 2116, 2118 may execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations enter the slow ALU 2120 because the slow ALU 2120 may include, but is not limited to, integer execution hardware for long-latency type operations such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations may be performed by the AGUs 2112, 2114. In at least one embodiment, the fast ALU 2116, the fast ALU 2118, and the slow ALU 2120 may perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALU 2116, the fast ALU 2118, and the slow ALU 2120 may be implemented to support various data bit sizes including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating-point ALU 2122 and the floating-point move unit 2124 may be implemented to support a certain range of operands with bits of various widths. In at least one embodiment, the floating-point ALU 2122 and the floating-point move unit 2124 may operate on 128-bit wide packed data operands in combination with SIMD and multimedia instructions.

[0356] In at least one embodiment, the microinstruction schedulers 2102, 2104, 2106 schedule dependent operations before the completion of the execution of the parent load. In at least one embodiment, since microinstructions can be speculatively scheduled and executed in the processor 2100, the processor 2100 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be dependent operations running in the pipeline that leave the scheduler temporarily without the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that used incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0357] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, the registers may be those that can be used from outside the processor (from the programmer's perspective). In at least one embodiment, the registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, the registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented using a variety of different techniques by circuits within the processor, such as dedicated physical registers, physical registers dynamically allocated using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also contains eight multimedia SIMD registers for packing data.

[0358] In at least one embodiment, regarding Fig.21 at least one of the components shown or described is used to implement the techniques and / or functions described in connection with Figure 1-5 In at least one embodiment, in at least one embodiment, regarding Fig.21 one or more of the components shown or described include logic or otherwise operate at least in part based on the number of indications (e.g., consecutive ACKs) indicating whether a signal has been successfully interpreted, identified, and / or selected for MCS and / or otherwise perform operations described in connection with Figure 1-5 to adjust one or more SNRs and / or SINRs by a variable amount. In at least one embodiment, at least one processor 2100 is used to perform the generation of one or more offsets 136, the generation of one or more valid SNRs 138, the selection of packet MCS information 144, the generation of one or more indications of SNR 132, and / or regarding Figure 1-5One or more other aspects shown and / or described therein. In at least one embodiment, at least one processor 2100 performs at least one aspect described with respect to Figure 1 processor 118, accelerator 122, processor 124, SNR regulator 134, and / or MCS selector 140 of Figure 2 SNR regulation 200 of Figure 3 technique 300 of Figure 4 processor 402 of Figure 5 and / or one or more APIs 510 of

[0359] Fig. 22 FIG. shows a block diagram of a processing system according to at least one embodiment. In at least one embodiment, system 2200 includes one or more processors 2202 and one or more graphics processors 2208, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2202 or processor cores 2207. In at least one embodiment, system 2200 is a processing platform integrated within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0360] In at least one embodiment, system 2200 can be included in or incorporated into a server-based gaming platform, including a game console such as a game and media console, a mobile game console, a handheld game console, or an online game console. In at least one embodiment, system 2200 is a mobile phone, a smartphone, a tablet computing device, or a mobile Internet device. In at least one embodiment, processing system 2200 can also be coupled to or integrated within a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, processing system 2200 is a television or set-top box device having one or more processors 2202 and a graphical interface generated by one or more graphics processors 2208.

[0361] In at least one embodiment, each of one or more processors 2202 includes one or more processor cores 2207 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of one or more processor cores 2207 is configured to process a particular instruction set 2209. In at least one embodiment, the instruction set 2209 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). In at least one embodiment, the processor cores 2207 can each process a different instruction set 2209, which can include instructions that help to emulate other instruction sets. In at least one embodiment, the processor cores 2207 can also include other processing devices, such as a digital signal processor (DSP).

[0362] In at least one embodiment, the processor 2202 includes a cache memory 2204. In at least one embodiment, the processor 2202 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory is shared among the various components of the processor 2202. In at least one embodiment, the processor 2202 also uses an external cache (e.g., a level three (L3) cache or a last level cache (LLC)) (not shown), and the external cache can be shared among the processor cores 2207 using known cache coherence techniques. In at least one embodiment, the processor 2202 further includes a register file 2206, and the processor can include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and instruction pointer registers). In at least one embodiment, the register file 2206 can include general-purpose registers or other registers.

[0363] In at least one embodiment, one or more processors 2202 are coupled to one or more interface buses 2210 to transfer communication signals, such as address, data, or control signals, between the processors 2202 and other components in the system 2200. In at least one embodiment, the interface bus 2210 can be a processor bus, such as a version of the Direct Media Interface (DMI) bus, in one embodiment. In at least one embodiment, the interface 2210 is not limited to the DMI bus and can include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 2202 includes an integrated memory controller 2216 and a Platform Controller Hub 2230. In at least one embodiment, the memory controller 2216 facilitates communication between the memory device and other components of the processing system 2200, while the Platform Controller Hub (PCH) 2230 provides connections to input / output (I / O) devices via a local I / O bus.

[0364] In at least one embodiment, the memory device 2220 can be a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a flash memory device, a Phase Change Memory device, or have suitable performance to be used as processor memory. In at least one embodiment, the storage device 2220 can be used as the system memory of the processing system 2200 to store data 2222 and instructions 2221 for use when one or more processors 2202 execute an application or process. In at least one embodiment, the memory controller 2216 is also coupled to an optional external graphics processor 2212, which can communicate with one or more graphics processors 2208 in the processor 2202 to perform graphics and media operations. In at least one embodiment, a display device 2211 can be connected to the processor 2202. In at least one embodiment, the display device 2211 can include one or more of internal display devices, such as in a mobile electronic device or a laptop device, or an external display device connected via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 2211 can include a Head-Mounted Display (HMD), such as a stereoscopic display device for Virtual Reality (VR) applications or Augmented Reality (AR) applications.

[0365] In at least one embodiment, the platform controller hub 2230 enables peripheral devices to be connected to the storage device 2220 and the processor 2202 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 2246, a network controller 2234, a firmware interface 2228, a wireless transceiver 2226, a touch sensor 2225, and a data storage device 2224 (e.g., a hard disk drive, a flash memory, etc.). In at least one embodiment, the data storage device 2224 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2225 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2226 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 2228 enables communication with the system firmware and can be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, the network controller 2234 can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 2210. In at least one embodiment, the audio controller 2246 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 2200 includes an optional legacy I / O controller 2240 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system 2200. In at least one embodiment, the platform controller hub 2230 can also be connected to one or more Universal Serial Bus (USB) controllers 2242, which connect input devices, such as a keyboard and mouse 2243 combination, a camera 2244, or other USB input devices.

[0366] In at least one embodiment, instances of the memory controller 2216 and the platform controller hub 2230 can be integrated into a discrete external graphics processor, such as the external graphics processor 2212. In at least one embodiment, the platform controller hub 2230 and / or the memory controller 2216 can be external to one or more processors 2202. For example, in at least one embodiment, the system 2200 can include an external memory controller 2216 and a platform controller hub 2230, which can be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with the processor 2202.

[0367] In at least one embodiment, at least one component shown or described with respect to Fig. 22 is used to implement in connection with Figure 1-5The described technology and / or functionality. In at least one embodiment, in at least one embodiment, regarding Fig. 22 One or more components shown or described include logic or otherwise for at least partially based on whether an indication signal is successfully interpreted, identifying and / or selecting an MCS and / or otherwise performing operations in connection with Figure 1-5 The number of indications (e.g., consecutive ACKs) described will adjust one or more SNRs and / or SINRs by a variable amount. In at least one embodiment, at least one graphics processor 2202 is used to perform the generation of one or more offsets 136, the generation of one or more effective SNRs 138, the selection of packet MCS information 144, the generation of one or more indications of SNR 132, and / or regarding Figure 1-5 One or more other aspects shown and / or described in Figure 1 Processor 118, accelerator 122, processor 124, SNR regulator 134, and / or MCS selector 140 of Figure 2 SNR adjustment 200 of Figure 3 Technique 300 of Figure 4 Processor 402 of Figure 5 At least one aspect described by one or more APIs 510 of

[0368] Fig.23 Is a block diagram of a processor 2300 having one or more processor cores 2302A - 2302N, an integrated memory controller 2314, and an integrated graphics processor 2308 according to at least one embodiment. In at least one embodiment, processor 2300 may include additional cores, up to and including additional core 2302N represented by the dashed box. In at least one embodiment, each processor core 2302A - 2302N includes one or more internal cache units 2304A - 2304N. In at least one embodiment, each processor core may also access one or more shared cache units 2306.

[0369] In at least one embodiment, the internal cache units 2304A - 2304N and the shared cache unit 2306 represent the cache memory hierarchy within the processor 2300. In at least one embodiment, the cache memory units 2304A - 2304N may include at least one level of instruction and data cache within each processor core and one or more levels of cache in the shared mid - level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest - level cache before the external memory is classified as the LLC. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2306 and 2304A - 2304N.

[0370] In at least one embodiment, the processor 2300 may further include a set of one or more bus controller units 2316 and a system agent core 2310. In at least one embodiment, the one or more bus controller units 2316 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 2310 provides management functions for various processor components. In at least one embodiment, the system agent core 2310 includes one or more integrated memory controllers 2314 to manage access to various external memory devices (not shown).

[0371] In at least one embodiment, one or more processor cores 2302A - 2302N include support for simultaneous multi - threading. In at least one embodiment, the system agent core 2310 includes components for coordinating and operating the cores 2302A - 2302N during multi - threading. In at least one embodiment, the system agent core 2310 may additionally include a power control unit (PCU) that includes logic and components for regulating one or more power states of the processor cores 2302A - 2302N and the graphics processor 2308.

[0372] In at least one embodiment, the processor 2300 further includes a graphics processor 2308 for performing graphics processing operations. In at least one embodiment, the graphics processor 2308 is coupled to the shared cache unit 2306 and the system agent core 2310 that includes one or more integrated memory controllers 2314. In at least one embodiment, the system agent core 2310 further includes a display controller 2311 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 2311 may also be an independent module coupled to the graphics processor 2308 via at least one interconnect, or may be integrated within the graphics processor 2308.

[0373] In at least one embodiment, the ring-based interconnect unit 2312 is used to couple the internal components of the processor 2300. In at least one embodiment, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 2308 is coupled to the ring interconnect 2312 via the I / O link 2313.

[0374] In at least one embodiment, the I / O link 2313 represents at least one of a variety of I / O interconnects, including a package I / O interconnect that facilitates communication between various processor components and the high-performance embedded memory module 2318 (e.g., an eDRAM module). In at least one embodiment, each of the processor cores 2302A - 2302N and the graphics processor 2308 uses the embedded memory module 2318 as a shared last-level cache.

[0375] In at least one embodiment, the processor cores 2302A - 2302N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2302A - 2302N are heterogeneous in terms of the instruction set architecture (ISA), where one or more of the processor cores 2302A - 2302N execute a common instruction set, while one or more other processor cores 2302A - 2302N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, in terms of the microarchitecture, the processor cores 2302A - 2302N are heterogeneous, where one or more cores with relatively high power consumption are coupled to one or more power cores with lower power consumption. In at least one embodiment, the processor 2300 may be implemented on one or more chips or as a SoC integrated circuit.

[0376] In at least one embodiment, regarding Fig.23 at least one of the components shown or described is used to implement the techniques and / or functions associated with Figure 1-5 the description. In at least one embodiment, in at least one embodiment, regarding Fig.23 one or more of the components shown or described include logic or otherwise are used to adjust one or more SNRs and / or SINRs by a variable amount based at least in part on the number of indications (e.g., consecutive ACKs) indicating whether a signal has been successfully interpreted, recognized, and / or selected for MCS and / or otherwise perform the operations associated with Figure 1-5 the description. In at least one embodiment, at least one graphics processor 2308 is used to perform the generation of one or more offsets 136, the generation of one or more valid SNRs 138, the selection of packet MCS information 144, the generation of one or more indications of SNR 132, and / or regarding Figure 1-5One or more of the other aspects shown and / or described therein. In at least one embodiment, at least one graphics processor 2308 performs with respect to Figure 1 processor 118, accelerator 122, processor 124, SNR regulator 134, and / or MCS selector 140 of Figure 2 SNR adjustment 200 of Figure 3 technique 300 of Figure 4 processor 402 of Figure 5 and / or one or more APIs 510 of

[0377] Fig.24 is a block diagram of a graphics processor 2400, which can be a discrete graphics processing unit or can be a graphics processor integrated with multiple processing cores. In at least one embodiment, the graphics processor 2400 communicates with registers on the graphics processor 2400 and commands placed in memory via a memory-mapped I / O interface. In at least one embodiment, the graphics processor 2400 includes a memory interface 2414 for accessing memory. In at least one embodiment, the memory interface 2414 is an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0378] In at least one embodiment, the graphics processor 2400 further includes a display controller 2402 for driving display output data to a display device 2420. In at least one embodiment, the display controller 2402 includes hardware for one or more overlay planes of the display device 2420 and a combination of multi-layer video or user interface elements. In at least one embodiment, the display device 2420 can be an internal or external display device. In at least one embodiment, the display device 2420 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In at least one embodiment, the graphics processor 2400 includes a video codec engine 2406 to encode, decode, or transcode media into one or more media coding formats, from one or more media coding formats, or between one or more media coding formats, the media coding formats including but not limited to Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC, and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1), and Joint Photographic Experts Group (JPEG) formats (such as JPEG) and MotionJPEG (MJPEG) formats.

[0379] In at least one embodiment, the graphics processor 2400 includes a block image transfer (BLIT) engine 2404 to perform two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfer. However, in at least one embodiment, one or more components of the graphics processing engine (GPE) 2410 are used to perform 2D graphics operations. In at least one embodiment, the GPE 2410 is a computing engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0380] In at least one embodiment, the GPE 2410 includes a 3D pipeline 2412 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 2412 includes programmable and fixed-function elements that perform various tasks and / or generate execution threads to the 3D / media subsystem 2415. Although the 3D pipeline 2412 can be used to perform media operations, in at least one embodiment, the GPE 2410 also includes a media pipeline 2416 for performing media operations, such as video post-processing and image enhancement.

[0381] In at least one embodiment, the media pipeline 2416 includes fixed-function or programmable logic units for performing one or more specialized media operations, such as video decode acceleration, video deinterlacing, and video encode acceleration, in place of or on behalf of the video codec engine 2406. In at least one embodiment, the media pipeline 2416 also includes a thread generation unit for generating threads to execute on the 3D / media subsystem 2415. In at least one embodiment, the generated threads perform media operation computations on one or more graphics execution units included in the 3D / media subsystem 2415.

[0382] In at least one embodiment, the 3D / media subsystem 2415 includes logic for executing the threads generated by the 3D pipeline 2412 and the media pipeline 2416. In at least one embodiment, the 3D pipeline 2412 and the media pipeline 2416 send thread execution requests to the 3D / media subsystem 2415, which includes thread dispatch logic for arbitrating various requests and dispatching them to available thread execution resources. In at least one embodiment, the execution resources include an array of graphics execution units for processing 3D and media threads. In at least one embodiment, the 3D / media subsystem 2415 includes one or more internal caches for thread instructions and data. In at least one embodiment, the subsystem 2415 also includes shared memory, which includes registers and addressable memory for sharing data between threads and storing output data.

[0383] In at least one embodiment, regarding Fig.24 at least one of the components shown or described is used to implement in connection with Figure 1-5 The described technology and / or functionality. In at least one embodiment, in at least one embodiment, regarding Fig.24 One or more components shown or described include logic or otherwise for at least partially based on whether an indication signal is successfully interpreted, identify and / or select MCS and / or otherwise perform operations in connection with Figure 1-5 The number of indications (e.g., consecutive ACK) described will adjust one or more SNR and / or SINR by a variable amount. In at least one embodiment, at least one graphics processor 2400 is used to perform the generation of one or more offsets 136, the generation of one or more effective SNR 138, the selection of packet MCS information 144, the generation of one or more indications of SNR 132 and / or regarding Figure 1-5 One or more other aspects shown and / or described in. In at least one embodiment, at least one graphics processor 2400 performs regarding Figure 1 Processor 118, accelerator 122, processor 124, SNR regulator 134 and / or MCS selector 140 of Figure 2 SNR regulation 200 of Figure 3 Technique 300 of Figure 4 Processor 402 of Figure 5 At least one aspect described by one or more APIs 510 of

[0384] Fig.25 Is a block diagram of a graphics processing engine 2510 of a graphics processor according to at least one embodiment. In at least one embodiment, the graphics processing engine (GPE) 2510 is Fig.24 A version of the GPE 2410 shown in. In at least one embodiment, the media pipeline 2516 is optional and may not be explicitly included in the GPE 2510. In at least one embodiment, a separate media and / or image processor is coupled to the GPE 2510.

[0385] In at least one embodiment, the GPE 2510 is coupled to or includes a command stream converter 2503 that provides a command stream to the 3D pipeline 2512 and / or the media pipeline 2516. In at least one embodiment, the command stream converter 2503 is coupled to a memory, which can be system memory or one or more of an internal cache memory and a shared cache memory. In at least one embodiment, the command stream converter 2503 receives commands from the memory and sends the commands to the 3D pipeline 2512 and / or the media pipeline 2516. In at least one embodiment, the commands are instructions, primitives, or micro-operations fetched from a ring buffer that stores commands for the 3D pipeline 2512 and the media pipeline 2516. In at least one embodim...

Claims

1. A processor, comprising: One or more circuits are configured to cause one or more signal-to-noise ratios to be adjusted by a variable amount based at least in part on a number of indications received by the processor indicating whether a signal was successfully interpreted.

2. The processor of claim 1, wherein the indication is an acknowledgement (ACK).

3. The processor of claim 1, wherein the number of indications is a number of consecutive indications, each indication indicating that a corresponding signal was decoded without error. 4 . The processor of claim 1 , wherein the indicated number is a number of consecutive acknowledgements (ACKs) sent by one or more user equipment (UE) devices.

5. The processor of claim 1, wherein the one or more circuits are configured to cause a modulation and coding scheme (MCS) to be selected based at least in part on the adjusted signal-to-noise ratio.

6. The processor of claim 1, wherein the processor is a processor of a radio network base station, the one or more signal-to-noise ratios are signal-to-interference-plus-noise (SINR) ratios, and the indication is sent by one or more user equipment (UE) devices.

7. The processor of claim 1, wherein the indicated number is a number of consecutive acknowledgements (ACKs), and the one or more circuits are configured to generate an offset value that decreases with each consecutive ACK.

8. A system comprising: One or more processors are configured to cause one or more signal-to-noise ratios to be adjusted by a variable amount based at least in part on a number of indications received by the one or more processors indicating whether a signal was successfully interpreted.

9. The system of claim 8, wherein the one or more processors are one or more processors of a radio network base station.

10. The system of claim 8, wherein the number of indications is a number of consecutive indications.

11. The system of claim 8, wherein the indicated number is a number of consecutive acknowledgements (ACKs) sent by one or more user equipment (UE) devices.

12. The system of claim 8, wherein the number of indications is the number of consecutive acknowledgments ACK sent by one or more user equipment (UE) devices, and the one or more processors are used to cause a modulation and coding scheme (MCS) to be selected based at least in part on the adjusted signal-to-noise ratio.

13. The system of claim 8, wherein the number of indications is a number of consecutive indications, and the one or more processors are configured to generate an offset value to be applied for link adaptation based at least in part on the number of consecutive indications.

14. A method comprising: One or more signal-to-noise ratios are adjusted by a variable amount based at least in part on a number of indications received by the processor indicating whether the signal was successfully interpreted.

15. The method of claim 14, wherein the indicated number is the number of consecutive acknowledgements (ACK) sent by one or more User Equipment (UE) devices.

16. The method according to claim 14, wherein the method comprises: A fifth generation 5G New Radio NR modulation and coding scheme MCS is selected based at least in part on the adjusted signal-to-noise ratio.

17. The method of claim 14, wherein the one or more signal-to-noise ratios are signal-to-interference-plus-noise ratios based at least in part on channel quality information (CQI) received from one or more user equipment (UE) devices.

18. The method of claim 14, wherein the indicated number is a number of consecutive acknowledgements (ACKs), and the variable amount decreases with each consecutive ACK.

19. The method according to claim 14, wherein the number of indications comprises the number of consecutive acknowledgements ACK received at a radio network base station from user equipment UE devices, and the method comprises: Generate an offset value that decreases with each consecutive ACK, adjust the signal to interference plus noise SINR value based at least in part on the offset value, select a fifth generation 5G New Radio NR wireless modulation and coding MCS scheme based at least in part on the adjusted SINR value, and send an indication of the selected MCS to the UE device.

20. A non-transitory computer readable medium having stored thereon a set of instructions, which when executed by one or more processors, cause the one or more processors to at least perform the method of claim 14.

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