Display substrate and display device
By setting up an anti-static unit on the display substrate, the problem of burning the test electrode caused by static accumulation in the electrical detection of the display panel is solved, effective dispersion and transmission of static electricity are achieved, and the reliability of detection is improved.
Patent Information
- Application Number
- CN202311748947.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-19
- Publication Date
- 2025-06-24
AI Technical Summary
During the electrical detection process of the display panel, the metal probe has a large voltage signal, which may cause static electricity, which in turn causes the problem of burning the test electrode.
An antistatic unit is provided on the display substrate, and an antistatic unit is connected between each adjacent two rows or two columns of test electrodes to transmit static electricity and disperse its influence.
Through the installation of the anti-static unit, the accumulation and propagation of static electricity between the test electrodes is effectively reduced, the burning of the test electrodes is avoided, and the reliability of electrical detection is improved.
Smart Images
Figure CN120201783A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of display technologies, and particularly to a display substrate and a display device. Background Art
[0002] After a display panel is manufactured, electrical tests are usually performed to prevent defective display panels from entering the subsequent production process. Among them, multiple test electrodes are provided on the display panel, and each test electrode is electrically connected to a signal line. During testing, a test signal is input to the test electrode using a metal probe, and it is detected whether the display panel lights up normally. Since the metal probe carries a relatively large voltage signal, a conductive path is formed when it contacts the test electrode, and relatively large static electricity may be generated. If the static electricity is not dissipated in time, the test electrode may be burned out. Summary of the Invention
[0003] The present disclosure provides a display substrate having a display area and a non-display area located around the display area. The display substrate includes:
[0004] A substrate;
[0005] Multiple signal lines and at least one test group provided on the substrate. The test group is located in the non-display area and includes multiple test electrodes arranged in M rows and N columns; each test electrode is connected to a signal line; both M and N are integers greater than 2;
[0006] Multiple static electricity prevention units for transmitting static electricity; wherein, static electricity prevention units are connected between every two adjacent rows of the test electrodes and between every two adjacent columns of the test electrodes, so that the multiple test electrodes are connected together through the multiple static electricity prevention units.
[0007] In some embodiments, the non-display area includes a chip setting area located on one side of the display area along a first direction; multiple pads are provided in the chip setting area; the first direction is the column direction in which the multiple test electrodes are arranged;
[0008] The test electrode is electrically connected to the pad through a first connection line, and the pad is electrically connected to the signal line, so that the test electrode is connected to the signal line through the first connection line and the pad; there is a first interval area between two adjacent test electrodes in the same row, and the first connection line is located outside the first interval area.
[0009] In some embodiments, static electricity prevention units are connected between every two adjacent test electrodes in the same row; the static electricity prevention units connected to two adjacent test electrodes in the same row are located in the first interval area;
[0010] An anti-static unit is connected between every two adjacent ones of the test electrodes in one column of the test electrodes.
[0011] In some embodiments, the test group is located on one side of the chip setting area along the second direction, and the second direction is the row direction in which the multiple test electrodes are arranged;
[0012] In the same test group, in the column of test electrodes that is farthest from the chip setting area, an anti-static unit is connected between every two adjacent ones of the test electrodes.
[0013] In some embodiments, an anti-static unit is connected between every two adjacent ones of the test electrodes in the first row and between every two adjacent ones of the test electrodes in the first column;
[0014] An anti-static unit is connected between the test electrode at the i-th row and the j-th column and the first connection line connected to the test electrode at the (i - 1)-th row and the first column; both i and j are integers greater than 1, i is less than or equal to the total number of rows of the test electrodes in the test group, and j is less than or equal to the total number of columns of the test electrodes in the test group.
[0015] In some embodiments, the non-display area includes a chip setting area, and the chip setting area is located on one side of the display area along the first direction; a plurality of pads are provided in the chip setting area; the first direction is the column direction in which the multiple test electrodes are arranged;
[0016] The test electrode is directly connected to the signal line and is electrically connected to the pad through a first connection line; there is a second spacer area between two adjacent test electrodes in the same column, and both the first connection line and the signal line are located outside the second spacer area.
[0017] In some embodiments, an anti-static unit is connected between every two adjacent ones of the test electrodes in the same column, and the anti-static units connected to two adjacent test electrodes in the same column are located in the second spacer area.
[0018] In some embodiments, an anti-static unit is connected between the signal lines connected to the test electrode at the first row and the m-th column and the test electrode at the last row and the (m + 1)-th column; m is an integer and is less than the total number of columns of the test electrodes in the test group.
[0019] In some embodiments, there is a third spacer area between every two adjacent columns of the test electrodes, the first connection line and the signal line are provided in the third spacer area, and the anti-static unit is located outside the third spacer area.
[0020] In some embodiments, the anti-static unit includes:
[0021] A first transistor, wherein a gate and a first pole of the first transistor are both electrically connected to a first transmission part of the anti-static unit;
[0022] A second transistor, wherein a gate and a first pole of the second transistor are both electrically connected to a second pole of the first transistor; a second pole of the second transistor is electrically connected to a second transmission part of the anti-static unit;
[0023] A third transistor, wherein a gate and a first pole of the third transistor are both electrically connected to the second transmission part, and a second pole of the third transistor is electrically connected to a first pole of the second transistor;
[0024] A fourth transistor, wherein a gate and a first pole of the fourth transistor are both electrically connected to a second pole of the third transistor; a second pole of the fourth transistor is electrically connected to the first transmission part;
[0025] Wherein, the first transmission part and the second transmission part are respectively used for connecting different test electrodes.
[0026] In some embodiments, the first transistor and the second transistor are both arranged along a third direction, the third transistor is located on one side of the second transistor along a fourth direction, the fourth transistor is located on one side of the first transistor along the fourth direction, the third direction is a direction from the first transmission part to the second transmission part; the fourth direction intersects with the third direction;
[0027] The anti-static unit further includes a first adapter, and a second pole of the first transistor, a gate and a first pole of the second transistor, a second pole of the third transistor, a gate and a first pole of the fourth transistor are all electrically connected to the first adapter.
[0028] In some embodiments, the first transmission part, the second transmission part, a gate of the first transistor, a gate of the second transistor, a gate of the third transistor, and a gate of the fourth transistor are all located in a first conductive layer, a first pole and a second pole of the first transistor, a first pole and a second pole of the second transistor, a first pole and a second pole of the third transistor, a first pole and a second pole of the fourth transistor are all located in a second conductive layer, and the second conductive layer is located on a side of the first conductive layer away from the substrate.
[0029] The first adapter is located on a side of the second conductive layer away from the substrate. The first adapter is electrically connected to a second pole of the first transistor through a first via hole, electrically connected to a gate of the second transistor through a second via hole, electrically connected to a first pole of the second transistor through a third via hole, electrically connected to a second pole of the third via hole through a fourth via hole, electrically connected to a first pole of the fourth transistor through a fifth via hole, and electrically connected to a gate of the fourth transistor through a sixth via hole.
[0030] The display substrate further includes a transparent electrode located in the display area. The first adapter is disposed on the same layer as the transparent electrode.
[0031] In some embodiments, the first transmission portion and a gate of the first transistor are formed integrally; a first pole of the first transistor and a second pole of the fourth transistor are formed integrally;
[0032] The anti-static unit further includes: a second adapter disposed on the same layer as the first adapter, and the second adapter is electrically connected to the first transmission portion and a first pole of the first transistor.
[0033] In some embodiments, the second transmission portion and a gate of the third transistor are formed integrally; a first pole of the third transistor and a second pole of the second transistor are formed integrally;
[0034] The anti-static unit further includes: a third adapter disposed on the same layer as the first adapter, and the third adapter is electrically connected to the second transmission portion and a first pole of the third transistor.
[0035] The present disclosure further provides a display device including the above-mentioned display substrate. Description of the Drawings
[0036] The drawings are used to provide a further understanding of the present disclosure, and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the drawings:
[0037] Figure 1 It is an overall schematic diagram of a display substrate provided in some embodiments.
[0038] Figure 2 For Figure 1 the circuit schematic diagram of the test group in
[0039] Figure 3 It is a schematic diagram of a display substrate provided in some embodiments of the present disclosure.
[0040] Figure 4 It is a schematic diagram of the connection between a test group and a pad provided in some embodiments of the present disclosure.
[0041] Figure 5 is Figure 4 The circuit schematic diagram of the test group in
[0042] Figure 6 The connection schematic diagram of the test group and the pad provided in some other embodiments of the present disclosure.
[0043] Figure 7 is Figure 6 The circuit schematic diagram of the test group in
[0044] Figure 8 The connection schematic diagram of the test group and the pad provided in still some other embodiments of the present disclosure.
[0045] Figure 9 is Figure 8 The circuit schematic diagram of the test group in
[0046] Figure 10 The circuit schematic diagram of the anti-static unit provided in some embodiments of the present disclosure.
[0047] Figure 11 The plan view of the anti-static unit provided in some embodiments of the present disclosure.
[0048] Figure 12 is Figure 11 The cross-sectional view along the line A-A' in
[0049] Figure 13 is Figure 11 The cross-sectional view along the line B-B' in
[0050] Figure 14 The plan view of the anti-static unit provided in a comparative example.
[0051] Figure 15 is Figure 14 The cross-sectional view along the line C-C' in
[0052] Figure 16 is Figure 14 The cross-sectional view along the line D-D' in Specific Embodiments
[0053] The following will describe in detail the specific embodiments of the present disclosure with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for the purpose of illustration and explanation of the present disclosure, and are not intended to limit the present disclosure.
[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following will clearly and completely describe the technical solutions of the embodiments of the present disclosure in conjunction with the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present disclosure.
[0055] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure shall have the ordinary meaning as understood by those of ordinary skill in the art belonging to the field of the present disclosure. The "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. Similarly, words such as "comprising" or "including" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. "Connection" or "coupling" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.
[0056] As used herein, "parallel" and "perpendicular" include the described situations and situations similar to the described situations, and the range of the similar situations is within an acceptable deviation range, where the acceptable deviation range is determined by those of ordinary skill in the art considering the measurements being discussed and the errors associated with the measurements of specific quantities (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism can be, for example, within 5° deviation; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, within 5° deviation.
[0057] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there may be an intermediate layer between the layer or element and the other layer or substrate.
[0058] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Accordingly, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing. Accordingly, the regions shown in the drawings are schematic in nature, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.
[0059] After the display panel is manufactured, electrical testing is usually performed to prevent defective display panels from entering the subsequent production process. Among them, a plurality of test electrodes are provided on the display panel, and each test electrode is electrically connected to a signal line. During testing, a test signal is input to the test electrode using a metal probe, and it is detected whether the display panel is normally lit. Since the metal probe carries a large voltage signal, a conductive path is formed when it contacts the test electrode, and relatively large static electricity may be generated. If the static electricity is not removed in time, the test electrode may be burned out. Therefore, an anti-static unit can be provided between some test electrodes to complete the transfer and transmission of large current signals between the test electrodes. Each time the large current signal passes through a test electrode, due to the capacitance and resistance of the anti-static unit itself, the current intensity will be partially attenuated.
[0060] Figure 1 It is an overall schematic diagram of a display substrate provided in some embodiments. Figure 2 For Figure 1 The circuit schematic diagram of the test group in Figure 1 As shown, the display substrate includes: a substrate 10 and a plurality of signal lines 40 and at least one test group TA provided on the substrate 10. The non-display area NA of the display panel includes a chip setting area WA located on one side of the display area AA along the first direction. Test groups TA are provided on both sides of the chip setting area WA along the second direction. The test group TA includes a plurality of test electrodes 20. Among them, in some products, the width of the non-display area NA is small. Therefore, the plurality of test electrodes 20 in the test group TA are arranged in at least three rows.
[0061] Among them, an anti-static unit 30 is connected between two adjacent test electrodes 20 in the same row. The anti-static unit 30 is used to transfer static electricity, so as to disperse static electricity in the same row. Among the plurality of signal lines 40, one is a common electrode line, and one of the plurality of test electrodes 20 is electrically connected to the common electrode line. Figure 2 In Figure 2In [the situation], when static electricity appears on the test electrode 20 in the third row, the static electricity can be transmitted through the anti-static unit 30 to the test electrode 20 connected to the common electrode line, and thus finally transmitted to the common electrode, thereby dispersing the static electricity. However, when static electricity appears on the test electrodes 20 in the first and second rows, this static electricity cannot be transmitted to the common electrode.
[0062] Figure 3 Schematic diagram of a display substrate provided in some embodiments of the present disclosure, Figure 4 Schematic diagram of the connection between a test group and pads provided in some embodiments of the present disclosure, Figure 5 is Figure 4 Circuit schematic diagram of the test group in [the figure], as Figure 3 shown, the display substrate includes: a substrate substrate 10 and a plurality of signal lines 40 and at least one test group TA provided on the substrate substrate 10. The test group TA is located in the non-display area NA and includes a plurality of test electrodes 20 arranged in M rows and N columns, where both M and N are integers greater than 2. Each test electrode 20 is connected to a signal line 40. Among them, the test electrode 20 can be directly connected to the signal line 40 or indirectly connected to the signal line 40 through other structures. The plurality of signal lines 40 can include a common electrode line and a plurality of driving signal lines 40 for providing driving signals to the gate driving circuit. The plurality of driving signal lines 40 can include a clock signal line 40 for providing a clock signal, a frame start signal line 40 for providing a frame start signal, a high-level signal line 40 for providing a high-level signal, a low-level signal line 40 for providing a low-level signal, and so on.
[0063] As Figure 4 and Figure 5 shown, the display substrate may further include a plurality of anti-static units 30 for transmitting static electricity. Among them, anti-static units 30 are connected between every two adjacent rows of test electrodes 20 and between every two adjacent columns of test electrodes 20, so that the plurality of test electrodes 20 are connected together through the plurality of anti-static units 30. In this case, when static electricity is generated on any one of the test electrodes 20 in the test group TA, the static electricity can be transmitted to the test electrode 20 connected to the common electrode line among the plurality of test electrodes 20, and thus finally transmitted to the common electrode through the test electrode 20 and the common electrode line, dispersing the static electricity.
[0064] In some embodiments, as Figure 3 shown, the non-display area NA includes a chip setting area WA, and the chip setting area WA is located on one side of the display area AA along the first direction; the first direction is the column direction in which the plurality of test electrodes 20 are arranged. Optionally, test groups TA are provided on both sides of the chip setting area WA along the second direction, where the second direction is perpendicular to the first direction.
[0065] As Figure 4As shown, multiple pads PAD are provided in the chip setting area WA, and the multiple pads PAD are used for bonding with the driving chip. For example, the multiple pads PAD include multiple first pads PAD1 and multiple second pads PAD2. The multiple first pads PAD1 are located on the side of the multiple second pads PAD2 away from the display area AA, and there may be a spacer area between the multiple first pads PAD1 and the multiple second pads PAD2. Optionally, the multiple first pads PAD1 are bonded and connected to the multiple input electrodes of the driving chip, and the multiple second pads PAD2 are bonded and connected to the multiple output electrodes of the driving chip.
[0066] Among them, as Figure 4 and Figure 5 shown, each test electrode 20 is electrically connected to a pad PAD through a first connection line 51, and each pad PAD is electrically connected to a signal line 40, so that the test electrode 20 is indirectly connected to the corresponding signal line 40 through the first connection line 51 and the pad PAD. Among them, there is a first spacer area SA1 between two adjacent test electrodes 20 in the same row, and the first connection line 51 is located outside the first spacer area SA1. For example, taking the row of test electrodes 20 closest to the display area AA in the test group TA as the first row of test electrodes 20, and the row of test electrodes 20 farthest from the display area AA as the last row of test electrodes 20; taking the column of test electrodes 20 closest to the display area AA in the test group TA as the last column of test electrodes 20, and the column of test electrodes 20 farthest from the display area AA as the first column of test electrodes 20. The first connection line 51 connected to each test electrode 20 includes a connected first trace portion 511 and a second trace portion 512. The first trace portion 511 is electrically connected to the test electrode 20, at least part of the first trace portion 511 is located on one side of the test electrode 20 along the first direction, a part of the second trace portion 512 is located in the spacer area between the multiple first pads PAD1 and the multiple second pads PAD2, and the second trace portion 512 is electrically connected to the second pad PAD2.
[0067] In some embodiments, an electrostatic protection unit 30 is connected between every two adjacent test electrodes 20 in the same row; the electrostatic protection units 30 connected to two adjacent test electrodes 20 in the same row are located in the first spacer area SA1. An electrostatic protection unit 30 is connected between every two adjacent test electrodes 20 in one column of test electrodes 20. For example, in each test group TA, in the column of test electrodes 20 farthest from the chip setting area WA, an electrostatic protection unit 30 is connected between every two adjacent test electrodes 20; no electrostatic protection unit 30 is provided between adjacent test electrodes 20 in the remaining columns to facilitate wiring.
[0068] In one example, in a column of test electrodes 20 that is farthest from the chip setting area WA, both ends of the electrostatic protection unit 30 between the i-th row and the (i - 1)-th row can be respectively connected to the first connection line 51 corresponding to the test electrodes 20 in the (i - 1)-th row and the test electrodes 20 in the i-th row. i is an integer greater than 1 and less than or equal to the total number of rows of the test electrodes 20 in the test group TA.
[0069] Figure 6 Schematic diagram of the connection between the test group and the pads provided in other embodiments of the present disclosure, Figure 7 is Figure 6 the circuit schematic diagram of the test group in. In other embodiments, as Figure 6 and Figure 7 shown, similar to Figure 4 , each test electrode 20 is electrically connected to a pad PAD through a first connection line 51, and each pad PAD is electrically connected to a signal line 40, so that the test electrode 20 is indirectly connected to the corresponding signal line 40 through the first connection line 51 and the pad PAD. Among them, there is a first spacer SA1 between two adjacent test electrodes 20 in the same row, and the first connection line 51 is located outside the first spacer SA1. The first connection line 51 connected to each test electrode 20 includes adjacent first trace portions 511 and second trace portions 512. The first trace portion 511 is electrically connected to the test electrode 20, at least part of the first trace portion 511 is located on one side of the test electrode 20 along the first direction, a part of the second trace portion 512 is located in the spacer area between the plurality of first pads PAD1 and the plurality of second pads PAD2, and the second trace portion 512 is electrically connected to the second pad PAD2.
[0070] Different from Figure 4 , in Figure 6 and Figure 7 , an electrostatic protection unit 30 is connected between every two adjacent test electrodes 20 in the first row and between every two adjacent test electrodes 20 in the first column. An electrostatic protection unit 30 is connected between the first connection line 51 connected to the test electrode 20 in the i-th row and j-th column and the first connection line 51 connected to the test electrode 20 in the (i - 1)-th row and the first column; both i and j are integers greater than 1.
[0071] In addition, in Figure 6 and Figure 7 , the electrostatic protection unit 30 is not placed in the first spacer SA1 between two adjacent test electrodes 20 in the same row, but the electrostatic protection unit 30 is arranged on one side of the test electrode 20 along the first direction. For example, it is arranged above or below the test electrode 20 in Figure 6 and Figure 7 .
[0072] In Figure 6 andFigure 7 In [the figure], since no static electricity prevention unit 30 is placed in the first spacer SA1 between two adjacent test electrodes 20 in the same row, the width of the test group TA in the second direction can be reduced, which is beneficial to reducing the border width of the display substrate.
[0073] Figure 8 The following is a schematic diagram of the connection between the test group and the pad provided in some other embodiments of the present disclosure. Figure 9 For Figure 8 the circuit schematic diagram of the test group in [the figure], as Figure 8 and Figure 9 shown, the test electrode 20 is electrically connected to the pad PAD through the first connection line 51 and is directly connected to the signal line 40. For example, one end of the first connection line 51 is connected to the test electrode 20, and the other end is electrically connected to the first pad PAD1. There is a second spacer SA2 between two adjacent test electrodes 20 in the same column, and a static electricity prevention unit 30 can be arranged in the second spacer SA2, while the first connection line 51 is located outside the second spacer SA2 to facilitate wiring.
[0074] Among them, as Figure 8 shown, there is a third spacer SA3 between every two adjacent columns of test electrodes 20, and the first connection line 51 and the signal line 40 are arranged in the third spacer SA3, and the static electricity prevention unit 30 is located outside the third spacer SA3 to prevent overcrowding of the structure in the third spacer SA3.
[0075] As Figure 8 and Figure 9 shown, static electricity prevention units 30 are connected between every two adjacent test electrodes 20 in the same column, and the static electricity prevention units 30 connected to two adjacent test electrodes 20 in the same column are located in the second spacer SA2.
[0076] As Figure 8 and Figure 9 shown, a static electricity prevention unit 30 is connected between the signal lines 40 of the test electrode 20 located in the first row and the mth column and the test electrode 20 located in the last row and the (m + 1)th column. Through the static electricity prevention units 30 between every two adjacent test electrodes 20 in each column and the static electricity prevention unit 30 connected between the test electrodes 20 in the first row and the mth column and the last row and the (m + 1)th column, multiple test electrodes 20 in the same test group TA can be connected together. m is an integer and is less than the total number of columns of the test electrodes 20 in the test group TA.
[0077] Figure 10 The following is the circuit schematic diagram of the static electricity prevention unit provided in some embodiments of the present disclosure. Figure 11 The following is the plan view of the static electricity prevention unit provided in some embodiments of the present disclosure. Figure 12 For Figure 11Cross-sectional view along line A-A' in Figure 13 is a cross-sectional view along Figure 11 line B-B' in
[0078] As Figures 10 to 13 shown, the anti-static unit 30 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. Among them, the gate T1_g and the first pole T1_1 of the first transistor T1 are both electrically connected to the first transmission part TR1 of the anti-static unit 30. The gate T2_g and the first pole T2_1 of the second transistor T2 are both electrically connected to the second pole T1_2 of the first transistor T1; the second pole T2_2 of the second transistor T2 is electrically connected to the second transmission part TR2 of the anti-static unit 30. The gate T3_g and the first pole T3_1 of the third transistor T3 are both electrically connected to the second transmission part TR2, and the second pole T3_2 of the third transistor T3 is electrically connected to the first pole T2_1 of the second transistor T2. The gate T4_g and the first pole T4_1 of the fourth transistor T4 are both electrically connected to the second pole T3_2 of the third transistor T3; the second pole T4_2 of the fourth transistor T4 is electrically connected to the first transmission part TR1. The first transmission part TR1 and the second transmission part TR2 are respectively used to connect different test electrodes 20.
[0079] It should be noted that the first transmission part TR1 can be directly connected to the test electrode 20 or indirectly connected. In the above embodiment, both ends of the anti-static unit 30 can be directly connected to two test electrodes 20. At this time, the first transmission part TR1 and the second transmission part TR2 are respectively connected to two test electrodes 20; or, one end of the anti-static unit 30 is connected to one test electrode 20, and the other end is connected to the first connection line 51 corresponding to the other test electrode 20. At this time, one of the first transmission part TR1 and the second transmission part TR2 is connected to one test electrode 20, and the other is connected to the first connection line 51 corresponding to the other test electrode 20.
[0080] When there is a large amount of static electricity on the test electrode 20 connected to the first transmission part TR1, the first transistor T1 and the second transistor T2 are turned on, so as to transfer the static electricity to the test electrode 20 connected to the second transmission part TR2; when there is a large amount of static electricity on the test electrode 20 connected to the second transmission part TR2, the third transistor T3 and the fourth transistor T4 are turned on, so as to transfer the static electricity to the test electrode 20 connected to the first transmission part TR1.
[0081] In Figure 11Among them, the first transistor T1 and the second transistor T2 are both arranged along the third direction. The third transistor T3 is located on one side of the second transistor T2 along the fourth direction, and the fourth transistor T4 is located on one side of the first transistor T1 along the fourth direction. The third direction is the direction from the first transmission part TR1 to the second transmission part TR2; the fourth direction intersects with the third direction, for example, they are perpendicular to each other. The electrostatic protection unit 30 further includes a first adapter TL1. The second pole T1_2 of the first transistor T1, the gate T2_g and the first pole T2_1 of the second transistor T2, the second pole T3_2 of the third transistor T3, the gate T4_g and the first pole T4_1 of the fourth transistor T4 are all electrically connected to the first adapter TL1.
[0082] As Figure 12 and Figure 13 shown, the display substrate includes a first conductive layer, a gate insulating layer GI, a semiconductor layer, a second conductive layer, a planarization layer PLN, and a third conductive layer that are sequentially disposed on the substrate 10 and along a direction away from the substrate 10. The first conductive layer and the second conductive layer can be made of metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. For example, the first conductive layer and the second conductive layer can include gold (Au), an alloy of gold, silver (Ag), an alloy of silver, aluminum (Al), an alloy of aluminum, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), an alloy of copper, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), an alloy of molybdenum, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. The first conductive layer and the second conductive layer can have a single layer or multiple layers. The gate insulating layer GI can include a silicon compound and a metal oxide. For example, the gate insulating layer GI can include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbonitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The gate insulating layer GI can be formed into a single layer or multiple layers. The planarization layer PLN can be made of an organic material. The third conductive layer can be made of a transparent conductive material, for example, indium tin oxide (ITO). Among them, the third conductive layer can be disposed on the same layer as the transparent electrode (such as a pixel electrode or a common electrode) in the display area AA.
[0083] The first transmission part TR1, the second transmission part TR2, the gate T1_g of the first transistor T1, the gate T2_g of the second transistor T2, the gate T3_g of the third transistor T3, and the gate T4_g of the fourth transistor T4 are all located in the first conductive layer; the active layers (T1_a to T4_a) of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all located in the semiconductor layer; the first pole T1_1 and the second pole T1_2 of the first transistor T1, the first pole T2_1 and the second pole T2_2 of the second transistor T2, the first pole T3_1 and the second pole T3_2 of the third transistor T3, and the first pole T4_1 and the second pole T4_2 of the fourth transistor T4 are all located in the second conductive layer, and the second conductive layer is located on the side of the first conductive layer away from the substrate 10.
[0084] The first adapter TL1 is located on the side of the second conductive layer away from the substrate 10. The first adapter TL1 is electrically connected to the second pole of the first transistor T1 through the first via V1, electrically connected to the gate T2_g of the second transistor T2 through the second via V2, electrically connected to the first pole T2_1 of the second transistor T2 through the third via V3, electrically connected to the second pole T3_2 of the third transistor T3 through the fourth via V4, electrically connected to the first pole T4_1 of the fourth transistor T4 through the fifth via V5, and electrically connected to the gate T4_g of the fourth transistor T4 through the sixth via V6, thereby connecting the second pole T1_2 of the first transistor T1, the gate T2_g and the first pole T2_1 of the second transistor T2, the second pole T3_2 of the third transistor T3, and the first pole T4_1 of the fourth transistor T4 together.
[0085] As Figure 12 and Figure 13 shown, the first transmission part TR1 is formed integrally with the gate of the first transistor T1; the first pole T1_1 of the first transistor T1 is formed integrally with the second pole T4_2 of the fourth transistor T4; the electrostatic protection unit 30 further includes: a second adapter TL2 provided on the same layer as the first adapter TL1, and the second adapter TL2 is electrically connected to the first transmission part TR1 and the first pole T1_1 of the first transistor T1. Among them, the second adapter TL2 is electrically connected to the first transmission part TR1 through the seventh via V7 and electrically connected to the first pole T1_1 of the first transistor T1 through the eighth via V8.
[0086] As Figure 12 and Figure 13As shown, the second transmission part TR2 and the gate T3_g of the third transistor T3 are formed integrally; the first pole T3_1 of the third transistor T3 and the second pole T2_2 of the second transistor T2 are formed integrally. The static electricity prevention unit 30 further includes: a third adapter TL3 disposed on the same layer as the first adapter TL1, and the third adapter TL3 is electrically connected to the second transmission part TR2 and the first pole T3_1 of the third transistor T3. Among them, the third adapter TL3 is electrically connected to the second transmission part TR2 through the ninth via V9 and is electrically connected to the first pole T3_1 of the third transistor T3 through the tenth via V10.
[0087] Figure 14 is a plan view of the static electricity prevention unit provided in a comparative example, Figure 15 is along Figure 14 the cross-sectional view taken along the line C-C' in Figure 16 is along Figure 14 the cross-sectional view taken along the line D-D' in
[0088] As Figure 14 shown, the static electricity prevention unit 30 also includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4, and the circuit connection relationship of the four transistors is as Figure 10 shown. The same as Figures 11 to 13 in Figures 14 to 16 the gates of the first transistor T1 to the fourth transistor T4 are located in the first conductive layer, the active layer is located in the semiconductor layer, and the source and drain are located in the second conductive layer. The first transmission part TR1 and the gate T1_g of the first transistor T1 are formed integrally, and the second transmission part TR2 and the gate T3_g of the third transistor T3 are formed integrally.
[0089] Different from Figures 11 to 13 in Figures 14 to 16Among them, the first transistor T1 and the fourth transistor T4 are arranged along the third direction, the second transistor T2 and the third transistor T3 are arranged along the third direction, the second transistor T2 and the first transistor T1 are arranged along the fourth direction, and the third transistor T3 and the fourth transistor T4 are arranged along the fourth direction. The gate T2_g of the second transistor T2 and the gate T4_g of the fourth transistor T4 are formed integrally. In addition, the electrostatic protection unit 30 further includes: a first connection member L1 and a second connection member L2 located in the second conductive layer. One end of the first connection member L1 is electrically connected to the first pole T1_1 of the first transistor T1, and the other end is electrically connected to the second pole T4_2 of the fourth transistor T4; wherein, the first connection member L1, the first pole T1_1 of the first transistor T1, and the second pole T4_2 of the fourth transistor T4 are formed into an integral structure. One end of the second connection member L2 is electrically connected to the second pole T2_2 of the second transistor T2, and the other end is electrically connected to the first pole T3_1 of the third transistor T3; wherein, the second connection member L2, the second pole T2_2 of the second transistor T2, and the first pole T3_1 of the third transistor T3 can be formed into an integral structure. The orthographic projections of the gates of the four transistors on the substrate 10 are all located between the orthographic projections of the first connection member L1 and the second connection member L2 on the substrate 10.
[0090] In Figures 14 to 16 Among them, the electrostatic protection unit 30 further includes a fourth transfer member TL4, a fifth transfer member TL5, a second transfer member TL2, and a third transfer member TL3 located in the third conductive layer. The second transfer member TL2 is electrically connected to the first transmission part TR1 through the seventh via V7 and electrically connected to the first pole T1_1 of the first transistor T1 through the eighth via V8. The third transfer member TL3 is electrically connected to the second transmission part TR2 through the ninth via V9 and electrically connected to the first pole T3_1 of the third transistor T3 through the tenth via V10. The fourth transfer member TL4 is electrically connected to the second pole T1_2 of the first transistor T1 through the first via V1, electrically connected to the first pole T4_1 of the fourth transistor T4 through the fifth via V5, and electrically connected to the gate T4_g of the fourth transistor T4 through the sixth via V6. The fifth transfer member TL5 is electrically connected to the gate T2_g of the second transistor T2 through the second via V2, electrically connected to the first pole T2_1 of the second transistor T2 through the third via V3, and electrically connected to the second pole T3_2 of the third transistor T3 through the fourth via V4, thereby connecting the second pole T1_2 of the first transistor T1, the gate T2_g and the first pole T2_1 of the second transistor T2, the second pole T3_2 of the third transistor T3, and the first pole T4_1 of the fourth transistor T4 together.
[0091] Compared with Figures 14 to 16 In Figures 11 to 13In this case, there is no need to provide the first connecting member L1 and the second connecting member L2, so that the width of the anti-static unit 30 (i.e., the dimension of the anti-static unit 30 in the fourth direction) can be reduced, and thus the area occupied by the anti-static unit 30 can be reduced, saving the wiring space. In one example, Figures 14 to 16 the width of the anti-static unit 30 in [case] is 84 μm, Figures 11 to 13 the width of the anti-static unit 30 in [another case] can be reduced to 51 μm.
[0092] An embodiment of the present disclosure further provides a display device, which includes the display substrate in the above embodiment.
[0093] The display device in the embodiment of the present disclosure may include any device or product with a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, electronic accessories, an electronic tattoo, or a smart watch), a television, etc.
[0094] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present disclosure. However, the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the present disclosure.
Claims
1. A display substrate having a display area and a non-display area located around the display area, characterized in that, The display substrate includes: a substrate substrate; a plurality of signal lines and at least one test group disposed on the substrate substrate, the test group being located in the non-display area and including a plurality of test electrodes arranged in M rows and N columns; each of the test electrodes is connected to one signal line; both M and N are integers greater than 2; a plurality of anti-static units for transmitting static electricity; wherein, the anti-static units are connected between every two adjacent rows of the test electrodes and between every two adjacent columns of the test electrodes, so that the plurality of test electrodes are connected together through the plurality of anti-static units.
2. The display substrate according to claim 1, wherein The non-display area includes a chip setting area, and the chip setting area is located on one side of the display area along a first direction; a plurality of pads are provided in the chip setting area; the first direction is the column direction in which the plurality of test electrodes are arranged; The test electrode is electrically connected to the pad through a first connection line, and the pad is electrically connected to the signal line, so that the test electrode is connected to the signal line through the first connection line and the pad; there is a first interval area between two adjacent test electrodes in the same row, and the first connection line is located outside the first interval area.
3. The display substrate according to claim 2, wherein The anti-static units are connected between every two adjacent test electrodes in the same row; the anti-static units connected to two adjacent test electrodes in the same row are located in the first interval area; The anti-static units are connected between every two adjacent test electrodes in one column of the test electrodes.
4. The display substrate according to claim 3, wherein The test group is located on one side of the chip setting area along a second direction, and the second direction is the row direction in which the plurality of test electrodes are arranged; In the same test group, in the column of test electrodes farthest from the chip setting area, the anti-static units are connected between every two adjacent test electrodes.
5. The display substrate according to claim 2, wherein The anti-static units are connected between every two adjacent test electrodes in the first row and between every two adjacent test electrodes in the first column; An anti-static unit is connected between the test electrode located in the i-th row and j-th column and the first connection line connected to the test electrode located in the (i-1)-th row and first column; Both i and j are integers greater than 1, i is less than or equal to the total number of rows of the test electrodes in the test group, and j is less than or equal to the total number of columns of the test electrodes in the test group.
6. The display substrate according to claim 1, characterized in that The non-display area includes a chip setting area, and the chip setting area is located on one side of the display area along a first direction; a plurality of pads are provided in the chip setting area; the first direction is the column direction in which the plurality of test electrodes are arranged; The test electrode is directly connected to the signal line and electrically connected to the pad through a first connection line; there is a second interval area between two adjacent test electrodes in the same column, and both the first connection line and the signal line are located outside the second interval area.
7. The display substrate according to claim 6, wherein The anti-static units are connected between every two adjacent test electrodes in the same column, and the anti-static units connected to two adjacent test electrodes in the same column are located in the second interval area.
8. The display substrate according to claim 7, wherein An anti-static unit is connected between a signal line connected to a test electrode located in the first row and the m-th column and a signal line connected to a test electrode located in the last row and the (m + 1)-th column; m is an integer and less than the total number of columns of the test electrodes in the test group.
9. The display substrate according to claim 6, wherein There is a third spacer region between every two adjacent columns of the test electrodes. The first connection line and the signal line are arranged in the third spacer region, and the anti-static unit is located outside the third spacer region.
10. The display substrate according to any one of claims 1 to 9, characterized in that, The anti-static unit includes: A first transistor, the gate and the first pole of the first transistor are both electrically connected to the first transmission part of the anti-static unit; A second transistor, the gate and the first pole of the second transistor are both electrically connected to the second pole of the first transistor; the second pole of the second transistor is electrically connected to the second transmission part of the anti-static unit; A third transistor, the gate and the first pole of the third transistor are both electrically connected to the second transmission part, and the second pole of the third transistor is electrically connected to the first pole of the second transistor; A fourth transistor, the gate and the first pole of the fourth transistor are both electrically connected to the second pole of the third transistor; the second pole of the fourth transistor is electrically connected to the first transmission part; Wherein, the first transmission part and the second transmission part are respectively used for connecting different test electrodes.
11. The display substrate according to claim 10, characterized in that, The first transistor and the second transistor are both arranged along a third direction. The third transistor is located on one side of the second transistor along a fourth direction, and the fourth transistor is located on one side of the first transistor along the fourth direction. The third direction is the direction from the first transmission part to the second transmission part; the fourth direction intersects with the third direction; The anti-static unit further includes a first adapter. The second pole of the first transistor, the gate and the first pole of the second transistor, the second pole of the third transistor, the gate and the first pole of the fourth transistor are all electrically connected to the first adapter.
12. The display substrate according to claim 11, wherein The first transmission part, the second transmission part, the gate of the first transistor, the gate of the second transistor, the gate of the third transistor and the gate of the fourth transistor are all located in a first conductive layer. The first pole and the second pole of the first transistor, the first pole and the second pole of the second transistor, the first pole and the second pole of the third transistor, the first pole and the second pole of the fourth transistor are all located in a second conductive layer. The second conductive layer is located on a side of the first conductive layer away from the substrate. The first adapter is located on a side of the second conductive layer away from the substrate. The first adapter is electrically connected to the second pole of the first transistor through a first via, electrically connected to the gate of the second transistor through a second via, electrically connected to the first pole of the second transistor through a third via, electrically connected to the second pole of the third via through a fourth via, electrically connected to the first pole of the fourth transistor through a fifth via, and electrically connected to the gate of the fourth transistor through a sixth via; The display substrate further includes a transparent electrode located in the display area, and the first adapter is arranged on the same layer as the transparent electrode.
13. The display substrate according to claim 11, wherein The first transmission part is formed integrally with the gate of the first transistor; the first pole of the first transistor is formed integrally with the second pole of the fourth transistor; The static electricity prevention unit further includes: a second adapter disposed on the same layer as the first adapter, and the second adapter is electrically connected to the first transmission part and the first pole of the first transistor.
14. The display substrate according to claim 11, wherein The second transmission part is formed integrally with the gate of the third transistor; the first pole of the third transistor is formed integrally with the second pole of the second transistor; The static electricity prevention unit further includes: a third adapter disposed on the same layer as the first adapter, and the third adapter is electrically connected to the second transmission part and the first pole of the third transistor.
15. A display device, characterized in that, A display substrate according to any one of claims 1 to 14.