Array substrate, light-emitting substrate and display device

Abstract

The invention discloses an array substrate, a light-emitting substrate and a display device, and belongs to the field of display. The array substrate comprises a substrate body (900), a first conductive layer (100) and a second conductive layer (200) which are insulated from each other are arranged on the substrate body (900) in a stacked mode, and the array substrate further comprises a plurality of light-emitting element terminal sets (10) arranged on the second conductive layer (200) in an array mode and used for being connected with light-emitting elements. A plurality of sensor terminal sets (30) located on the second conductive layer 200 (200) are further arranged and used for being connected with sensors, and the sensors are used for sensing the light-emitting elements so that the light-emitting conditions of the surrounding light-emitting elements can be rapidly and effectively monitored, various parameters such as the light-emitting elements can be adjusted more precisely in time, and it is ensured that the performance of the light-emitting elements is stable.

Description

[0001] This disclosure is a divisional application. The application number of the original application is 202180000440.5, the application date is March 10, 2021, and the invention title is "Array Substrate, Light-Emitting Substrate, and Display Device". Technical Field

[0002] This disclosure relates to the field of display technologies, and more particularly, to an array substrate, a light-emitting substrate, and a display device. Background Art

[0003] MiniLED, also known as sub-millimeter light-emitting diodes, has a chip size of approximately between 100 and 300 um; while MicroLED has a chip size of less than 100 um. Currently, the research and development of the applications of MiniLED and MicroLED in the backlight field and the display field are continuously deepening in order to achieve products with better quality.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of this disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] The purpose of this disclosure is to overcome the deficiencies of the above prior art and provide an array substrate, a light-emitting substrate, and a display device.

[0006] According to one aspect of this disclosure, an array substrate is provided, which includes a substrate, and a first conductive layer and a second conductive layer that are stacked and insulated from each other on the substrate. Wherein, the array substrate further includes:

[0007] A plurality of light-emitting element terminal groups arranged in an array, disposed on the second conductive layer, and used for coupling with light-emitting elements;

[0008] A plurality of sensor terminal groups, disposed on the second conductive layer, and used for coupling with sensors;

[0009] The orthographic projection of the sensor terminal group on the substrate does not overlap with the orthographic projection of the light-emitting element terminal group on the substrate; the sensor terminal group includes an input terminal and an output terminal; the corresponding sensor includes an input pin and an output pin, the input terminal is used for electrically connecting with the input pin, and the output terminal is used for electrically connecting with the output pin;

[0010] A first signal line group, disposed on the first conductive layer, electrically connected to the sensor terminal group, and used for driving the sensor to sense;

[0011] A second signal line group, disposed on the first conductive layer, electrically connected to the light-emitting element terminal group, and used for driving the light-emitting element to emit light;

[0012] A plurality of light-emitting element terminal groups are connected in series, and the sensor terminal group is located outside the polygon corresponding to the plurality of light-emitting element terminal groups connected in series; the polygon corresponding to the plurality of light-emitting element terminal groups connected in series is a polygon obtained by sequentially connecting the positions of the plurality of outermost light-emitting element terminal groups in the plurality of light-emitting element terminal groups connected in series. According to an embodiment of the present disclosure, four light-emitting element terminal groups are connected in series; the polygon corresponding to the four light-emitting element terminal groups connected in series is a quadrilateral.

[0013] According to an embodiment of the present disclosure, two of the sides of the quadrilateral are parallel to the row direction, and the other two sides are parallel to the column direction;

[0014] Alternatively, two opposite sides of the quadrilateral form an angle with the row direction, and the other two opposite sides form an angle with the column direction.

[0015] According to an embodiment of the present disclosure, the array substrate further includes:

[0016] A driving circuit terminal group is provided on the second conductive layer for coupling with a driving circuit; the orthographic projection of the driving circuit terminal group on the substrate has no overlap with the orthographic projections of the light-emitting element terminal group and the sensor terminal group on the substrate.

[0017] According to an embodiment of the present disclosure, the driving circuit terminal group is located outside the polygon corresponding to the plurality of light-emitting element terminal groups connected in series.

[0018] According to an embodiment of the present disclosure, each of the light-emitting elements coupled to a plurality of light-emitting element terminal groups connected in series forms a light-emitting unit;

[0019] The array substrate can be used to form P rows and Q columns of the light-emitting units, and each driving circuit terminal group drives one of the light-emitting units;

[0020] Among them, the positions of the driving circuit terminal groups corresponding to the four light-emitting units with coordinates (a, b), (a + 1, b), (a + 1, b + 1), and (a, b + 1) are sequentially connected to form a convex quadrilateral; the convex quadrilateral is composed of two triangles;

[0021] The light-emitting unit with coordinates (a, b) is the light-emitting unit in the a-th row and the b-th column;

[0022] The light-emitting unit with coordinates (a + 1, b) is the light-emitting unit in the (a + 1)-th row and the b-th column;

[0023] The light-emitting unit with coordinates (a, b + 1) is the light-emitting unit in the a-th row and the (b + 1)-th column;

[0024] The light-emitting unit with coordinates (a + 1, b + 1) is the light-emitting unit in the (a + 1)-th row and the (b + 1)-th column;

[0025] where 1 ≤ a ≤ P - 1, 1 ≤ b ≤ Q - 1, and both a and b are positive integers.

[0026] According to an embodiment of the present disclosure, the two triangles are two isosceles triangles or two equilateral triangles;

[0027] The isosceles triangle or the equilateral triangle is formed by connecting the positions of three of the four driving circuit terminal groups corresponding to the light-emitting units in sequence.

[0028] According to an embodiment of the present disclosure, the line connecting the centers of gravity of two adjacent triangles arranged in the same row is parallel to the row direction; and / or, the line connecting the centers of gravity of two adjacent triangles arranged in the same column is parallel to the column direction.

[0029] According to another aspect of the present disclosure, there is provided a light-emitting substrate, including:

[0030] The above-described array substrate;

[0031] Light-emitting elements, coupled to the light-emitting element terminal group of the array substrate;

[0032] Sensors, coupled to the sensor terminal group of the array substrate.

[0033] According to still another aspect of the present disclosure, there is provided a display device including the above-described light-emitting substrate.

[0034] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0036] Figure 1 It is a partial structural schematic diagram of an array substrate of a mini LED according to the present disclosure;

[0037] Figure 2 is Figure 1 a partial enlarged schematic diagram of the M area in

[0038] Figure 3 is a schematic diagram of the arrangement of light-emitting units;

[0039] Figure 4 It is a schematic structural diagram of a sensor terminal group;

[0040] Figure 5 It is Figure 4 a schematic cross-sectional view taken along the A-A direction in

[0041] Figure 6 a schematic diagram showing the arrangement of a sensor terminal group and signal lines;

[0042] Figure 7 It shows Figure 6 a schematic structural diagram of the first conductive layer of

[0043] Figure 8 a schematic diagram showing the arrangement of signal lines of the sensor terminal group in an embodiment;

[0044] Figure 9 It shows Figure 8 a schematic partial structure diagram of the array substrate;

[0045] Figure 10 It is Figure 9 a schematic enlarged partial view of the M area in

[0046] Figure 11 It is Figure 9 a schematic structural diagram of a sensor terminal group in

[0047] Figure 12 It shows Figure 9 the wiring diagram of the first conductive layer in

[0048] Figure 13 a schematic structural diagram of the first lead;

[0049] Figure 14 a schematic diagram showing the arrangement of signal lines of the sensor terminal group in yet another embodiment;

[0050] Figure 15 It shows Figure 14 a schematic partial structure diagram of the array substrate;

[0051] Figure 16 It is Figure 14 a schematic structural diagram of a sensor terminal group in

[0052] Figure 17 It shows Figure 14 the wiring of the first conductive layer in

[0053] Figure 18 It shows Figure 14 a schematic diagram of the transmission paths of input and output signals in

[0054] Figure 19 Shows a partial structural schematic diagram of an array substrate in yet another embodiment;

[0055] Figure 20 is Figure 19 a partial enlarged schematic diagram of area M in

[0056] Figure 21 is Figure 19 a structural schematic diagram of a sensor terminal group in

[0057] Figure 22 is Figure 19 a partial enlarged schematic diagram of area M including a capacitor terminal group in

[0058] Figure 23 a structural schematic diagram of a capacitor terminal group.

[0059] Description of reference numerals:

[0060] 100, first conductive layer; 200, second conductive layer; 300, insulating layer; 400, insulating layer; 900, substrate; 10, light-emitting element terminal group; 11, anode terminal; 12, cathode terminal; 101, light-emitting unit; 20, driving circuit terminal group; 21, input terminal; 22, power supply terminal; 23, output terminal; 24, first common voltage terminal; 30, sensor terminal group; 31, input terminal; 32, output terminal; 33, power supply terminal; 34, second common voltage terminal; 40, capacitor terminal group; 41, first capacitor terminal; 42, second capacitor terminal; 101, input signal line; 102, output signal line; 103, power supply signal line; 104, first common voltage signal line; 105, first lead; 1051, first column lead; 1052, first row lead; 106, second lead; 107, third lead; 108, fourth lead; 201, second common voltage signal line; 202, driving voltage signal line; 203, power line; 204, source address line; 205, auxiliary common voltage signal line; 5, slot. Detailed implementation manners

[0061] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote the same or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic diagrams provided for the embodiments of the present disclosure and are not necessarily drawn to scale.

[0062] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component described as "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0063] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second", "third", etc. are used only as labels and are not a limitation on the quantity of their objects.

[0064] Embodiments of the present disclosure provide an array substrate on which light-emitting elements can be bonded to serve as a backlight source of a Mini-LED display device. A sensor can also be bonded to the array substrate to sense the light-emitting performance of the light-emitting elements, facilitating monitoring of the light-emitting condition of the backlight source.

[0065] In the embodiments of the present disclosure, Figure 1 is a schematic partial structure diagram of an array substrate of a mini LED of the present disclosure, Figure 2 is Figure 1 a partial enlarged schematic diagram of the M area in Figure 3 is a schematic structure diagram of a sensor terminal group, Figure 4 is Figure 3 a cross-sectional schematic diagram taken along the A-A direction in Figures 1 - 4 Referring to

[0066] In the embodiments of the present disclosure, the first conductive layer 100 is used to arrange various signal lines, including a first signal line group for driving a sensor and a second signal line group for the light-emitting element to emit light. In some embodiments, a stacked structure of MoNb / Cu / MoNb can be formed in sequence by a sputtering process, where the bottom MoNb is used to improve adhesion, the top MoNb is used for anti-oxidation, and the middle layer Cu serves as the main part of the signal line. The material has the characteristic of low resistivity. At the same time, the width and thickness of the signal line can be further increased to further reduce the resistance of the signal line. In other embodiments, the middle layer Cu can be formed by an electroplating process. Then, the bottom layer can be made of MoNiTi as a seed layer by a sputtering process to increase the nucleation density of metal Cu grains during electroplating. Finally, an anti-oxidation layer of MoNiTi or MoNb can be formed by a sputtering process.

[0067] The second conductive layer 200 is provided with a plurality of light-emitting element terminal groups 10 coupled to the light-emitting elements. The second conductive layer 200 is also provided with a plurality of sensor terminal groups 30 connected to the sensors. The sensor terminal groups 30 are distributed between the light-emitting element terminal groups 10, and the orthographic projection of the sensor terminal groups 30 on the substrate has no overlap with the orthographic projection of the light-emitting element terminal groups 10 on the substrate. The second conductive layer 200 can form a stacked structure of MoNb / Cu / CuNi in sequence by a sputtering process, where the bottom MoNb is used to improve adhesion, and the top surface uses CuNi to balance anti-oxidation and die bonding firmness.

[0068] It should be noted that the light-emitting element terminal group 10 of the present disclosure is used to electrically connect the light-emitting element to the second signal line group on the substrate. The light-emitting element can be bonded to the array substrate by welding. Therefore, the light-emitting element terminal group 10 can be a pad group. The light-emitting element can also be directly prepared on the substrate by a film-forming process. Therefore, the light-emitting element terminal group 10 can also be an electrode group that plays a conductive role. Similarly, the sensor terminal group 30 of the present disclosure can also be a pad group or an electrode group.

[0069] Setting a sensor on the array substrate can quickly and effectively monitor the light-emitting conditions of the surrounding light-emitting elements, so as to timely and more precisely adjust various parameters such as the current, voltage, and brightness of the light-emitting elements to ensure the stable performance of each light-emitting element.

[0070] Sensors can be of various types according to their functions. For example, the sensor can be a temperature sensor to detect the temperature of the surrounding light-emitting elements, and timely adjust parameters such as voltage and current to avoid system insensitivity caused by overheating or wire breakage caused by too high voltage or current. The sensor can also be a photosensitive sensor to detect the brightness of the surrounding light-emitting elements, and timely adjust the brightness of each light-emitting element to make the brightness of each light-emitting element consistent and stably emit light. In one embodiment, the sensor can be an integrated sensor integrated on a chip and bonded to the array substrate through the sensor terminal group 30.

[0071] The following further details the array substrate in the embodiments of the present disclosure:

[0072] Reference Figure 1 and Figure 2 , multiple light-emitting elements are arranged in an array. One light-emitting unit 101 includes 4 serially connected light-emitting elements. Among them, the light-emitting element electrically connected to the driving voltage signal line 202 is used as the starting point of the series connection of these 4 light-emitting elements, and the light-emitting element electrically connected to the control circuit is used as the end point of the series connection of these 4 light-emitting elements. The 4 light-emitting elements are driven by one control circuit. Therefore, a fourth lead 108 is also provided in the second conductive layer 200 of the array substrate. The fourth lead 108 sequentially connects the 4 light-emitting element terminal groups 10 to make the 4 light-emitting elements in series as one light-emitting unit 101. It should be noted that in the embodiments provided by the embodiments of the present disclosure, the number of light-emitting elements in each light-emitting unit is not limited and can be any number such as 5, 6, 7, 8, etc., rather than being limited to 4. At the same time, the light-emitting element can be an LED or any other form of light-emitting element.

[0073] In some examples, in specific implementation, in combination with Figure 1 shown, connecting the light-emitting elements in the same light-emitting unit 101 in sequence can form a polygon. For example, when the light-emitting unit 101 includes 4 light-emitting elements, the sequential connection of these 4 light-emitting elements can form a quadrilateral. Two sides of the quadrilateral can be parallel to the row direction, and the other two sides can be parallel to the column direction. Or, two sides of the quadrilateral can also have an angle with the row direction, and the other two sides can also have an angle with the column direction. Therefore, the four light-emitting element terminal groups 10 in each light-emitting unit 101 are also arranged in a corresponding shape.

[0074] Correspondingly, connecting the positions where the four light-emitting element terminal groups 10 corresponding to the four light-emitting elements in one light-emitting unit 101 are located can obtain a polygon (shown by the dotted box X in the figure), specifically, it can be a parallelogram. It can be understood that the vertices of the quadrilateral can be the geometric centers of each light-emitting element terminal group 10. It should be noted here Figure 2 the dotted box X in Figure 1The difference of the dashed boxes in the middle Figure 2 The dashed box X in the middle is used to indicate the position where the light-emitting element terminal group 10 is located. Figure 1 The dashed boxes in the middle only roughly depict the division manner of the light-emitting units 101. In some examples, during specific implementation, among the light-emitting units 101 adjacent in the row direction, the light-emitting elements located at the same position in each light-emitting unit 101 may be arranged approximately on the same straight line in the row direction. Further, among the light-emitting units adjacent in the column direction, the light-emitting elements located at the same position in each light-emitting unit 101 may be arranged approximately on a straight line in the column direction. Therefore, the light-emitting element terminal groups 10 in the row direction and the column direction are also arranged according to the corresponding rules.

[0075] Further, among the four mutually connected-in-series light-emitting element terminal groups 10, the fourth lead 108 between any two light-emitting element terminal groups 10 connected in series through the fourth lead 108 includes a plurality of sub-segments extending in the row direction and / or the column direction. Composing the fourth lead of a plurality of sub-segments including the row and column directions is convenient for manufacturing, and can reduce the probability of short circuit between two terminals in the same light-emitting element terminal group, and reduce the risk of breakage of the fourth lead that may be caused by the step difference existing in the gap between the signal line and the adjacent signal line in the first conductive layer. For specific reference Figure 2 , the fourth lead 108 of the upper-left light-emitting element terminal group 10 extends to the lower-left light-emitting element terminal group 10 in sequence along the column direction, the row direction, and the column direction.

[0076] Reference Figure 2 , in one embodiment, the light-emitting element terminal group 10 includes two terminals, one is the anode terminal 11, and the other is the cathode terminal 12. The anode terminal 11 is connected to an anode pin of the light-emitting element, and the cathode terminal 12 is connected to the other cathode pin of the light-emitting element.

[0077] The light-emitting element of the present disclosure is driven to emit light by a control circuit. Therefore, the array substrate of the present disclosure is further provided with a drive circuit terminal group 20. Similar to the light-emitting element and the sensor, the drive circuit can also be integrated in a chip and bonded to the array substrate by a soldering method. Therefore, the drive circuit terminal group 20 can be a pad group, and can also be directly prepared on the substrate by a film-forming process. Therefore, the drive circuit terminal group 20 can also be an electrode group that plays a conductive role. It can be understood that the orthographic projection of the drive circuit terminal group 20 on the substrate does not overlap with the orthographic projections of the light-emitting element terminal group 10 and the sensor terminal group 30 on the substrate.

[0078] In one embodiment, the control circuit for driving the light-emitting element to emit light can be a microchip. The size (e.g., length) of the microchip can be on the order of dozens or hundreds of micrometers, and the chip area is about tens of thousands of square micrometers, hundreds of square micrometers or even smaller, similar to the size of Mini-LEDs, featuring miniaturization and being convenient for integration into the array substrate 10 (e.g., bonded and coupled to the surface of the array substrate 10), simplifying the overall structure and facilitating the realization of thinness and lightness. Each control circuit directly drives one light-emitting unit 101, avoiding problems such as complex operation and easy flickering in the line scanning control method. Moreover, the driving circuit 110 has fewer port numbers, fewer required signals, a simple control method, a simple wiring method, and low costs.

[0079] Figure 1 and Figure 2 The structure of the driving circuit terminal group 20 coupled to the driving circuit is also shown. The driving circuit terminal group 20 includes four terminals, namely an input terminal 21 for connecting to the Di pin of the driving circuit, a power supply terminal 22 for connecting to the Pwr pin of the driving circuit, an output terminal 23 for connecting to the Out pin of the driving circuit, and a common voltage terminal 24 for connecting to the Gnd pin of the driving circuit.

[0080] Reference Figure 1 and Figure 2, a second signal line group for driving the light-emitting element to emit light is provided in the first conductive layer 100, and the second signal line group includes a second common voltage signal line 201, a driving voltage signal line 202, a power line 203, and a source address line 204; the above-mentioned input terminal 21 is configured to receive a first input signal, and the first input signal is, for example, an address signal, for selecting the driving circuit of the corresponding address. For example, the first input signal can be the 8-bit starting address information transmitted from the source address line 204, and the address of the first driving circuit corresponding to it can be known by parsing the address signal. The power terminal 22 is configured to receive a second input signal, and the second input signal is, for example, a power line carrier communication signal from the power line 203. The second input signal not only provides electrical energy for the driving circuit, but also transmits communication data to the driving circuit, and the communication data can be used to determine the light-emitting duration of the corresponding light-emitting unit, thereby controlling its visual light-emitting brightness. The output terminal 23 is configured to output a relay signal to the next-level driving circuit in a cascade relationship in a first time period, and the relay signal includes address information. By parsing the address signal, the address of the corresponding driving circuit can be known; the output terminal 23 is also configured to form a signal loop for the corresponding light-emitting unit in a second time period, so that the light-emitting unit can emit a corresponding brightness. The common voltage terminal 24 is configured to receive a common voltage signal, such as a ground signal from the second common voltage signal line 201. In the embodiment of the present disclosure, the above-mentioned second common voltage signal line 201, the driving voltage signal line 202, the power line 203, and the source address line 204 all extend in the column direction and are arranged at intervals in the row direction.

[0081] Combination Figure 1 As shown, the arrangement of four light-emitting elements and a driving circuit in a light-emitting unit 101 is used as a repeating unit, and the array substrate may include a plurality of repeating units, and adjacent repeating units are arranged at intervals and periodically arranged along the row direction and the column direction. In this way, a light-emitting unit group can be repeatedly arranged as a repeating unit. For example, in the plurality of light-emitting units arranged in the column direction, the relative positions of the plurality of light-emitting elements and the driving circuit in each light-emitting unit can be substantially the same; and in the light-emitting units arranged in the row direction, the relative positions of the plurality of light-emitting elements and the driving circuit in two adjacent light-emitting units can be arranged in a centrally symmetrical manner.

[0082] like Figure 2As shown, the drive circuit terminal group 20 is located outside the quadrilateral (shown by the dotted box X in the figure) obtained by sequentially connecting the positions of the four light-emitting element terminal groups 10 connected in series, so as to facilitate the wiring design of the fourth lead 108 and minimize the influence of the drive circuit on the light emission of the light-emitting element. It can be understood that when each light-emitting unit includes n×m light-emitting element terminal groups, the positions of the multiple light-emitting element terminal groups located at the outermost sides of the light-emitting unit can be sequentially connected to obtain a polygon, and the drive circuit terminal group 20 is located outside the polygon. Here, the positions of the outermost light-emitting element terminal groups in the light-emitting unit refer to the geometric centers of the above-mentioned light-emitting element terminal groups; the non-outermost light-emitting element terminal groups in the light-emitting unit are located inside the aforementioned polygon.

[0083] For ease of description, the light emitting units 101 in the array substrate are labeled according to the arrangement of rows and columns according to coordinates. For example, there are a total of P rows and Q columns of light emitting units 101 on the array substrate, and the light emitting unit 101 in the ath row and bth column can be mapped to the coordinates (a, b), 1≤a≤P, 1≤b≤Q, and P, Q, a, and b are all positive integers. Figure 3 Schematic diagram showing the arrangement structure and coordinates of some light emitting units 101 .

[0084] In one embodiment, the locations of the drive circuit terminal groups corresponding to the four light-emitting units 101 with coordinates (a, b), (a+1, b), (a, b+1), and (a+1, b+1) are connected in sequence to obtain a convex quadrilateral, such as a parallelogram, specifically, a rectangle or a square. Obviously, each convex quadrilateral is composed of two triangles, and the two triangles are composed of the locations of the three drive circuit terminal groups 20 in the four light-emitting units 101.

[0085] In some embodiments, each parallelogram may be composed of two isosceles triangles or regular triangles, and the isosceles triangles or regular triangles are composed of the positions of three drive circuit terminal groups 20 in the four light-emitting units 101. When each parallelogram is composed of two regular triangles, the distances between the drive circuit terminal groups 20 can be close. It should be noted that the "isosceles triangle" and "regular triangle" described here are idealized descriptions. In actual products, due to the influence of process and equipment accuracy, the general shape can be an isosceles triangle or regular triangle.

[0086] In some embodiments, reference Figures 1 - 3, the drive circuit terminal groups 20 in the light-emitting units (1, 1), the drive circuit terminal groups 20 in the light-emitting units (1, 2), and the drive circuit terminal groups 20 in the light-emitting units (2, 1) are respectively located at the three vertices of a triangle, for example, they can be at the three vertices of the first triangle. The drive circuit terminal groups 20 in the light-emitting units (2, 1), the drive circuit terminal groups 20 in the light-emitting units (1, 2), and the drive circuit terminal groups 20 in the light-emitting units (2, 2) can be respectively located at the three vertices of a triangle, for example, at the three vertices of the second triangle. The drive circuit terminal groups 20 in the light-emitting units (2, 1), the drive circuit terminal groups 20 in the light-emitting units (2, 2), and the drive circuit terminal groups 20 in the light-emitting units (3, 1) can be respectively located at the three vertices of a triangle, for example, at the three vertices of the third triangle. The drive circuit terminal groups 20 in the light-emitting units (3, 1), the drive circuit terminal groups 20 in the light-emitting units (2, 2), and the drive circuit terminal groups 20 in the light-emitting units (3, 2) can be respectively located at the three vertices of a triangle, for example, at the three vertices of the fourth triangle. The drive circuit terminal groups 20 in the light-emitting units (1, 2), the drive circuit terminal groups 20 in the light-emitting units (1, 3), and the drive circuit terminal groups 20 in the light-emitting units (2, 3) can be respectively located at the three vertices of a triangle, for example, at the three vertices of the fifth triangle; the drive circuit terminal groups 20 in the light-emitting units (2, 3), the drive circuit terminal groups 20 in the light-emitting units (1, 2), and the drive circuit terminal groups 20 in the light-emitting units (2, 2) can be respectively located at the three vertices of a triangle, for example, at the three vertices of the sixth triangle; the drive circuit terminal groups 20 in the light-emitting units (1, 3), the drive circuit terminal groups 20 in the light-emitting units (1, 4), and the drive circuit terminal groups 20 in the light-emitting units (2, 3) can be respectively located at the three vertices of a triangle, for example, at the three vertices of the seventh triangle.

[0087] Among them, the line connecting the centroids of any two adjacent triangles in the row direction and the column direction is parallel to the row direction or the column direction. For example, the line connecting the centroid of the first triangle and the centroid of the third triangle is parallel to the column direction; and the line connecting the centroid of the second triangle and the centroid of the fourth triangle is also parallel to the column direction. The line connecting the centroid of the first triangle, the centroid of the fifth triangle, and the centroid of the seventh triangle is parallel to the row direction; and the line connecting the centroid of the second triangle and the centroid of the sixth triangle is parallel to the row direction.

[0088] The arrangement rules of the other drive circuit terminal groups 20 are the same as above, and so on, which will not be elaborated here.

[0089] The arrangement of the driving circuit terminal groups 20 corresponding to the multiple light-emitting units 101 on the array substrate can be designed according to the above rules, which will not be elaborated here. In some examples, during specific implementation, in the row direction, taking the setting mode of the light-emitting element terminal group 10 and the driving circuit terminal group 20 corresponding to one light-emitting unit as a repeating unit, the array substrate can include multiple repeating units, and adjacent repeating units are arranged at intervals and are periodically arranged in the row direction. In this way, one light-emitting unit can be used as a repeating unit for repeated arrangement to form an array substrate. In this way, among the light-emitting units arranged in the row and column directions, the relative positions of the multiple light-emitting element terminal groups 10 and the driving circuit terminal groups 20 in each light-emitting unit can be basically the same.

[0090] Reference Figure 4 , is a schematic structural diagram of a sensor terminal group 30, and the sensor terminal group 30 includes an input terminal 31 for connecting to the R x pin of the sensor, an output terminal 32 for connecting to the T x pin of the sensor, a power supply terminal 33 for connecting to the V + pin of the sensor, and a common voltage terminal 34 for connecting to the Gnd pin of the sensor.

[0091] Figure 5 is Figure 4 a cross-sectional schematic diagram taken along the A-A direction in, and a first signal line group for driving the sensor to sense is arranged in the first conductive layer 100. The first signal line group includes an input signal line 101, an output signal line 102, a power supply signal line 103, and a first common voltage signal line 104. The above-mentioned signal lines extend in the column direction and are arranged in the row direction. The input terminal 31 is electrically connected to the input signal line 101, the output terminal 32 is electrically connected to the output signal line 102, the power supply terminal 33 is electrically connected to the power supply signal line 103, and the common voltage terminal 34 is electrically connected to the first common voltage signal line 104.

[0092] The functions of the first common voltage signal line 104 and the second common voltage signal line 201 are both to provide a ground voltage. Therefore, the second common voltage signal line 201 and the first common voltage signal line 104 can be combined into one signal line, so that a common voltage signal can be provided for the sensor and the driving circuit at the same time without increasing the number of signal lines.

[0093] The sensor provided by the embodiments of the present disclosure can be used to sense temperature. For example, the sensor includes a thermistor triode, and the voltage change between its base and emitter is used to sense the temperature change. It also includes an analog-to-digital conversion unit to convert the analog signal representing the voltage change into a digital signal. Further, it can also include signal processors such as denoising and filtering to further process the digital signal, so that the measured value of the corresponding temperature change obtained by converting the digital signal is relatively accurate. By comparing the measured value of the temperature change with the standard value, the cause of the temperature change can be determined. For example, it may be a circuit problem such as current in the area to be measured or a packaging problem in the area to be measured. By making adjustments or repairs for different problems, the effects of temperature monitoring and improving product yield can be achieved.

[0094] The sensor terminal group 30 can be located at the gap between two adjacent light-emitting units, as Figure 2 shown. In other embodiments, the sensor terminal group 30 can also be located between the terminal groups 10 of each light-emitting element in the light-emitting unit, as long as the area where the light-emitting unit is located can be sensed. Regardless of which setting method, multiple sensor terminal groups 30 can be arranged in an array in the row direction and the column direction on the array substrate, so that the sensor can monitor the temperature of the light-emitting units in different areas.

[0095] The number of sensors is designed according to the sensing accuracy requirements for the array substrate, and can be multiple or only one. Correspondingly, the number of sensor terminal groups 30 is also one or more.

[0096] In the present disclosure, in order to achieve more accurate inspection and regulation, the number of sensor terminal groups 30 is multiple and is distributed at the gaps between the light-emitting units. Taking Figure 6 as an example, it is a schematic diagram of the arrangement of a sensor terminal group 30 and signal lines. The figure schematically shows the structure in which 15 sensor terminal groups 30 are evenly arranged on the array substrate in a 3-row and 5-column manner.

[0097] It can be understood that the number and arrangement method of the sensor terminal groups 30 are not unique. Each sensor can sense the surrounding light-emitting elements. In order to ensure that the sensed data is helpful for monitoring the actual performance of the light-emitting elements, the number and position of the sensors can be set according to the number and range of the light-emitting elements that each sensor can sense, so that all the sensing ranges of the sensors can just cover all the light-emitting elements without duplicate sensing. Figure 6The sensor terminal groups therein are distributed in the row direction and the column direction. The sensor terminal groups in each row or each column are located on the same straight line, and the adjacent two sensor terminal groups have the same interval, so as to make the test more accurate. In other embodiments, according to the test requirements, the sensors in each row or each column can also be arranged in other forms. For example, the sensors in each row or each column are not located on the same straight line, as long as the sensing purpose can be achieved.

[0098] The connection relationship of the sensors will be described below. There may be N sensors on the array substrate, where N is greater than or equal to 1 and is an integer.

[0099] In some cases, the N sensors are cascaded with each other, that is, the T x pin of the nth-stage sensor is connected to the R x pin of the (n + 1)th-stage sensor, and the R x pin of the first-stage sensor is connected to the input signal line 101, and the T x pin of the Nth-stage sensor is connected to the output signal line 102, where n is an integer greater than 1 and less than N - 1. The R x pin of the first-stage sensor is connected to the input signal line 101 through the input terminal 31 in the sensor terminal group corresponding to the sensor, for receiving the input signal; the output pin T x of the Nth-stage sensor is connected to the output signal line 102 through the output terminal 32 in the corresponding sensor terminal group, for transmitting the signal sensed by the sensor to the external circuit. The input signal is generated based on a communication protocol, and is used to perform a series of configurations and settings on each stage of the sensor: in the power-on stage, the input signal is configured to sequentially assign address information to the first-stage sensor to the Nth-stage sensor; in the initial configuration stage, the input signal is configured to sequentially specify the sensing accuracy and sensing range, etc. of the physical quantity (such as temperature) of the first-stage sensor to the Nth-stage sensor; in the sensing stage, the input signal is configured to specify the xth-stage sensor to perform the sensing function and output the corresponding sensing signal. It can be understood that in the sensing stage, only one sensor performs the sensing function each time, and the other stages of sensors can be equivalently regarded as (N - 1) resistors connected in series with the sensor performing the sensing function, so as to be able to perform sensing at a specific position on the array substrate. Therefore, in the sensing stage, by configuring the input signal, each stage of the sensor can be sequentially specified to perform the sensing function, so as to obtain the sensing signals at all positions on the array substrate.

[0100] In some cases, the N sensors can also be independent of each other. In order to avoid too many signal lines and complex overall wiring, the sensors located in the same column can be connected to the same power signal line 103, the same input signal line 101, and the same output signal line 102. The R xThe pin is connected to the input signal line 101 through the input terminal 31 in the sensor terminal group corresponding to the sensor, and is used to receive the input signal; the output pins T of each sensor x are connected to the output signal line 102 through the output terminal 32 in the corresponding sensor terminal group, and are used to transmit the signal sensed by the sensor to the external circuit. Each sensor is pre-set with address information, and the address information of each sensor is different. The input signal is generated based on a communication protocol for configuring and setting each sensor. In the initial configuration stage, the input signal with the attached address information is configured to specify the sensing accuracy and sensing range of the corresponding sensor for the physical quantity (such as temperature), etc.; in the sensing stage, the input signal with the attached address information is configured to specify a certain sensor to perform the sensing function and output the corresponding sensing signal. It can be understood that in the sensing stage, only one sensor performs the sensing function at a time, and the other sensors connected to the same input signal line 101 and the same output signal line 102 as the sensor performing the sensing function do not work, so that the sensing at a specific position on the array substrate can be realized. Therefore, in the sensing stage, by configuring the input signal, different sensors at different positions can be sequentially specified to perform the sensing function, so that the sensing signals at all positions on the array substrate can be obtained.

[0101] In one embodiment, referring to Figures 1 - 7 wherein, Figure 6 corresponding to Figure 1 the layout of the sensor terminal group 30 and the signal lines in the array substrate, Figure 7 shows Figure 6 the structure of the first conductive layer 100. As shown in the figure, the number of input signal lines 101 is equal to the number of sensor terminal groups 30 in the row direction, and the number of output signal lines 102 is also equal to the number of sensor terminal groups 30 in the row direction. In the column direction, the input terminals 31 of the sensor terminal groups 30 in the same column are connected to the same input signal line 101, and the output terminals 32 of the sensor terminal groups 30 in the same column are connected to the same output signal line 102. That is to say, only one input signal line 101 and one output signal line 102 are provided in each column, thereby reducing the number of input signal lines 101 and output signal lines 102.

[0102] In another embodiment, referring to Figures 8 - 12 , Figure 8 shows the layout of the signal lines of the sensor terminal group 30 in this embodiment, Figure 9 shows a partial structural schematic diagram of the array substrate in this embodiment, Figure 10 is Figure 9 a partial enlarged schematic diagram of the M area in Figure 11 is Figure 9Schematic diagram of the structure of a sensor terminal group 30 Figure 12 shows Figure 8 the wiring mode of the first conductive layer 100 in. As shown in the figure, the number of input signal lines 101 is equal to the number of sensor terminals in the row direction, and the number of output signal lines 102 is equal to the number of sensor terminals in the row direction. In the column direction, among two adjacent sensor terminal groups 30 in the same column, the output terminal 32 of one sensor terminal group 30 is electrically connected to the input terminal 31 of the other sensor terminal group 30; among the sensor terminal groups 30 in the same column, the input terminal 31 of the first sensor terminal group 30 is connected to an input signal line 101, and the output terminal 32 of the last sensor terminal group 30 is connected to an output signal line 102, so that all the sensors in each column are connected in series, and the signals used to configure the sensors can be transmitted to each sensor in the same column.

[0103] For example, in the structure shown in the figure, the input terminal 31 of the sensor terminal group 30 in the bottom row of the first column is connected to the input signal line 101, and its output sub-terminal 32 is connected to the input terminal 31 of the sensor terminal group 30 in the second row from the bottom of this column. The input terminal 31 of the sensor terminal group 30 in the second row from the bottom of this column is connected to the input terminal 31 of the sensor terminal group 30 in the third row from the bottom of this column. Connecting upward according to this rule, the output terminal 32 of the sensor terminal group 30 in the top row of the first column is connected to the output signal line 102, so that the sensors in the first column can be connected in series. According to the same rule, the sensor terminal groups 30 in each column are connected, so that the sensors in each column can be connected in series. Based on this series connection form, only one input signal line 101 and one output signal line 102 are provided in each column, and moreover, the input signal line 101 and the output signal line 102 only need to be arranged above and below the array substrate respectively, and can be connected to the array substrate bonding area through edge routing, without passing through the entire array substrate up and down. Compared with Figure 5 the wiring mode shown, the space occupied by the lines is further reduced.

[0104] In this embodiment, since the output terminal 32 of one sensor terminal group 30 is electrically connected to the input terminal 31 of the other sensor terminal group 30 among two adjacent sensor terminal groups 30, the two input terminals can be connected by arranging leads in the second conductive layer 200.

[0105] In one embodiment, referring to Figure 13, the array substrate further includes a plurality of first leads 105, and the first leads 105 connect the output terminals and input terminals of two adjacent sensor terminal groups 30. The first leads 105 include first column leads 1051 extending in the column direction and first row leads 1052 extending in the row direction. Each first column lead 1051 is disposed on the first conductive layer 100, and each first row lead 1052 is disposed on the second conductive layer 200. The first column leads 1051 and the first row leads 1052 are electrically connected through vias. Taking the first lead 105 shown in the figure as an example, the first lead 105 includes one first column lead 1051 and two first row leads 1052. The two first row leads 1052 extend laterally from the output terminal and the input terminal respectively, and the two first row leads 1052 are simultaneously electrically connected to the longitudinal first column lead 1051 through vias, so that the output terminals and input terminals of two adjacent sensor terminal groups 30 are electrically connected. Figure 13 (a) shows the case where the first column leads 1051 and the first row leads 1052 do not cross each other. Figure 13 (b) shows the case where the first column leads 1051 and the first row leads 1052 cross each other.

[0106] In this embodiment, the first column leads 1051 connecting the sensor terminal groups 30 in the same column are arranged in the column direction, so that all the first column leads 1051 occupy the least space in the column direction.

[0107] In yet another embodiment, referring to Figures 14 - 17 , Figure 14 shows the signal line layout mode of the sensor terminal group 30 in this embodiment, Figure 15 shows a partial structural schematic diagram of the array substrate in this embodiment, Figure 15 the partial enlarged schematic diagram of the M area in Figure 10 is the same as Figure 16 and Figure 14 is a structural schematic diagram of a sensor terminal group 30 in Figure 17 shows Figure 14The wiring method of the first conductive layer 100 in []. As shown in the figure, the number of input signal lines 101 and the number of output signal lines 102 are both 1. In the column direction, among two adjacent sensor terminal groups 30 in the same column, the output terminal 32 of one sensor terminal group 30 is electrically connected to the input terminal 31 of the other sensor terminal group 30. That is, all the sensors in each column are connected in series. Further, among two adjacent columns of sensor terminal groups 30, the output terminal 32 of the sensor terminal group 30 in the first row or the last row of one column is electrically connected to the input terminal 31 of the sensor terminal group 30 in the first row or the last row of the other column, so that all the sensors are connected in series. Among all the sensor terminal groups 30 connected in series, the input terminal 31 of the first sensor terminal group 30 is connected to the input signal line 101, and the output terminal 32 of the last sensor terminal group 30 is connected to the output signal line 102, and the signals for configuring the sensors can be transmitted to all the sensors on the array substrate.

[0108] Figure 17 shows a schematic diagram of the transmission path of the input signal and the output signal corresponding to this embodiment. Figure 18 schematically shows the structure in which 15 sensor terminal groups 30 are arranged in an array on the array substrate in a 3-row and 5-column manner. The 15 points A, B, C,....., M, N, O respectively represent 15 sensors; each small square in the figure represents a light-emitting unit. Each small square on the abscissa represents a column of light-emitting units, and each small square on the ordinate represents a row of light-emitting units. All the light-emitting units are arranged in an array according to rows and columns, and the orthographic projection of the sensor terminal group 30 on the array does not overlap with the light-emitting unit. Figure 18 The coordinate values beside each letter in [] are used to represent the position of the terminal sensor on the array substrate. For example, A(8.5, 38.5) means that the sensor terminal A is located between the 8th and 9th columns of light-emitting units and between the 38th and 39th rows of light-emitting units.

[0109] In some embodiments, m×n sensors are connected in series one by one in an S shape column by column and row by row, or, m×n sensors are numbered one by one in a Z shape row by row and column by column. For example, Figure 18As shown, when m = 3 and n = 5, sensor A is connected to the input signal line 101 through the input terminal 31 of its corresponding sensor terminal group 30. Then, sensor A and each sensor in the same column are connected in series in turn. For example, sensors A, B, and C are connected in series in turn; then sensor C is connected in series with the closest adjacent sensor D in the same row; sensor D and each sensor in the same column are connected in series in turn. For example, sensors D, E, and F are connected in series in turn; and so on. Sensor O is connected to the output signal line 102 through the output terminal 32 of its corresponding sensor terminal group 30, realizing the series connection of 15 sensor terminal groups 30. Based on this series connection form, only one input signal line 101 and one output signal line 102 need to be provided on the array substrate at least. The input signal line 101 and the output signal line 102 only need to be connected to the first and last sensors among the multiple sensors with a series connection relationship respectively, without passing through the entire array substrate vertically. This series connection form can greatly reduce the number of signal lines compared with Figure 6 the connection method of the sensor terminal groups corresponding to the multiple sensors shown, thereby saving the wiring space of the array substrate. In this embodiment, since the output terminal 32 of one sensor terminal group 30 is electrically connected to the input terminal 31 of another sensor terminal group 30 among two adjacent sensor terminal groups 30, the two terminals can be connected by providing leads in the second conductive layer 200.

[0110] In one embodiment, referring to Figure 16 , the array substrate further includes a plurality of first leads 105. The first leads 105 connect the output sub-terminals and input sub-terminals of two adjacent sensor terminal groups 30. The first leads 105 include first column leads 1051 extending in the column direction and first row leads 1052 extending in the row direction. Each first column lead 1051 is provided in the first conductive layer 100, and each first row lead 1052 is provided in the second conductive layer 200. The first column leads 1051 and the first row leads 1052 are electrically connected through vias. Taking the first lead 105 shown in the figure as an example, the first lead 105 includes one first column lead 1051 and two first row leads 1052. The two first row leads 1052 extend horizontally from the output sub-terminal and the input sub-terminal respectively, and the two first row leads 1052 are simultaneously electrically connected to the longitudinal first column lead 1051 through vias, so that the output terminal 32 and the input terminal 31 of two adjacent sensor terminal groups 30 are electrically connected. Figure 16 (a) shows the case where the first column lead 1051 and the first row lead 1052 do not cross each other, Figure 16 (b) shows the case where the first column lead 1051 and the first row lead 1052 cross each other.

[0111] In this embodiment, the first column leads 1051 connecting the sensor terminal groups 30 in the same column are arranged in the column direction, so that all the first column leads 1051 occupy the least space in the column direction.

[0112] Reference Figure 6 , Figure 8 , Figure 14 , in these embodiments, the number of power signal lines 103 is equal to the number of sensor terminals in the row direction; in the column direction, the power terminals 33 of the sensor terminal groups 30 in the same column are connected to the same power signal line 103, thereby reducing the number of power signal lines 103. Since the power signal line 103 extends in the column direction, the power terminal 33 can be connected to the power signal line 103 by arranging horizontal leads in the second conductive layer 200. In structures such as Figure 7 , Figure 12 , Figure 17 shown, the power signal line 103 and the first column lead 1051 are arranged side by side, and enough space should be reserved between them to avoid signal interference.

[0113] Similarly, referring to Figure 6 , Figure 8 , Figure 14 , in these embodiments, the number of the first common voltage signal lines 104 is also equal to the number of the sensor terminal groups 30 in the row direction; in the column direction, the common voltage terminals 34 of the sensor terminal groups 30 in the same column are connected to the same first common voltage signal line 104 (i.e., the second common voltage signal line 201), thereby reducing the number of common voltage signal lines.

[0114] In one embodiment, the array substrate further includes a common voltage signal line auxiliary line 205 disposed in the second conductive layer 200. The common voltage signal line auxiliary line 205 is electrically connected to the first common voltage signal line through a via hole to increase the signal transmission path through two-layer routing and improve the signal transmission intensity. Referring to Figures 19 - 21 , Figure 19 shows a partial structural schematic diagram of the array substrate of this embodiment, Figure 20 is Figure 19 a partial enlarged schematic diagram of the M area in Figure 21This is a schematic structural diagram of a sensor terminal group 30 in this embodiment. An exemplary wiring manner of an auxiliary common voltage signal line 205 is shown in the figure. The common voltage signal line is in a grid shape and covers the gaps adjacent to each light-emitting unit. In the thickness direction of the array substrate, the auxiliary common voltage signal line 205 of this embodiment is located above the driving voltage signal line 202. Since the sensor terminal and the auxiliary common voltage signal line 205 are both located in the second conductive layer 200, the common voltage sub-terminal 34 can be directly connected to the auxiliary common voltage signal line 205. In other embodiments, the auxiliary common voltage signal line 205 can also be of other shapes, and the present disclosure does not make special limitations on this.

[0115] For the terminal group 30 of each of the above structures and the signal lines connected thereto correspondingly, they all need to occupy the wiring space of the array substrate. In one embodiment, the orthographic projections of the sensor terminal group 30, the light-emitting element terminal group 10, and the driving circuit terminal group 20 on the substrate are at least partially overlapped with the orthographic projection of the second signal line group on the substrate, so as to save wiring space. Further, the orthographic projection of the sensor terminal group 30 on the substrate and the orthographic projections of the light-emitting element terminal group 10 and the driving circuit terminal group 20 on the substrate are respectively located in the orthographic projections of different signal lines in the second signal line group on the substrate. Specifically, in an embodiment such as Figure 1 , Figure 9 , Figure 15 shown, the orthographic projection of the light-emitting element terminal group 10 that occupies most of the space overlaps with the orthographic projection of the wider second common voltage signal line 201 on the substrate 900, the orthographic projection of the driving circuit terminal group 20 on the substrate also overlaps with the orthographic projection of the second common voltage signal line 201, and the orthographic projection of the sensor terminal group 30 on the substrate 900 overlaps with the orthographic projection of the driving voltage signal line 202, thereby saving wiring space.

[0116] For the above input signal line 101, output signal line 102, power supply signal line 103, and first lead 105, each signal line corresponding to each column of the sensor terminal group 30 is located between a second common voltage signal line 201 and a driving voltage signal line 202. In order to make the most of the existing space for wiring, appropriate slots can be made on the edge of the second common voltage signal line 201 or the driving voltage signal line 202. If there are at least two adjacent signal lines extending in the column direction, and there is an overlapping area in the orthographic projection on any straight line parallel to the column direction, the slotting position can correspond to this overlapping area, so that the at least two adjacent signals can obtain a larger wiring space, thereby improving the utilization rate of the substrate. Refer to Figure 16(b), it can be understood that since there is an overlapping area in the orthographic projection of two adjacent longitudinally extending first column leads 1051 on any straight line parallel to the column direction, the size of the two first column leads 1051 in the row direction occupied by the corresponding part in the overlapping area is relatively wide (including the line width of a single first column lead 1051 and the spacing between adjacent first column leads 1051 in the row direction). By opening a groove 5 on the left side of the second common voltage signal line 201 (i.e., at the position corresponding to the above overlapping area), the corresponding part of the two first column leads 1051 in the overlapping area can correspond to a larger space in the row direction. The shape of the groove 5 includes, but is not limited to, a rectangle in the figure. The size or position of the groove 5 can be designed according to the routing method of the sizes of each signal line or lead, and the present application does not specifically limit it.

[0117] In one embodiment, referring to Figure 23 , the array substrate further includes a plurality of capacitor terminal groups 40. The capacitor terminal groups 40 are provided on the second conductive layer 200 and are used for bonding capacitors. The capacitor terminal group 40 includes a first capacitor terminal 41 and a second capacitor terminal 42. The first capacitor terminal 41 is connected to the power supply terminal 33, and the second capacitor terminal 42 is connected to the common voltage terminal 34, thereby being able to reduce the noise generated by the sensor and making the overall electricity of the array substrate more stable.

[0118] Figure 22 For Figure 18 a partial enlarged schematic diagram of the M area in which the capacitor terminal group 40 is included, Figure 23 is a schematic structural diagram of the capacitor terminal group 40. The array substrate further includes a second lead 106 and a third lead 107 provided on the second conductive layer 200. One end of the second lead 106 is connected to the first capacitor terminal 41, and the other end is connected to the power supply signal line 103 through a via. One end of the third lead 107 is connected to the first capacitor terminal 41, and the other end is connected to the power supply terminal 33 of the sensor terminal group 30.

[0119] As Figure 23As shown, in this embodiment, since the auxiliary line 205 of the common voltage signal line is disposed on the second conductive layer 200, and the common voltage terminal 34 is directly connected to the auxiliary line 205 of the common voltage signal line, therefore, the second capacitor terminal 42 of the capacitor terminal group 40 is also connected to the auxiliary line 205 of the common voltage signal line, that is, electrically connected to the first common voltage signal line 104, so as to conduct the static electricity generated near the capacitor to the common voltage signal line, and avoid damage to the array substrate caused by static electricity release. It should be noted that the common voltage terminal 34, the second capacitor terminal 42 and the auxiliary line of the common voltage signal line are all disposed on the second conductive layer 200. It can be understood that the auxiliary line 205 of the common voltage signal line and other signal lines disposed on the second conductive layer need to be covered by an insulating layer above to prevent oxidation of the lines and affect the electrical performance; and the upper surfaces of the respective terminals disposed on the second conductive layer need to be electrically connected to the components, so they are exposed. Therefore, the common voltage terminal 34 and the second capacitor terminal 42 can also be regarded as a part of the auxiliary line 205 of the common voltage signal line.

[0120] It should be noted that the "extending along a direction" and "extending along a column direction" described in the present disclosure both refer to that the overall trend of the signal line is along the row direction or the column direction, and local bending to avoid other line structures or inclination within the allowable process error is allowed, rather than limiting it to a standard straight line.

[0121] The array substrate provided by the embodiment of the present disclosure can be either installed with a light-emitting device and used as a substrate with a light-emitting function, or further applied to a display device as a backlight unit.

[0122] After a light-emitting element, a sensor, and a driving chip are installed on the array substrate of the present disclosure, a hemispherical microstructure can also be fabricated above the light-emitting element, the sensor, and the driving chip, which serves to protect the above structures to prevent them from being scratched during production and transportation. Specifically, the microstructure above the light-emitting element is made of a light-transmitting material, and further can have an optical shaping effect on the emitted light of the light-emitting element, such as improving the light efficiency or increasing the light output at a positive viewing angle. The microstructures above the sensor and the driving chip can be made of a transparent material or a material with a light-absorbing function, which is not limited herein.

[0123] The embodiment of the present invention further provides a display device, which includes the array substrate in the above embodiment. Since the display device includes the above array substrate, it has the same beneficial effects, and the present invention will not elaborate herein.

[0124] The present invention does not specifically limit the applicability of the display device, and it can be any product or component with a flexible display function, such as a television, a notebook computer, a tablet computer, a wearable display device, a mobile phone, an in-vehicle display, a navigation device, an e-book, a digital photo frame, an advertising light box, etc.

[0125] Other embodiments provided by the present disclosure will be readily contemplated by those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the embodiments provided by the present disclosure, which follow the general principles provided by the embodiments of the present disclosure and include well-known knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The specification and examples are only regarded as exemplary, and the true scope and spirit of the embodiments provided by the present disclosure are pointed out by the appended claims.

Claims

1. An array substrate, characterized in that, It includes a substrate. A first conductive layer and a second conductive layer which are insulated from each other are stacked on the substrate. Wherein, the array substrate further includes: A plurality of array-arranged light-emitting element terminal groups, which are arranged on the second conductive layer and used for coupling with light-emitting elements; Several sensor terminal groups, which are arranged on the second conductive layer and used for coupling with sensors; The orthographic projection of the sensor terminal group on the substrate has no overlap with the orthographic projection of the light-emitting element terminal group on the substrate; the sensor terminal group includes an input terminal and an output terminal; the corresponding sensor includes an input pin and an output pin, the input terminal is used for electrically connecting with the input pin, and the output terminal is used for electrically connecting with the output pin; A first signal line group, which is arranged on the first conductive layer and electrically connected with the sensor terminal group, and is used for driving the sensor to sense; A second signal line group, which is arranged on the first conductive layer and electrically connected with the light-emitting element terminal group, and is used for driving the light-emitting element to emit light; Several light-emitting element terminal groups are connected in series, and the sensor terminal group is located outside the polygon corresponding to the several series-connected light-emitting element terminal groups; the polygon corresponding to the several series-connected light-emitting element terminal groups is a polygon obtained by sequentially connecting the positions of the outermost light-emitting element terminal groups among the several series-connected light-emitting element terminal groups.

2. The array substrate according to claim 1, wherein Four light-emitting element terminal groups are connected in series; the polygon corresponding to the four series-connected light-emitting element terminal groups is a quadrilateral.

3. The array substrate according to claim 2, wherein, Two of the sides of the quadrilateral are parallel to the row direction, and the other two sides are parallel to the column direction; Or, two of the opposite sides of the quadrilateral have an included angle with the row direction, and the other two opposite sides have an included angle with the column direction.

4. The array substrate according to claim 1, wherein The array substrate further includes: A driving circuit terminal group, which is arranged on the second conductive layer and used for coupling with a driving circuit; the orthographic projection of the driving circuit terminal group on the substrate has no overlap with the orthographic projections of the light-emitting element terminal group and the sensor terminal group on the substrate.

5. The array substrate according to claim 4, wherein The driving circuit terminal group is located outside the polygon corresponding to the several series-connected light-emitting element terminal groups.

6. The array substrate according to claim 4, wherein Each of the light-emitting elements coupled by several series-connected light-emitting element terminal groups forms a light-emitting unit; The array substrate can be used to form P rows and Q columns of the light-emitting units, and each driving circuit terminal group drives one light-emitting unit; Among them, the positions of the driving circuit terminal groups corresponding to the four light-emitting units with coordinates (a, b), (a + 1, b), (a + 1, b + 1), and (a, b + 1) are sequentially connected to form a convex quadrilateral; the convex quadrilateral is composed of two triangles; The light-emitting unit with coordinates (a, b) is the light-emitting unit in the a-th row and the b-th column; The light-emitting unit with coordinates (a + 1, b) is the light-emitting unit in the (a + 1)-th row and the b-th column; The light-emitting unit with coordinates (a, b + 1) is the light-emitting unit in the a-th row and the (b + 1)-th column; The light-emitting unit with coordinates (a + 1, b + 1) is the light-emitting unit in the (a + 1)-th row and the (b + 1)-th column; Among them, 1 ≤ a ≤ P - 1, 1 ≤ b ≤ Q - 1, and a and b are both positive integers.

7. The array substrate according to claim 6, wherein The two triangles are two isosceles triangles or two equilateral triangles; The isosceles triangle or the equilateral triangle is formed by connecting the positions of three of the four driving circuit terminal groups corresponding to the light-emitting units in sequence.

8. The array substrate according to claim 6, wherein The line connecting the centers of gravity of two adjacent triangles arranged in the same row is parallel to the row direction; and / or, the line connecting the centers of gravity of two adjacent triangles arranged in the same column is parallel to the column direction.

9. A light-emitting substrate, characterized in that, Comprising: The array substrate according to any one of claims 1-8; A light-emitting element, coupled to the light-emitting element terminal group of the array substrate; A sensor, coupled to the sensor terminal group of the array substrate.

10. A display device, characterized in that, Comprising the light-emitting substrate according to claim 9.

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