Display panel and preparation method thereof

Abstract

The invention provides a display panel and a preparation method thereof. The display panel comprises an array substrate, a pixel retaining wall, a pixel opening, a partition structure, a charge generation layer and a cathode layer. The side, away from the array substrate, of each pixel retaining wall is provided with an interval opening. The partition structures are located in the interval openings and located between every two adjacent pixel openings in the first direction. In the thickness direction of the array substrate in the direction close to the array substrate, the cross section of the partition structure in the thickness direction of the array substrate and the first direction gradually shrinks inwards, and a notch is formed between the side wall of the partition structure and the side wall of the interval opening. The charge generation layer is located in the pixel opening, on the surface of the pixel retaining wall and on the surface of the partition structure, and is disconnected at the notch. The cathode layer is located on the surface of the charge generation layer and continuously extends at the gap. The cross section of the partition structure gradually shrinks inwards, so that the charge generation layer is broken at the notch. The width of the gap can be reduced after the charge generation layer is formed, so that the cathode layer can be continuous at the gap.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to a display panel and a method for manufacturing the same. Background Art

[0002] In related technologies, the tandem technology of an Organic Light-Emitting Diode (OLED) display can improve the lifespan of the product, reduce power consumption, increase brightness, etc. However, in general tandem devices of OLEDs, some organic layers with relatively high conductivity (such as charge generation layers, etc.) are prone to causing serious lateral leakage current between pixels of the display panel, resulting in color bleeding defects in pixels of the display panel at low gray levels, seriously affecting the yield and image quality.

[0003] To address the above problems, currently, mainly by introducing a partition structure, the charge generation layer between pixels in the OLED device is broken. However, the current partition structure also breaks the cathode layer, resulting in an increase in power consumption. Summary of the Invention

[0004] The purpose of this application is to provide a display panel and a method for manufacturing the same, aiming to disconnect the charge generation layer at the sidewall of the partition structure while keeping the cathode layer continuous to reduce power consumption.

[0005] This application provides a display panel, including: an array substrate; pixel barriers located on the array substrate, and pixel openings located between adjacent pixel barriers, wherein the side of the pixel barrier facing away from the array substrate has a spaced opening; a partition structure located in the spaced opening, the partition structure being located between two adjacent pixel openings along a first direction, and the first direction is perpendicular to the thickness direction of the array substrate; in the thickness direction of the array substrate along the direction close to the array substrate, the cross-section of the partition structure gradually shrinks in the thickness direction of the array substrate and the first direction, and there is a gap between the sidewall of the partition structure and the sidewall of the spaced opening; a charge generation layer located in the pixel opening, on the surface of the pixel barrier, and on the surface of the partition structure, and the charge generation layer is discontinuously arranged at the gap; a cathode layer located on the surface of the charge generation layer, and the cathode layer continuously extends at the gap.

[0006] In some embodiments, the pixel barrier includes a first barrier and a second barrier, and the first barrier and the second barrier are respectively located on two sides of the spaced opening along the first direction; the gap is located at least at one of the positions between the first barrier and the partition structure and between the second barrier and the partition structure.

[0007] In some embodiments, an angle is formed between the side wall of the spacing opening and the array substrate, the angle is oriented toward the partition structure, and the angle is greater than or equal to 90 degrees.

[0008] In some embodiments, in the same notch, the side wall of the spacing opening and the side wall of the partition structure are parallel to each other.

[0009] In some embodiments, the notch includes a first opening end and a second opening end oppositely arranged along the thickness direction of the array substrate, the first opening end is farther away from the array substrate than the second opening end; the width of the first opening end along the first direction is 0.2 microns to 1.5 microns.

[0010] In some embodiments, the ductility of the material of the cathode layer is stronger than the ductility of the material of the charge generation layer.

[0011] In some embodiments, a cross section of the partition structure along the thickness direction of the array substrate and the first direction is an inverted trapezoid with a short side facing the array substrate.

[0012] In some embodiments, the pixel blocking wall includes a first pixel definition layer located on the array substrate; the spacing opening penetrates the first pixel definition layer and exposes the array substrate; and the partition structure contacts the array substrate.

[0013] In some embodiments, the pixel blocking wall includes a first pixel definition layer and a second pixel definition layer, the first pixel definition layer is located on the array substrate, and the second pixel definition layer is located on the side of the first pixel definition layer away from the array substrate; the spacing opening passes through the second pixel definition layer and exposes the first pixel definition layer; the partition structure is in contact with the first pixel definition layer.

[0014] In some embodiments, a height of the partition structure along the thickness direction of the array substrate is less than or equal to a height of the spacing opening along the thickness direction of the array substrate.

[0015] In some embodiments, it also includes: a first light-emitting functional layer, located in the pixel opening, on the surface of the pixel blocking wall and on the surface of the partition structure; a second light-emitting functional layer, located between the charge generating layer and the cathode layer, and continuously extending at the gap.

[0016] In some embodiments, the pixel openings are arranged in an array along a first direction and a second direction, the first direction is perpendicular to the thickness direction of the array substrate, and the second direction is perpendicular to the first direction and the thickness direction of the array substrate respectively; the pixel retaining walls are arranged in a grid shape around the pixel openings, and the partition structures are arranged in a grid shape around the pixel openings.

[0017] In some embodiments, the grid-shaped partition structure has a plurality of intersections, and the partition structure is discontinuously provided at at least one of the intersections.

[0018] An embodiment of the present application further provides a method for manufacturing a display panel, including: providing an array substrate; forming pixel barriers and pixel openings located between adjacent pixel barriers on the array substrate, wherein a side of the pixel barrier facing away from the array substrate has a spaced opening; forming a partition structure in the spaced opening, the partition structure being located between two adjacent pixel openings along a first direction, the first direction being perpendicular to the thickness direction of the array substrate; along the direction close to the array substrate in the thickness direction of the array substrate, a cross-section of the partition structure gradually shrinks in the thickness direction and the first direction of the array substrate, and there is a notch between a side wall of the partition structure and a side wall of the spaced opening; forming a charge generation layer on a surface within the pixel opening, on a surface of the pixel barrier, and on a surface of the partition structure, the charge generation layer being discontinuously provided at the notch; forming a cathode layer on a surface of the charge generation layer, the cathode layer continuously extending at the notch.

[0019] The present application provides a display panel and a method for manufacturing the same. The pixel barrier has a spaced opening, and there is a notch between a side wall of the partition structure and a side wall of the spaced opening. Since the cross-section of the partition structure gradually shrinks along the direction close to the array substrate in the thickness direction of the array substrate, the charge generation layer will be discontinuous at the notch. Since the width of the notch will be reduced after the charge generation layer is formed, when the cathode layer is formed thereon, the cathode layer can be continuous at the notch due to the small notch. Therefore, the present application can reduce the lateral leakage current of the charge generation layer and also reduce power consumption. Description of the Drawings

[0020] The following will clearly show the technical solutions and other beneficial effects of the present application by describing the specific embodiments of the present application in detail with reference to the drawings.

[0021] Figure 1 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application;

[0022] Figure 2 is a schematic cross-sectional structure diagram of a display panel provided by some embodiments of the present application;

[0023] Figure 3 is a schematic cross-sectional structure diagram of a display panel provided by some embodiments of the present application;

[0024] Figure 4 is a schematic cross-sectional structure diagram of a display panel provided by some embodiments of the present application;

[0025] Figure 5 It is a schematic cross-sectional structure diagram of a display panel provided by some embodiments of the present application;

[0026] Figure 6 It is a schematic top view structure diagram of a pixel opening and partition structure provided by some embodiments of the present application;

[0027] Figure 7 It is a schematic top view structure diagram of a pixel opening and partition structure provided by some embodiments of the present application;

[0028] Figure 8 It is a schematic flow diagram of a method for manufacturing a display panel provided by some embodiments of the present application;

[0029] Figure 9 and Figure 10 It is a schematic cross-sectional structure diagram of a display panel during the formation process provided by some embodiments of the present application. Detailed Embodiments

[0030] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present application.

[0031] Please refer to Figure 1 , Figure 1 It is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application.

[0032] The display panel includes an array substrate 10, a pixel definition layer 20, a partition structure 30, a light-emitting functional layer 40, a charge generation layer 50, and a cathode layer 60. The pixel definition layer 20 is located on the array substrate 10 and has a pixel opening P. The partition structure 30 is located on the pixel definition layer 20 between adjacent pixel openings P, and the light-emitting functional layer 40 is located within the pixel opening P. The charge generation layer 50 is discontinuously provided on the sidewall of the partition structure 30. The cathode layer 60 is located on the surface of the charge generation layer 50, and the cathode layer 60 is discontinuously provided on the sidewall of the partition structure 30.

[0033] Since the partition structure 30 is provided on the pixel definition layer 20, it will disconnect all the film layers formed in this area. For example, the partition structure 30 disconnects both the charge generation layer 50 and the cathode layer 60.

[0034] In some embodiments, when some film layers (such as an electron or hole transport layer, an electron or hole injection layer) in the light-emitting functional layer 40 are formed as common film layers on the pixel definition layer 20, they will also be disconnected.

[0035] Based on this, a display panel according to an embodiment of the present application includes: an array substrate; pixel barriers located on the array substrate, and pixel openings located between adjacent pixel barriers, wherein a side of the pixel barrier facing away from the array substrate has a spaced opening; a partition structure located in the spaced opening, the partition structure being located between two adjacent pixel openings along a first direction, the first direction being perpendicular to the thickness direction of the array substrate; in the direction of approaching the array substrate along the thickness direction of the array substrate, a cross-section of the partition structure gradually contracts along the thickness direction and the first direction of the array substrate, and there is a gap between a side wall of the partition structure and a side wall of the spaced opening; a charge generation layer located in the pixel opening, on a surface of the pixel barrier, and on a surface of the partition structure, and the charge generation layer is discontinuously provided at the gap; and a cathode layer located on a surface of the charge generation layer, and the cathode layer continuously extends at the gap.

[0036] In the display panel provided by the embodiment of the present application, the pixel barrier has a spaced opening, and there is a gap between the side wall of the partition structure and the side wall of the spaced opening. Since the cross-section of the partition structure gradually contracts along the thickness direction and the first direction of the array substrate, the charge generation layer will be discontinuous at this gap. Since the width of the gap will be reduced after the charge generation layer is formed, when the cathode layer is formed thereon, the cathode layer can be continuous at this gap due to the small gap. Therefore, the embodiment of the present application can reduce the lateral leakage current of the charge generation layer while reducing the power consumption.

[0037] The structure of the display panel provided by the embodiment of the present application will be described below with reference to the accompanying drawings.

[0038] Please refer to Figure 2 , Figure 2 which is a schematic cross-sectional structure diagram of a display panel provided by some embodiments of the present application.

[0039] The display panel 100 includes an array substrate 10, pixel barriers 70, pixel openings P, a partition structure 30, a charge generation layer 50, and a cathode layer 60. The pixel barriers 70 are located on the array substrate 10, and the pixel openings P are located between adjacent pixel barriers 70. One side of the pixel barriers 70 facing away from the array substrate 10 has spaced openings C. The partition structure 30 is located within the spaced openings C. The partition structure 30 is located between two adjacent pixel openings P along a first direction X, and the first direction X is perpendicular to the thickness direction Z of the array substrate 10. In the direction along the thickness direction Z of the array substrate 10 and approaching the array substrate 10, the cross-section of the partition structure 30 gradually shrinks inward along the thickness direction Z and the first direction X of the array substrate 10, and there is a notch T between the side wall of the partition structure 30 and the side wall of the spaced opening C. The charge generation layer 50 is located within the pixel openings P, on the surfaces of the pixel barriers 70, and on the surface of the partition structure 30, and the charge generation layer 50 is discontinuously provided at the notch T. The cathode layer 60 is located on the surface of the charge generation layer 50, and the cathode layer 60 continuously extends at the notch T.

[0040] It should be noted that in this application, "the charge generation layer 50 is located on the surface of..." includes that the charge generation layer 50 is in direct contact with the surface; it also includes that the charge generation layer 50 is indirectly located on the surface, that is, there may be other film layers between the surface and the charge generation layer 50. The same description for other structures (such as the cathode layer 60) is the same.

[0041] It should be noted that Figure 2 It mainly shows the structure on the array substrate 10. For the specific structure of the array substrate 10, reference can be made to the description of the embodiments below.

[0042] As Figure 2 shown, the pixel openings P are located between pixel barriers 70 adjacent to each other along the first direction X.

[0043] In some embodiments, a plurality of pixel openings P are arranged in an array along the first direction X and the second direction Y, and the pixel barriers 70 are located between two adjacent pixel openings P. Among them, both the first direction X and the second direction Y are perpendicular to the thickness direction Z of the array substrate 10, and the first direction X can be perpendicular to the second direction Y.

[0044] It should be noted that Figure 2 It only shows the pixel openings P adjacent to each other in one direction (such as the first direction X) and the structure therebetween to show the partitioning situation of the partition structure 30 for other film layers in one direction.

[0045] It can be understood that the side of the pixel barrier 70 facing away from the array substrate 10 has a spaced opening C, indicating that the spaced opening C is located on the surface of the pixel barrier 70 facing away from the array substrate 10 (i.e., the upper surface shown in the figure). That is to say, the spaced opening C can extend downward from the upper surface of the pixel barrier 70, can extend into the interior of the pixel barrier 70, or can extend to the lower surface of the pixel barrier 70.

[0046] In some embodiments, the pixel barrier 70 includes a first pixel defining layer 71 located on the array substrate 10. The spaced opening C penetrates through the first pixel defining layer 71 and exposes the array substrate 10, and the partition structure 30 is in contact with the array substrate 10. Herein, "penetrates through" means that the spaced opening C extends from the upper surface of the pixel barrier 70 to the lower surface of the pixel barrier 70.

[0047] The pixel opening P also penetrates through the first pixel defining layer 71, that is, the pixel opening P and the spaced opening C are arranged at intervals within the first pixel defining layer 71, and the spaced opening C is located between two adjacent pixel openings P along the first direction X.

[0048] The display panel 100 may further include an anode layer 80. The anode layer 80 is located on the array substrate 10. The first pixel defining layer 71 also covers the anode layer 80, and the pixel opening P exposes the anode layer 80.

[0049] In some embodiments, the depth of the pixel opening P along the thickness direction Z of the array substrate 10 is less than the depth of the spaced opening C along the thickness direction Z of the array substrate 10.

[0050] In some embodiments, there is an included angle A1 (which can be referred to as the first included angle) between the side wall of the spaced opening C and the array substrate 10. The included angle A1 faces the partition structure 30, and the included angle A1 is greater than or equal to 90 degrees. When the included angle A1 is equal to 90 degrees, the spaced opening C is an opening with equal width up and down; when the included angle A1 is greater than 90 degrees, the spaced opening C is an opening with a larger upper part and a smaller lower part.

[0051] There is a second included angle A2 between the side wall of the partition structure 30 and the array substrate 10. The second included angle A2 faces the notch T, and the second included angle A2 is greater than 90 degrees.

[0052] In some embodiments, within the same notch T, the side walls of the spaced opening C and the partition structure 30 are parallel to each other.

[0053] As Figure 2 shown, the partition structure 30 is located within the spaced opening C, indicating that the spaced opening C can accommodate the partition structure 30.

[0054] In some embodiments, the height of the partition structure 30 in the thickness direction Z of the array substrate 10 is less than or equal to the height of the spacer opening C in the thickness direction Z of the array substrate 10, which can prevent the partition structure 30 from being too high and affecting the evaporation process of the film layer.

[0055] It can be understood that when the height of the partition structure 30 in the thickness direction Z of the array substrate 10 is equal to the height of the spacer opening C in the thickness direction Z of the array substrate 10, it is beneficial for the cathode layer 60 to be continuous at the notch T when the cathode layer 60 is formed.

[0056] As Figure 2 shown, in the direction of the thickness direction Z of the array substrate 10 close to the array substrate 10, the cross-section of the partition structure 30 in the thickness direction Z and the first direction X of the array substrate 10 gradually shrinks inward. Therefore, when the charge generation layer 50 is formed, the upper surface of the partition structure 30 will block the material from falling onto the lower sidewall of the partition structure 30, so that the charge generation layer 50 can be disconnected at the upper sidewall of the partition structure 30. And since the charge generation layer 50 is formed after the notch T, the remaining width at the notch T will be reduced, so that the cathode layer 60 can continuously extend at the notch T.

[0057] It can be understood that "shrinking inward" means that the cross-section shrinks in the direction away from the notch T and gradually shrinks from top to bottom.

[0058] In some embodiments, the cross-section of the partition structure 30 in the thickness direction Z and the first direction X of the array substrate 10 is an inverted trapezoid with the short side facing the array substrate 10. Such an inverted trapezoid partition structure 30 is beneficial for implementation in the process.

[0059] In some embodiments, the ductility of the material of the cathode layer 60 is stronger than the ductility of the material of the charge generation layer 50. In this way, it is beneficial for the cathode layer 60 to form a continuous film layer at the notch T.

[0060] As Figure 2 shown, there is at least one notch T between the sidewall of the partition structure 30 and the sidewall of the spacer opening C.

[0061] In some embodiments, the pixel barrier 70 includes a first barrier and a second barrier, and the first barrier and the second barrier are respectively located on both sides of the spacer opening C in the first direction X. The notch T is located at least at one of between the first barrier and the partition structure 30 and between the second barrier and the partition structure 30.

[0062] That is to say, the notch T can be located on both sides of the partition structure 30 along the first direction X (i.e., there are two notches T), then one partition structure 30 can partition the charge generation layer 50 at two places, which can improve the partitioning effect.

[0063] The notch T can also be only located on one side of the partition structure 30 along the first direction X (i.e., there is one notch T). When the notch T is only located on one side of the partition structure 30, the other side of the partition structure 30 is in contact with the side wall of the spacer opening C.

[0064] In some embodiments, the notch T includes a first opening end and a second opening end that are oppositely arranged along the thickness direction Z of the array substrate 10. The first opening end is farther from the array substrate 10 than the second opening end, and the width W of the first opening end along the first direction X is 0.2 micrometers to 1.5 micrometers.

[0065] As Figure 2 shown, the first opening end is the upper end of the notch T, and the second opening end is the lower end of the notch T.

[0066] It should be noted that if the width W of the first opening end along the first direction X is less than 0.2 micrometers, it may cause the charge generation layer 50 to be incompletely disconnected at the notch T; if the width W of the first opening end along the first direction X is greater than 1.5 micrometers, it may cause the cathode layer 60 to be discontinuous at the notch T.

[0067] The display panel 100 may further include a first light-emitting functional layer 41 and a second light-emitting functional layer 42. The first light-emitting functional layer 41 is within the pixel opening P and is located between the anode layer 80 and the charge generation layer 50; the second light-emitting functional layer 42 is within the pixel opening P and is located between the charge generation layer 50 and the cathode layer 60.

[0068] The first light-emitting functional layer 41 may include a first hole injection layer, a first hole transport layer, a first electron blocking layer, a first hole blocking layer, and a first electron transport layer from bottom to top. The second light-emitting functional layer 42 may include a second hole transport layer, a second electron blocking layer, a second hole blocking layer, a second electron transport layer, and a second electron injection layer from bottom to top.

[0069] The display panel 100 may further include a first light-emitting layer and a second light-emitting layer (not shown). The first light-emitting layer is located between the first electron blocking layer and the first hole blocking layer, that is, sandwiched in the first light-emitting functional layer 41; the second light-emitting layer is located between the second electron blocking layer and the second hole blocking layer, that is, sandwiched in the second light-emitting functional layer 42.

[0070] Within the same pixel opening P, the emission color of the first light-emitting layer is the same as the emission color of the second light-emitting layer.

[0071] See also Figure 3 , Figure 3 is a schematic diagram of a cross-sectional structure of a display panel provided in some embodiments of the present application. Figure 2 The difference between the embodiments lies in the structure of the pixel retaining wall 70.

[0072] The pixel blocking wall 70 includes a first pixel definition layer 71 and a second pixel definition layer 72 . The first pixel definition layer 71 is located on the array substrate 10 , and the second pixel definition layer 72 is located on a side of the first pixel definition layer 71 away from the array substrate 10 .

[0073] The spacing opening C penetrates the second pixel definition layer 72 and exposes the first pixel definition layer 71 , so that the partition structure 30 is in contact with the first pixel definition layer 71 .

[0074] The pixel opening P is located between adjacent pixel blocking walls 70 . As the thickness of the pixel blocking walls 70 increases, the depth of the pixel opening P increases, thereby increasing the space between the light-emitting function layer 40 and the light-emitting layer.

[0075] On the other hand, the spacing opening C and the partition structure 30 are formed in the second pixel definition layer 72 , which can be designed in a larger space than that formed in the first pixel definition layer 71 .

[0076] See also Figure 4 and Figure 5 , Figure 4 and Figure 5 is a schematic diagram of a cross-sectional structure of a display panel provided in some embodiments of the present application. Figure 2 and Figure 3 The same thing in the embodiments is that the first light-emitting layer and the second light-emitting layer are both located in the pixel opening P.

[0077] Figure 4 Example and Figure 2 The difference between the embodiments is that the first light-emitting functional layer 41 and the second light-emitting functional layer 42 are Figure 5 Example and Figure 3 The difference between the embodiments also lies in the first light-emitting functional layer 41 and the second light-emitting functional layer 42 .

[0078] like Figure 4 and Figure 5 As shown, the first light-emitting functional layer 41 is located in the pixel opening P, on the surface of the pixel blocking wall 70 and on the surface of the partition structure 30, and the second light-emitting functional layer 42 is located between the charge generating layer 50 and the cathode layer 60. That is, the second light-emitting functional layer 42 also extends to the surface of the pixel blocking wall 70 and the surface of the partition structure 30.

[0079] In some embodiments, the second light-emitting functional layer 42 continuously extends at the notch T, which is beneficial to the continuous extension of the cathode layer 60 on the second light-emitting functional layer 42.

[0080] In some embodiments, the first light-emitting functional layer 41 may be continuous or discontinuous at the notch T, depending on the width of the notch T. Among them, some film layers in the first light-emitting functional layer 41 may be discontinuous at the notch T, and some other film layers in the first light-emitting functional layer 41 may be continuous at the notch T.

[0081] Please refer to Figure 6 and Figure 7 , Figure 6 and Figure 7 are top-view structural schematic diagrams of the pixel opening and partition structure provided by some embodiments of the present application, mainly for showing the relative positional relationship between the pixel opening P and the partition structure 30.

[0082] The pixel openings P are arranged in an array along a first direction X and a second direction Y. The first direction X is perpendicular to the thickness direction Z of the array substrate 10, and the second direction Y is perpendicular to both the first direction X and the thickness direction Z of the array substrate 10.

[0083] The display panel includes sub-pixels arranged in an array along the first direction X and the second direction Y. Each sub-pixel corresponds to a pixel opening P (or an anode layer 80). The sub-pixels include red pixels, green pixels, and blue pixels.

[0084] As Figure 6 shown, the pixel barriers 70 are arranged in a grid around the pixel openings P, and the partition structure 30 is arranged in a grid around the pixel openings P. Therefore, the charge generation layers 50 between adjacent sub-pixels are completely partitioned.

[0085] Among them, the charge generation layer 50 can be discontinuous on one side of the partition structure 30 (reference can be made to Figure 2 ), or can be discontinuous on opposite sides of the partition structure 30.

[0086] As Figure 7 shown, the grid-shaped partition structure 30 has a plurality of intersections H, and the partition structure 30 is discontinuously arranged at at least one of the intersections H. Therefore, the partition structure 30 partitions the straight connection of the charge generation layers 50 between adjacent sub-pixels, and increases the transmission path of the charges in the charge generation layer 50 between adjacent sub-pixels, reducing the lateral charge transmission ability therein.

[0087] Embodiments of the present application further provide a method for manufacturing a display panel. Please refer to Figure 8 , Figure 8It is a schematic flowchart of a method for manufacturing a display panel provided by some embodiments of the present application. The method for manufacturing the display panel includes:

[0088] Step S1: Provide an array substrate.

[0089] Step S2: Form pixel barriers and pixel openings located between adjacent pixel barriers on the array substrate. The side of the pixel barrier facing away from the array substrate has a spaced opening.

[0090] Step S3: Form a partition structure in the spaced opening. The partition structure is located between two adjacent pixel openings along a first direction, and the first direction is perpendicular to the thickness direction of the array substrate. Along the direction close to the array substrate in the thickness direction of the array substrate, the cross-section of the partition structure gradually shrinks in the thickness direction and the first direction of the array substrate, and there is a notch between the side wall of the partition structure and the side wall of the spaced opening.

[0091] Step S4: Form a charge generation layer on the surface within the pixel opening, on the surface of the pixel barrier, and on the surface of the partition structure. The charge generation layer is discontinuously provided at the notch.

[0092] Step S5: Form a cathode layer on the surface of the charge generation layer. The cathode layer continuously extends at the notch.

[0093] In the method for manufacturing a display panel provided by the embodiments of the present application, the pixel barrier has a spaced opening, and there is a notch between the side wall of the partition structure and the side wall of the spaced opening. Since the cross-section of the partition structure gradually shrinks in the direction close to the array substrate in the thickness direction of the array substrate, the charge generation layer will be discontinuous at the notch. Since the width of the notch will be reduced after the charge generation layer is formed, when the cathode layer is formed thereon, the cathode layer can be continuous at the notch due to the small notch. Therefore, the present application can reduce the lateral leakage current of the charge generation layer and also reduce the power consumption.

[0094] The following describes the method for manufacturing a display panel provided by the embodiments of the present application with reference to the accompanying drawings.

[0095] Please refer to Figure 9 and Figure 10 , Figure 9 and Figure 10 are schematic cross-sectional structure diagrams of a display panel during the formation process provided by some embodiments of the present application.

[0096] Step S1: Provide an array substrate 10.

[0097] The method of forming the array substrate 10 may include: providing a substrate 11; forming a first transistor TFT1 and a second transistor TFT2 on the substrate 11, where the types of the first transistor TFT1 and the second transistor TFT2 are different; and forming a planarization layer PL on the first transistor TFT1 and the second transistor TFT2.

[0098] The first transistor TFT1 includes, from bottom to top, a first active layer 121, a first gate layer 131, and a second gate layer 132. The second transistor TFT2 includes, from bottom to top, a third gate layer 133, a second active layer 122, and a fourth gate layer 134, where the second gate layer 132 and the third gate layer 133 are arranged on the same layer.

[0099] The first transistor TFT1 further includes a first source electrode 141 and a first drain electrode 142 connected to both sides of the first active layer 121. The second transistor TFT2 further includes a second source electrode 143 and a second drain electrode 144 connected to both sides of the second active layer 122. The first source electrode 141, the first drain electrode 142, the second source electrode 143, and the second drain electrode 144 are arranged on the same layer. Among them, the second source electrode 143 is connected to one end of the first active layer 121 through a via hole to realize the electrical connection between the first drain electrode 142 and the second source electrode 143, and the first drain electrode 142 is connected to the anode layer 80 through a via hole.

[0100] Step S2: Form a pixel barrier 70 on the array substrate 10 and a pixel opening P located between adjacent pixel barriers 70. The side of the pixel barrier 70 facing away from the array substrate 10 has a spacer opening C.

[0101] In some embodiments, before forming the pixel barrier 70 and the pixel opening P, an anode layer 80 may be formed on the array substrate 10.

[0102] In some embodiments, referring to Figure 9 , the method of forming the pixel barrier 70 and the pixel opening P includes: forming a first initial pixel definition layer on the array substrate 10; forming the pixel opening P and the spacer opening C in the first initial pixel definition layer. Among them, the pixel opening P exposes the anode layer 80, and the first initial pixel definition layer between adjacent pixel openings P forms a first pixel definition layer 71, and the first pixel definition layer 71 serves as the pixel barrier 70, and the spacer opening C penetrates through the first pixel definition layer 71 (i.e., the pixel barrier 70).

[0103] For example, a half-tone mask plate (Half Notch Tone Mask) may be used to form the pixel opening P and the spacer opening C.

[0104] In some embodiments, referring to Figure 10, the method for forming the pixel barrier 70 and the pixel opening P includes: forming a first initial pixel definition layer on the array substrate 10; forming a pixel opening P exposing the anode layer 80 in the first initial pixel definition layer; forming a second initial pixel definition layer on the first initial pixel definition layer; forming a spacer opening C in the second initial pixel definition layer. Wherein, the first initial pixel definition layer between adjacent pixel openings P forms a first pixel definition layer 71, the second initial pixel definition layer on both sides of the spacer opening C forms a second pixel definition layer 72, and the pixel barrier 70 includes the first pixel definition layer 71 and the second pixel definition layer 72.

[0105] Step S3: Form a partition structure 30 in the spacer opening C. The partition structure 30 is located between two adjacent pixel openings P along the first direction X, and the first direction X is perpendicular to the thickness direction Z of the array substrate 10; along the direction close to the array substrate 10 in the thickness direction Z of the array substrate 10, the cross-section of the partition structure 30 gradually shrinks inward along the thickness direction Z and the first direction X of the array substrate 10, and there is a notch T between the side wall of the partition structure 30 and the side wall of the spacer opening C.

[0106] The method for forming the partition structure 30 includes: performing a lithography process of negative photoresist using a single mask plate to form an inverted trapezoidal negative photoresist isolation column (i.e., the partition structure 30) in the spacer opening C, and two notches T are formed between the spacer opening C and the partition structure 30.

[0107] Step S4: Form a charge generation layer 50 on the surface within the pixel opening P, on the surface of the pixel barrier 70, and on the surface of the partition structure 30. The charge generation layer 50 is discontinuously provided at the notch T. Please refer to Figures 2 to 5 。

[0108] In some embodiments, the process for forming the charge generation layer 50 includes an evaporation process.

[0109] Step S5: Form a cathode layer 60 on the surface of the charge generation layer 50. The cathode layer 60 continuously extends at the notch T. Please refer to Figures 2 to 5 。

[0110] In some embodiments, the process for forming the cathode layer 60 includes an evaporation process.

[0111] The description of the above embodiments is only used to help understand the technical solutions and their core ideas of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: include: An array substrate; A pixel blocking wall located on the array substrate, and a pixel opening located between adjacent pixel blocking walls, wherein a side of the pixel blocking wall facing away from the array substrate has a spacing opening; A partition structure is located in the spacing opening, the partition structure is located between two adjacent pixel openings along a first direction, the first direction is perpendicular to the thickness direction of the array substrate; in the thickness direction of the array substrate along a direction close to the array substrate, the cross section of the partition structure along the thickness direction of the array substrate and the first direction gradually shrinks inward, and a gap is provided between a side wall of the partition structure and a side wall of the spacing opening; A charge generation layer is located in the pixel opening, on the surface of the pixel blocking wall and on the surface of the partition structure, and the charge generation layer is disconnected at the notch; The cathode layer is located on the surface of the charge generating layer, and the cathode layer continuously extends at the notch.

2. The display panel according to claim 1, characterized in that: The pixel blocking wall comprises a first blocking wall and a second blocking wall, wherein the first blocking wall and the second blocking wall are respectively located at two sides of the spacing opening along the first direction; The notch is located at least one of between the first retaining wall and the partition structure and between the second retaining wall and the partition structure.

3. The display panel according to claim 1 or 2, characterized in that: An angle is formed between the side wall of the spacing opening and the array substrate, the angle is oriented toward the partition structure, and the angle is greater than or equal to 90 degrees.

4. The display panel according to claim 3, characterized in that: In the same notch, the side wall of the spacing opening and the side wall of the partition structure are parallel to each other.

5. The display panel according to claim 2, characterized in that: The notch comprises a first opening end and a second opening end which are arranged opposite to each other along the thickness direction of the array substrate, and the first opening end is farther away from the array substrate than the second opening end; The width of the first opening end along the first direction is 0.2 micrometers to 1.5 micrometers.

6. The display panel according to claim 1, characterized in that: The ductility of the material of the cathode layer is stronger than the ductility of the material of the charge generation layer.

7. The display panel according to claim 1, characterized in that: The cross section of the partition structure along the thickness direction of the array substrate and the first direction is an inverted trapezoid with the short side facing the array substrate.

8. The display panel according to claim 1, characterized in that: The pixel blocking wall comprises a first pixel definition layer located on the array substrate; the spacing opening penetrates the first pixel definition layer and exposes the array substrate; and the partition structure contacts the array substrate.

9. The display panel according to claim 1, characterized in that: The pixel blocking wall comprises a first pixel definition layer and a second pixel definition layer, wherein the first pixel definition layer is located on the array substrate, and the second pixel definition layer is located on a side of the first pixel definition layer away from the array substrate; The spacing opening penetrates the second pixel definition layer and exposes the first pixel definition layer; The partition structure contacts the first pixel definition layer.

10. The display panel according to claim 1, characterized in that: A height of the partition structure along the thickness direction of the array substrate is less than or equal to a height of the spacing opening along the thickness direction of the array substrate.

11. The display panel according to claim 1, characterized in that: Also includes: A first light-emitting functional layer is located in the pixel opening, on the surface of the pixel blocking wall and on the surface of the partition structure; The second light-emitting functional layer is located between the charge generating layer and the cathode layer and continuously extends at the gap.

12. The display panel according to claim 1, characterized in that: The pixel openings are arranged in an array along a first direction and a second direction, the first direction is perpendicular to the thickness direction of the array substrate, and the second direction is perpendicular to the first direction and the thickness direction of the array substrate respectively; The pixel blocking walls are arranged around the pixel openings in a grid shape, and the partition structures are arranged around the pixel openings in a grid shape.

13. The display panel according to claim 12, characterized in that: The grid-shaped partition structure has a plurality of intersections, and the partition structure is disconnected at at least one of the intersections.

14. A method for preparing a display panel, characterized in that: include: Providing an array substrate; Forming pixel blocking walls and pixel openings located between adjacent pixel blocking walls on the array substrate, wherein a side of the pixel blocking wall facing away from the array substrate has a spacing opening; A partition structure is formed in the spacing opening, the partition structure is located between two adjacent pixel openings along a first direction, the first direction is perpendicular to the thickness direction of the array substrate; in the thickness direction of the array substrate along a direction close to the array substrate, the cross section of the partition structure along the thickness direction of the array substrate and the first direction gradually shrinks inward, and a gap is provided between a side wall of the partition structure and a side wall of the spacing opening; forming a charge generation layer in the pixel opening, on the surface of the pixel blocking wall and on the surface of the partition structure, wherein the charge generation layer is disconnected at the notch; A cathode layer is formed on the surface of the charge generating layer, and the cathode layer continuously extends at the notch.

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