Memory system and operating method for improving

Abstract

A method of operating a memory system may include maintaining one or more last write page tables, periodically updating the one or more last write page tables to include at least one page sequence number of a last page being written in a flash medium, determining a last checkpoint in the flash medium, periodically updating and saving the checkpoint, and storing the last checkpoint in the flash medium. The method includes determining at least one page sequence number in one or more last written page tables, verifying a page having the highest page sequence number in the one or more last written page tables, verifying a page having a page sequence number in the one or more last written page tables after the verified page having the page sequence number until an uncorrectable error correction code (UECC) appears, and reconstructing the mapping table from a page from the last checkpoint to the last verified page before the UECC appears.

Description

Technical Field

[0001] The present disclosure relates to flash memories, and more particularly, to a method and system for improving performance after an unexpected power failure. Background Art

[0002] Non-volatile memory devices are sometimes referred to as flash memories, such as NAND flash used in solid state drives (SSDs). SSDs provide a relatively reliable and easily accessible method for storing data when power is off. However, an SSD still includes a volatile memory portion for fast data transfer between a host and memory chips, such as static random access memory (SRAM) or dynamic random access memory (DRAM). When an unexpected power failure occurs, if the data stored in the volatile memory portion is not saved to the NAND memory, it may be lost or interrupted. Summary of the Invention

[0003] Aspects of the present disclosure provide a method of operating a memory system. The method may include maintaining one or more last written page tables, periodically updating the one or more last written page tables to include at least one page sequence number of the last page being written to a flash medium, determining a last checkpoint in the flash medium, periodically updating and saving the checkpoint, determining at least one page sequence number in the one or more last written page tables, verifying a page having the highest page sequence number in the one or more last written page tables, verifying pages having page sequence numbers after the verified page having a page sequence number in the one or more last written page tables until an uncorrectable error correction code (UECC) occurs, and reconstructing a mapping table based on the pages from the last checkpoint until the last verified page before the UECC occurs.

[0004] In an embodiment, maintaining the last written page table may further include periodically updating the last written page table to include at least one page sequence number of pages of different data types. In an embodiment, the data type of a page is one of a checkpoint type, a garbage collection / merge type, or a user data type.

[0005] In an embodiment, the one or more last written page tables are periodically updated to include at least one page sequence number of pages between two checkpoints.

[0006] In an embodiment, the one or more last written page tables are periodically saved to the flash medium. In an embodiment, the one or more last written page tables are periodically saved when the checkpoint is saved to the flash medium.

[0007] In an embodiment, in response to the page having the highest page sequence number in the one or more last written page tables being invalid, the method may further include verifying the page having the second highest page sequence number in the one or more last written page tables.

[0008] Aspects of the present disclosure provide a memory system including a controller and a memory device. The controller may be configured to maintain one or more last written page tables, periodically update the one or more last written page tables to include at least one page sequence number of the last page being written to a flash memory medium, determine a last checkpoint in the flash memory medium, periodically update and save the checkpoint, determine at least one page sequence number in the one or more last written page tables, verify the page having the highest page sequence number in the one or more last written page tables, verify the pages having page sequence numbers after the verified page having a page sequence number in the one or more last written page tables until an uncorrectable error correction code (UECC) occurs, and reconstruct a mapping table based on the pages from the last checkpoint until the last verified page before the occurrence of the UECC.

[0009] Aspects of the present disclosure provide a non - transitory computer - readable medium storing instructions that, when executed by a processor, cause the processor to perform the method. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The various embodiments of the present disclosure presented as examples will be described in detail with reference to the following drawings, in which like reference numerals represent like elements, and in which:

[0011] Figure 1 A block diagram of an example system 100 having a memory device is shown in accordance with some aspects of the present disclosure.

[0012] Figure 2A A view of an example memory card having a memory device is shown in accordance with some aspects of the present disclosure.

[0013] Figure 2B A view of an example solid - state drive (SSD) having a memory device is shown in accordance with some aspects of the present disclosure.

[0014] Figure 3 A schematic diagram of an example memory device including peripheral circuits is shown in accordance with some aspects of the present disclosure.

[0015] Figure 4 A side view of a cross - section of an example memory cell array including NAND memory strings is shown in accordance with some aspects of the present disclosure.

[0016] Figure 5A block diagram showing an example memory device including a memory cell array and peripheral circuits according to some aspects of the present disclosure.

[0017] Figure 6 An example of a block layout according to aspects of the present disclosure is shown.

[0018] Figure 7 The impact of abnormal power-off on data stored on the SSD is shown.

[0019] Figure 8 The process 800 of power-off recovery during normal operation is shown.

[0020] Figure 9 A flowchart of the block reconstruction process in the SSD is shown.

[0021] Figure 10 An example of sorting pages with different data during sudden power-off recovery is shown.

[0022] Figure 11 An example of sorting pages using the last-written page table according to the present disclosure is shown.

[0023] Figure 12 The process 1200 of reconstructing the mapping table according to aspects of the present disclosure is shown. Detailed Description

[0024] Figure 1 A block diagram showing an example system 100 having a memory device according to some aspects of the present disclosure. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage body. As Figure 1 shown, the system 100 can include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 can be a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host 108 can be configured to send data to the memory device 104 or receive data from the memory device 104.

[0025] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can manage the data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment such as a Solid State Drive (SSD) or an Embedded Multimedia Card (eMMC), which is used as a data storage body for mobile devices (such as smart phones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller 106 can be configured to control the operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions regarding the data stored in or to be stored in the memory device 104, including (but not limited to) bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process Error Correction Code (ECC) for data read from or written to the memory device 104. Any other suitable functions can also be performed by the memory controller 106, such as formatting the memory device 104. Consistent with some aspects of the present disclosure, the memory controller 106 is configured to perform mapping table reconstruction after an abnormal power failure recovery, as described in detail below.

[0026] The memory controller 106 can communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with an external device through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial-ATA protocol, Parallel-ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0027] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 102 can be implemented and packaged into different types of end-user electronic products. In Figure 2AIn one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 may also include a memory card connector 204 that couples the memory card 202 to a host (e.g., Figure 1 the host 108 in). In another example as shown in Figure 2B , the memory controller 106 and multiple memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include an SSD connector 208 that couples the SSD 206 to a host (e.g., Figure 1 the host 108 in). In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than that of the memory card 202.

[0028] Figure 3 Schematic circuit diagram showing an example memory device 300 including peripheral circuits according to some aspects of the present disclosure. The memory device 300 may be an example of the memory device 104 in Figure 1 . The memory device 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, where the memory cells 306 are provided in the form of an array of NAND memory strings 308, and each NAND memory string 308 extends vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or a charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor or a charge-trapping type memory cell including a charge-trapping transistor.

[0029] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also referred to as a triple-level cell (TLC)), or four bits per cell (also referred to as a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal stored values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programmed levels from an erased state by writing one of three possible nominal stored values to the cell. A fourth nominal stored value can be used for the erased state.

[0030] As Figure 3 shown, each NAND memory string 308 can include a source select gate (SSG) 310 at its source extreme and a drain select gate (DSG) 312 at its drain extreme. The SSG 310 and DSG 312 can be configured to activate the selected NAND memory string 308 (a column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same block 304 are coupled through the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all of the NAND memory strings 308 in the same block 304 have an array common source (ACS). According to some embodiments, the DSG 312 of each NAND memory string 308 is coupled to a respective bit line 316 from which data can be read or written via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the DSG 312) or a deselect voltage (e.g., 0V) to the respective DSG 312 via one or more DSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the SSG 310) or a deselect voltage (e.g., 0V) to the respective SSG 310 via one or more SSG lines 315.

[0031] As Figure 3As shown, the NAND memory strings 308 can be organized into multiple blocks 304, and each block 304 can have, for example, a common source line 314 coupled to the ACS. In some embodiments, each block 304 is a basic data unit for an erase operation, i.e., all memory cells 306 on the same block 304 are erased simultaneously. To erase the memory cells 306 in a selected block 304, the source line 314 coupled to the selected block 304 and the unselected blocks 304 in the same plane as the selected block 304 can be biased with an erase voltage (Vers), such as a high positive voltage (e.g., 20V or higher). It should be understood that in some examples, the erase operation can be performed at a half-block level, a quarter-block level, or at a level with any suitable number of blocks or any suitable fraction of a block. The memory cells 306 of adjacent NAND memory strings 308 can be coupled by word lines 318, and which row of memory cells 306 is selected by the word lines 318 is affected by read and program operations. In some embodiments, each word line 318 is coupled to multiple memory cells 306 in a block.

[0032] Figure 4 A cross-sectional schematic diagram of an example memory array 301 including NAND memory strings 308 according to some aspects of the present disclosure is shown. The NAND memory strings 308 can include a stacked structure 404, and the stacked structure 404 includes multiple gate layers 406 and multiple insulating layers 408 that are alternately stacked in sequence, and the memory string 308 vertically penetrates the gate layers 406 and the insulating layers 408. The gate layers 406 and the insulating layers 408 can be alternately stacked, and two adjacent gate layers 406 are separated by one insulating layer 408. The number of pairs of gate layers 406 and insulating layers 408 in the stacked structure 404 can determine the number of memory cells included in the memory array 301.

[0033] The constituent material of the gate layer 406 can include a conductive material. The conductive material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 406 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 406 includes a doped polysilicon layer. Each gate layer 406 can include a control gate surrounding the memory cell. The gate layer 406 at the top of the stacked structure 404 can extend laterally as an upper select gate line, the gate layer 406 at the bottom of the stacked structure 404 can extend laterally as a lower select gate line, and the gate layer 406 extending laterally between the upper select gate line and the lower select gate line can be used as a word line layer.

[0034] In some embodiments, the stack structure 404 may be disposed on the substrate 402. The substrate 402 may include silicon (e.g., single-crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0035] The peripheral circuit 302 may be coupled to the memory cell array 301 via bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed-signal circuits for facilitating the operation of the memory cell array 301 by applying voltage signals and / or current signals to each target memory cell 306 and sensing voltage signals and / or current signals from each target memory cell 306 via the bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some example peripheral circuits including a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518 are shown. It should be understood that in some examples, additional peripheral circuits not shown Figure 5 may also be included.

[0036] The page buffer / sense amplifier 504 may be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 may store a page of programming data (write data) to be programmed into the memory cells 306. In another example, the page buffer / sense amplifier 504 may perform a programming verification operation to ensure that data has been properly programmed into the memory cells 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 may also sense a low-power signal from the bit line 316 representing the data bits stored in the memory cells 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 may be configured to be controlled by the control logic 512 and select one or more NAND memory strings 308 by applying bit line voltages generated from the voltage generator 510.

[0037] The row decoder / word line driver 508 may be configured to be controlled by the control logic 512, the select / deselect block 304 of the memory cell array 301, and the select / deselect word lines 318 of the block 304. The row decoder / word line driver 508 may be further configured to drive the word lines 318 with word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the SSG lines 315 and the DSG lines 313. The row decoder / word line driver 508 may be configured to apply a read voltage to a selected word line 318 during a read operation of the memory cells 306 coupled to the selected word line 318.

[0038] The voltage generator 510 may be configured to be controlled by the control logic 512 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301. The control logic 512 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. The register 514 may be coupled to the control logic 512 and include a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit.

[0039] The interface 516 may be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and status information received from the control logic 512, and relay the control commands received from the host to the control logic 512 and the status information received from the control logic 512 to the host. The interface 516 may also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data input / output (I / O) interface and a data buffer to buffer and relay data to and from the memory cell array 301.

[0040] Return reference Figure 1 The memory controller 106 may be configured to maintain a mapping table for mapping logical addresses to corresponding physical addresses. In some embodiments, the number of logical addresses is different from the number of physical addresses. For example, data stored at multiple logical addresses may be written into a memory cell having one physical address. The mapping table may be referred to as a logical-to-physical (L2P) table for mapping two addresses. To retrieve a specific piece of data, the host 108 may provide the logical address of the target data, and the memory controller may utilize the L2P mapping table to identify the physical address of the target data in the memory device 104 and retrieve the stored data.

[0041] Several methods can be used to store and maintain the L2P mapping table. One such method is single-level direct L2P mapping. Under this mapping scheme, the mapping table includes entries for each page and a summary page for metadata at the end of each block containing logical block address information. The L2P mapping table can be stored in a memory device within the flash memory controller. For example, the L2P mapping table can be stored in a static random access memory (SRAM) device. For example, the L2P mapping table can be stored in a dynamic random access memory (DRAM) device. Single-level direct L2P mapping can contain mapping information for the entire flash memory device. Therefore, the single-level direct page mapping scheme requires a large amount of storage space (about 1-2MB per GB of user storage) to store the L2P mapping table.

[0042] Another method for storing and maintaining the L2P mapping table is the multi-level mapping scheme. For example, the multi-level mapping scheme can group multiple adjacent logical blocks together and can include a page global directory for each grouped block. The page global directory can be stored in a memory device (e.g., SRAM or DRAM) within the flash memory controller for fast access. The mapping scheme also includes a page middle directory and a page table, which are stored and maintained in pages at the memory cell level located in the spare area of the NAND memory device. The page table contains the physical block number and physical page number of the data.

[0043] The flash translation layer (“FTL”) is an algorithm that can be executed in the memory controller 106 to convert logical addresses to physical addresses. Under single-level direct L2P mapping, the FTL can be utilized to read and scan the L2P mapping table stored within the flash memory controller. Under the multi-level mapping scheme, the FTL can be utilized to read the page global directory stored in the flash memory controller and access the spare memory cells of the NAND memory device to obtain the page middle directory and the page table in order to retrieve the requested data address.

[0044] Since the L2P mapping tables are typically stored in volatile memory devices such as SRAM or DRAM for faster access during operation, they are vulnerable to power loss. During a planned power outage, the L2P mapping tables can be saved by the memory controller to the NAND flash memory device before the power loss. The L2P mapping tables can be reconstructed or recovered by the host from the saved data from the memory device. However, when an abnormal power outage event (e.g., a sudden power outage event) occurs, the L2P mapping tables cannot be saved to the memory device in time and the data stored therein is lost. The memory system needs to undergo a sudden power outage recovery to restore the last state after powering on again.

[0045] During power-up, the memory controller begins by reading metadata stored in the NAND flash memory device. The metadata can include information about the NAND flash memory device, such as its structure, block status, wear-leveling data, and any bad blocks. The memory controller also reads checkpoint data stored in the NAND flash memory. The checkpoint indicates that data stored prior to the checkpoint has been verified for storage in the NAND flash memory cells. For example, the checkpoint can indicate the page sequence numbers of the pages that have been verified for storage in the NAND flash memory. The checkpoint is created by the FTL periodically or when specific conditions are met. For example, the FTL can create a checkpoint every few data blocks written to the NAND flash memory.

[0046] Figure 6 An example of a block layout in accordance with aspects of the present disclosure is shown. The SSD can include a code block (CODEBLK), a quick boot table (QBT), a system information block (SYSINFO), a table block (TABLE), and a checkpoint block (CHKPT). For example, as Figure 6 shown, the SSD can include eight dies of memory cells and can include one code block, three quick boot tables, two system information blocks, eight table blocks, and two checkpoint blocks. The code block can be used to store a firmware bin. Each die can include two blocks for the code block. The quick boot tables can be used to store subsequent indexes of checkpoint indexes and can be used for normal power-down recovery. Each quick boot table can be divided into two groups, each group covering four dies. The system information block can be used to store metadata, such as error logs and event logs. The table blocks can be used to store mapping tables (e.g., L2P tables), bad block tables, wear-leveling tables, etc. The checkpoint block can be used to store a snapshot of the data stored on the NAND flash memory (i.e., the checkpoint).

[0047] Figure 7 An illustration of the impact of an abnormal power-down on data stored on the SSD is shown. A sudden power-down can affect the cache of the NAND flash memory. During normal SSD operation, host data cached in the memory controller buffer 702 is flushed to the NAND bank 704 using a timestamp. Checkpoint information stored in the memory controller buffer 702 is periodically flushed to the NAND bank 704 using a timestamp. The checkpoint information can be used to indicate the primary mapping table and / or the secondary mapping table of different blocks of the NAND flash memory. The L2P mapping table temporarily stored in the memory controller buffer 702 is flushed to the NAND bank 704 using a timestamp. When an abnormal power loss occurs, host data, checkpoint information, and the L2P mapping table that have not been flushed to the NAND bank 704 may be lost or corrupted, which can affect the data integrity of the SSD.

[0048] Figure 8 Shows the process of power - off recovery during normal operation. This process can start from S801 and proceed to S802.

[0049] At S802, the memory controller can verify the Quick Boot Table (QBT) stored in the system. If it is determined that the QBT is valid, the process can proceed to S810 to perform QBT recovery and can end at S899.

[0050] If the memory controller determines that the QBT is invalid, the process can proceed to S820 to perform an abnormal power - off reconstruction process.

[0051] At S820, the memory controller can sort the pages within the NAND block by timestamp. Different data flushed into the NAND block may not follow the logical addresses of the host or the memory controller. For example, two consecutive pages can store table data and host data, while their logical addresses may not be consecutive. Therefore, the NAND blocks in the SSD need to be sorted by the timestamp of the NAND block.

[0052] At S830, the memory controller can restore the snapshot from the checkpoint. The snapshot can be restored based on the sorted NAND blocks, and the timestamp of each page / block is associated.

[0053] At S840, the memory controller can double - check whether the table data or host data is consistent by confirming the recovery.

[0054] At S850, the memory controller can restore the table change through the head block recovery. The memory controller can update any mapping table according to the restored NAND block. The process can proceed to S899 and end at S899.

[0055] Figure 9 Shows the flowchart of the block reconstruction process in the SSD. The reconstruction follows the order as Figure 9 shown, first restoring the checkpoint information, and then data blocks such as host data blocks, table blocks, and any other data - type blocks. The data flushed before the checkpoint can be considered valid, so the reconstruction process starts from the last valid checkpoint. Next, the system information block is reconstructed, and then the head page is reconstructed. Each block can include a head page, and the head page can include the metadata or user data of the block. The head page of each block is reconstructed according to the restored block and the reconstructed system information block. Next, the table and host data can be restored according to the pages restored or reconstructed since the start of the reconstruction process. The head page can be refreshed accordingly to include the updated metadata of the corresponding block at the end.

[0056] Figure 10An example of sorting pages with different data during a sudden power failure recovery is shown. The pages shown to the right of the sorting process 1001 represent the pages stored in the NAND memory. The pages are sorted according to the data type of the pages (e.g., sorted in data block 1002, table block 1003, garbage collection / merge block 1004, etc.). The pages within each block may not have consecutive page sequence numbers (i.e., page indices). Since the pages before the checkpoint in each block can be considered valid, the sorting process 1001 only needs to sort and verify the pages flushed after the checkpoint. The sorting process 1001 sorts the pages according to PgSN, regardless of the data type of the pages. Then the sorted pages (i.e., to the right of the sorting process 1001) can be verified until an uncorrectable error correction code appears.

[0057] However, depending on system preferences, the number of pages after the checkpoint that need to be sorted and verified may be large. The number of pages to be verified directly affects the sudden power failure recovery time, which affects the system power-on time. Therefore, according to aspects of the present disclosure, the last written page can be periodically determined to reduce the number of pages to be verified.

[0058] In an embodiment, the memory controller can periodically save the index (e.g., PgSN) of the last written page of different types of pages. Each type of page can have a different suitable saving frequency for the PgSN of the last written page. In an embodiment, the memory controller can save the PgSN of the last written page after a fixed number of the same type of pages have been flushed to the NAND memory. In an embodiment, the memory controller can save the PgSN of the last written page after a fixed time has passed.

[0059] Figure 11 An example of sorting pages using the last written page table according to the present disclosure is shown. The pages stored in the NAND memory are in the same order as the Figure 11 pages shown. The difference is that the last written page of each data block is recorded. For the page with PgSN 126 for data block 1102, for the page with PgSN 128 for table block 1103, and for the page with PgSN 130 for GC / merge block 1104, the last written page is recorded. In some embodiments, the table of PgSNs of the last written pages of different data blocks can be temporarily saved in the SRAM and periodically flushed to a dedicated section of the NAND memory. In some embodiments, the memory controller records the PgSN of the last written page at least once between two checkpoints of each block.

[0060] During the sorting process 1101, the memory controller needs to first determine the checkpoint for each block and then scan the last-written page table stored in the NAND memory. For example, the memory controller can scan the last-written page table and determine that PgSNs 126, 128, and 130 are stored therein. Then, the memory controller can scan the page with the highest PgSN to verify the data within the page with PgSN 130. If the page is verified, the memory controller can start performing a reconstruction and recovery process on any page sorted after the page with the highest PgSN in the last-written page table. For example, as Figure 11 shown, the memory controller can determine that the data is valid within the page with PgSN 130 and only needs to verify the pages with PgSNs 131, 132, and 133 until a UECC occurs.

[0061] However, in some cases, a sudden power outage may occur when updating the last-written page table. For example, although the PgSN is flushed in the NAND memory, the page with the highest PgSN in the last-written page table is invalid. In such a case, the memory controller needs to verify the page with the second-highest PgSN in the last-written page table. For example, as Figure 11 shown, when the memory controller determines that the data of the page with PgSN 130 is invalid, it continues to scan and verify the page with PgSN 128. If it is verified, the memory controller can verify the pages after the page with PgSN 128 until a UECC occurs. Otherwise, the memory controller can verify the previous pages with PgSNs in the last-written page table until a page can be verified, and then continue to verify any pages after the verified page with PgSN in the last-written page table until a UECC occurs. Then, the memory controller can use all the pages from the checkpoint until the last page before the UECC occurs to reconstruct the mapping table.

[0062] Figure 12 FIG. shows a process 1200 for reconstructing a mapping table according to aspects of the present disclosure. In some embodiments, process 1200 is performed by a memory controller, such as memory controller 106 of memory system 102. Process 1200 can start at S1201 and proceed to S1210.

[0063] At S1210, the memory controller may maintain one or more last written page tables. The one or more last written page tables are periodically updated to include at least one page sequence number of the last page being written to the flash medium. In one embodiment, the one or more last written page tables are periodically updated to include at least one page sequence number of pages of different data types. For example, one last written page table may be maintained to include one page sequence number of the last written page in a table block, one page sequence number of the last written page in a data block, and / or one page sequence number of the last written page in a garbage collection / merge block.

[0064] In one embodiment, the one or more last written page tables are flushed to the flash medium. In one embodiment, the one or more last written page tables are periodically updated to include at least one page sequence number of pages between two checkpoints. In one embodiment, when saving a checkpoint to the flash medium, the one or more last written page tables are periodically saved. In one embodiment, the one or more last written page tables are temporarily saved in SRAM.

[0065] At S1220, the memory controller may determine the last checkpoint in the flash medium and periodically update and save the checkpoint.

[0066] At S1230, the memory controller may determine at least one page sequence number in the one or more last written page tables. For example, the memory controller may read any page sequence number in the last written page table saved in the flash medium.

[0067] At S1240, the memory controller may verify the page with the highest page sequence number in the one or more last written page tables. In one embodiment, if the page with the highest page sequence number in the one or more last written page tables is invalid, the memory controller may verify the page with the second highest page sequence number in the one or more last written page tables and continue to verify until the page with a page sequence number in the one or more last written page tables is valid or the last checkpoint is read.

[0068] At S1250, the memory controller may verify the pages with page sequence numbers after the verified page with a page sequence number in the one or more last written page tables until an uncorrectable error correction code (UECC) occurs.

[0069] At S1260, the memory controller may reconstruct the mapping table based on all the pages from the last checkpoint until the last page before the UECC occurs. Then, process 1200 may proceed to S1299 and terminate at S1299.

[0070] The processes and functions described herein can be implemented as a computer program that, when executed by one or more processors, can cause the one or more processors to perform the corresponding processes and functions. The computer program can be stored or distributed on a suitable medium, such as an optical storage medium or a solid-state medium provided together with or as part of other hardware. The computer program can also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems. For example, the computer program can be obtained and loaded into a device, including obtaining the computer program through a physical medium or a distributed system (including, for example, from a server connected to the Internet).

[0071] The computer program can be accessed from a computer-readable medium that provides program instructions for use by or in conjunction with a computer or any instruction execution system. The computer-readable medium can include any device that stores, communicates, propagates, or transports the computer program for use by or in conjunction with the instruction execution system, apparatus, or device. The computer-readable medium can be a magnetic, optical, electronic, electromagnetic, infrared, or semiconductor system (or apparatus or device), or a propagation medium. The computer-readable medium can include a computer-readable non-transitory storage medium, such as semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), magnetic disk, and optical disk, among others. The computer-readable non-transitory storage medium can include all types of computer-readable media, including magnetic storage media, optical storage media, flash media, and solid-state storage media.

[0072] Although aspects of the present disclosure have been described in connection with specific embodiments of the present disclosure presented as examples, alternatives, modifications, and variations can be made to the examples. Accordingly, the embodiments set forth herein are intended to be illustrative and not restrictive. Changes can be made without departing from the scope of the claims set forth below.

Claims

1. A method of operating a memory system, comprising: Maintaining one or more last-written page tables, and periodically updating the one or more last-written page tables to include at least one page sequence number of the last page being written to a flash memory medium; Determining a last checkpoint in the flash memory medium, and periodically updating and saving the checkpoint; Determining the at least one page sequence number in the one or more last-written page tables; Verifying a page having the highest page sequence number in the one or more last-written page tables; Verifying pages having page sequence numbers after the verified page having a page sequence number in the one or more last-written page tables until an uncorrectable error correction code (UECC) appears; and Reconstructing a mapping table based on pages from the last checkpoint up to the last verified page before the UECC appears.

2. The method according to claim 1, wherein Maintaining the last-written page table further includes periodically updating the last-written page table to include at least one page sequence number of pages of different data types.

3. The method according to claim 2, wherein, The data type of the page is one of a checkpoint type, a garbage collection / merging type, or a user data type.

4. The method according to claim 1, wherein, Periodically updating the one or more last-written page tables to include at least one page sequence number of pages between two checkpoints.

5. The method according to claim 1, wherein, Periodically saving the one or more last-written page tables to the flash memory medium.

6. The method according to claim 5, wherein When saving the checkpoint to the flash memory medium, periodically saving the one or more last-written page tables.

7. The method according to claim 1, further comprising: In response to the page having the highest page sequence number in the one or more last-written page tables being invalid, verifying a page having the second highest page sequence number in the one or more last-written page tables.

8. A memory system including a controller and a memory device, the controller being configured to: Maintaining one or more last-written page tables, and periodically updating the one or more last-written page tables to include at least one page sequence number of the last page being written to a flash memory medium; Determining a last checkpoint in the flash memory medium, and periodically updating and saving the checkpoint; Determining the at least one page sequence number in the one or more last-written page tables; Verifying a page having the highest page sequence number in the one or more last-written page tables; Verifying pages having page sequence numbers after the verified page having a page sequence number in the one or more last-written page tables until an uncorrectable error correction code (UECC) appears; and Reconstructing a mapping table based on pages from the last checkpoint up to the last verified page before the UECC appears.

9. The memory system according to claim 8, wherein, The controller is further configured to periodically update the last-written page table to include at least one page sequence number of pages of different data types.

10. The memory system according to claim 9, wherein, The data type of the page is one of a checkpoint type, a garbage collection / merging type, or a user data type.

11. The memory system according to claim 8, wherein, Periodically updating the one or more last-written page tables to include at least one page sequence number of pages between two checkpoints.

12. The memory system according to claim 8, wherein, Periodically saving the one or more last-written page tables to the flash memory medium.

13. The memory system according to claim 12, wherein, When saving the checkpoint to the flash medium, the one or more last-written page tables are saved periodically.

14. The memory system according to claim 8, further comprising: In response to the page having the highest page sequence number in the one or more last-written page tables being invalid, verifying the page having the second-highest page sequence number in the one or more last-written page tables.

15. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform a method, the method comprising: Maintaining one or more last-written page tables, periodically updating the one or more last-written page tables to include at least one page sequence number of the last page being written to the flash medium; Determining the last checkpoint in the flash medium, periodically updating and saving the checkpoint; Determining the at least one page sequence number in the one or more last-written page tables; Verifying the page having the highest page sequence number in the one or more last-written page tables; Verifying the pages having page sequence numbers after the verified page having a page sequence number in the one or more last-written page tables until an uncorrectable error correction code (UECC) appears; and Reconstructing a mapping table based on the pages from the last checkpoint until the last verified page before the appearance of the UECC.

16. The non-transitory computer-readable medium according to claim 15, wherein, Maintaining the last-written page table further comprises periodically updating the last-written page table to include at least one page sequence number of pages of different data types.

17. The non-transitory computer-readable medium according to claim 16, wherein, The data type of the page is one of a checkpoint type, a garbage collection / merging type, or a user data type.

18. The non-transitory computer-readable medium according to claim 15, wherein, Periodically updating the one or more last-written page tables to include at least one page sequence number of the pages between two checkpoints.

19. The non-transitory computer-readable medium according to claim 15, wherein, Periodically saving the one or more last-written page tables to the flash medium.

20. The non-transitory computer-readable medium according to claim 19, wherein, When saving the checkpoint to the flash medium, the one or more last-written page tables are saved periodically.

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