Load-related method for reducing quiescent current during multi-cell to single-cell battery regulation

Abstract

The techniques disclosed herein may enable efficient regulation of power delivered from one or more batteries to a circuit or system having a power control device having two or more modes of operation. In a first mode of operation, the power control device may select a first power circuit to deliver power to the system load at a first static current, and in a second mode of operation, the power control device may select at least one additional power circuit to deliver power to the system load at a second static current. The first quiescent current is significantly less than the second quiescent current such that operation of the first power circuit corresponds to a lower power mode than the additional power circuit. The ideal diode circuit may be configured to selectively couple an output of each of the power circuits to a system load.

Description

Background Art

[0001] Electronic devices can use various battery topologies as power solutions. Some battery topologies can include multiple individual battery cells connected in series, in parallel, or a combination of series and parallel battery cells. The available power provided by a battery pack can be determined by the cell configuration and the rated parameters of the individual battery cells.

[0002] The total number of battery cells connected in series in a battery pack can be referred to as the S count; where 1S indicates a single cell, 2S indicates two cells in series, 3S indicates three cells in series, 4S indicates four cells in series, and so on. Similarly, the total number of battery cells connected in parallel in a battery pack can be referred to as the P count; where 1P indicates a single cell, 2P indicates two cells in parallel, 3P indicates three cells in parallel, and so on. The series-parallel configuration can be indicated by the S and P counts, such as xxSyyP. For example, a 1S3P configuration includes one series (1S) battery cell that is paralleled 3 times (3P), for a total of 3 cells, while a 4S2P configuration includes four series cells (4S) that are paralleled 2 times (2P), for a total of 8 cells.

[0003] The total power available in a battery pack depends on the cell configuration and cell parameters. Battery rated parameters typically include voltage (V) and capacity (C). An example battery cell can have a nominal rated voltage of 3.7V and a capacity of 2000 mAh. For this example, a 2S configuration can provide 7.4V (i.e., 3.7V × 2) with a capacity of 2000 mAh, while a 2P configuration can provide 3.7V with a capacity of 4000 mAh (i.e., 2000 mAh × 2), and a 3S3P configuration can provide 11.1V (i.e., 3.7V × 3) with a capacity of 6000 mAh. Thus, a battery pack with a configuration given as xxSyyP provides a total rated voltage (VR) determined according to the individual cell voltage (V), such as VR = xxV, and a total capacity (CR) determined according to the individual cell capacity (C), such as CR = yyC. The voltage and load requirements of an electronic device will determine the appropriate cell configuration needed in the battery pack.

[0004] This disclosure contemplates new techniques for providing efficient power delivery from power sources such as batteries and battery packs to system loads. Compared to conventional solutions, the disclosed solutions can be implemented with reduced circuit complexity, which improves reliability and reduces the total cost. The power consumption reduction achieved by the solutions of this disclosure can extend the storage time of battery-powered devices because the power consumption in storage and standby modes is significantly reduced. The disclosure herein is made in view of these and other considerations. Summary of the Invention

[0005] The techniques disclosed herein can achieve efficient regulation of power delivered from one or more batteries to a circuit or system having a power control device with two or more operating modes. In a first operating mode, the power control device can select a first power circuit to deliver power to a system load at a first quiescent current, while in a second operating mode, the power control device can select at least one additional power circuit to deliver power to the system load at a second quiescent current. The first quiescent current is significantly less than the second quiescent current, such that operation of the first power circuit corresponds to a lower power mode than the additional power circuit. An ideal diode circuit can be configured to selectively couple the output of each power circuit to the system load.

[0006] In some examples, the power control device described herein can employ a state machine or modal topology to detect and control selection of a particular power circuit that actively couples power to the system load.

[0007] In some additional examples, the method of the power control device described herein can employ a state machine or modal topology to detect and control selection of a particular power circuit that actively couples power to the system load.

[0008] Compared to conventional solutions, the currently described techniques can achieve a solution with reduced circuit complexity. As a result, a reduction in component cost, manufacturing cost, and an increase in reliability can be achieved. The power consumption reduction achieved by the solution of the present disclosure can extend the storage time of battery-powered devices, as the power consumption in storage and standby modes can be significantly reduced.

[0009] In some embodiments, a power control device for a battery-operated system is described, the power control device including: control logic circuitry configured to detect a power state of the system and responsive thereto provide one or more control signals to a control terminal; an ideal diode circuit that selectively couples power from one or more of a first power input terminal and a second power input terminal to a power output terminal in response to one or more control signals from the control terminal, wherein the power output terminal is coupled to the system; a first power circuit that receives power from a power terminal of the battery and provides a first regulated power signal to the first power input terminal; and a second power circuit that receives power from the power terminal of the battery and selectively provides a second regulated power signal to the second power input terminal when activated in response to a control signal from the control terminal, wherein the power consumed by the second power circuit is higher than the power consumption of the first power circuit.

[0010] In some additional embodiments, a power control device for a battery-operated system is described. The power control device includes: control logic circuitry configured to detect a power state of the system and responsively provide one or more control signals to a control terminal; an ideal diode circuit that selectively couples power from one or more of a first power input terminal and a second power input terminal to a power output terminal in response to the one or more control signals from the control terminal, wherein the power output terminal is coupled to the system; a linear regulator circuit that receives power from a power terminal of the battery and provides a first regulated power signal to the first power input terminal, wherein the linear regulator circuit operates at a first quiescent current; and a switched-mode power supply circuit that receives power from the power terminal of the battery and selectively provides a second regulated power signal to the second power input terminal when activated in response to a control signal from the control terminal, wherein the switched-mode power supply circuit operates at a second quiescent current that is substantially higher than the first quiescent current.

[0011] Some embodiments describe a method for delivering power from a battery-operated power control device to a system. The method includes: operating a state machine of the power control device in one of a first operating mode, a second operating mode, and a third operating mode; selectively coupling power from one or more of a main power circuit and an auxiliary power circuit to the system based on the operating mode of the state machine; in the first operating mode: disabling one or more main power circuits; enabling the auxiliary power circuit; monitoring system power; and transitioning from the first operating mode to the second operating mode when system power is detected as ON; in the second operating mode: enabling one or more main power circuits; monitoring system power; and transitioning from the second operating mode to the third operating mode when system power is detected as OFF; in the third operating mode: starting a countdown timer; monitoring system power and the countdown timer; transitioning from the third operating mode to the second operating mode when system power is detected as ON before the countdown timer expires; and transitioning from the third operating mode to the first operating mode when system power is not detected as ON and the shutdown timer expires.

[0012] By reading the following detailed description and reviewing the associated drawings, other features and advantages will become apparent which are not specifically described above. The present summary is provided to introduce a series of concepts in a simplified form, which will be further described in the detailed description below. The present summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. For example, the term "technique" may refer to one or more of systems, methods, computer-readable instructions, modules, algorithms, hardware logic, and / or operations as permitted by the above context and the entire document. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The specific implementation manners will be described with reference to the accompanying drawings. In the figures, the leftmost digit(s) of the reference numeral indicate(s) the figure in which the reference numeral first appears. The same reference numerals in different figures represent similar or identical items. References to individual items among a plurality of items may use reference numerals with a sequence of letters to refer to each individual item. General references to items may use specific reference numerals without a sequence of letters.

[0014] Figure 1 A first example battery-powered circuit or system arranged according to the embodiments described herein is schematically shown.

[0015] Figure 2 A second example battery-powered circuit or system arranged according to the embodiments described herein is schematically shown.

[0016] Figure 3 A state diagram of an example battery-powered circuit or system arranged according to the embodiments described herein is shown.

[0017] Figure 4 Another state diagram of another example battery-powered circuit or system arranged according to the embodiments described herein is shown.

[0018] Figure 5 Another state diagram of yet another example battery-powered circuit or system arranged according to the embodiments described herein is shown.

[0019] Figure 6 Another state diagram of yet another example battery-powered circuit or system arranged according to the embodiments described herein is shown.

[0020] Figure 7 A flowchart of an example process showing various example battery-powered circuits or systems arranged according to the embodiments described herein is shown. Specific implementation manners

[0021] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and which illustrate, by way of example, specific example configurations in which the concepts may be practiced. These configurations are described in sufficient detail to enable those skilled in the art to practice the techniques disclosed herein, and it should be understood that other configurations may be utilized and other changes may be made without departing from the spirit or scope of the presented concepts. Accordingly, the following detailed description should not be considered limiting, and the scope of the presented concepts is defined only by the appended claims.

[0022] Throughout the specification and claims, unless the context clearly dictates otherwise, the following terms have the meanings explicitly associated herein. The meanings of "a", "an", and "the" include plural references, and the meaning of "in" includes "in" and "on". The term "connected" refers to a direct electrical connection between the connected items without any intermediate device. The term "coupled" refers to a direct electrical connection between the connected items, or an indirect connection through one or more passive or active intermediate devices and / or components. The terms "circuit" and "component" refer to a single component or multiple components, whether active or passive, that are coupled to provide the desired function. The term "signal" refers to at least power, current, voltage, data, radio wave, magnetic wave, electromagnetic wave, or optical signal. Depending on the context, the term "coupled" can refer to wave or field coupling effects, which can involve corresponding optical fields, magnetic fields, electric fields, or combined electromagnetic fields.

[0023] The present disclosure contemplates new techniques for providing efficient power delivery from power sources such as batteries and battery packs to system loads. Compared with conventional solutions, the disclosed solutions can be implemented with reduced circuit complexity, which improves reliability and reduces the total cost. The power consumption reduction achieved by the solutions of the present disclosure can extend the storage time of battery-powered devices because the power consumption in storage and standby modes is significantly reduced. The disclosure herein is made in view of these and other considerations.

[0024] Efficient regulation of the power delivered to a circuit or system can be provided through at least two operating modes. A first power circuit can be employed to deliver power to the system load at a first quiescent current, while at least one additional power circuit can be employed to deliver power to the system load at a second quiescent current. The first quiescent current is significantly less than the second quiescent current, such that the operation of the first power circuit corresponds to a lower power mode than the additional power circuit. An ideal diode circuit is configured to selectively couple the output of each power circuit to the system load.

[0025] A state machine can detect and control the selection of a particular power circuit that actively couples power to the system load. By employing the disclosed techniques, the power consumption in the resulting system and circuit can be significantly reduced, which can be preferred in battery-powered solutions. Compared with traditional solutions, the circuit complexity is reduced, which further reduces the cost and improves the reliability. In addition, due to the reduced power consumption in storage and standby modes, the storage time of an exemplary battery-powered circuit can be significantly extended.

[0026] The above features, techniques, and advantages, as well as other aspects, will become more apparent based on the additional details provided below.

[0027] Figure 1Schematically shows a first example battery-powered circuit or system 100 arranged in accordance with embodiments described herein. The example shown includes a battery 110, control logic circuitry 120, a plurality of power circuits 130, an ideal diode circuit 140, and a system 150.

[0028] The battery 110 can correspond to a single-cell or multi-cell battery in a battery pack that includes an array of individual (1S) battery cells 111. For a multi-cell battery pack, each of the plurality of individual cells 111 can be provided in a series (xxS), parallel (yyP), or combined series-parallel (xxSyyP) configuration. The power output of the battery 110 can be provided at battery power terminals 10, which can correspond to a single terminal, or a set of terminals for positive, negative, and ground (e.g., VP, VN, GND, etc.).

[0029] The control logic circuitry 120 can correspond to digital logic circuitry that can be operated with power from the battery 110 (connections not shown), provide one or more control signals to control terminals 20, and monitor and / or provide feedback and control signals to / from the system 150 and / or the ideal diode circuit 140 at control terminal 24. The control logic circuitry 120 can include any kind of combinational logic gates, latches, registers, and other functions required for appropriate dynamic control to implement the various features described herein. In some examples, the control logic circuitry 120 can be implemented in discrete components, while in other examples, the control logic circuitry can be implemented as an integrated component, such as in a programmable logic device (PLD), programmable logic array (PLA), field programmable gate array (FPGA), microcontroller unit (MCU), or another integrated circuit (IC) type solution. In various examples, the functions of the control logic circuitry 120 can be used to implement a state machine with various operating states or modes, as will be further described below.

[0030] The power circuits 130 can correspond to any number (N) of individual power circuits (e.g., 131, 132,..., 133) that may be required in the system 150 to accommodate different system power efficiency and load requirements (e.g., load currents I L1 , I L2 , ……, I L3 ). Thus, each of the power circuits 130 can consist of a linear regulator circuit or a switched-mode power supply circuit as needed. Each of the power circuits receives power from the battery's power terminals 10 and can be selectively enabled in response to corresponding control signals (e.g., EN1, EN2,..., EN3) from the corresponding control terminals among control terminals 20, 21, 22, and 23 to provide a corresponding regulated power signal to the corresponding power input terminals among power input terminals 31, 32, and 33.

[0031] As Figure 1 shown, each of the first power circuit 131, the second power circuit 132, and the third power circuit 133 may receive power from the power terminal 10 of the battery 110; wherein the first power circuit 131 provides a first regulated power signal to the first power input terminal 31, the second power circuit 132 provides a second regulated power signal to the second power input terminal 32, and the third power circuit 133 provides a third regulated power signal to the third power input terminal 33. Also as shown, the second power circuit 132 may be coupled to the control terminal 20 to receive a control signal 22 for selective activation, while the third power circuit 133 may be coupled to the control terminal 20 to receive another control signal 23 for selective activation. For Figure 1 an example, the first power circuit 131 is always activated and does not have a control input; however, in other examples, the first power circuit 131 may be coupled to the control terminal 20 to receive another control signal 21 for selective activation.

[0032] The ideal diode circuit 140 includes a plurality of power input terminals designated as power input terminals 31, 32, and 33; and a common power output terminal designated as the power output terminal 40. As shown, each of the power input terminals 31, 32, and 33 corresponds to the output of one of the power circuits 130, 131, 132, and 133. The ideal diode circuit 140 further includes switch circuits 141, 142, and 143 and an ideal diode controller circuit 144. The inputs of the switch circuits 141, 142, and 143 are coupled to the corresponding power input terminals among the power input terminals 31, 32, and 33, and the outputs of the switch circuits are coupled together at the common power output terminal 40. The ideal diode controller circuit 144 has an input coupled to the control logic circuit at the control terminal 24 and an output coupled to the selection control terminal 117. In operation, the ideal diode controller circuit 144 is configured by the control logic circuit 120 to selectively activate one or more of the switch circuits 141, 142, and 143 via a selection control signal at the selection control terminal 117. When more than one of the switch circuits 141, 142, and / or 143 is simultaneously active, the ideal diode circuit 140 effectively operates in an OR configuration, where power is delivered in parallel from the active switch paths to the common output terminal 40.

[0033] The active switch effectively provides a closed circuit to couple power from a corresponding power input terminal in the power input terminals to the power output terminal; while the inactive (or deactivated) switch effectively provides an open circuit that decouples the corresponding power input terminal from the power output terminal. For example, the activated switch circuit 141 couples power from the power input terminal 31 to the power output terminal 40, the activated switch circuit 142 couples power from the power input terminal 32 to the power input terminal 40, and the activated switch circuit 143 couples power from the power input terminal 33 to the power output terminal 40. Thus, the ideal diode circuit 140 selectively couples power from one or more of the first power input terminal 31, the second power input terminal 32, and the third power input terminal 33 to the power output terminal 40 in response to one or more control signals from the selection control terminal 117.

[0034] The system 150 is shown to include a load 151 and a power management circuitry or 152, but is not limited thereto, and may include many other circuits and functions. The load 151 represents the total power consumption of the system 150, such as the different load current amounts required by the system (e.g., load currents I L1 、I L2 、……、I L3 ). The power management circuitry or 152 provides various functions that may be required for monitoring, regulating, and / or controlling the power delivered to the system 150 for proper system load management, as well as other functions such as battery charging (not shown). Additionally, the power management circuitry 151 may provide one or more feedback signals to the control logic circuitry 120, where one or more of the feedback signals may be used to activate or deactivate various operating modes.

[0035] In some examples, the power management circuit 151 may be implemented with a PMIC or a power management integrated circuit. The PMIC may provide complementary power management functions in a compact form. In a simple example, the PMIC may simply provide voltage regulation from a power voltage (e.g., the output of a battery source or another power circuit) to a target voltage that the system 150 may require. Additional functions that the PMIC may provide include voltage, current, power, temperature, and fault status monitoring of the system, where the PMIC may provide a feedback signal in response to one or more of these monitored system states. For example, the PMIC may provide a feedback signal to indicate when a rising power supply (VDDIO rising) is detected, when a falling power supply (VDDIO falling) is detected, a power ON state (PON) is detected, or when a power OFF state (POFF) is detected. Other faults may also be detected, such as overvoltage, undervoltage, overcurrent, overtemperature, undertemperature, etc. In some examples, the PMIC may provide a feedback signal to activate or deactivate the storage mode. In other examples, the PMIC may also provide a feedback signal indicating a change in the system power requirement based on the detected change in load current.

[0036] Figure 2 A second example battery-powered circuit or system 200 arranged in accordance with embodiments described herein is schematically illustrated. Similar to Figure 1 the Figure 2 example shown includes a battery 110, control logic circuitry 120, a plurality of power circuits 130, an ideal diode circuit 140, and a system 150. However, Figure 2 the example of

[0037] has been simplified for two power circuits 150, which will become clear in the discussion below. Q1 As shown, the first power circuit 231 may correspond to a linear regulator operating at a first quiescent current (I Q2 ), while the second power circuit 232 may correspond to a switched-mode power supply operating at a second quiescent current (I Q1 ). The first quiescent current (I Q2 ) may be significantly lower than the second quiescent current (I Q2 ), such that I Q1 >I Q1 . For example, the linear regulator circuit may have a first quiescent current (I Q2)。These values are merely example ranges and are not intended to be limiting. Through the operation of the control logic circuitry, the selective operation of the linear regulation 231 and the switched-mode power supply 232 can thus facilitate the lower and higher current load conditions (e.g., I L1 , I L2 , etc.) that system 150 may require.

[0038] Example linear regulator circuits that can be used in the power circuit can include: a Zener diode circuit, a low-dropout regulator (LDO) circuit, a series regulator circuit, a shunt regulator circuit, or a combination thereof. Example switched-mode power supply circuits that can be used in the power circuit can include a DC-DC converter circuit, a boost regulator circuit, a buck regulator circuit, or a combination thereof.

[0039] Figure 2 The ideal diode circuit 140 is further shown. Each of the first switch circuit 241 and the second switch circuit 242 can include a power MOS field-effect transistor device (MOSFET) that is configured to operate in an ideal diode configuration. Example MOS devices can include p-type or n-type MOS devices that have a low voltage drop across their drain and source terminals when active, such as in the range of about 10 mV to about 200 mV. The ideal diode circuit can include additional components, such as capacitors and Zener diodes, that are configured to provide power filtering and protection against reverse bias conditions.

[0040] The MOS devices 241 and 242 are configured to simulate an ideal diode with a very low forward voltage drop and negligible reverse current. Other ideal characteristics can include low operating quiescent current, very low off current, stable forward voltage, and fast reverse current response. The MOS devices are connected such that when the MOS is off, its body diode blocks reverse current, and when the MOS is on during forward conduction, the forward voltage drop and power consumption are low. The ideal diode controller 144 senses the reverse current through the active MOS device and turns it off, allowing the body diode to block the reverse current.

[0041] Example ideal diode controllers can include the LM66100, LM66200, TPS2410, and TPS2419 manufactured by Texas Instruments. Ideal diode controllers come in various configurations, some of which include the control of one, two, or more MOS devices, and some of which include (multiple) MOS devices integrated with the ideal controller. Thus, the implementation of the ideal diode circuit 140 can include: a single integrated circuit for an ideal diode controller with an integrated power MOS device, a single integrated circuit for an ideal diode controller with an external power MOS device, multiple integrated circuits (each with its own ideal diode controller and integrated power MOS device), or multiple integrated circuits (each with its own ideal diode controller and external power MOS device), or some combination thereof.

[0042] System 150 can be any electronic device or circuit that may require a battery-powered solution. Some examples can include battery cells coupled in series, such as one (1S), two (2S), three (3S), four (4S), or more cells in series. In some example systems, a mobile processor device (not shown) in the system may need to maintain a main voltage (e.g., VDD or VSYS) within a specific operating range corresponding to the voltage of a 1S battery pack. The mobile processor device can be sensitive to heat dissipation and may therefore need to efficiently convert from the higher voltage of the battery pack to the 1S battery voltage. One problem with very efficient conversion is that even when the regulator is in pulse frequency modulation (PFM) mode, the quiescent current (I Q ) can be quite high (e.g., in the order of 100 μA to 500 μA or more). For example, the total quiescent current of a reference product evaluated according to the present disclosure is approximately 400 μA in the OFF mode, where 190 μA of the quiescent current is generated by regulating the 2S battery voltage to the 1S voltage level.

[0043] As described and shown herein, two power circuits 130 can be placed in parallel, where the ideal diode circuit 140 is configured to select one or more sources from the two sources of the two power circuits 130 to deliver power to the load 151 of the system 150. The control circuit 120 can use a state machine and / or other combinational logic to determine when to enable or disable the main power circuit (or other power circuits). For Figure 2 an example, the main power circuit can be a switched-mode power supply (SMPS), and the auxiliary power circuit can be a linear regulator, such as a low-dropout regulator (LDO).

[0044] The control circuit 120 can be configured to detect when the system 150 is in the OFF or ON state (e.g., POFF of PON) via feedback from either the power management circuit 152 of the system 150 or the ideal diode controller 144 of the ideal diode circuit 140. The control circuit 120 can also be configured to determine when the system 150 has been in the OFF state for a period of time before disabling the main power circuit. The control circuit 120 can also be configured to detect the power ON state, such as when the system 150 starts to boot or a power ON sequence, or when some other power ON trigger event (PON) is detected, where after the power ON state is detected, the main power can be enabled.

[0045] Compared with conventional solutions, the overall static current of the currently disclosed examples can reduce the current (or power) consumption by up to 95%. This reduced power consumption can translate into additional shelf life of several months (e.g., an additional 2 to 6 months). Although power consumption and shelf life can be extended by simply using a 1S battery pack, this solution is impractical because in many applications, system power delivery and load requirements call for a 2S or larger battery pack option.

[0046] Traditional solutions attempt to reduce the static current (I Q ) by using the PFM operation mode of a buck regulator instead of the pulse width modulation or PWM mode. The PFM mode can significantly reduce the power of PWM mode operation. However, the present disclosure recognizes that PFM mode regulation relies on a power topology with an inherent power consumption cost (increased I Q ), and this power consumption cost does not exist in linear regulators.

[0047] Other traditional solutions can use a switched-capacitor voltage divider topology. In these switched-capacitor solutions, two capacitors are initially connected in series for charging, and then these two capacitors are switched to a parallel configuration to produce an output voltage that is half of the initial power voltage. The switched-capacitor method can also have high power consumption (increased I Q ), because the circuit needs to switch between these two states at a relatively high frequency to maintain a stable system output voltage. In one example, the I Q of the switched-capacitor topology is approximately 400 μA, which is even greater than the I Q of the buck regulator in the PFM mode. In addition, there are practical limitations on how much current the switched-capacitor solution can provide without using an unreasonable capacitor area. The same total output power of the switched-capacitor solution can be achieved using the solutions described herein, with a much smaller area used in the overall implementation.

[0048] The currently disclosed technology provides a novel solution for power, while providing reduced static current, reduced area or footprint, and reduced complexity. The currently disclosed solution divides the power design into two parts. During normal active operation, power such as a buck regulator can be used to efficiently power the system. During low-power operation, a linear regulator such as an LDO can be used to provide minimum power to the system. Although the linear regulator does not provide a large amount of power, it is capable of providing sufficient power to keep the system running intact. For example, the linear regulator can provide sufficient power for registers and a real-time clock (RTC) in a power management circuit (e.g., PMIC) to operate reliably.

[0049] Accordingly, the solution described herein has many advantages, including but not limited to extending the shelf life of products stored before activation, low static current of devices in an inactive mode, and efficient power supply to the system in an active mode. Other advantages can include reduced circuit complexity, reduced circuit area or footprint, and reduced manufacturing cost. The storage time is expected to increase by a certain magnitude (e.g., double or more), and thus the device can stay in memory for a longer time before the system clock needs to be reset, which is crucial for some users who may not activate these devices for a long time.

[0050] Figure 3 FIG. 300 is a state diagram showing an example battery-powered circuit or system arranged according to an embodiment described herein. State diagram 300 includes three operating states designated as State 1, State 2, and State, which are managed by control logic circuit 120.

[0051] In a first operating state (State 1, 310), the system is considered to be in the OFF mode. For this first operating state or OFF mode 310, a first power circuit is enabled or ON, and other power circuits are disabled or OFF. In some examples, the first power circuit (e.g., 131) is always enabled in OFF mode 310, while in other examples, the first power circuit is enabled in OFF mode 320 via a control signal (e.g., EN1) asserted (e.g., logic 1) by control logic circuit 120. In OFF mode 310, other power circuits (e.g., 132, 133, etc.) are disabled via corresponding control signals (e.g., EN2, ……, EN N ) de-asserted (e.g., logic 0) by control logic circuit 120.

[0052] In OFF mode 310, ideal diode circuit 140 can couple first power input terminal 31 to power output terminal 40 in response to one or more control signals from control logic circuit 120. Control logic circuit 120 is also configured to monitor the system power state (e.g., via feedback signal 24 from the PMIC and / or ideal diode controller). When the system power state is detected as ON (312, System Power ON DET), control logic circuit 120 transitions from the first operating state (State 1, 310) to the second operating state (State 2, 320).

[0053] In the second operating state (State 2, 320), the system is considered to be in ON mode. For this second operating state or ON mode 320, the first power circuit and all other power circuits can be enabled or ON. In some examples, the first power circuit (e.g., 131) is always enabled in ON mode 320, while in other examples, the first power circuit is enabled in ON mode 220 via a control signal (e.g., EN1) asserted (e.g., logic 1) by control logic circuit 120. In still other examples, the first power circuit can be disabled in ON mode 320 via a control signal (e.g., EN1) de-asserted (e.g., logic 0). Other power circuits (e.g., 132, 133, etc.) can be enabled in ON mode 320 via corresponding control signals (e.g., EN2, …, EN N ) asserted (e.g., logic 1) by control logic circuit 120.

[0054] In ON mode 320, ideal diode circuit 140 can couple both first power input terminal 31 and second power input terminal 32 to power output terminal 40 in response to a control signal from control logic circuit 120. Control logic circuit 120 is also configured to monitor the system power state in ON mode 320 (e.g., via feedback signal from the PMIC and / or ideal diode controller). When the system power state is detected as OFF (323, System Power OFF DET), control logic circuit 120 transitions from the second operating state (State 2, 320) to the third operating state (State 3, 330), and a countdown timer is initiated (e.g., the timer is reset and starts counting down).

[0055] In the third operating state (State 3, 330), the system is considered to be in a shutdown mode. For this third operating state or shutdown mode 330, the first power circuit and all other power circuits can maintain their current operation (e.g., enabled or ON) from the ON mode 320. In some examples, the first power circuit (e.g., 131) remains enabled (e.g., if enabled in the ON mode), while in other examples, the first power circuit can remain disabled (e.g., if disabled in the ON mode). The other power circuits (e.g., 132, 133, etc.) remain enabled in the shutdown mode 330 via corresponding control signals (e.g., EN2, …, EN N ) that are held asserted (e.g., logic 1) by the control logic circuit 120.

[0056] In the shutdown mode 330, the ideal diode circuit 140 can continue to couple both the first power input terminal 31 and the second power input terminal 32 to the power output terminal 40 in response to a control signal from the control logic circuit 120. The control logic circuit 120 is also configured to monitor the system power state (e.g., via feedback from the PMIC and / or the ideal diode controller) in the shutdown mode 330. When the system power state continues to be detected as OFF (333, countdown) in the shutdown mode 330, the countdown timer continues to count down to the expiration time. If the countdown timer reaches the expiration time (331, countdown timer elapsed or expired) without detecting system power ON, the control logic circuit 120 transitions from the third operating state (State 3, 330) to the first operating state (State 1, 310). However, if the system power is detected as ON (332, system power OFF DET) in the shutdown mode 330 before the countdown timer expires, the control logic circuit 120 transitions from the third operating state (State 3, 330) to the second operating state (State 2, 320).

[0057] The expiration time can be adjusted based on the desired performance. For example, the expiration time can be short (e.g., 15 seconds, 30 seconds, 1 minute, 2 minutes, 3 minutes, etc.) in the power saving mode, longer (e.g., 5 minutes, 10 minutes, 15 minutes, 30 minutes) in the medium power consumption mode, or very long (e.g., 1 hour, 2 hours, 3 hours, etc.) in the high power consumption mode. Although the above examples are described as countdown timers, any suitable timer mechanism is equally appropriate. Thus, the timer can be configured to count up or down to be triggered at the desired elapsed time.

[0058] Figure 4FIG. 400 shows another state diagram of another example battery-powered circuit or system arranged according to the embodiments described herein. The state diagram 400 includes three operating states designated as state 1, state 2, and state 3, which are managed by the control logic circuit 120. For Figure 4 the example, the first power circuit may be a linear regulator circuit, the second power circuit may be a switched-mode power supply, the ideal diode circuit includes two power MOS devices, and the system includes a PMIC.

[0059] In the first operating state (state 1, 410), the system is considered to be in the OFF mode. For this first operating state or OFF mode 410, a linear regulator circuit (such as an LDO circuit) may be enabled or ON, and the switched-mode power supply circuit may be disabled or OFF. In some examples, in the OFF mode 410, the linear regulator circuit (e.g., 231) is always enabled, while in other examples, the linear regulator circuit is enabled in the OFF mode 410 via a control signal (e.g., EN1) asserted (e.g., logic 1) by the control logic circuit 120. In other examples, in the OFF mode 410, the linear regulator circuit may be disabled via a control signal (e.g., EN1) de-asserted (e.g., logic 0). In the OFF mode 410, the switched-mode power supply circuit (e.g., 232) is disabled via a corresponding control signal (e.g., EN2) de-asserted (e.g., logic 0) by the control logic circuit 120.

[0060] In the OFF mode 410, the ideal diode circuit 140 couples the first power input terminal 31 to the power output terminal 40 through the power MOS device 241 in response to a control signal 117 from the ideal diode controller 144, where one or more control signals 117 may respond to a control signal 24 from the control logic circuit 120. The control logic circuit 120 is also configured to monitor the system power state (e.g., via a feedback signal 24 from the PMIC and / or the ideal diode controller). When the PMIC (412, PMIC PON) detects that the system power state is ON, the control logic circuit 120 transitions from the first operating state (state 1, 410) to the second operating state (state 2, 420).

[0061] In the second operating state (state 2, 420), the system is considered to be in the ON mode. For this second operating state or ON mode 420, both the linear regulator circuit and the switched-mode power supply circuit can be enabled or ON. In some examples, the linear regulator circuit (e.g., 231) is always enabled in the ON mode 420, while in other examples, the linear regulator circuit is enabled in the ON state 420 via a control signal (e.g., EN1) asserted (e.g., logic 1) by the control logic circuit 120. In still other examples, the linear regulator circuit can be disabled in the ON mode 420 via a control signal (e.g., EN1) de-asserted (e.g., logic 0). The switched-mode power supply circuit (e.g., 232) can be enabled in the ON mode 420 via a corresponding control signal (e.g., EN2) asserted (e.g., logic 1) by the control logic circuit 120.

[0062] In the ON mode 420, the ideal diode circuit 140 couples both the first power input terminal 31 and the second power input terminal 32 to the power output terminal 40 through the operation of the first power MOS device 241 and the second power MOS device 242. The first power MOS device 241 and the second power MOS device 242 respond to one or more control signals 117 from the ideal diode controller 144. In some examples, one or more control signals 117 can be generated by the ideal diode controller 144 in response to one or more control signals 24 from the control logic circuit 120. The control logic circuit 120 is also configured to monitor the system power state (e.g., via feedback from the PMIC 152 and / or the ideal diode controller 144). When the system power state is detected as OFF (423, PMIC VDDIO drops), the control logic circuit 120 transitions from the second operating state (state 2, 420) to the third operating state (state 3, 430), and the countdown timer is initiated (e.g., the timer is reset and the countdown starts).

[0063] In the third operating state (state 3, 430), the system is considered to be in the shutdown mode. For this third operating state or shutdown mode, the linear regulator circuit 231 and the switched-mode power supply circuit 232 can maintain their current operation (e.g., enabled or ON) from the ON mode 420. In some examples, the linear regulator circuit 232 remains enabled (e.g., if enabled in the ON mode), while in other examples, the linear regulator circuit 232 remains disabled (e.g., if disabled in the ON mode). The switched-mode power supply circuit 232 remains enabled in the shutdown mode 430 via a corresponding control signal (EN2,..., EN N ) maintained asserted (e.g., logic 1) by the control logic circuit 120.

[0064] In the shutdown mode 430, the ideal diode circuit 140 can continue to couple both the first power input terminal 31 and the second power input terminal 32 to the power output terminal 40 in response to a control signal from the control logic circuit 120. The control logic circuit 120 is also configured to monitor the system power state via feedback from the PMIC 152 and / or the ideal diode controller 144. When the system power state continues to be detected as OFF (433, countdown) in the shutdown mode 430, the countdown timer continues to count down to the expiration time. If the countdown timer reaches the expiration time (431, timer elapsed or expired) without detecting system power ON, the control logic circuit 120 transitions from the third operating state (state 3, 430) to the first operating state (state 1, 410). However, if the system power is detected as ON in the shutdown mode 430 by the PMIC (432, PMIC PON or PMIC VDDIO rising) before the countdown timer expires, the control logic circuit 120 transitions from the third operating state (state 3, 430) to the second operating state (state 2, 420).

[0065] As described above, the expiration time can be adjusted based on the desired performance. For example, the expiration time can be short (e.g., 15 seconds, 30 seconds, 1 minute, 2 minutes, 3 minutes, etc.) in the power saving mode, longer (e.g., 5 minutes, 10 minutes, 15 minutes, 30 minutes) in the medium power consumption mode, or very long (e.g., 1 hour, 2 hours, 3 hours, etc.) in the high power consumption mode. Although the above examples are described as countdown timers, any suitable timer mechanism is equally appropriate. Thus, the timer can be configured to count up or down to be triggered at the desired elapsed time.

[0066] Figure 5 Another state diagram 500 of another example battery-powered circuit or system arranged in accordance with the embodiments described herein is shown. Figure 5 The example state diagram 500 of is substantially similar to Figure 3 the state diagram 300 of, with similar component labels being the same. The state diagram 500 also includes a fourth operating state designated as state 4.

[0067] In the fourth operating state (540, state 4), the system is considered to be in the storage mode. For this fourth operating state or storage mode 540, the system power is OFF, and all power circuits are disabled or OFF. In storage mode 540, the first power circuit (e.g., 131) can be disabled via a control signal (e.g., EN1) that is de-asserted (e.g., logic 0) by the control logic circuit 120. In storage mode 540, other power circuits (e.g., 132, 133, etc.) can be disabled via corresponding control signals (e.g., EN2, ……, EN N ) that are de-asserted (e.g., logic 0) by the control logic circuit 120. The control logic circuit 120 can also be configured to monitor the system state (e.g., via feedback signal 24 from the PMIC and / or ideal diode controller, or by directly monitoring other circuits such as power switches).

[0068] In storage mode 540, since the power circuits are disabled and no (or minimal) power is delivered to the system 150, power is saved. Storage mode 540 can be deactivated by various mechanisms, such as any mechanical, electrical, electromechanical, or software-based mechanism. In one example, storage mode 540 is activated via software- or hardware-based initialization as part of late production factory initialization (504, activate storage). In another example, storage mode 540 is activated via software- or hardware-based initialization that can be initiated from any other operating state of the control logic circuit 120 (e.g., 534, activate storage). In some examples, the system 150 can be a portable device, such as a laptop computer, that is intentionally placed in long-term storage mode by a system administrator when the portable device is expected to be in an inactive or unused state for a long time.

[0069] In storage mode 540, when the storage mode is deactivated (541, deactivate storage), the control logic circuit 120 can transition from the fourth operating state (540, storage) to the first operating state (310, state 1) or OFF mode. For example, when the power button is first pressed after the portable device leaves the factory or otherwise exits long-term storage and the system power is initialized, the system 150 can be activated. In other examples, software mechanisms can be employed to deactivate the storage mode.

[0070] Figure 6 FIG. 600 shows another state diagram of another example battery-powered circuit or system arranged in accordance with the embodiments described herein. Figure 6 The example state diagram 600 is substantially similar to Figure 4 the state diagram 400, and like components are labeled the same. The state diagram 600 also includes a fourth operating state designated as state 4.

[0071] In the fourth operating state (640, State 4), the system is considered to be in a storage mode. For this fourth operating state or storage mode 640, the system power is OFF, and all regulator circuits are disabled or OFF. In storage mode 640, the linear regulator circuit (e.g., 231) can be disabled via a control signal (e.g., EN1) that is de-asserted (e.g., logic 0) by the control logic circuit 120. In storage mode 540, the switched-mode power supply circuit (e.g., 232) can be disabled via a corresponding control signal (e.g., EN2) that is de-asserted (e.g., logic 0) by the control logic circuit 120. The control logic circuit 120 can also be configured to monitor the system state (e.g., via a feedback signal 24 from the PMIC and / or ideal diode controller, or by directly monitoring other circuits such as power switches).

[0072] In storage mode 640, power is conserved since the power circuits are disabled and no (or minimal) power is delivered to the system 150. Storage mode 640 can be deactivated by a variety of mechanisms, such as any mechanical, electrical, electromechanical, or software-based mechanism. In one example, storage mode 640 is activated via a software- or hardware-based initialization as part of a late production factory initialization (604, Activate Storage). In another example, storage mode 640 is activated via a software- or hardware-based initialization that can be initiated from any other operating state of the control logic circuit 120 (e.g., 634, Activate Storage). In some examples, the system 150 can be a portable device, such as a laptop computer, that is intentionally placed in a long-term storage mode by a system administrator when the portable device is expected to be in an inactive or unused state for an extended period of time.

[0073] In storage mode 640, when the storage mode is deactivated (612, Deactivate Storage), the control logic circuit 120 can transition from the fourth operating state (640, Storage) to the first operating state (410, State 1) or the OFF mode. For example, when the power button is first pressed after the portable device leaves the factory or otherwise exits long-term storage and the system power is initialized, the system 150 can be activated. In other examples, software mechanisms can be employed to deactivate the storage mode.

[0074] Figure 7FIG. 700 is a flow chart of an example process 700 that illustrates various example battery-powered circuits or systems arranged in accordance with the embodiments described herein. Process 700 is shown as a collection of blocks in a logical flow chart that represents a sequence of operations that can be implemented in hardware, software, or a combination thereof. In a software context, the blocks represent computer-executable instructions that, when executed by one or more processors, perform the recited operations. Generally, computer-executable instructions include routines, programs, objects, components, data structures, etc. that perform or implement particular functions. The order of the operations described should not be construed as a limitation, and any number of the described blocks can be implemented in any order and / or in parallel combination to implement the process. Other processes described in this disclosure should be construed accordingly.

[0075] The described processes and methods can be implemented as part of a power control device that can include control logic circuitry, ideal diode circuitry, and a system as described previously herein, interfacing with a plurality of power circuits. The system can correspond to a portable electronic device (such as a laptop computer), a body-worn device (such as a VR headset or a head-mounted display (HMD) device), or another portable electronic device. In some examples, the power control device can be configured to operate in operating modes including, but not limited to, the first, second, third, and fourth operating modes described above. Optionally, the power control device can also be configured to exclude the fourth operating mode from some implementations.

[0076] At block 702, a battery-operated power control device activates a storage mode, in which the power control device can be configured to disable all power circuits that effectively reduce system power consumption. The method employed by the power control device at block 702 can include one or more of the following: initializing the state machine of the power control device in the storage mode (storage), and disabling the main power circuit and the auxiliary power circuit.

[0077] At block 703, the power control device monitors a signal to determine whether to deactivate the storage mode (deactivate storage mode) or remain in the storage mode. When the power control device remains in the storage mode, the method can continue from block 703 to block 702. Alternatively, when the power control device transitions from the storage mode to the first operating mode (e.g., OFF) when the storage mode is deactivated, the method can continue from block 703 to block 704. Thus, the method employed by the power control device in the storage mode can include transitioning from the storage mode to the first operating mode (e.g., OFF) when the storage mode is deactivated.

[0078] At block 704, the OFF mode is activated by the power control device, where the power control device may be configured to enable an auxiliary power circuit (e.g., a linear regulator circuit) and disable the main power circuit (e.g., a SMPS circuit). Thus, the method employed by the power control device at block 704 may include: disabling one or more main power circuits and enabling an auxiliary power circuit. At block 705, in the OFF mode, the power control device monitors the system power. Thus, the method employed by the power control device at block 705 may include monitoring the system power. At block 706, the method evaluates the signal monitored by the power control device. When the power control device remains in the OFF mode, the method may continue from block 706 to block 705. Alternatively, when the system power is detected as ON, when the power control device transitions from the OFF mode to the ON mode, the method may continue from block 706 to block 707. Thus, the method employed by the power control device at block 706 may include: transitioning from a first operating mode (OFF) to a second operating mode (ON) when the system power is detected as ON).

[0079] At block 707, the ON mode is activated by the power control device, where the power control device may be configured to enable one or more main power circuits (e.g., a switched-mode power supply circuit). Thus, the method employed by the power control device at block 707 may include: enabling one or more main power circuits and enabling an auxiliary power circuit. At block 708, in the ON mode, the power control device monitors the system power. Thus, the method employed by the power control device at block 708 may include monitoring the system power. At block 709, the method evaluates the signal monitored by the power control device. When the power control device remains in the ON mode, the method may continue from block 709 to block 708. Alternatively, when the system power is detected as OFF, when the power control device transitions from the ON mode to the shutdown mode, the method may continue from block 709 to block 710. Thus, the method employed by the power control device at block 709 may include: transitioning from a second operating mode (ON) to a third operating mode (shutdown) when the system power is detected as OFF).

[0080] At block 710, a power-off mode is activated by a power control device, where the power control device continues to enable one or more main power circuits (e.g., a switched-mode power supply circuit) and starts or begins a countdown timer. Thus, the method employed by the power control device at block 710 may include: resetting or starting the countdown timer. At block 711, in the power-off mode, the power control device monitors the system power and the power-off timer. Thus, the method employed by the power control device at block 711 may include monitoring the system power and monitoring the power-off timer (or countdown timer). At block 712, the method evaluates the signals monitored by the power control device. When the system power remains detected as OFF, the method may continue from block 712 to block 713. Alternatively, when the system power is detected as ON, the method may continue from block 714 to block 707, where the power control device transitions from the power-off mode to the ON mode when the system power is detected as ON. When the countdown timer has not fully elapsed, the method continues from block 713 to block 711 so that the countdown continues. Alternatively, when the countdown timer has fully elapsed and thus expired, the method continues from block 713 to block 704. Thus, the method employed by the power control device at block 712 may include: transitioning from a third operating mode (power-off) to a second operating mode (ON) when the system power is detected as ON before the countdown timer has elapsed. Thus, the method employed by the power control device at block 713 may include: transitioning from a third operating mode (power-off) to a first operating mode (OFF) when the system power is not detected as ON and the power-off timer has elapsed.

[0081] The disclosure presented herein also includes the subject matter set forth in the following sections:

[0082] Example Section A: A power control device for a system (150) operated by a battery (110), the device comprising: control logic circuitry (120) configured to detect the power state of the system (150) and responsive thereto provide one or more control signals to a control terminal (20); an ideal diode circuit (140) selectively coupling power from one or more of a first power input terminal (31) and a second power input terminal (32) to a power output terminal (40) in response to one or more control signals from the control terminal (20), wherein the power output terminal (40) is coupled to the system (150); a first power circuit (131) receiving power from a power terminal (10) of the battery (110) and providing a first regulated power signal to the first power input terminal (31); and a second power circuit (132) receiving power from the power terminal (10) of the battery (110) and selectively providing a second regulated power signal to the second power input terminal (32) when activated in response to a control signal from the control terminal (20), wherein the power consumed by the second power circuit is higher than the power consumption of the first power circuit.

[0083] Example Section B: The power control device according to the preceding section, wherein the control logic circuitry comprises a state machine (300) configured to operate in a first operating state (State 1, OFF) or a second operating state (State 2, ON) such that: in the first operating state (State 1, OFF), the ideal diode circuit (140) couples the first power input terminal (31) to the power output terminal (40) in response to one or more control signals; in the second operating state (State 2, ON), the ideal diode circuit (140) couples the second power input terminal (32) to the power output terminal (40) in response to one or more control signals; and when the system power is detected as ON (312) in the first operating state (State 1, OFF), the state machine transitions to the second operating state (State 2, ON).

[0084] Example Section C: The power control device according to any one of the preceding sections, wherein the state machine (300) is further configured to operate in a third operating state (State 3, shutdown) such that: when the system power is detected as OFF (323) in the second operating state (State 2, ON), the state machine transitions to the third operating state (State 3, shutdown) and a countdown timer is initiated; and when the system power remains detected as OFF (333) in the third operating state (State 3, shutdown), the countdown timer continues.

[0085] Example section D: A power control device according to any one of the foregoing sections, wherein the state machine (300) is further configured such that: when the system power is detected as ON (332) before the expiration of the countdown timer in the third operating state (state 3, shutdown), the state machine transitions to the second operating state (state 2, ON); and when the system power remains detected as OFF (333) in the third operating state (state 3, shutdown) and the countdown timer expires, the state machine transitions to the first operating state (state 1, OFF).

[0086] Example section E: A power control device according to any one of the foregoing sections, wherein the control logic circuit (120) includes a state machine (500) configured to operate in a first operating state (state 1, OFF), a second operating state (state 2, ON), or a fourth operating state (state 4, storage) such that: in the first operating state (state 1, OFF), the ideal diode circuit (140) couples the first power input terminal (31) to the power output terminal (40) in response to one or more control signals; in the second operating state (state 2, ON), the ideal diode circuit (140) couples the second power input terminal (32) to the power output terminal (40) in response to one or more control signals; in the fourth operating state (state 4, storage), the system power is OFF and all power circuits are deactivated; when the storage device is deactivated in the fourth operating state (state 4, storage), the state machine transitions to the first operating state (state 1, OFF); and when the system power is detected as ON (312) in the first operating state (state 1, OFF), the state machine transitions to the second operating state (state 2, ON).

[0087] Example section F: A power control device according to any one of the foregoing sections, wherein the state machine (500) is further configured to operate in a third operating state (state 3, shutdown) such that: when the system power is detected as OFF (323) in the second operating state (state 2, ON), the state machine transitions to the third operating state (state 3, shutdown) and the countdown timer is initiated; and when the system power remains detected as OFF (333) in the third operating state (state 3, shutdown), the countdown timer continues.

[0088] Example section G: A power control device according to any one of the preceding sections, wherein the state machine (500) is further configured such that: when the system power is detected as ON (332) before the expiration of a countdown timer in the third operating state (state 3, shutdown), the state machine transitions to the second operating state (state 2, ON); when the system power remains detected as OFF (333) in the third operating state (state 3, shutdown) and the countdown timer expires, the state machine transitions to the first operating state (state 1, OFF); and when the storage device is activated (504, 534), the state machine transitions to the fourth operating state (state 4, storage).

[0089] Example section H: A power control device according to any one of the preceding sections, wherein the battery includes a plurality of battery cells configured in series, parallel, or a combination thereof.

[0090] Example section I: A power control device according to any one of the preceding sections, wherein the first power circuit includes a linear regulator circuit corresponding to one or more of a Zener diode circuit, a low dropout regulator circuit, a series regulator circuit, a shunt regulator circuit, or a combination thereof.

[0091] Example section J: A power control device according to any one of the preceding sections, wherein the second power circuit includes a switched-mode power supply (SMPS) circuit corresponding to one or more of a DC-DC converter circuit, a boost regulator circuit, a buck regulator circuit, a buck-boost regulator circuit, or a combination thereof.

[0092] Example section K: A power control device according to any one of the preceding sections, wherein the first power circuit includes a linear regulator circuit having a lower quiescent current, and wherein the second power circuit includes a switched-mode power supply circuit having a higher quiescent current, wherein the higher quiescent current is substantially greater than the lower quiescent current.

[0093] Example section L: A power control device according to any one of the preceding sections, wherein the first power circuit includes a linear regulator circuit having a first quiescent current in a first range of from about 1 μA to about 25 μA, and wherein the second power circuit includes a switched-mode power supply circuit having a second quiescent current in a second range of from about 100 μA to about 500 μA.

[0094] Example section M: A power control device according to any one of the preceding sections, wherein the ideal diode circuit includes: a first switch circuit configured to selectively couple a first power input terminal to a power output terminal; a second switch circuit configured to selectively couple a second power input terminal to the power output terminal; and an ideal diode controller circuit configured to selectively activate one or more of the first switch circuit and the second switch circuit based on one or more control signals from a control logic circuit.

[0095] Example section N: A power device according to any of the preceding sections, wherein the first switching circuit and the second switching circuit each include a power MOS field effect transistor (MOSFET) device.

[0096] Example section O: A power device according to any of the preceding sections, wherein the system includes a power management integrated circuit (PMIC), the PMIC receives power from the power output terminal, delivers power to the load of the system, and provides a feedback signal to one or more of the control circuit and the ideal diode circuit.

[0097] Example section P: A power control device for a system (150) operated by a battery (110), the device comprising: control logic circuitry (120) configured to detect the power state of the system (150) and responsively provide one or more control signals to a control terminal (20); an ideal diode circuit (140) selectively coupling power from one or more of a first power input terminal (31) and a second power input terminal (32) to a power output terminal (40) in response to one or more control signals from the control terminal (20), wherein the power output terminal (40) is coupled to the system (150); a linear regulator circuit (231) receiving power from a power terminal (10) of the battery (110) and providing a first regulated power signal to the first power input terminal (31), wherein the linear regulator circuit (231) operates at a first quiescent current (IQ1); and a switched-mode power supply circuit (232) receiving power from the power terminal (10) of the battery (110) and selectively providing a second regulated power signal to the second power input terminal (32) when activated in response to a control signal from the control terminal (20), wherein the switched-mode power supply circuit (232) operates at a second quiescent current (IQ2), the second quiescent current being substantially higher than the first quiescent current (IQ1).

[0098] Example section Q: For the power control device according to any one of the foregoing sections, the control logic circuit (120) further includes a state machine (400), the state machine being configured to operate in a first operating state (state 1, OFF), a second operating state (state 2, ON), or a third operating state (state 3, shutdown), such that: in the first operating state (state 1, OFF), the ideal diode circuit (140) couples the first power input terminal (31) to the power output terminal (40) in response to one or more control signals; in the second operating state (state 2, ON), the ideal diode circuit (140) couples the second power input terminal (32) to the power output terminal (40) in response to one or more control signals; when the system power is detected as ON (312) in the first operating state (state 1, OFF), the state machine transitions to the second operating state (state 2, ON); when the system power is detected as OFF (323) in the second operating state (state 2, ON), the state machine transitions to the third operating state (state 3, shutdown), and a countdown timer is initiated; when the system power remains detected as OFF (333) in the third operating state (state 3, shutdown), the countdown timer continues; when the system power is detected as ON (332) before the countdown timer expires in the third operating state (state 3, shutdown), the state machine transitions to the second operating state (state 2, ON); and when the system power remains detected as OFF (333) in the third operating state (state 3, shutdown) and the countdown timer expires, the state machine transitions to the first operating state (state 1, OFF).

[0099] Example section R: For the power control device according to any of the foregoing sections, the control logic circuit (120) further includes a state machine (600), the state machine being configured to operate in a first operating state (state 1, OFF), a second operating state (state 2, ON), a third operating state (state 3, shutdown), or a fourth operating state (state 4, storage) such that: the state machine (600) is initialized to the fourth operating state (state 4, storage), where the system power is OFF and both the linear power regulator circuit (231) and the power circuit (232) are disabled; in the first operating state (state 1, OFF), the ideal diode circuit (140) couples the first power input terminal (31) to the power output terminal (40) in response to one or more control signals; in the second operating state (state 2, ON) and the third operating state (state 3, shutdown), the ideal diode circuit (140) couples the second power input terminal (32) to the power output terminal (40) in response to one or more control signals; when the storage mode is deactivated (612) in the fourth operating state (state 4, storage), the state machine transitions to the first operating state (state 1, OFF); when the system power is detected as ON (312) in the first operating state (state 1, OFF), the state machine transitions to the second operating state (state 2, ON); when the system power is detected as OFF (323) in the second operating state (state 2, ON), the state machine transitions to the third operating state (state 3, shutdown) and a countdown timer is initiated; when the system power remains detected as OFF (333) in the third operating state (state 3, shutdown), the countdown timer continues; when the system power is detected as ON (332) before the countdown timer expires in the third operating state (state 3, shutdown), the state machine transitions to the second operating state (state 2, ON); and when the system power remains detected as OFF (333) and the countdown timer expires in the third operating state (state 3, shutdown), the state machine transitions to the first operating state (state 1, OFF).

[0100] Example section S: A method for delivering power from a power control device operated by a battery (110) to a system (150), the method comprising: operating a state machine of the power control device in one of a first operating mode, a second operating mode, and a third operating mode; selectively coupling power from one or more of a main power circuit and an auxiliary power circuit to the system (150) based on the operating mode of the state machine; in the first operating mode (OFF): disabling (704) one or more main power circuits; enabling (704) the auxiliary power circuit; monitoring (705) system power; and transitioning from the first operating mode (OFF) to the second operating mode (ON) when the system power is detected as ON (706); in the second operating mode (ON): enabling (707) one or more main power circuits; monitoring (708) system power; and transitioning from the second operating mode (ON) to the third operating mode (shutdown) when the system power is detected as OFF (709); in the third operating mode (shutdown): starting (710) a countdown timer; monitoring (711) system power and the countdown timer; transitioning from the third operating mode (shutdown) to the second operating mode (ON) when the system power is detected as ON (712) before the countdown timer expires (713); and transitioning from the third operating mode (shutdown) to the first operating mode (OFF) when the system power is not detected as ON (712) and the shutdown timer expires (713).

[0101] Example section T: The method according to any of the preceding sections, further comprising initializing the state machine of the power control device in a fourth operating mode (storage); in the fourth operating mode (storage): disabling (702) the main power circuit and the auxiliary power circuit; and transitioning (703) from the fourth operating mode (storage) to the first operating mode (OFF) when the fourth operating mode (storage) is deactivated.

[0102] It should be understood that the configurations and / or methods described herein are examples, and these specific embodiments or examples should not be considered restrictive, as many variations are possible. Thus, in a particular implementation, various systems, circuits, and / or devices may be decomposed into additional functions or circuits, and / or combined with other functions or circuits. Similarly, the specific routines, processes, or methods described herein may represent one or more of any number of processing strategies. Thus, the various acts shown and / or described may be performed in the order shown and / or described, in other orders, in parallel, or omitted. Likewise, the order of the above processes or methods may be changed. Accordingly, the subject matter includes all novel and non-obvious combinations and sub-combinations of the methods, processes, circuits, devices, systems, and configurations, as well as other features, functions, and / or properties disclosed herein, and any and all equivalents thereof.

[0103] Finally, although various configurations have been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended representations is not necessarily limited to the specific features or acts described. On the contrary, the specific features and acts are disclosed as example forms of implementing the claimed subject matter.

Claims

1. A power control device for a battery-operated system, the device comprising: Control logic circuitry configured to detect a power state of the system and responsive thereto provide one or more control signals to a control terminal; An ideal diode circuit selectively coupling power from one or more of a first power input terminal and a second power input terminal to a power output terminal in response to one or more control signals from the control terminal, wherein the power output terminal is coupled to the system; A first power circuit receiving power from a power terminal of the battery and providing a first regulated power signal to the first power input terminal; And A second power circuit receiving power from the power terminal of the battery and selectively providing a second regulated power signal to the second power input terminal when activated in response to the control signal from the control terminal, wherein the power consumed by the second power circuit is higher than the power consumption of the first power circuit.

2. The power control device according to claim 1, wherein the control logic circuitry includes a state machine configured to operate in a first operating state or a second operating state such that: In the first operating state, the ideal diode circuit couples the first power input terminal to the power output terminal in response to the one or more control signals; In the second operating state, the ideal diode circuit couples the second power input terminal to the power output terminal in response to the one or more control signals; And When the system power is detected as ON in the first operating state, the state machine transitions to the second operating state.

3. The power control device according to claim 2, wherein the state machine is further configured to operate in a third operating state such that: When the system power is detected as OFF in the second operating state, the state machine transitions to the third operating state and a countdown timer is initiated; and When the system power remains detected as OFF in the third operating state, the countdown timer continues.

4. The power control device according to claim 3, wherein the state machine is further configured such that: When the system power is detected as ON in the third operating state before the countdown timer expires, the state machine transitions to the second operating state; and When the system power remains detected as OFF in the third operating state and the countdown timer expires, the state machine transitions to the first operating state.

5. The power control device according to claim 1, wherein the control logic circuitry includes a state machine configured to operate in a first operating state, a second operating state, or a fourth operating state such that: In the first operating state, the ideal diode circuit couples the first power input terminal to the power output terminal in response to the one or more control signals; In the second operating state, the ideal diode circuit couples the second power input terminal to the power output terminal in response to the one or more control signals; In the fourth operating state, the system power is OFF and all power circuits are deactivated; When the storage device is deactivated in the fourth operating state, the state machine transitions to the first operating state; And When the system power is detected as ON in the first operating state, the state machine transitions to the second operating state.

6. The power control device according to claim 5, wherein the state machine is further configured to operate in a third operating state such that: When the system power is detected as OFF in the second operating state, the state machine transitions to the third operating state and a countdown timer is initiated; and When the system power remains detected as OFF in the third operating state, the countdown timer continues.

7. The power control device according to claim 6, wherein the state machine is further configured such that: When the system power is detected as ON in the third operating state before the countdown timer expires, the state machine transitions to the second operating state; When the system power remains detected as OFF in the third operating state and the countdown timer expires, the state machine transitions to the first operating state; and When the storage device is activated, the state machine transitions to the fourth operating state.

8. The power control device according to claim 1, wherein the battery includes a plurality of battery cells configured in series, parallel, or a combination thereof.

9. The power control device according to claim 1, wherein the first power circuit includes a linear regulator circuit corresponding to one or more of a Zener diode circuit, a low dropout regulator circuit, a series regulator circuit, a shunt regulator circuit, or a combination thereof.

10. The power control device according to claim 1, wherein the second power circuit includes a switch mode power supply (SMPS) circuit corresponding to one or more of a DC-DC converter circuit, a boost regulator circuit, a buck regulator circuit, a buck-boost regulator circuit, or a combination thereof.

11. The power control device according to claim 1, wherein the first power circuit includes a linear regulator circuit having a lower quiescent current, and wherein the second power circuit includes a switch mode power supply circuit having a higher quiescent current, wherein the higher quiescent current is substantially greater than the lower quiescent current.

12. The power control device according to claim 1, wherein the first power circuit includes a linear regulator circuit having a first quiescent current in a first range of from about 1 μA to about 25 μA, and wherein the second power circuit includes a switch mode power supply circuit having a second quiescent current in a second range of from about 100 μA to about 500 μA.

13. The power control device according to claim 1, wherein the ideal diode circuit comprises: A first switching circuit configured to selectively couple the first power input terminal to the power output terminal; A second switching circuit configured to selectively couple the second power input terminal to the power output terminal; And An ideal diode controller circuit configured to selectively activate one or more of the first switching circuit and the second switching circuit based on the one or more control signals from the control logic circuit.

14. The power control device according to claim 13, wherein each of the first switching circuit and the second switching circuit comprises a power MOS field effect transistor (MOSFET) device.

15. The power control device according to claim 1, wherein the system comprises a power management integrated circuit (PMIC), the power management integrated circuit (PMIC) receives power from the power output terminal, delivers power to the load of the system, and provides a feedback signal to one or more of the control circuit and the ideal diode circuit.

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