Power management chip test analysis system

Abstract

The invention relates to the technical field of chip testing, and discloses a power management chip test analysis system, which comprises a data acquisition unit, a data processing unit, a feature extraction unit, a performance analysis unit, a fault diagnosis unit and a result display unit, comprehensively acquires voltage, current and temperature data of a chip, effectively filters out interference through a unique preprocessing mode, and displays the result. The data accuracy is greatly improved; through a scientific performance index extraction method, multiple performance indexes of the chip can be accurately obtained; in a performance evaluation link, the output voltage stability, the current efficiency and the overheating risk of the chip can be intuitively judged by comparing with a preset threshold value; in the aspect of fault diagnosis, the chip faults can be efficiently judged and accurately positioned by combining matching analysis based on a database constructed by a large number of known fault chip tests; and the result display unit visually displays various analysis results, assists related personnel to quickly know the condition of the chip, and takes improvement, maintenance or replacement measures in time.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and particularly to a power management chip test and analysis system. Background Art

[0002] In the complex system of modern electronic devices, the power management chip is a core hub, and its performance directly affects the overall performance of the device. From smartphones, tablets to industrial control devices, new energy vehicles, etc., all kinds of electronic devices highly rely on power management chips to achieve efficient power conversion and distribution, ensure the stable operation of the device, reduce energy consumption and extend battery life. With the continuous expansion of the functions and the continuous improvement of the performance of electronic devices, the performance requirements for power management chips are becoming increasingly stringent. It is necessary to ensure the accurate and stable output of voltage and current under various working conditions, and also to have high conversion efficiency to reduce energy loss. At the same time, it is necessary to effectively control the chip temperature to avoid performance degradation or even failure caused by overheating. To meet these requirements, it is crucial to comprehensively and accurately test and analyze the performance of power management chips.

[0003] However, there are many shortcomings in the current power management chip test and analysis technology. In the traditional data acquisition link, it is difficult to comprehensively and accurately capture the voltage, current and temperature data of different parts of the chip, resulting in data loss or deviation, which affects the accuracy of subsequent analysis. In terms of performance index extraction, past methods are mostly limited to simple calculations and cannot deeply explore the key performance characteristics of the chip under complex operating conditions. The evaluation and analysis methods are often not comprehensive enough, and can only roughly judge the chip performance from a single dimension, and cannot comprehensively consider the correlation and influence between multiple performance indicators. Fault diagnosis is even more challenging. Due to the lack of a systematic fault feature library and accurate matching algorithms, it is difficult to quickly and accurately locate the type and location of chip faults. These problems seriously hinder the R & D process of power management chips and restrict the improvement of product performance and reliability guarantee.

[0004] Therefore, developing a system that can comprehensively and accurately test and analyze power management chips has become an urgent need to improve the quality and reliability of electronic devices. Summary of the Invention

[0005] The purpose of the present invention is to provide a power management chip test and analysis system, which solves the technical problems raised in the background art.

[0006] The purpose of the present invention can be achieved by the following technical solutions:

[0007] A power management chip test and analysis system includes:

[0008] The data acquisition unit is used to obtain various operation data from different parts of the power management chip to be tested, including voltage data, current data and temperature data of the power management chip;

[0009] The data processing unit is used to preprocess the acquired operation data to remove interference and unify the format;

[0010] The feature extraction unit is used to extract various performance indicators of the chip based on the preprocessed operation data of various types;

[0011] The performance analysis unit is used to evaluate and analyze the power management chip according to the extracted performance indicators;

[0012] The fault diagnosis unit is used to judge whether there is a fault in the power management chip and locate the fault position according to the extracted performance indicators;

[0013] The result display unit is used to display the results obtained by the feature extraction unit, the performance analysis unit and the fault diagnosis unit to relevant personnel.

[0014] As a further solution of the present invention: the preprocessing method is as follows:

[0015] StepC1: Mark the voltage data, current data and temperature data of the power management chip as V t , L t and T t , where t = 1, 2,... e, and e represents the number of acquisition time nodes within a predetermined observation period. V t , L t and T t respectively represent the voltage value, current value and temperature value of the power management chip at the t-th acquisition time node;

[0016] StepC2: Select the voltage data of the power management chip;

[0017] Then pass through;

[0018] Calculate the filtered voltage value V1t at the t-th acquisition time node;

[0019] In the formula, t - 1 is the previous acquisition time node before the t-th acquisition time node, t + 1 is the next acquisition time node after the t-th acquisition time node, and the value range of t in the formula is 2, 3,... e - 1;

[0020] StepC3: Calculate the filtered current value and temperature value at each acquisition time node in the manner of StepC2.

[0021] As a further solution of the present invention: the extraction method of performance indicators is as follows:

[0022] Step G1. Stability analysis:

[0023] Obtain the pre - processed voltage data V1 within the observation period t , calculate the average value of the voltage data, and label it as V1 p ;

[0024] Then, combine the voltage data with its average value, calculate the standard deviation of the voltage data, and label it as V1 b ;

[0025] Among them,

[0026] Step G2. Efficiency analysis:

[0027] First, at the same acquisition time node, obtain the input voltage and input current of the power management chip, and label them as V in and L in ;

[0028] Then, through P in = V in ×L in , calculate the input power P of the power management chip in ;

[0029] Then, at the same acquisition time node, obtain the output voltage and output current of each output port of the power management chip, and label them as V out，i and L out，i ;

[0030] Among them, i = 1, 2,... n, representing the number of all output ports of the power management chip;

[0031] Then, through calculate the output power P of the power management chip out ;

[0032] After that, through calculate the current efficiency PX of the power management chip;

[0033] Step G3. Performance analysis:

[0034] Obtain the pre - processed temperature data T1 within the observation period t , calculate the average value of the temperature data, and label it as T1 p ;

[0035] Among them,

[0036] Then, through: Calculate the temperature change rate TC of the power management chip;

[0037] In the formula, s represents the interval duration between two adjacent acquisition time nodes, and the interval durations between all adjacent acquisition time nodes are the same.

[0038] As a further solution of the present invention: the evaluation and analysis method is as follows:

[0039] StepK1. Compare the standard deviation V1 of the voltage data corresponding to the power management chip to be tested b with the preset voltage stability threshold Vy:

[0040] If V1 b > Vy, it means that the output voltage of the power management chip is in an unstable state;

[0041] If V1 b ≤Vy, it means that the stable state of the output voltage of the power management chip is good;

[0042] StepK2. Compare the current efficiency PX corresponding to the power management chip to be tested with the preset current efficiency threshold Xy:

[0043] When PX ≥ Xy, it is determined that the current efficiency of the power management chip is high;

[0044] When PX < Xy, it is determined that the current efficiency of the power management chip is low;

[0045] StepK3. Compare the average value T1 of the temperature data corresponding to the power management chip to be tested p and the temperature change rate TC with the corresponding preset temperature threshold Ty and temperature change threshold TCy respectively:

[0046] When any one of T1 p > Ty and TC > TCy holds, it is determined that the power management chip has an overheating risk;

[0047] When both T1 p ≤Ty and TC ≤ TCy hold, it is determined that the power management chip has no overheating risk.

[0048] As a further solution of the present invention: the fault judgment method is as follows:

[0049] StepD1. Extract the pre-established fault database, where the fault database stores known fault types, corresponding fault feature vectors, and fault occurrence location information;

[0050] Step D2. Obtain various performance indicators corresponding to the power management chip to be tested, then match and analyze them with the fault feature vectors in the fault database, and determine the diagnostic result of the power management chip to be tested.

[0051] As a further solution of the present invention: The matching and analysis method is as follows:

[0052] Step D2.1. Mark various performance indicators corresponding to the power management chip to be tested as test feature vectors Fj, where j = 1, 2,..., m, and m represents the number of performance indicators;

[0053] Step D2.2. Mark each performance indicator of the fault feature vector corresponding to the same known fault type and known fault location in the fault database as [Fmin j，k , Fmax j，k , where k = 1, 2,..., g, and g represents the serial number of the fault feature vector corresponding to the same known fault type and known fault location in the fault database;

[0054] Step D2.3. Through:

[0055]

[0056] Calculate the matching degree Rk between the test feature vector of the power management chip to be tested and each fault feature vector corresponding to the same known fault type and known fault location;

[0057] Then compare the matching degree Rk with the preset matching degree threshold Ry, and select the known fault type and known fault location corresponding to the maximum Rk with Rk > Ry from the fault database as the diagnostic result.

[0058] As a further solution of the present invention: The establishment method of the fault database is as follows:

[0059] First, select several power management chips with known fault types and known fault locations, and conduct multiple test analyses on them respectively:

[0060] The test analysis method is to first obtain various operation data on the power management chips with known fault types and known fault locations through the data acquisition unit, then preprocess the acquired operation data through the data processing unit, and then extract various performance indicators of the power management chips with known fault types and known fault locations based on the preprocessed various operation data by the feature extraction unit;

[0061] Next, extract the multiple test analysis results on the power management chip for relevant known fault types and known fault locations. At the same time, extract the multiple test analysis results corresponding to the power management chips with the same known fault type and known fault location, and then organize and analyze the extracted test analysis results.

[0062] As a further solution of the present invention: Among them, the fault database contains fields corresponding to fault types, fault locations, and fault feature vectors.

[0063] As a further solution of the present invention: The organization and analysis method is as follows:

[0064] Import the fault types of relevant power management chips into the fields corresponding to the fault types in the fault database;

[0065] Import the fault locations of relevant power management chips into the fields corresponding to the fault locations in the fault database;

[0066] From the extracted test analysis results, extract the corresponding maximum and minimum values in each performance index, and form the corresponding fault performance index range. Then, use the fault performance index ranges corresponding to each performance index as the fault feature vectors and import them into the fields corresponding to the fault feature vectors.

[0067] The beneficial effects of the present invention:

[0068] In the present invention, the data acquisition unit comprehensively collects voltage, current, and temperature data of different parts of the chip, providing rich information for chip status monitoring. The unique data preprocessing method filters the data at each time node through a specific formula, effectively removing interference and unifying the format, greatly improving the accuracy and reliability of the data, and laying a solid foundation for subsequent analysis.

[0069] In the present invention, through a series of steps such as stability analysis, efficiency analysis, and performance analysis, multiple performance indexes such as voltage average value, standard deviation, current efficiency, temperature average value, and change rate are accurately extracted from the preprocessed data. These indexes comprehensively and accurately reflect the performance characteristics of the chip, providing rich and accurate basis for chip performance evaluation.

[0070] In the present invention, by comparing the extracted performance indexes with preset thresholds, the key performances such as the stability of the chip output voltage, current efficiency, and overheating risk can be scientifically and intuitively evaluated. The clear judgment criteria enable the staff to quickly and accurately judge whether the chip performance meets the standards, helping to control the product quality.

[0071] In the present invention, by establishing a fault database and matching and analyzing the performance indicators of the chip to be tested with the fault feature vectors in the database, it is possible to efficiently determine whether the chip is faulty and accurately locate the fault type and location. The fault database is constructed based on the test analysis of a large number of known faulty chips and has high reliability. The unique matching analysis method further improves the accuracy and efficiency of fault diagnosis by calculating the matching degree and comparing it with the threshold, saving the time and labor costs for troubleshooting.

[0072] In the present invention, the result display unit visually presents the results of feature extraction, performance analysis, and fault diagnosis to relevant personnel, facilitating the timely understanding of the chip performance and fault conditions, and then taking corresponding measures, such as improving the chips with poor performance, repairing or replacing faulty chips, improving product quality and production efficiency, which has important application value in actual production. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] The present invention will be further described below with reference to the accompanying drawings.

[0074] Figure 1 It is a system block diagram of a power management chip test and analysis system of the present invention.

[0075] Figure 2 It is a schematic flow chart of the feature extraction unit in a power management chip test and analysis system of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0076] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0077] Embodiment 1

[0078] Please refer to Figure 1 and Figure 2 As shown, the present invention is a power management chip test and analysis system, including:

[0079] A data acquisition unit for obtaining various types of operating data from different parts of the power management chip to be tested;

[0080] Among them, the various types of operating data include voltage data, current data, and temperature data of the power management chip;

[0081] In this embodiment, the voltage data is the voltage values of the chip in different working states collected in real time by connecting a voltage sensor to the input and output pins of the power management chip; the current data is obtained by connecting a current sensor in series in the current transmission path of the power management chip; the temperature data is obtained by installing temperature sensors on the surface of the power management chip and in the key internal heat - generating areas, and acquiring the operating temperature of the chip.

[0082] A feature extraction unit, configured to extract various performance indicators of the chip based on the collected various operation data.

[0083] The extraction method of the performance indicators is as follows:

[0084] StepG1. Stability analysis:

[0085] Obtain the voltage data V1 collected within the observation period t , and calculate the average value of the voltage data, and mark it as V1 p ;

[0086] Then, combine the voltage data with its average value, calculate the standard deviation of the voltage data, and mark it as V1 b ;

[0087] Among them,

[0088] StepG2. Efficiency analysis:

[0089] First, at the same acquisition time node, obtain the input voltage and input current of the power management chip, and mark them as V in and L in ;

[0090] Then, through P in = V in ×L in , calculate the input power P of the power management chip in ;

[0091] Then, at the same acquisition time node, obtain the output voltage and output current of each output port of the power management chip, and mark them as V out，i and L out，i ;

[0092] Among them, i = 1, 2,... n, representing the number of all output ports of the power management chip;

[0093] Then, through calculate the output power P of the power management chip out ;

[0094] After that, through calculate the current efficiency PX of the power management chip.

[0095] Step G3. Performance Analysis:

[0096] Obtain the temperature data T1 collected during the observation period t , calculate the average value of the temperature data, and label it as T1 p ;

[0097] Among them,

[0098] Then, through: Calculate the temperature change rate TC of the power management chip;

[0099] In the formula, s represents the interval duration between two adjacent acquisition time nodes, and the interval duration between each adjacent acquisition time node is the same;

[0100] The fault diagnosis unit is used to judge whether there is a fault in the power management chip and locate the fault location according to the extracted performance indicators;

[0101] The fault judgment method is as follows:

[0102] Step D1. Extract the pre-established fault database. Among them, the fault database stores known fault types, corresponding fault feature vectors, and fault occurrence location information;

[0103] Step D2. Obtain the performance indicators corresponding to the power management chip to be tested, and then perform matching analysis with the fault feature vectors in the fault database. The matching analysis method is as follows:

[0104] Step D2.1. Mark the performance indicators corresponding to the power management chip to be tested as the test feature vector Fj, where j = 1, 2,..., m, and m represents the number of performance indicators;

[0105] In this embodiment, F1 represents the standard deviation of the voltage data corresponding to the power management chip to be tested, F2 represents the average value of the voltage data corresponding to the power management chip to be tested, F3 represents the current efficiency corresponding to the power management chip to be tested, F4 represents the average value of the temperature data corresponding to the power management chip to be tested, and F5 represents the temperature change rate corresponding to the power management chip to be tested;

[0106] Step D2.2. Mark each performance indicator of the fault feature vector corresponding to the same known fault type and known fault location in the fault database as [Fmin j，k , Fmax j，k , where k = 1, 2,..., g, and g represents the serial number of the fault feature vector corresponding to the same known fault type and known fault location in the fault database;

[0107] Step D2.3: Through:

[0108]

[0109] Calculate the matching degree Rk between the test feature vector of the power management chip to be tested and the corresponding fault feature vectors of each known fault type and known fault location;

[0110] Then compare the matching degree Rk with the preset matching degree threshold Ry, and select the known fault type and known fault location corresponding to the largest Rk with Rk > Ry from the fault database as the diagnosis result;

[0111] Embodiment 1 constructs a power management chip test and analysis system. The data acquisition unit obtains operation data such as voltage, current, and temperature from different parts of the chip, providing a basis for subsequent analysis. The feature extraction unit calculates various performance indicators of the chip based on the acquired data, such as voltage stability, current efficiency, and temperature change rate, etc., comprehensively reflecting the chip performance. The fault diagnosis unit utilizes the pre-established fault database, and by matching and analyzing the performance indicators with the fault feature vectors, can accurately determine whether the chip has a fault and locate the fault location, providing an effective means for the quality inspection and problem troubleshooting of the chip, and helping to improve the accuracy and efficiency of chip testing.

[0112] Embodiment 2

[0113] Please refer to Figure 1 and Figure 2 As shown, as Embodiment 2 of the present invention, when the present application is specifically implemented, compared with Embodiment 1, the technical solution of this embodiment is only different from that of Embodiment 1 in that this embodiment further includes:

[0114] A performance analysis unit, used to evaluate and analyze the power management chip according to the extracted performance indicators, and the evaluation and analysis method is as follows:

[0115] Step K1: Compare the standard deviation V1 of the voltage data corresponding to the power management chip to be tested b with the preset voltage stability threshold Vy:

[0116] If V1 b > Vy, it means that the output voltage of the power management chip is in an unstable state;

[0117] If V1 b ≤ Vy, it means that the stable state of the output voltage of the power management chip is good;

[0118] Step K2: Compare the current efficiency PX corresponding to the power management chip to be tested with the preset current efficiency threshold Xy:

[0119] When PX ≥ Xy, it is determined that the current efficiency of the power management chip is high;

[0120] When PX < Xy, it is determined that the current efficiency of the power management chip is low;

[0121] StepK3. Compare the average value T1 of the temperature data corresponding to the power management chip to be tested p and the temperature change rate TC with the corresponding preset temperature threshold Ty and temperature change threshold TCy respectively:

[0122] When either of T1 p > Ty and TC > TCy holds, it is determined that the power management chip has an overheating risk;

[0123] When both of T1 p ≤ Ty and TC ≤ TCy hold, it is determined that the power management chip has no overheating risk;

[0124] Based on Embodiment 1, Embodiment 2 adds a performance analysis unit. This unit determines the output voltage stability by comparing the voltage standard deviation of the chip with the preset voltage stability threshold, evaluates the high and low current efficiency by comparing the current efficiency with the current efficiency threshold, and determines whether there is an overheating risk by comparing the average temperature and the temperature change rate with the corresponding thresholds respectively. This enables the system to not only detect faults but also perform multi-dimensional evaluations on the performance status of the chip, helping users better understand the chip performance and thus reasonably select and use the chip in different application scenarios, improving the reliability and adaptability of chip applications.

[0125] Embodiment 3

[0126] Please refer to Figure 1 and Figure 2 As shown, as Embodiment 3 of the present invention, in the specific implementation of this application, compared with Embodiment 1 and Embodiment 2, the technical solution of this embodiment is to combine and implement the solutions of the above-mentioned Embodiment 1 and Embodiment 2. The difference between the technical solution of this embodiment and Embodiment 1 and Embodiment 2 is only that this embodiment further includes:

[0127] A result display unit for displaying the results obtained by the feature extraction unit, the performance analysis unit, and the fault diagnosis unit to relevant personnel.

[0128] Embodiment 3 integrates the solutions of Embodiment 1 and Embodiment 2 and adds a result display unit. This unit visually displays the results obtained by the feature extraction unit, performance analysis unit, and fault diagnosis unit to relevant personnel, making the test analysis results easier to obtain and understand. Whether it is chip performance index data, performance evaluation conclusions, or fault diagnosis information, they can be presented in a timely and clear manner, greatly improving the information transmission efficiency and facilitating technicians to quickly make decisions based on these results, such as the improvement direction of the chip, adjustment of usage scenarios, etc., enhancing the practicality and convenience of the entire chip test analysis process.

[0129] Embodiment 4

[0130] Please refer to Figure 1 and Figure 2 As shown in, as Embodiment 4 of the present invention, when the present application is specifically implemented, compared with Embodiment 1, Embodiment 2, and Embodiment 3, the difference between this embodiment and Embodiment 1, Embodiment 2, and Embodiment 3 is only that this embodiment further includes:

[0131] A data processing unit for preprocessing the collected operation data to remove interference and unify the format;

[0132] The preprocessing method is as follows:

[0133] StepC1: Mark the voltage data, current data, and temperature data of the power management chip as V t , L t and T t , where t = 1, 2,..., e, e represents the number of acquisition time nodes within a predetermined observation period, and V t , L t and T t respectively represent the voltage value, current value, and temperature value of the power management chip at the t-th acquisition time node;

[0134] StepC2: Select the voltage data of the power management chip;

[0135] Then pass through;

[0136] Calculate the filtered voltage value V1t at the t-th acquisition time node;

[0137] In the formula, t - 1 is the previous acquisition time node before the t-th acquisition time node, t + 1 is the next acquisition time node after the t-th acquisition time node, and the value range of t in the formula is 2, 3,..., e - 1;

[0138] StepC3: Calculate the filtered current values and temperature values at each acquisition time node in the same way as StepC2;

[0139] Among them, the feature extraction unit extracts various performance indicators of the chip based on various types of preprocessed operation data;

[0140] In the fourth embodiment, on the basis of the previous embodiments, a data processing unit is added. This unit preprocesses the collected voltage, current, and temperature data, removes interference and unifies the format through a specific algorithm to obtain filtered data. This process effectively improves the data quality, making the performance indicators extracted by the subsequent feature extraction unit based on the preprocessed data more accurate and reliable, reducing the impact of data noise and inconsistent formats on the analysis results, thereby enhancing the stability of the entire test analysis system and the credibility of the analysis results, and providing a more solid data basis for chip performance evaluation and fault diagnosis.

[0141] Embodiment Five

[0142] Please refer to Figure 1 and Figure 2 As shown in the figure, as the fifth embodiment of the present invention, in the specific implementation of the present application, compared with the first, second, third, and fourth embodiments, the technical solution of this embodiment lies in combining the solutions of the above-mentioned first, second, third, and fourth embodiments. The difference between the technical solution of this embodiment and the first, second, third, and fourth embodiments is only that the establishment method of the fault database is also proposed in this embodiment, and the method is as follows:

[0143] First, select several power management chips with known fault types and known fault locations, and conduct multiple test analyses on them respectively:

[0144] The test analysis method is to first obtain various operation data on the power management chips with known fault types and known fault locations through the data acquisition unit, then preprocess the collected operation data through the data processing unit, and then extract various performance indicators of the power management chips with known fault types and known fault locations based on the preprocessed various operation data through the feature extraction unit;

[0145] Among them, the fault database contains fields corresponding to fault types, fault locations, and fault feature vectors.

[0146] Next, extract the multiple test analysis results on the relevant power management chips with known fault types and known fault locations, and at the same time extract the multiple test analysis results corresponding to the same power management chips with known fault types and known fault locations, and then organize and analyze the extracted test analysis results. The organization and analysis method is as follows:

[0147] Import the fault types of the relevant power management chips into the fields corresponding to the fault types in the fault database;

[0148] Import the fault location of the relevant power management chip into the field corresponding to the fault location in the fault database;

[0149] From the extracted test analysis results, extract the corresponding maximum and minimum values in each performance index, and form the corresponding fault performance index range. Then, use the fault performance index ranges corresponding to each performance index as the fault feature vectors and import them into the fields corresponding to the fault feature vectors;

[0150] Embodiment 5 proposes a method for establishing a fault database. By selecting multiple power management chips with known fault types and locations for multiple test analyses, obtaining their operating data, and after processing and feature extraction, organizing and analyzing the test results. Import the fault type, fault location, and the fault performance index range extracted from the test results, that is, the fault feature vector, into the corresponding fields of the fault database. This establishment method enables the fault database to have rich and accurate data support, can more accurately match the chip performance index, improve the accuracy of the fault diagnosis unit in judging faults and locating fault locations, and provide a strong guarantee for the reliability of the chip test analysis system.

[0151] Embodiment 6

[0152] Please refer to Figure 1 and Figure 2 As shown in, as Embodiment 6 of the present invention, in the specific implementation of this application, compared with Embodiment 1, Embodiment 2, Embodiment 3, Embodiment 4, and Embodiment 5, the technical solution of this embodiment is to combine and implement the solutions of the above Embodiment 1, Embodiment 2, Embodiment 3, Embodiment 4, and Embodiment 5.

[0153] Embodiment 6 integrates the solutions of the previous five embodiments and has the advantages of each embodiment. Through data acquisition, comprehensive operating data is obtained. The data processing unit improves the data quality. The feature extraction unit accurately calculates the performance index. The performance analysis unit evaluates the chip performance from multiple dimensions. The fault diagnosis unit accurately judges faults. The result display unit intuitively presents the results, and a perfect fault database establishment method. The entire system forms a complete, efficient, and accurate power management chip test analysis system, which comprehensively guarantees the smooth progress of the chip test analysis work from data acquisition to result application, greatly improves the efficiency, accuracy, and practicality of the chip test analysis, and meets the needs of different users for chip performance detection and fault troubleshooting.

[0154] The above formulas are all dimensionless and take their numerical values for calculation. The formulas are obtained by collecting a large amount of data for software simulation to obtain a formula closest to the actual situation. The preset parameters and threshold selection in the formulas are set by those skilled in the art according to the actual situation.

[0155] As described above, it is only the specific implementation manner of the present application. However, the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims described above.

Claims

1. A power management chip test and analysis system, characterized in that: include: A data acquisition unit, used to obtain various operating data from different parts of the power management chip to be tested, including voltage data, current data and temperature data of the power management chip; The feature extraction unit is used to obtain various operating data from different parts of the power management chip to be tested and extract various performance indicators of the chip; the method is to calculate the standard deviation of the voltage data within the observation period; at the same time, the input power and output power are calculated through the input voltage, input current, output voltage and output current of the power management chip to be tested, and then the current efficiency is calculated; the temperature change rate is calculated by calculating the average value of the temperature data within the observation period and combining the length of the adjacent acquisition time interval; The fault diagnosis unit marks the performance index of the power management chip to be tested as a test feature vector, calculates the matching degree between the test feature vector and each fault feature vector in a pre-established fault database, and then determines the fault type and fault location corresponding to the power management chip to be tested based on the matching degree and the corresponding preset matching degree threshold; wherein the fault database contains known fault types, corresponding fault feature vectors and fault location information.

2. A power management chip test and analysis system according to claim 1, characterized in that: The performance indicators are extracted as follows: Step G1, stability analysis: Get the pre-processed voltage data V1 within the observation period t , and calculate the average value of the voltage data and mark it as V1 p ; Then combine the voltage data with its mean value, calculate the standard deviation of the voltage data, and mark it as V1 b ; Step G2, efficiency analysis: First, at the same acquisition time node, the input voltage and input current of the power management chip are obtained and marked as V in and L in ; Then through P in =V in ×L in , calculate the input power P of the power management chip in ; Then, at the same acquisition time node, the output voltage and output current of each output port of the power management chip are obtained and marked as V out，i and L out，i ; Wherein, i=1, 2, ... n, represents the number of all output ports of the power management chip; Then through Calculate the output power P of the power management chip out ; Afterwards through Calculate the current efficiency PX of the power management chip; Step G3, Performance Analysis: Get the preprocessed temperature data T1 within the observation period t , and calculate the average value of the temperature data and mark it as T1 p ; Then pass: Calculate the temperature change rate TC of the power management chip; Where s represents the interval between two adjacent collection time nodes, and the interval between each adjacent collection time node is the same.

3. A power management chip test and analysis system according to claim 2, characterized in that: The fault judgment method is as follows: Step D1, extracting a pre-established fault database, wherein the fault database stores known fault types, corresponding fault feature vectors, and location information of the fault occurrence; Step D2, obtaining various performance indicators corresponding to the power management chip to be tested, then matching and analyzing them with the fault feature vectors in the fault database, and determining the diagnosis result of the power management chip to be tested.

4. A power management chip test and analysis system according to claim 3, characterized in that: The matching analysis is as follows: Step D2.1, mark each performance index corresponding to the power management chip to be tested as a test feature vector Fj, where j = 1, 2, ... m, and m represents the number of performance indexes; Step D2.2, mark each performance index of the fault feature vector corresponding to the same known fault type and known fault location in the fault database as [Fmin j，k , Fmax j，k ], where k = 1, 2, ... g, g represents the sequence number of the fault feature vector corresponding to the same known fault type and known fault position in the fault database; Step D 2.3, through: Calculate the matching degree Rk between the test feature vector of the power management chip to be tested and the fault feature vectors corresponding to the same known fault type and known fault position; Then, the matching degree Rk is compared with a preset matching degree threshold Ry, and the known fault type and known fault location corresponding to Rk with the largest value and Rk>Ry are selected from the fault database as the diagnosis result.

5. A power management chip testing and analysis system according to claim 1, characterized in that: Also includes: The data processing unit is used to pre-process the collected operation data. The pre-processing method is as follows: Step C1, mark the voltage data, current data and temperature data of the power management chip as V t , L t and T t , t=1, 2, ...e, e represents the number of acquisition time nodes in the predetermined observation period, V t , L t and T t They respectively refer to the voltage value, current value and temperature value of the power management chip at the tth acquisition time node; Step C2, select the voltage data of the power management chip; Then passed; Calculate the filtered voltage value V1t at the tth acquisition time node; In the formula, t-1 is the collection time node before the t-th collection time node, t+1 is the collection time node after the t-th collection time node, and the value range of t in the formula is 2, 3, ... e-1; Step C3, according to the method of Step C2, calculate the filtered current value and temperature value at each acquisition time node; Among them, the feature extraction unit extracts various performance indicators of the power management chip from various pre-processed operating data.

6. A power management chip test and analysis system according to claim 1, characterized in that: Also includes: The performance analysis unit is used to evaluate and analyze the power management chip according to the extracted performance indicators; the evaluation and analysis method is as follows: Step K1. Compare the standard deviation of the voltage data corresponding to the power management chip to be tested with the preset voltage stability threshold, and determine whether the voltage of the power management chip is stable based on the comparison result: Step K2, compare the current efficiency corresponding to the power management chip to be tested with the preset current efficiency threshold, and determine the current efficiency of the power management chip based on the comparison result: Step K3, compare the average value and temperature change rate of the temperature data corresponding to the power management chip to be tested with the corresponding preset temperature threshold and temperature change threshold, and determine whether the power management chip has an overheating risk based on the comparison result.

7. A power management chip test and analysis system according to claim 6, characterized in that: In Step K1: If the standard deviation of the voltage data exceeds the voltage stability threshold, it means that the output voltage of the power management chip is in an unstable state; otherwise, it means that the output voltage of the power management chip is in a good stable state.

8. A power management chip test and analysis system according to claim 6, characterized in that: In StepK2: When the current efficiency is greater than or equal to the current efficiency threshold, it is determined that the current efficiency of the power management chip is high; otherwise, it is determined that the current efficiency of the power management chip is low.

9. A power management chip test and analysis system according to claim 6, characterized in that: In Step K3: When the average value of the temperature data does not exceed the temperature threshold and the temperature change rate does not exceed the temperature change threshold, it is determined that the power management chip does not have an overheating risk; otherwise, it is determined that the power management chip has an overheating risk.

10. A power management chip test and analysis system according to claim 6, characterized in that: Also includes: The result display unit is used to display the results obtained by the feature extraction unit, the performance analysis unit and the fault diagnosis unit to relevant personnel.

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