A testing method for protecting system card components

Abstract

The present invention relates to the field of nuclear power plant protection systems, and particularly to a test method for protection system cards. The test method is as follows: indicator lamp tests and logic function tests are sequentially performed on all protection system cards; the logic function test specifically includes sequentially testing each non-triggering condition and the lowest triggering condition; the type of the protection system card is confirmed; for logic cards, delay unit tests, self-holding unit tests and anti-interference tests are sequentially performed; for signal cards, response time tests are sequentially performed; for output cards, self-holding unit tests and response time tests are sequentially performed. The present invention comprehensively tests the performance of the cards and has high reliability.

Description

Technical Field

[0001] The present invention relates to the field of nuclear power plant protection systems, and in particular to a test method for protection system cards. Background Art

[0002] The protection system of a nuclear power plant consists of a large number of analog cards, and the cards are composed of a large number of CMOS devices, triodes, optocouplers, etc. Once the internal devices of the card are damaged, the resulting refusal to operate or malfunction will directly affect the safety of the power station.

[0003] For the cards to be replaced and put into use, generally, continuous power supply is provided, and the appearance of the cards is observed for any abnormal conditions. At the same time, indicator light tests and logic function tests are carried out. The test steps are as follows: 1. Power on a single functional block to verify that the indicator light indicates normal function; 2. Power on the input that triggers the logical action to verify the normal logic function.

[0004] The following problems exist in this test method:

[0005] 1. The logical combination is the main body of the test. During the logical combination test, the corresponding indicator lights will light up and go out accordingly. Observing the indicator lights while conducting the logical test greatly increases the test time, disrupts the thinking of the test personnel, and reduces the test efficiency.

[0006] 2. When verifying the logical function, only the correct triggering of the logical function is verified, but for the input that does not trigger the action, the non-triggering of the output is not verified.

[0007] 3. The test is not comprehensive. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a test method for protection system cards, which comprehensively tests the performance of the cards and has high reliability.

[0009] The present invention provides a test method for protection system cards, including the following steps:

[0010] Step 1: Conduct indicator light tests and logical function tests on all protection system cards in sequence;

[0011] The logical function test is specifically to test each non-triggering condition and the lowest triggering condition in sequence;

[0012] After both tests pass, proceed to the subsequent steps;

[0013] Step 2: Confirm the type of the protection system card;

[0014] The protection system cards include logic cards, signal cards, and output cards;

[0015] Step 3: For the logic card, perform delay unit test, self-holding unit test and anti-interference test in sequence;

[0016] Conduct response time tests on signal cards in sequence;

[0017] For output cards, perform self-holding unit test and response time test in sequence;

[0018] The self-holding unit test verifies the reliability of the self-holding unit under different state switching by a cycle of set, reset, set and reset;

[0019] The anti-interference test specifically includes:

[0020] Simulate the logic state closest to the trigger condition;

[0021] Perform forward and reverse tests respectively, record the voltage values when the output states change, and compare the flip voltage difference during the forward test, as well as the difference between the supply voltage and the flip voltage value during the reverse test;

[0022] Take a relatively small value and compare it with the design reference value to judge the anti-interference performance.

[0023] In a specific embodiment of the present invention, a relay contact performance test is also performed before the response time test.

[0024] In a specific embodiment of the present invention, the self-holding unit test is verified using a relay as an execution component, specifically including:

[0025] When the initial state of the self-holding unit is unknown, it is first placed in the set position;

[0026] Then change the input and input the reset signal to verify whether the relay can normally release the self-holding state;

[0027] Input the set signal again, reapply the set signal to trigger the self-holding function, and verify whether the relay can be correctly set again;

[0028] Finally, apply the reset signal again to ensure that the relay is finally in the reset state.

[0029] In a specific embodiment of the present invention, the anti-interference test specifically includes:

[0030] For m / n logic, the initial state is set to (m-1) / n state to simulate the sensitivity to interference when closest to the trigger condition;

[0031] The untriggered input signal gradually increases its voltage until the system output state changes to triggered, and the voltage value at this time is recorded as V1;

[0032] The triggered input signal gradually reduces the voltage until the system output state returns to the untriggered state, and the voltage value at this time is recorded as V2;

[0033] Anti-interference voltage V 抗 is min{V1, V DD - V2};

[0034] V DD is the power supply voltage of the logic unit;

[0035] The anti-interference ability is expressed as |V 抗 - V 参考 |;

[0036] V 抗 and V 参考 are closer, indicating stronger anti-interference ability; |V 抗 - V 参考 | ≤ 0.5V is considered qualified.

[0037] In a specific embodiment of the present invention, the relay contact performance test specifically includes:

[0038] Contact resistance test; Insulation resistance test; Contact capacity test; Action time and release time test; Mechanical life and electrical life test; Environmental adaptability test; Dynamic contact resistance test; Contact bounce test.

[0039] In a specific embodiment of the present invention, the response time test specifically includes:

[0040] For m / n logic, the input signal sets it to the (m - 1) / n state. When the last logic-conforming signal is transmitted in, it is recorded as the 0 moment, and the moment when the output flips is recorded as T2. If T2 is less than the reference response time for the field, the function of the card is qualified;

[0041] If T2 is greater than the reference response time, the function of the card is unqualified.

[0042] In a specific embodiment of the present invention, the field reference response time is the time difference between the flip of the logic-conforming signal and the flip of the output signal. The response times of different cards are different, and the reference response time is set to 20 ms.

[0043] In a specific embodiment of the present invention, the delay unit test specifically includes:

[0044] Record the input moment of the delay unit of the protection system card as 0, record its output moment as T, and judge the difference between the output moment and the input moment to obtain the delay time T 延时 ;

[0045] Judge whether the delay time meets the process requirements. If it meets, proceed with subsequent tests; if not, it is determined as unqualified.

[0046] In a specific embodiment of the present invention, the passing standard for the delay time is T 延时 ≤T 参考 ±10%.

[0047] In a specific embodiment of the present invention, the indicator light test specifically includes the following steps:

[0048] Apply power to all protection system cards by inputting signals at one time, and observe the indicator light status of each protection system card;

[0049] If the indicator light does not light up, the protection system card is unqualified;

[0050] If the indicator light flashes, perform a logic function test.

[0051] Compared with the prior art, the test method for the protection system card of the present invention designs a complete test sequence and test method for different card types, realizing a comprehensive evaluation of the functions and performances of the cards; through enhancing the test method, the present invention not only verifies the correct triggering of the logic function, but also comprehensively covers various performance indicators of the protection system cards, ensuring the comprehensiveness of the test, thereby timely discovering potential safety hazards of the cards; it can more accurately simulate the actual working environment, improve the reliability of the test results, and effectively avoid serious consequences such as nuclear leakage caused by insufficient testing; it can timely discover potential problems of nuclear safety cards, provide possibilities for fault prevention and early intervention, and reduce the risk of nuclear safety accidents; by improving the comprehensiveness and reliability of the test, the present invention can effectively avoid serious consequences such as nuclear leakage caused by card failures, and ensure the safe operation of nuclear facilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 Represents the flowchart of the test method for the protection system card;

[0053] Figure 2 Represents the 2 / 4 logic schematic diagram;

[0054] Figure 3 Represents the schematic diagram of the anti-interference test curve. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0055] To further understand the present invention, the implementation solutions of the present invention will be described below in conjunction with embodiments. However, it should be understood that these descriptions are only for further explaining the features and advantages of the present invention, rather than limiting the present invention.

[0056] The embodiments of the present invention disclose a test method for a protection system card, as Figure 1As shown, it includes the following steps:

[0057] Step 1: Conduct indicator light tests and logic function tests on all protection system cards in sequence;

[0058] The indicator light test specifically includes the following steps:

[0059] Apply power to all protection system cards by inputting signals at once, and observe the indicator light status of each protection system card;

[0060] If the indicator light does not light up, the protection system card is unqualified;

[0061] If the indicator light flashes, conduct a logic function test;

[0062] The logic function test adopts a non-repeating test method, and specifically includes the following steps:

[0063] Verify each non-trigger condition;

[0064] Verify the lowest trigger condition;

[0065] If both tests pass, proceed to the subsequent steps;

[0066] Step 2: Confirm the type of the protection system card;

[0067] The protection system cards include logic cards, signal cards, and output cards;

[0068] Step 3: Conduct a delay unit test, a self-holding unit test, and an anti-interference test on the logic cards in sequence;

[0069] Conduct a relay contact performance test and a response time test on the signal cards in sequence;

[0070] Conduct a self-holding unit test, a relay contact performance test, and a response time test on the output cards in sequence;

[0071] The delay unit test specifically includes:

[0072] Record the input time of the delay unit of the protection system card as 0, and record the output time as T. Judge the difference between the output time and the input time to obtain the delay time T 延时 ;

[0073] Judge whether the delay time meets the process requirements. If it meets, proceed to the subsequent test. If it does not meet, it is determined as unqualified;

[0074] The qualified standard of the delay time is T 延时 ≤T 参考 ±10%, T 参考 Specifically 1 second, 5 seconds, 10 seconds, etc.

[0075] The self-holding unit test is verified with a relay as the execution component, specifically including:

[0076] When the initial state of the self-holding unit is unknown, first place it in the set position;

[0077] The purpose is to eliminate the interference of the uncertain initial state and ensure that the test starting point is consistent. Verify whether the relay can be normally set; for example, the relay contacts close and maintain the operating state.

[0078] Subsequently, change the input, input the reset signal, and verify whether the relay can normally release the self-holding state;

[0079] Input the set signal again, re-apply the set signal, trigger the self-holding function, and verify whether the relay can be correctly set again;

[0080] Finally, apply the reset signal again to ensure that the relay is finally in the reset state.

[0081] Through the cycle of "set → reset → set → reset", the reliability of the self-holding unit under different state switches is verified;

[0082] Forced setting is used as the starting point to avoid misjudgment of test results due to unknown initial states.

[0083] Safety first:

[0084] Force reset at the end of the test, which conforms to the "Fail-Safe" principle of nuclear power plants and ensures that the system returns to a risk-free state.

[0085] Through forced state switching and closed-loop verification, the uncertainty of the initial state is efficiently eliminated, the functional boundary of the self-holding unit is comprehensively covered, and at the same time, the requirements for "final state safety" in nuclear safety are strictly observed.

[0086] The purpose of the anti-interference test is to verify that the logic trigger module can still accurately judge the input signal in the presence of noise or voltage fluctuations, avoiding mis-triggering or failure.

[0087] Specifically including:

[0088] Initial state setting: For m / n logic, set the initial state to the (m - 1) / n state to simulate the sensitivity to interference when approaching the trigger condition;

[0089] Positive test: Gradually increase the voltage of the untriggered input signal until the system output state changes to trigger, and record the voltage value at this time as V1; the voltage value V1 represents the lower limit of interference that the trigger module can withstand during the rising process of the input signal;

[0090] Reverse test: Gradually reduce the voltage of the triggered input signal until the system output state returns to the untriggered state. Record the voltage value at this time as V2. The voltage value V2 represents the upper limit of interference that the trigger module can withstand during the decline of the input signal.

[0091] Calculation of anti-interference ability: Anti-interference voltage V 抗 is min{V1, V DD -V2};

[0092] The anti-interference ability is expressed as |V 抗 -V 参考 |.

[0093] V DD is the power supply voltage of the logic unit.

[0094] The standard for judging the anti-interference ability is: The closer V 抗 is to V 参考 , the stronger the anti-interference ability;

[0095] |V 抗 -V 参考 | ≤ 0.5V is considered qualified.

[0096] By quantifying the noise tolerance of the logic module, ensure its reliable operation in an interference environment.

[0097] The response time test specifically includes: When a signal with logical compliance is transmitted, record it as the 0 moment, and record the moment when the output flips as T2. If T2 is less than the reference response time for the site, the function of the card is qualified;

[0098] If T2 is greater than the reference response time, the function of the card is unqualified.

[0099] More specifically, for m / n logic, the input signal sets it to the (m - 1) / n state. When the last signal with logical compliance is transmitted, record it as the 0 moment, and record the moment when the output flips as T2. If T2 is less than the reference response time for the site, the function of the card is qualified;

[0100] If T2 is greater than the reference response time, the function of the card is unqualified.

[0101] The reference response time for the site is the time difference between the flip of the signal with logical compliance and the flip of the output signal. The response times of different cards are different, and the reference response time is set to 20ms.

[0102] The performance of the relay contacts is an important performance indicator for the output of the card. The relay contact performance test is carried out after the logic function test. If the test fails, although the overall card can output and perform logic processing, it cannot form the linkage of multiple cards after being connected to the system. It must be completed after the logic test and before the response time test.

[0103] The relay contact performance test specifically includes:

[0104] (1) Contact resistance test;

[0105] The purpose is to verify the conductive performance when the contacts are closed, and to avoid overheating or signal attenuation caused by poor contact.

[0106] Specifically, it includes the following steps:

[0107] Apply power to the relay coil to ensure that the contacts are fully closed;

[0108] Apply a constant current across the contacts;

[0109] Measure the voltage difference across the contacts with a high-precision voltmeter;

[0110] Calculate the contact resistance value by dividing the voltage difference by the constant current.

[0111] Judgment criterion: It is required to be ≤100mΩ.

[0112] (2) Insulation resistance test;

[0113] The purpose of this test is to ensure that there is no leakage current when the contacts are open, and to prevent misoperation.

[0114] Specifically, it includes the following steps:

[0115] Disconnect the power supply of the relay coil to ensure that the contacts are in the normally open state;

[0116] Apply a 500V DC voltage across the contacts for 1 minute;

[0117] Record the insulation resistance value after stabilization.

[0118] Judgment criterion: The insulation resistance between the contacts ≥100MΩ.

[0119] (3) Contact capacity test;

[0120] The purpose of this test is to verify the switching ability of the contacts under the rated load, and to avoid ablation or adhesion.

[0121] Specifically, it includes the following steps:

[0122] Connect the rated load across the contacts, such as 250V AC / 10A;

[0123] Repeatedly make and break contacts at a frequency of 1 Hz for at least 1000 times;

[0124] Record the voltage drop and current waveform when the contacts are closed;

[0125] Monitor the contact temperature rise.

[0126] After testing, observe whether the contact surface is burned, adhered or oxidized.

[0127] Judgment criteria: There is no physical damage to the contacts, the contact resistance change is ≤10%, and the temperature rise does not exceed the allowable value.

[0128] An extended test can also be added, which is to apply 120% of the rated load for a short time to verify the transient withstand capability.

[0129] (4) Action time and release time test;

[0130] The purpose of this test is to ensure that the relay responds quickly to commands and avoid system delays.

[0131] The specific steps include:

[0132] Send a step pulse signal to the coil and start the oscilloscope timing at the same time;

[0133] Record the time from coil energization to contact closure;

[0134] Record the time from coil de-energization to contact opening.

[0135] Judgment criteria: action time ≤ 10ms, release time ≤ 5ms.

[0136] (5) Mechanical life and electrical life test;

[0137] The purpose of this test is to evaluate the durability of contacts in long-term use.

[0138] The specific steps include:

[0139] Mechanical life test: Cycle the contacts on and off at a rated frequency (e.g. 10 Hz) until they fail;

[0140] Record the number of operations, the number of operations ≥ 10 7 Second-rate.

[0141] Electrical life test: Cycle the contacts on and off under rated load until failure. Record the number of operations, ≥ 10 5 Second-rate.

[0142] The qualification criteria are that after the end of the service life, the contact resistance change is ≤20%, and there is no adhesion or breakage.

[0143] (6) Environmental adaptability test;

[0144] The purpose of this test is to verify the reliability of the contacts under extreme environments.

[0145] The tests include:

[0146] Temperature cycle test:

[0147] Place the relay in an environment of -40°C to 85°C and cycle 100 times.

[0148] Measure the contact resistance and insulation resistance after the test.

[0149] Damp heat test:

[0150] Place it at a temperature of 40°C and a humidity of 95% RH for 96 hours.

[0151] Check the oxidation or corrosion of the contacts.

[0152] Salt spray test:

[0153] Expose it to 5% NaCl salt spray for 48 hours.

[0154] The change in contact resistance after the test should be ≤15%.

[0155] (7) Dynamic contact resistance test (DCR);

[0156] The purpose of this test is to monitor the stability of the contacts under small currents and detect microscopic defects.

[0157] Specifically, it includes the following steps:

[0158] Pass a tiny current (such as 10 mA) between the contacts and continuously monitor the contact resistance;

[0159] Analyze the resistance fluctuations and identify instantaneous open circuits or sudden increases in resistance;

[0160] The criterion for passing the judgment is: the resistance fluctuation range ≤±5%.

[0161] (8) Contact bounce test;

[0162] The purpose of this test is to detect the instantaneous disconnection caused by mechanical vibration when the contacts close.

[0163] Specifically, it includes the following steps:

[0164] Energize the trigger coil and capture the voltage waveform at the moment when the contacts close;

[0165] Analyze the number of jitters and the duration in the waveform.

[0166] The criterion for passing the judgment is: the bounce time ≤1 ms and the number of bounces ≤3 times.

[0167] The present invention fully considers various functions of the card and designs a reasonable test sequence, thereby reducing the test time as much as possible and simplifying the operation of personnel on the basis of comprehensive and reliable testing.

[0168] The logic function test is the main component. If the logic function test fails to pass and complete, subsequent anti-interference testing becomes meaningless, and the delay unit, self-holding circuit, relay contact performance, and response time cannot be performed. As part of the logic components, the delay unit and self-holding circuit are important supplements to the logic function. If they fail to pass successfully, the anti-interference level test becomes meaningless. Relay contact performance, as a key performance indicator of the card output, is performed after the logic combination test is completed. If this test fails, although the entire card can output and perform logic processing, it cannot form a multi-card linkage after being connected to the system. Therefore, it must be completed after the logic test is completed and before the response time test. Response time, as another performance indicator of the card, is an important supplement to the performance indicators. The importance of the protection system requires that the card response time is within a certain range. If the performance exceeds this range, it will not respond in a timely manner when the unit needs to shut down or perform a special action, which is of great significance.

[0169] In order to further understand the present invention, the testing method of the protection system card provided by the present invention is described in detail below in conjunction with the embodiments. The protection scope of the present invention is not limited by the following embodiments.

[0170] Example 1

[0171] Step 1: Perform indicator light test and logic function test on all protection system cards in sequence;

[0172] Input signals and power all protection system cards at once, and observe the indicator light status of each protection system card;

[0173] If the indicator light is off, the protection system card is unqualified;

[0174] If the indicator light flashes, perform a logic function test;

[0175] The specific logic function test is as follows: Take the logic of taking two out of four as an example, as shown in the attached Figure 2 As shown, combine all the possibilities of 0 / 4, 1 / 4, and 2 / 4 and check the output. Figure 2Taking the case where the valid value shown is high level and recorded as 1, when all four inputs of A, B, C, and D are low level, check whether the output Y is low level; when any one of A, B, C, and D is high level, check whether the output Y is low level; when any two of A, B, C, and D are high level, check whether the output Y is high level. Among them, if the Y detection for 0 / 4 is high level, the Y detection for 1 / 4 is low level, and the Y detection for 2 / 4 is low level, it indicates that the logic combination function test of the card is qualified, while for the logic combinations of 3 / 4 and 4 / 4, no tests are performed, achieving a comprehensive and streamlined logic test.

[0176] Step 2: Confirm the type of the protection system card;

[0177] The protection system card includes a logic card, a signal card, and an output card;

[0178] Step 3: Conduct the delay unit test, self-holding unit test, and anti-interference test on the logic card in sequence;

[0179] The specific delay unit test includes:

[0180] Record the input moment of the delay unit of the protection system card as 0, record the output moment as T, judge the difference between the output moment and the input moment, and obtain the delay time;

[0181] Judge whether the delay time meets the process requirements. If it meets, conduct subsequent tests; if not, it is determined as unqualified;

[0182] During the specific self-holding unit test: first set the S terminal to be valid and the R terminal to be invalid, test the state of the contact K, and confirm that the current state is the set state. Set the S terminal to be invalid and the R terminal to be valid, test the state of the contact K, and confirm successful reset; set the S terminal to be valid and the R terminal to be invalid, test the state of the contact K, and confirm successful setting. Finally, set the S terminal to be invalid and the R terminal to be valid, test the state of the contact K, and confirm successful reset.

[0183] The anti-interference test includes: taking the logic two-out-of-four as an example, as shown in the attachment Figure 2 Set A to high level, and B, C, and D to low level. At this time, the logic degrades to 1 / 3. Gradually increase the voltage at point B starting from 0V, measure the state of Y. When the state at Y just flips, record the voltage applied at B as V1; set A and B to high level, gradually decrease the voltage at point B starting from V DD Start, measure the state of Y. When the state of Y flips, record the voltage of B as V2. The anti-interference voltage V_anti takes the average of V1 and V DD-The smaller value in V2. The value of the anti-interference voltage to a certain extent represents the anti-misoperation and anti-blocking capabilities of the card module. The closer its value is to the reference voltage, the better the performance. For different card module power supply voltages, the reference voltage values are different. For a 12V logic component, the anti-interference voltage is about 5.8V. In the anti-interference voltage test of the card module, if |V 抗 -V 参考 | ≤ 0.5V, it is considered qualified.

[0184] The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art of this technology, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0185] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A test method for protecting system cards, characterized in that, It includes the following steps: Step 1: Conduct indicator light tests and logic function tests on all protection system cards in sequence; The specific logic function test is to test each non-trigger condition and the lowest trigger condition in sequence; After both tests pass, proceed to the subsequent steps; Step 2: Confirm the type of the protection system card; The protection system card includes a logic card, a signal card, and an output card; Step 3: Conduct a delay unit test, a self-holding unit test, and an anti-interference test on the logic card in sequence; Conduct a response time test on the signal card in sequence; Conduct a self-holding unit test and a response time test on the output card in sequence; The self-holding unit test verifies the reliability of the self-holding unit under different state switches through a cycle of setting, resetting, setting, and resetting; The specific anti-interference test includes: Simulate the logic state closest to the trigger condition; Conduct forward and reverse tests respectively, record the voltage values when the output state changes, compare the flip voltage difference during the forward test, and the difference between the supply voltage and the flip voltage value during the reverse test; Take the relatively smaller value and compare it with the design reference value to judge the anti-interference performance.

2. The test method for protecting the system card according to claim 1, characterized in that Before the response time test, a relay contact performance test is also conducted.

3. The test method for protecting system card components according to claim 1, wherein The self-holding unit test is verified with a relay as the execution component, and specifically includes: When the initial state of the self-holding unit is unknown, first place it in the set position; Subsequently, change the input and input a reset signal to verify whether the relay can normally release the self-holding state; Input the set signal again, re-apply the set signal to trigger the self-holding function, and verify whether the relay can be correctly set again; Finally, apply the reset signal again to ensure that the relay is finally in the reset state.

4. The test method for protecting the system card according to claim 1, characterized in that The specific anti-interference test includes: For m / n logic, set the initial state to the (m - 1) / n state to simulate the sensitivity to interference when closest to the trigger condition; Gradually increase the voltage of the non-triggered input signal until the system output state changes to triggered, and record the voltage value at this time as V1; Gradually decrease the voltage of the triggered input signal until the system output state returns to non-triggered, and record the voltage value at this time as V2; Anti-interference voltage V 抗 is min{V1, V DD - V2}; V DD Power supply voltage for the logic unit; The anti-interference ability is expressed as |V 抗 -V 参考 |; V 抗 is closer to V 参考 , the stronger the anti-interference ability is indicated; |V 抗 -V 参考 | ≤ 0.5V is considered qualified.

5. The test method for protecting system cards according to claim 2, characterized in that, The specific relay contact performance test includes: Contact resistance test; insulation resistance test; contact capacity test; operation time and release time test; mechanical life and electrical life test; environmental adaptability test; dynamic contact resistance test; contact bounce test.

6. The test method for protecting system card components according to claim 1, characterized in that, The specific response time test includes: For m / n logic, input a signal to place it in the (m - 1) / n state. When the last logic-conforming signal is transmitted in, record it as the 0 moment, and record the moment when the output flips as T2. If T2 is less than the reference response time for the site, the function of the card is qualified; If T2 is greater than the reference response time, the function of the card is unqualified.

7. The test method for protecting the system card according to claim 6, characterized in that, The site reference response time is the time difference between the flip of the logic-conforming signal and the flip of the output signal. The response times of different cards are different, and the reference response time is set to 20 ms.

8. The test method for the protection system card as claimed in claim 1, characterized in that, The specific delay unit test includes: Record the input time of the delay unit of the protection system card as 0, record its output time as T, judge the difference between the output time and the input time, and obtain the delay time T 延时 ; Judge whether the delay time meets the process requirements. If it meets, conduct subsequent tests; if not, it is judged as unqualified.

9. The test method for protecting system card components according to claim 8, characterized in that The passing standard for the delay time is T 延时 ≤T 参考 ±10%.

10. The test method for the protection system card according to claim 1, characterized in that, The specific steps for the indicator light test are as follows: Apply power to all protection system cards by inputting signals at one time, and observe the indicator light status of each protection system card; If the indicator light does not light up, the protection system card is unqualified; If the indicator light flashes, conduct a logic function test.

Images