Verification method of low-power-consumption narrowband communication chip based on UVM

Abstract

The invention relates to the technical field of chip verification, in particular to a verification method of a low-power-consumption narrowband communication chip based on a UVM (Universal Verification Model), which comprises the following steps: firstly, constructing a verification platform based on a UVM framework; based on the verification platform and the test function points, the environment configuration module configures the reference model and the input component; then, the to-be-tested system starts to run, and corresponding data or interrupt response is generated; at the moment, a monitor in the verification platform is inserted into a monitoring node, and the running state and data output of the to-be-tested system are captured in real time; and then, comparing the captured data with a calculation result of the reference model, recording the result, reading an interrupt register or other indication registers of the system to be tested at the same time, and comparing the result with an expected result to judge the correctness. In this way, the technical problems that in the prior art, a chip verification method is insufficient in function coverage rate, lacks system-level random verification and is low in verification efficiency are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, and particularly to a verification method for a low-power narrowband communication chip based on UVM. Background Art

[0002] With the continuous development of communication technologies, low-power narrowband communication chips have been widely used in fields such as the Internet of Things and intelligent devices. In the design process of low-power narrowband communication chips, the verification link is an important means to ensure the correctness and reliability of chip functions. However, the design of low-power narrowband communication chips needs to meet the low-power requirements while ensuring the efficiency and stability of the communication link. To achieve this goal, verification plays a crucial role in the chip design process.

[0003] Currently, the design of low-power narrowband communication chips lacks a complete system-level randomness verification. In some designs, only the data path of a single link algorithm is verified, and in some designs, only the function point control algorithm of the system is verified. These cannot support good functional coverage in the design of communication chips and whether the system can operate normally under special conditions.

[0004] In summary, the existing chip verification methods have problems such as insufficient functional coverage, lack of system-level randomness verification, and low verification efficiency. Summary of the Invention

[0005] The purpose of the present invention is to provide a verification method for a low-power narrowband communication chip based on UVM, aiming to solve the technical problems of insufficient functional coverage, lack of system-level randomness verification, and low verification efficiency in the existing chip verification methods.

[0006] To achieve the above purpose, a verification method for a low-power narrowband communication chip based on UVM adopted by the present invention includes the following steps:

[0007] Build a verification platform based on the UVM framework;

[0008] Based on the verification platform and test function points, configure the reference model and input components respectively by the environment configuration module;

[0009] Subsequently, the system under test starts to run, generating corresponding data or interrupt responses;

[0010] During the operation of the system under test, monitoring nodes are inserted by the monitor in the verification platform to capture the running state and data output of the system under test in real time;

[0011] After that, compare the captured data with the calculation results of the reference model and record the results. At the same time, read the interrupt register or other indication registers of the system under test and compare with the expected results to judge the correctness.

[0012] Among them, the constructed verification platform includes a reference model, an input component, an output component, a scoreboard, and an environment configuration module;

[0013] The reference model is a system control algorithm model and a communication algorithm model. On the one hand, it is used to verify whether the baseband circuit in the system under test performs correct digital signal processing according to the algorithm model. On the other hand, it controls the system under test to run corresponding functions and monitors whether the system can run to the corresponding state or generate corresponding interrupt feedback;

[0014] The input component is used to generate corresponding data when testing a certain function of the system under test and finally input it into the system under test through the SPI interface;

[0015] The scoreboard is used to compare whether the output of the reference model matches the output of the system under test;

[0016] The environment configuration module is all the configuration files of the system under test and is associated with the function and performance indicators of the system.

[0017] Among them, when the environment configuration module configures the reference model and the input component respectively:

[0018] After the configuration of the reference model is completed, it can independently run the algorithm C code and record the calculation results. At the same time, the configuration of the environment configuration module is mapped into control instructions for the system under test.

[0019] Among them, the configuration of the internal registers of the system under test is completed through the SPI interface communication protocol.

[0020] Among them, when comparing the captured data with the calculation results of the reference model and recording the results:

[0021] The comparison is made on the scoreboard and the comparison results are recorded.

[0022] A verification system for a low-power narrowband communication chip based on UVM includes units for executing the verification method of the low-power narrowband communication chip based on UVM as described above.

[0023] A verification method for a low-power narrowband communication chip based on UVM of the present invention. First, based on the UVM framework, a verification platform is constructed. Based on the verification platform and test function points, the environment configuration module configures the reference model and input components respectively. Subsequently, the system under test starts to run, generating corresponding data or interrupt responses. At this time, monitors in the verification platform insert monitoring nodes to capture the running state and data output of the system under test in real time. After that, the captured data is compared with the calculation results of the reference model and the results are recorded. At the same time, the interrupt register or other indication registers of the system under test are read and compared with the expected results to judge the correctness. In this way, the technical problems of insufficient functional coverage, lack of system-level randomness verification, and low verification efficiency in the existing chip verification methods are solved.

[0024] Through the UVM-based verification of the present invention, the system is comprehensively and randomly verified from two aspects of the algorithm implementation path and the control path, so as to achieve a greater coverage rate, ensure that the system can still correctly execute the corresponding functions and the correctness of the communication link interconnection under boundary conditions. In addition, it can also save the verification time of designers, and ensure the design quality while efficiently achieving the system design purpose.

[0025] For a system containing complex algorithms and control logic, using the verification method described in the invention can cover the verification boundaries required by the design, help design engineers quickly locate the problem points where the algorithm goes wrong, and support the application reliability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0027] Figure 1 is a principle block diagram of the verification method for a low-power narrowband communication chip based on UVM of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] The following will describe in detail the embodiments of the present invention. The examples of the embodiments are shown in the drawings. The embodiments described below with reference to the drawings are exemplary and are intended to explain the present invention and should not be construed as a limitation of the present invention.

[0029] Please refer to Figure 1 , Figure 1 is a principle block diagram of the verification method for a low-power narrowband communication chip based on UVM of the present invention.

[0030] The present invention provides a verification method for a low-power narrowband communication chip based on UVM, comprising the following steps:

[0031] S1. Based on the UVM framework, construct a verification platform;

[0032] For this specific embodiment, the constructed verification platform includes a reference model, an input component, an output component, a scoreboard, and an environment configuration module;

[0033] The reference model is a system control algorithm model and a communication algorithm model. On the one hand, it is used to verify whether the baseband circuit in the system under test performs correct digital signal processing according to the algorithm model. On the other hand, it controls the system under test to run corresponding functions and monitors whether the system can run to the corresponding state or generate corresponding interrupt feedback;

[0034] The input component is used to generate corresponding data when testing a certain function of the system under test and finally input it into the system under test through the SPI interface; it can be understood as an analog of the process of an external MCU controlling the chip. And it includes a sequence generator, a driver, a monitor, etc. For the output component, it is used to monitor the output interface of the system under test and also includes monitoring of data link nodes, control of system state switching, and automation processes.

[0035] The scoreboard is used to compare whether the output of the reference model matches the output of the system under test; this is also an important basis for judging whether the system under test works properly according to the setting.

[0036] The environment configuration module is all the configuration files of the system under test, which are associated with the functions and performance indicators of the system. It not only acts on the system under test but also on the reference model to monitor whether the outputs of the system under test and the reference model can be aligned under the same configuration.

[0037] S2. Based on the verification platform and test function points, the environment configuration module configures the reference model and the input component respectively;

[0038] For this specific embodiment, when the environment configuration module configures the reference model and the input component respectively:

[0039] After the configuration of the reference model is completed, it can independently run the algorithm C code and record the calculation results. At the same time, the configuration of the environment configuration module is mapped into control instructions for the system under test;

[0040] The configuration of the internal registers of the system under test is completed through the SPI interface communication protocol.

[0041] S3. Subsequently, the system under test starts to run, generating corresponding data or interrupt responses;

[0042] S4. During the operation of the system under test, the monitor in the verification platform inserts monitoring nodes to capture the running status and data output of the system under test in real time;

[0043] S5. Then, compare the captured data with the calculation results of the reference model and record the results. At the same time, read the interrupt register or other indication registers of the system under test and compare with the expected results to judge the correctness.

[0044] For this specific embodiment, when comparing the captured data with the calculation results of the reference model and recording the results:

[0045] Conduct the comparison on the scoreboard and record the comparison results.

[0046] Using the verification method of a low-power narrowband communication chip based on UVM in this embodiment, first, build a verification platform based on the UVM framework; based on the verification platform and test function points, the environment configuration module configures the reference model and input components respectively; subsequently, the system under test starts to run, generating corresponding data or interrupt responses; at this time, the monitor in the verification platform inserts monitoring nodes to capture the running status and data output of the system under test in real time; then, compare the captured data with the calculation results of the reference model and record the results. At the same time, read the interrupt register or other indication registers of the system under test and compare with the expected results to judge the correctness. In this way, the technical problems of insufficient functional coverage, lack of system-level randomness verification, and low verification efficiency in the existing chip verification methods are solved.

[0047] Through the UVM-based verification of the present invention, the system is comprehensively and randomly verified from both the algorithm implementation path and the control path, so as to achieve a greater coverage rate, ensure that the system can still correctly run the corresponding functions and the correctness of the communication link interconnection under boundary conditions. In addition, it can also save the verification time of designers, ensure the design quality while efficiently achieving the system design purpose.

[0048] For a system containing complex algorithms and control logics, using the verification method of the present invention can cover the verification boundaries required by the design, help design engineers quickly locate the problem points where the algorithms go wrong, and support the application reliability of the chip.

[0049] The above-disclosed is only a preferred embodiment of the present invention. Of course, it cannot be used to limit the scope of the rights of the present invention. Those of ordinary skill in the art can understand all or part of the processes of implementing the above embodiments, and the equivalent changes made according to the claims of the present invention still fall within the scope covered by the present invention.

Claims

1. A verification method for a low-power narrowband communication chip based on UVM, characterized in that: The steps include: Build a verification platform based on the UVM framework; Based on the verification platform and test function points, the environment configuration module configures the reference model and input components respectively; Then, the system under test starts to run and generates corresponding data or interrupt response; During the operation of the system under test, the monitor in the verification platform is inserted into the monitoring node to capture the operating status and data output of the system under test in real time; Afterwards, the captured data is compared with the calculation results of the reference model and the results are recorded. At the same time, the interrupt register or other indication register of the system under test is read and compared with the expected results to determine the correctness.

2. the verification method of the low-power narrowband communication chip based on UVM as claimed in claim 1, is characterized in that, The constructed verification platform includes reference model, input components, output components, scoreboard, and environment configuration module; The reference model is a system control algorithm model and a communication algorithm model. On the one hand, it is used to verify whether the baseband circuit in the system under test performs correct digital signal processing according to the algorithm model. On the other hand, it controls the system under test to run the corresponding functions and monitors whether the system can run to the corresponding state or generate corresponding interrupt feedback. The input component is used to generate corresponding data when the system under test tests a certain function, and finally inputs it into the system under test through the SPI interface; The scoreboard is used to compare whether the output of the reference model matches the output of the system under test; The environment configuration module is the entire configuration file of the system to be tested, which is associated with the system's functions and performance indicators.

3. the verification method of the low-power narrowband communication chip based on UVM as claimed in claim 2, is characterized in that, When the environment configuration module configures the reference model and input components respectively: After the configuration of the reference model is completed, the algorithm C code can be run independently and the calculation results can be recorded. At the same time, the configuration of the environment configuration module is mapped into control instructions for the system under test.

4. The verification method of the low-power narrowband communication chip based on UVM as claimed in claim 3, characterized in that, The configuration of the internal registers of the system under test is completed through the SPI interface communication protocol.

5. The verification method of the low-power narrowband communication chip based on UVM as claimed in claim 4, characterized in that, When comparing the captured data with the calculation results of the reference model and recording the results: Compare and record the results on the scoreboard.

6. A verification system for a low-power narrowband communication chip based on UVM, characterized in that: The invention comprises a unit for executing the verification method of the UVM-based low-power narrowband communication chip as claimed in claim 5.

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