Chip verification method and device, electronic equipment and storage medium

Abstract

The invention provides a chip verification method and device, electronic equipment and a storage medium. The chip verification method comprises the steps that a chip model of a chip is acquired, and the chip model comprises a physical layer interface and a function model; an expected offset used for simulating a time sequence offset in the access operation process between the physical layer interface and the function model is written into the chip model, so that the physical layer interface trains the time sequence of the access operation between the physical layer interface and the function model based on the expected offset; in response to the completion of the training of the chip model, obtaining an operation offset used for compensation and obtained by the physical layer interface based on the training; and determining the offset adjustment capability of the physical layer interface according to the operation offset and the expected offset. According to the chip verification method, the offset adjustment capability of the physical layer interface can be detected before silicon is applied.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a chip verification method and apparatus, an electronic device, and a storage medium. Background Art

[0002] In the field of chip design and manufacturing, the tape-out of chips (i.e., chip trial production) is extremely costly due to complex manufacturing steps and expensive equipment costs. Therefore, if there are errors in the design, it may lead to the scrapping of an entire batch of chips, causing huge economic losses.

[0003] To avoid losses caused by non-compliant or low-quality finished chips after tape-out, it is very important to conduct thorough verification and testing before tape-out. Chip verification and testing are important means to detect potential defects in chips in advance, which can avoid various problems that may occur after silicon (i.e., after the chip is actually manufactured). Therefore, it is necessary to conduct a detailed evaluation and verification of the chip's capabilities before silicon (i.e., before the chip is actually manufactured). Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a chip verification method, which includes: obtaining a chip model of a chip, where the chip model includes a physical layer interface and a function model; writing an expected offset for simulating a timing offset during an access operation between the physical layer interface and the function model into the chip model, so that the physical layer interface trains the timing of the access operation between the physical layer interface and the function model based on the expected offset; in response to the end of the training of the chip model, obtaining an operation offset for compensation obtained by the physical layer interface based on the training; and determining the offset adjustment ability of the physical layer interface according to the operation offset and the expected offset.

[0005] For example, in the chip verification method provided by at least some embodiments of the present disclosure, writing an expected offset for simulating a timing offset during an access operation between the physical layer interface and the function model into the chip model includes: writing the expected offset into a target register in the chip model for the physical layer interface to read for training.

[0006] For example, in the chip verification method provided by at least some embodiments of the present disclosure, enabling the physical layer interface to train the timing of the access operation between the physical layer interface and the function model based on the expected offset includes: in response to the start of the training of the chip model, enabling the physical layer interface to obtain the expected offset written into the chip model and use it as the current offset between the physical layer interface and the function model for training.

[0007] For example, in the chip verification method provided by at least some embodiments of the present disclosure, before starting the training of the chip model, the chip verification method further includes: configuring the training mode of the chip model so that the chip model is trained in a set working mode.

[0008] For example, in the chip verification method provided by at least some embodiments of the present disclosure, before starting the training of the chip model, the chip verification method includes: configuring the operating frequency of the chip model to determine the expected offset according to the set operating frequency.

[0009] For example, in the chip verification method provided by at least some embodiments of the present disclosure, the functional model includes multiple memory particle models; before starting the training of the chip model, the chip verification method further includes: obtaining the encoding of each memory particle model in the functional model according to the set particle encoding rule and the encoding requirement of the physical layer interface; determining the expected offset corresponding to each memory particle model in the functional model according to the encoding of each memory particle model in the functional model and the set operating frequency.

[0010] For example, in the chip verification method provided by at least some embodiments of the present disclosure, the expected offset includes an expected offset value and an expected offset direction. Determining the expected offset corresponding to each memory particle model in the functional model includes: determining the predetermined offset range corresponding to the set operating frequency according to the storage standard protocol supported by the functional model; determining the expected offset value and the expected offset direction of each memory particle model in the functional model according to the predetermined offset range.

[0011] For example, in the chip verification method provided by at least some embodiments of the present disclosure, determining the expected offset value and the expected offset direction of each memory particle model in the functional model according to the predetermined offset range includes: obtaining an offset reference value; in response to starting the training of the chip model, determining the expected offset value and the expected offset direction of each memory particle model in the functional model according to the offset reference value and the predetermined offset range.

[0012] For example, in the chip verification method provided by at least some embodiments of the present disclosure, enabling the physical layer interface to obtain the expected offset written into the chip model and using it as the current offset between the physical layer interface and the functional model for training includes: obtaining an operation offset according to the offset reference value and the absolute value of the offset value of the expected offset obtained by the physical layer interface.

[0013] For example, in the chip verification method provided by at least some embodiments of the present disclosure, writing the expected offset into the target register in the chip model includes: storing the respective corresponding expected offset value and expected offset direction of each memory particle model in the functional model into the target register corresponding to each memory particle model according to the expected offset.

[0014] For example, in the chip verification method provided by at least some embodiments of the present disclosure, the physical layer interface is made to obtain the expected offset written into the chip model and use it as the current offset between the physical layer interface and the functional model for training. It further includes: respectively obtaining, according to the physical layer interface, the expected offset value and the expected offset direction stored in the target register corresponding to each memory die model, and making the physical layer interface perform offset calculation based on the obtained expected offset value and the obtained expected offset direction to obtain the offset value of the operation offset for compensation and the offset direction of the operation offset for each memory die model.

[0015] For example, in the chip verification method provided by at least some embodiments of the present disclosure, determining the offset adjustment ability of the physical layer interface according to the operation offset and the expected offset includes: comparing the expected offset direction and the operation offset direction to determine whether the offset direction of the physical layer interface is correct; comparing the expected offset value and the operation offset value to determine the offset error value of the physical layer interface.

[0016] For example, in the chip verification method provided by at least some embodiments of the present disclosure, determining the offset adjustment ability of the physical layer interface according to the operation offset and the expected offset further includes: in response to the incorrect offset direction of the physical layer interface, determining that there is an error in the internal logic or algorithm of the physical layer interface; in response to the correct offset direction of the physical layer interface, outputting the offset error value of the physical layer interface.

[0017] For example, in the chip verification method provided by at least some embodiments of the present disclosure, in the training of the chip model, it includes: in response to the chip model being in the retraining state or the normal working mode, sending an offset update instruction to the physical layer interface and updating the operation offset for compensation obtained based on the training to the offset register of the physical layer interface.

[0018] For example, in the chip verification method provided by at least some embodiments of the present disclosure, the chip is a DDR chip and the functional model is a DRAM model.

[0019] For example, in the chip verification method provided by at least some embodiments of the present disclosure, before starting the training of the chip model, the chip verification method further includes: configuring the precision mode of the chip model to configure the training step size.

[0020] At least one embodiment of the present disclosure further provides a chip verification device. The chip verification device includes a chip model corresponding to the chip, which includes a physical layer interface and a functional model. Among them, the chip verification device includes an expected offset module and an inspection module. The expected offset module is configured to write an expected offset for simulating the timing offset during the access operation between the physical layer interface and the functional model into the chip model, so that the physical layer interface trains the timing of the access operation between the physical layer interface and the functional model based on the expected offset. The inspection module is configured to, in response to the end of the training of the chip model, obtain the operation offset for compensation obtained by the physical layer interface based on the training; and determine the offset adjustment ability of the physical layer interface according to the operation offset and the expected offset.

[0021] For example, in the chip verification device provided by at least some embodiments of the present disclosure, it further includes a configuration module. The configuration module is configured to perform one or more of the following configurations: configure the training mode of the chip model so that the chip model is trained in a set working mode; configure the working frequency of the chip model to determine the expected offset according to the set working frequency; configure the accuracy mode of the chip model to configure the training step size of the training; configure the particle coding rule of the chip model so that each memory particle model in the functional model is encoded according to the set particle coding rule.

[0022] At least some embodiments of the present disclosure further provide an electronic device. The electronic device includes at least one memory and at least one processor. The at least one memory is configured to store computer-executable instructions; and the at least one processor is configured to execute the computer-executable instructions. When the computer-executable instructions are executed by the at least one processor, the chip verification method provided by any embodiment of the present disclosure is implemented.

[0023] At least some embodiments of the present disclosure further provide a non-transitory storage medium. The non-transitory storage medium non-transitorily stores computer-executable instructions. Among them, when the computer-executable instructions are executed by at least one processor, the chip verification method provided by any embodiment of the present disclosure is implemented. Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0025] Figure 1 Shows a timing diagram of a write operation that meets the requirements of the DDR protocol;

[0026] Figure 2 Shows a timing diagram of a read operation that meets the requirements of the DDR protocol;

[0027] Figure 3 Shows a schematic diagram of the actual timing of a DDR write operation;

[0028] Figure 4 Shows a schematic diagram of the actual timing of a DDR read operation;

[0029] Figure 5 Shows a schematic flowchart of a chip verification method provided by at least one embodiment of the present disclosure;

[0030] Figure 6 Shows a flowchart of an example of a chip verification method provided by at least one embodiment of the present disclosure;

[0031] Figure 7 Shows a block diagram of a chip verification device provided by at least one embodiment of the present disclosure;

[0032] Figure 8 Shows a schematic diagram of an example of a chip verification device provided by at least one embodiment of the present disclosure;

[0033] Figure 9 Shows a block diagram of an electronic device provided by at least one embodiment of the present disclosure;

[0034] Figure 10 Shows a block diagram of an electronic device provided by at least one embodiment of the present disclosure; and

[0035] Figure 11 Shows a schematic diagram of a non - transitory storage medium provided by at least one embodiment of the present disclosure. Detailed implementation manners

[0036] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0037] Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "a", "an" or "the" do not denote a quantity limitation, but mean that there is at least one. Words such as "comprising" or "including" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0038] The following describes this disclosure through several specific embodiments. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted. When any component of an embodiment of this disclosure appears in more than one drawing, the component is denoted by the same or similar reference numerals in each drawing.

[0039] The terms used in this disclosure are those general terms that are currently widely used in the art in consideration of the functions of this disclosure, but these terms may vary according to the intentions of those of ordinary skill in the art, precedents, or new technologies in the art. In addition, specific terms may be selected by the applicant, and in such cases, their detailed meanings will be described in the detailed description of this disclosure. Therefore, the terms used in the specification should not be construed as simple names, but based on the meanings of the terms and the overall description of this disclosure.

[0040] Flowcharts are used in this disclosure to illustrate the operations performed by the systems according to the embodiments of this application. It should be understood that the operations before or below do not necessarily have to be performed precisely in order. On the contrary, various steps can be processed in reverse order or simultaneously as needed. At the same time, other operations can also be added to these processes, or one or several steps can be removed from these processes.

[0041] The DDR (Double Data Rate) memory system is, for example, one of the very important parts in a chip, mainly including a DDR controller (Double Data Rate Controller), a DDR PHY (DDR Physical Layer Interface), and a DDR memory module. Among them, the PHY (Physical Layer) in the chip refers to the circuit of the physical layer interface, and the memory module is, for example, a dynamic random access memory (DRAM Memory Module). The DDR controller is connected to the DDR PHY, and the DDR PHY is connected to the DDR memory module, forming a communication link of DDR controller <-> DDR PHY <-> DDR memory. Since the PHY in the chip is crucial for the entire chip, verifying the ability to train and adjust errors of the PHY before chip silicon is an important means to detect chip defects in advance.

[0042] The parallel signals transmitted in parallel through multiple parallel data lines in the DDR memory system are limited by signal integrity problems such as interference, reflection, crosstalk, and timing control difficulties faced with the increase in data transmission rate. Therefore, it is difficult for parallel signals to reach a high operating frequency, and the DDR PHY needs to convert them into serial signals for routing on the circuit board to improve signal integrity. The role of the DDR controller is to convert upstream read / write control requests, etc. into commands that the DDR memory can recognize, and generate the timing of address read / write control signals.

[0043] DDR technology allows data transmission on both the rising and falling edges of the clock signal, thus doubling the data transmission rate compared to technologies that only transmit data on the rising or falling edge. Since the introduction of DDR technology, it has gone through multiple iterations of versions. DDR5 is the fifth-generation product of DDR memory technology. Below, for example, DDR5 will be used for illustration and description.

[0044] The function of the DDR PHY is to handle timing during access operations (read operations and write operations), and send out the signals of the above DDR controller in a better timing. However, limited by the internal logic and algorithms of the DDR PHY, the DDR PHY will cause a certain delay when transmitting signals. In order to make the output signals of the DDR PHY meet the requirements of the DDR protocol, the DDR PHY needs to be trained. The DDR PHY adjusts the delay line (Driver Side Delay Line) at the sending end so that the DDR memory can successfully sample the control signal and data signal at the receiving end.

[0045] The above-mentioned "training" refers to a series of tests and calibration operations performed by the controller after the system is started or reset to determine the optimal operating parameters and apply these parameters to subsequent normal operations. This initialization process aims to optimize and ensure the accuracy and reliability of data transmission. By adjusting the timing parameters to compensate for various physical effects on the signal path, such as delay, reflection, crosstalk, etc., the best data read / write performance can be achieved. For example, when a large offset or other problems are detected during the operation of a DDR memory device, dynamic adjustment or retraining (re-training) is performed. For example, the DDR controller can be set to perform retraining regularly, which helps to compensate for the long-term accumulated errors caused by temperature drift, power supply noise, etc.

[0046] Figure 1 Fig. shows a timing diagram of a write operation that meets the requirements of the DDR protocol.

[0047] As Figure 1 shown, during the write operation, the command / address bus is used to transmit command and address information. For example, the command or address signal is CA[13:0]. The command signal (CMD) is used to indicate the type of command sent by the memory controller to the memory module. For example, in the write operation, the command type is "WRITE" (write command). After the write command, the CMD signal will show a series of "DES" (data enable suffix) to indicate the end of command transmission. The chip select signal (CS0_n) remains low during the write operation to indicate that a specific memory chip is selected for the write operation. The clock signals (CK_t and CK_c) are used to synchronize data transmission, where CK_t and CK_c are two phases of the clock signal. For example, the data strobe signal used to indicate the time window of data validity is called the data eye diagram (Data Eye). The data bus transmits data under the control of the data strobe signals (DQS_t and DQS_c). In the write operation, the data strobe signal is synchronized with the clock signal to ensure that the data is sampled in the correct clock cycle.

[0048] For example, in Figure 1 , after the time interval (tWPRE) required between the write operation and the precharge operation, the rising or falling edge of the data strobe signal (such as DQS_t) needs to be aligned with the center position of each data bit in the data signal DQ[15:0] on the data bus to ensure that the storage module (such as the memory module) can correctly acquire the data, and then it will enter the write stabilization time (tWPST).

[0049] The write latency in a write operation is used to determine the number of clock cycles required from the issuance of a write command until the data is written into memory. For example, the write latency (WL) is determined based on the write command latency CWL or CL (CAS Latency). For example, the write latency WL = CWL = (CL - 2).

[0050] Figure 2 Fig. shows a timing diagram of a read operation that meets the requirements of the DDR protocol.

[0051] In a read operation, the command / address bus transmits the read command and address information. For example, the command or address signal is CA[13:0]. The command signal (CMD) is used to indicate the type of command sent by the memory controller to the memory module. For example, in a read operation, the command type is "Read" (read command). After the read command, the CMD signal will show a series of "DES" (Data Enable Suffix) to indicate the end of the command transmission. The chip select signal (CS_N) remains low during the read operation to indicate that a specific memory chip is selected for the read operation. The clock signals (CK_t and CK_c) are used to synchronize data transmission, where CK_t and CK_c are two phases of the clock signal. The data bus transmits data under the control of the data strobe signals (DQS_t and DQS_c).

[0052] In a read operation, the rising or falling edge of the data strobe signal (such as DQS_t) is used to indicate the validity of the data. Therefore, for example, in Figure 2 After the time interval (tRPRE) required between the read operation and the precharge operation, the rising or falling edge of the data strobe signal (such as DQS_t) needs to be aligned with the edge of each data bit in the data signal DQ[15:0] on the data bus, and then it will enter the read stable time (tRPST) to ensure that the memory controller can sample the data at the correct moment. The read latency (RL) is equal to the CAS latency (CL) because the CAS latency defines the time from the issuance of the read command until the data can be sampled by the memory controller.

[0053] Figure 1 and Figure 2 Fig. shows that during the initialization process, the DDR PHY can find the ideal delay parameters (such as the read latency RL and the write latency WL) through initialization training (TRAIN) to meet the read and write timing requirements of the DDR protocol. For example, at the DDR PHY side, the optimal delay parameters can be found by adjusting the delay line of the internal receiver (Receiver Side Delay Line) to enable the DDR PHY to successfully sample the output signal of the memory die in the DDR memory.

[0054] During the operation of the chip, due to environmental changes such as external temperature, humidity, and voltage, as well as the influence of the chip's own structure, the optimal point of the PHY delay parameter may change, and the DDR timing on the actual chip will also change.

[0055] Figure 3 Fig. shows the actual timing diagram of a DDR write operation.

[0056] As Figure 3 shown, the timing relationship between the data strobe signal (such as DQS) on the PHY side and the data signal (such as DQ) on the data bus satisfies that the rising edge of the data strobe signal aligns with the center position of each data bit in the data signal DQ[15:0] on the data bus. For example, the rising edge of the data strobe signal aligns with the center position of data bit D0. However, there is an obvious offset error on the memory DRAM side (as Figure 3 shown, the rising edge of the data strobe signal on the DRAM side actually aligns with the center position of data bit D1, and data bit D0 is not aligned with the data strobe signal). This causes the data signal DQ[15:0] not to be correctly written into the memory DRAM (for example, the written data will lose data bit D0).

[0057] Figure 4 Fig. shows the actual timing diagram of a DDR read operation.

[0058] As Figure 4 shown, the timing relationship between the data strobe signal (such as DQS) on the DRAM side and the data signal (such as DQ) on the data bus satisfies that the rising edge of the data strobe signal needs to align with the edge of each data bit in the data signal DQ[15:0] on the data bus. For example, the rising edge of the data strobe signal aligns with the edge of data bit D0. However, when the data is transferred from the DRAM side to the PHY side, there is an obvious offset error on the PHY side (as Figure 4 shown, the second rising edge of the data strobe signal on the PHY side actually aligns with the edge of data bit D1, and data bit D0 is not aligned with the edge of the data strobe signal). This causes the data signal DQ[15:0] not to be correctly read out from the memory DRAM (for example, the read data will lose data bit D0).

[0059] As Figure 3 and Figure 4 During the actual write and read operations, there is a delay offset phenomenon on different sides, that is, there is an offset error during the write and read operations.

[0060] Regarding this delay offset phenomenon, the PHY can be re-initialized and trained (TRAIN) completely again to find the ideal delay parameter. However, the entire initialization training process of the PHY requires reloading the firmware, which takes a long time and will greatly affect the bandwidth of the chip. Or, during normal operation, the delay parameter that has the greatest impact on the read direction of the chip's read operation and the write direction of the write operation can be selected for retraining (RETRAIN). Retraining occurs during the chip's execution process, and the appropriate delay parameter in the current environment is obtained to ensure the normal operation of the chip's read and write operations. In the write direction, the PHY needs to output a data strobe signal (DQS) and a data signal (DQ) that conform to the write timing of the DDR protocol, so that the memory DRAM can correctly sample the data signal; in the read direction, the PHY needs to obtain the correct data signal (DQ), and obtain and return the data of the data signal completely to the memory controller. This retraining (RETRAIN) method can be adjusted in real time during the chip's operation, with almost no additional time consumption and almost no impact on the chip's bandwidth.

[0061] The inventors of the present disclosure noticed that after the current training of the PHY (initialization training TRAIN or retraining RETRAIN) is completed, it is detected whether the training is correct by the correctness of the read and write operations. However, even if the read and write operations are correct, it cannot be guaranteed that they fully meet the protocol requirements. For example, in the write direction of the write operation, the rising edge of the data strobe signal (DQS) may not exactly align with the center position of the data signal (DQ). When this offset error does not exceed 1 / 2 of a clock cycle, it will not affect the current read and write operations (for example, at a frequency of 3200 Mbps, 1 / 2 of a clock cycle is 156 ps, and as long as the offset error does not exceed 156 ps, the read and write operations will not go wrong). However, such delay parameters for the read and write operations are not optimal. If such delay parameters are used, the chip may face problems such as weak anti-interference ability and poor signal quality after silicon (i.e., after the chip is actually manufactured).

[0062] Moreover, the inventors of the present disclosure also noticed that although starting retraining (RETRAIN) during the operation of the chip can play a role in real-time adjustment during the chip's operation, the adjustment space for the chip that has already started running after silicon is limited. Determining the ideal delay parameter of the physical layer interface (PHY) through initialization training (TRAIN) or retraining (RETRAIN) is crucial for the performance and reliability of the entire chip. Therefore, it is necessary to conduct a detailed evaluation and verification of the adjustment ability of the PHY before silicon (i.e., before the chip is actually manufactured), especially the precise evaluation of the retraining (RETRAIN) process of the PHY, in order to improve the performance and reliability of the entire chip and avoid the increased costs and risks caused by poor performance or unreliability of the finished chip after tape-out.

[0063] At least one embodiment of the present disclosure provides a chip verification method, including: obtaining a chip model of a chip, where the chip model includes a physical layer interface and a functional model; writing an expected offset for simulating a timing offset during an access operation between the physical layer interface and the functional model into the chip model, so that the physical layer interface trains the timing of the access operation between the physical layer interface and the functional model based on the expected offset; in response to the end of the training of the chip model, obtaining an operation offset for compensation obtained by the physical layer interface based on the training; and determining the offset adjustment ability of the physical layer interface according to the operation offset and the expected offset.

[0064] In the chip verification method of the above embodiment of the present disclosure, by obtaining a chip model including a physical layer interface and a functional model of the chip before silicon, simulating the timing offset between the physical layer interface and the functional model to dynamically give an expected offset, and then simulating and training during the simulation process of front-end chip verification, so as to compare the operation offset obtained by the physical layer interface through training with the expected offset written into the chip model before, so that the offset adjustment ability of the physical layer interface can be determined through training before silicon, improving the accuracy of verifying and testing the physical layer interface before silicon, thereby improving the accuracy of chip design, reducing possible problems after silicon, and thus reducing the overall tape-out cost and risk.

[0065] The following will illustrate each embodiment of the present disclosure with specific examples.

[0066] Figure 5 The flowchart of a chip verification method provided by at least one embodiment of the present disclosure is shown.

[0067] As Figure 5 shown, in some embodiments of the present disclosure, the above chip verification method includes steps S30 - S33 described below.

[0068] Step S30, obtaining a chip model of a chip, where the chip model includes a physical layer interface and a functional model.

[0069] Step S31, writing an expected offset for simulating a timing offset during an access operation between the physical layer interface and the functional model into the chip model, so that the physical layer interface trains the timing of the access operation between the physical layer interface and the functional model based on the expected offset.

[0070] Step S32, in response to the end of the training of the chip model, obtaining an operation offset for compensation obtained by the physical layer interface based on the training.

[0071] Step S33, determining the offset adjustment ability of the physical layer interface according to the operation offset and the expected offset.

[0072] In an embodiment of the present disclosure, the chip model can be a model obtained by simulating a real chip and capable of simulating the internal logic of the real chip. For example, the chip model is written in a hardware description language (such as Verilog or HDL). For example, after running, the chip model can simulate the chip to perform write operations and read operations according to a standard protocol. For example, it can receive a write command and write write data, and receive a read command and return read data. For example, it can be performed according to the DDR standard protocol.

[0073] The physical layer interface (Physical Layer Interface, PHY) is the physical layer interface whose accuracy needs to be verified and tested (hereinafter also simply referred to as PHY).

[0074] The functional model can be a model that can cooperate with the physical layer interface to perform write operations and read operations according to a standard protocol, and is used to simulate a storage module (such as a memory module) on a real chip.

[0075] In some embodiments of the present disclosure, the chip in the above chip verification method is a DDR (Double DataRate) chip, and the functional model is a DRAM (Dynamic Random Access Memory) model. For example, the physical layer interface (PHY) can be a DDR PHY.

[0076] For example, the functional model can be a DRAM model set according to the DRAM protocol requirements. Access operations (including read operations and write operations, hereinafter also simply referred to as read-write operations) can be performed between the PHY and the functional model. For example, the link for performing read-write operations between the PHY and the functional model is also called a read-write link.

[0077] For example, the above PHY may not have undergone initialization training (TRAIN), or may have undergone initialization training (TRAIN) and obtained an offset reference value after initialization training. For example, the delay register in the PHY that has undergone initialization training (TRAIN) stores the offset reference value.

[0078] For example, in step S31, the expected offset is used to simulate the delay generated on the data line due to temperature and voltage changes in the real chip. For example, the expected offset is used to simulate the timing offset during the access operation between the physical layer interface and the functional model.

[0079] The expected offset can be applied to the read-write link between the PHY and the functional model in the chip model. For example, the expected offset can be written and stored in the chip model, and the expected offset can be applied to the functional model.

[0080] For example, to better test the read and write operations of the PHY and the functional model in the chip model, a read / write link connection interface can be set on the read / write link between the PHY and the functional model. This read / write link connection interface connects the PHY and the functional model, forming a read / write link of PHY - read / write link connection interface - functional model. For example, on the one hand, when the chip model is in the normal working mode, this read / write link connection interface can enable the transmission of address control commands and perform read / write operations between the PHY and the DRAM according to the timing requirements of the DRAM protocol. On the other hand, the read / write link connection interface can be used to receive the expected offsets generated on the data line due to temperature and voltage changes in the simulated real chip. For example, the expected offsets can be applied to the read / write link connection interface.

[0081] The expected offsets can be generated in software or in hardware. For example, to simulate the irregular timing offsets during the access operation of a real chip, the expected offsets can be generated randomly.

[0082] In some embodiments of the present disclosure, in the above chip verification method, step S31 may further include step S310:

[0083] Step S310, writing the expected offsets into the target register in the chip model for the physical layer interface to read for training.

[0084] For example, the target register in the chip model can be a register in the functional model used to store the current data strobe signal (such as DQS) and data signal (such as DQ) offsets during operation. For example, for the DDR5 technical standard, the target registers can be registers MR46 and MR47 in the DRAM model serving as the functional model.

[0085] For example, after the expected offsets are generated, the expected offsets can be regarded as the current offsets generated by the real chip in the normal working mode. For example, taking the functional model conforming to the DDR5 technical standard as an example, the values corresponding to the expected offsets can be written into the corresponding registers MR46 and MR47 in the functional model.

[0086] In some embodiments of the present disclosure, in the above chip verification method, step S31 may further include step S311:

[0087] Step S311, in response to the start of training of the chip model, enabling the physical layer interface to obtain the expected offsets written into the chip model and using them as the current offsets between the physical layer interface and the functional model for training.

[0088] The training initiated for the chip model can be the initialization (TRAIN) training initiation of the chip model or the retraining (RETRAIN) initiation of the chip model. Retraining (RETRAIN) is an operation process after the initialization (TRAIN) training, for example, it is retraining initiated again according to an instruction.

[0089] For example, the storage controller or PHY in the chip model can be made to send an expected offset acquisition instruction to the functional model, so that the PHY can obtain the expected offset written in the destination register in the functional model of the chip model before or after responding to the training initiation (instruction) of the chip model, so that the PHY can obtain this expected offset. For example, the storage controller can be a DDR controller. For example, the DDR controller can send an expected offset acquisition instruction to the PHY, and then the PHY sends the expected offset acquisition instruction to the functional model. The PHY peeks (acquires) the expected offset written in the destination register when reading the command stream related to the expected offset acquisition instruction in response to the training initiation (instruction) of the chip model, and the PHY saves the obtained expected offset. For example, the expected offset acquisition instruction can be an MRR (Mode Register Read) instruction, and the MRR instruction is used to obtain the values of register MR46 and register MR47 from the destination register of the DDR DRAM.

[0090] It should be noted that after the expected offset is written into the target register in the chip model, the obtained expected offset obtained by the PHY from the target register according to the expected offset acquisition instruction and the expected offset can be values that are numerically different. For example, the obtained expected offset is the offset peeked (acquired) by the analog PHY according to the command stream related to the expected offset acquisition instruction, and the obtained expected offset is a value with a corresponding calculation relationship with the expected offset according to the regulations of the DDR technical standard.

[0091] Before the training initiation of the chip model, the training parameters required in the training environment can be configured through a configuration module. For example, the configuration module can be configured through a configuration interface, and the configuration interface can be, for example, an apb interface, an axi interface, or other protocol interfaces. The embodiments of the present disclosure do not limit this.

[0092] For example, before the training initiation of the chip model, step S40 can also be included in the above chip verification method:

[0093] Step S40, configure the training mode of the chip model so that the chip model conducts training in a set working mode.

[0094] For example, the training mode of the chip model includes a power switching mode, a normal working mode (read / write mode), or other modes, etc. The embodiments of the present disclosure do not limit this.

[0095] For example, in the power switching mode, the functions to be executed after training can be determined according to the training mode encoding configured in the configuration module. For example, taking the chip model as the model of the DDR chip, the encoding of 0x8 represents the RETRAIN operation, and the encoding of 0x18 represents the RETRAIN+RELOCK operation. During the operation of starting retraining (RETRAIN), the DDR controller sends an SRE (Self-Refresh Enter) instruction to the functional model (such as DRAM) to make the functional model enter the self-refresh state. At this time, the control right of the functional model will be switched from the DDR controller to the PHY. Then, the PHY sends an SRX (Self-Refresh Exit) command to make the functional model exit the self-refresh state and start the retraining (RETRAIN). After the retraining (RETRAIN) is completed, the PHY sends an SRE instruction to the functional model, and then switches the control right of the functional model from the PHY to the DDR controller.

[0096] For example, in the normal read / write mode, the PHY performs training operations in the background. When there is an offset update instruction, the PHY automatically updates the current delay register.

[0097] For example, in step S32, during the training process, the PHY obtains the expected offset written by the functional model in the chip model to the destination register, and gets the obtained expected offset. Then, the PHY calculates according to the obtained expected offset through its own internal logic or algorithm of the PHY to obtain the operation offset. For example, the PHY stores the operation offset in the delay register. After the training of the chip model is completed, the operation offset for compensation obtained by the PHY based on the training can be obtained. For example, the operation offset can be obtained by reading the delay register in the PHY.

[0098] The operation offset is the actual timing offset during the access operation between the PHY and the functional model obtained according to the applied expected offset.

[0099] For example, in step S33, the offset adjustment ability of the physical layer interface can be determined by comparing the operation offset and the expected offset and according to the deviation between the operation offset and the expected offset. For example, the error range can be calculated by comparing the operation offset and the expected offset, and the offset error is output, thereby evaluating the adjustment ability of the PHY in the chip model.

[0100] In at least one of the above embodiments of the present disclosure, an expected offset dynamically generated by simulating the timing offset in the real access operation process is applied to the chip model at the start of training, and the timing of the access operation between the physical layer interface and the functional model is trained based on the expected offset. Then, the operation offset of the physical layer interface is obtained at the end of training. Thus, the offset adjustment ability of the physical layer interface can be determined according to the operation offset and the expected offset, enabling the ability to adjust the delay during the training of the physical layer interface to be evaluated in advance through front-end verification before the chip is fabricated from silicon. This can solve the problems caused by inappropriate internal logic and algorithms of the physical layer interface before the chip is fabricated from silicon, avoid possible defects after the chip is fabricated from silicon, and save the economic cost and time cost of tape-out.

[0101] In some embodiments of the present disclosure, before starting the training of the chip model, the above chip verification method further includes step S41:

[0102] Step S41, configure the operating frequency of the chip model to determine the expected offset according to the set operating frequency.

[0103] For example, before starting the training, the operating frequency of the chip model can be configured. For example, the operating frequency of the chip model supports switching between multiple different operating frequencies. For example, there are 4 operating frequencies. The embodiments of the present disclosure do not limit the number of supported operating frequencies.

[0104] After configuring the operating frequency of the chip model (after switching the operating frequency of the chip model), the set operating frequency is used as the current operating frequency. For example, in response to the start signal of the training of the chip model, the expected offset can be determined according to the set operating frequency.

[0105] The operating frequency can be the operation period of the access operation. The operation period can be the clock cycle. For example, the state of the processor can be updated or basic logical operations can be performed within one clock cycle; or, the operation period can be the machine cycle or the instruction cycle. For example, it can be the machine cycle or the instruction cycle required to execute a complete instruction. For example, one machine cycle or instruction cycle can include multiple clock cycles.

[0106] In some embodiments of the present disclosure, the functional model includes multiple memory particle models; before starting the training of the chip model, the above chip verification method further includes steps S42 and S43.

[0107] Step S42, according to the set particle coding rule and the coding requirement of the physical layer interface, obtain the coding of each memory particle model in the functional model.

[0108] Step S43: Determine the expected offset corresponding to each memory cell model in the functional model according to the encoding of each memory cell model in the functional model and the set operating frequency.

[0109] For example, in step S42, when the functional model is a DRAM model, the multiple memory cell models included in the functional model are DRAM cell models.

[0110] For example, the granule encoding rule of the chip model can be configured so that each memory cell model in the functional model is encoded according to the set granule encoding rule. For example, the granule encoding rule can be to encode each of the multiple memory cell models in the functional model (such as DRAM) in the PDA (PerDRAM Addressability) mode according to the requirements of the PHY. For example, in the PDA mode, the DDR controller or PHY can encode each DRAM cell model by sending a specific command.

[0111] For example, in step S43, different offsets can be set for different memory cell models according to the set operating frequency and the encoding of each memory cell model.

[0112] For example, each memory cell model can be encoded (such as numbered) according to the encoding requirements of the physical layer interface. For example, the encoding requirements of the physical layer interface can be determined according to the situation of the memory module (such as the memory module) on the real chip.

[0113] For example, the encoding requirements of the physical layer interface can be determined according to the layout of the memory module. For example, in a dual in-line memory module (DIMM), there are different maximum quantity limits and encoding methods for memory cells with different bit widths. For example, for memory cells with a bit width of X4, there can be at most 10 memory cells on a dual in-line memory module, then the corresponding 10 memory cell models on the functional model can be encoded as 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, or other custom numbers. For example, for memory cells with a bit width of X8, there can be at most 5 memory cells on a dual in-line memory module, then the corresponding 5 memory cell models on the functional model can be encoded as 0, 1, 2, 3, 4, or other custom numbering methods can also be used. The specific encoding method for multiple memory cell models is not limited in this disclosure.

[0114] In some embodiments of the present disclosure, the expected offset includes an expected offset value and an expected offset direction. Determining the expected offset corresponding to each memory cell model in the functional model in the above chip verification method includes steps S44 and S45.

[0115] Step S44: Determine a predetermined offset range corresponding to a set operating frequency according to the storage standard protocol supported by the functional model.

[0116] Step S45: Determine the expected offset value and expected offset direction of each storage granule model in the functional model according to the predetermined offset range.

[0117] For example, in step S44, if the storage standard protocol supported by the functional model is the DRAM protocol, the predetermined offset range can be determined according to the offset range supported by the DRAM protocol at the corresponding set operating frequency. Different storage standard protocols supported by the functional model may have different offset ranges supported by the set operating frequency under the corresponding supported storage standard protocol. For example, the offset ranges supported at different set operating frequencies can be determined according to the Tdqs2dq parameter (representing the time delay from the edge of the data strobe signal (DQS) to the valid edge of the data signal (DQ)) and the Tdqs2ck parameter (representing the time delay from the edge of the data strobe signal (DQS) to the edge of the clock signal (CK)) supported by the DRAM protocol.

[0118] For example, in step S45, according to the predetermined offset range determined above, the expected offset value and expected offset direction of each storage granule model can be randomly generated within the predetermined offset range.

[0119] In some embodiments of the present disclosure, step S45 in the above chip verification method includes steps S450 and S451.

[0120] Step S450: Obtain an offset reference value.

[0121] Step S451: In response to the start of training of the chip model, determine the expected offset value and expected offset direction of each storage granule model in the functional model according to the offset reference value and the predetermined offset range.

[0122] For example, for the retraining process, the offset reference value can be obtained after the retraining starts. For example, the offset reference value can be the offset value (golden value) DQS2DQ_base of the reference of the data strobe signal (DQS) and the data signal (DQ) in the initialization training (TRAIN) phase.

[0123] For example, in step S451, for the RETRAIN process, after the chip model has been initialized and trained (TRAIN), the results of the initialization training (TRAIN) are read to obtain the offset reference value of the PHY. For example, the expected offset value and the expected offset direction of each memory cell model in the functional model can be determined randomly based on the offset reference value and within a predetermined offset range. For example, the expected offset value and the expected offset direction of each memory cell model in the functional model can also be determined by other means based on the offset reference value and within a predetermined offset range.

[0124] In some embodiments of the present disclosure, in the above chip verification method, step S310 further includes step S3101:

[0125] Step S3101: According to the expected offset, for each memory cell model in the functional model, store the corresponding expected offset value and the expected offset direction into the target register corresponding to each memory cell model.

[0126] For example, each memory cell model in the functional model corresponds to its own target register, and the expected offset value and the expected offset direction of each memory cell model in the functional model can be stored in the target register corresponding to each memory cell model respectively.

[0127] For example, within a predetermined offset range, the expected offset direction and the expected offset value can be randomly generated for different memory cell models in the functional model. The expected offset direction and the expected offset value corresponding to each memory cell model are applied to the chip model to simulate the irregular timing offsets of each memory cell caused by the different arrangements and wiring of different memory cells in the memory module of the real chip, as well as the different influences of temperature and voltage changes. For example, the generated expected offset direction and the expected offset value can be applied at the read / write link connection interface of the chip model.

[0128] It should be noted that for different memory cell models, in addition to the random generation method, the expected offset direction and the expected offset magnitude (value) can also be generated by other means. The specific method for generating the expected offset is not limited in the present disclosure.

[0129] By generating the expected offset direction and the expected offset value for multiple memory cell models corresponding to multiple memory cells of the real storage module in the functional model, the simulation of the functional model is closer to the working conditions of the storage module of the real chip, so that the real chip can be better tested and verified before silicon through the functional model.

[0130] In some embodiments of the present disclosure, in the above chip verification method, step S311 further includes step S3110 or step S3111.

[0131] Step S3110: Obtain the expected offset value and the expected offset direction stored in the target register corresponding to each memory particle model respectively according to the physical layer interface, and enable the physical layer interface to perform offset calculation based on the obtained expected offset value and the obtained expected offset direction, so as to obtain the offset value of the operation offset for compensation and the offset direction of the operation offset for each memory particle model; or

[0132] Step S3111: Obtain the operation offset according to the offset reference value and the absolute value of the offset value of the expected offset obtained by the physical layer interface.

[0133] For example, for step S3110, the PHY can obtain the expected offset value and the expected offset direction stored in the respective target registers of each memory particle model in the function model respectively. The PHY performs offset calculation based on the obtained expected offset value and the obtained expected offset direction, so as to obtain the respective corresponding operation offset value and operation offset direction of each memory particle model.

[0134] It should be noted that the offset calculation is performed by the PHY according to its own internal logic or algorithm. The obtained expected offset value and the obtained expected offset direction are obtained by the simulated PHY peeking (obtaining) according to the command stream related to the expected offset obtaining instruction, which are different from the expected offset value and the expected offset direction.

[0135] For example, for step S3111, the obtained expected offset value can be converted into the absolute value of the offset value of the expected offset (also referred to as the expected offset value), and the operation offset can be obtained according to the operation result of the offset reference value and the absolute value of the offset value of the expected offset obtained by the physical layer interface.

[0136] For example, the operation offset value and the operation offset direction of each memory particle model can be stored in the delay register of the PHY respectively. For example, the data of the delay register includes a delay size field and a delay direction field; for example, the operation offset value can be stored at the position of the delay size field stored in the delay register, and the operation offset direction can be stored at the position of the delay direction field stored in the delay register.

[0137] In some embodiments of the present disclosure, in the above chip verification method, step S33 further includes step S330:

[0138] Step S330: Compare the expected offset direction and the operation offset direction to determine whether the offset direction of the physical layer interface is correct; compare the expected offset value and the operation offset value to determine the offset error value of the physical layer interface.

[0139] For example, the expected offset value and the expected offset direction corresponding to each memory particle model in the function model can be obtained separately.

[0140] The operation offsets of each memory particle model in the function model can be obtained separately from the chip model. For example, the operation offset includes an operation offset value and an operation offset direction. For example, the latency size field storing the operation offset value and the latency direction field storing the operation offset direction of each memory particle model in the PHY can be read.

[0141] It should be noted that when the values read from the latency size field and the latency direction field are not in the same unit as the expected offset value and the expected offset direction, the values read from the latency size field and the latency direction field can be subjected to unit conversion to obtain an operation offset value and an operation offset direction that are in the same unit as the expected offset value and the expected offset direction.

[0142] For example, for each memory particle model in the function model, the expected offset direction and the operation offset direction of each memory particle model can be compared separately, so that it can be determined whether the offset direction of the PHY is correct for each memory particle model. For example, if the expected offset direction of a certain memory particle model is the direction of increasing offset, while the operation offset direction is the direction of decreasing offset, then the offset direction of the PHY of this memory particle model is incorrect.

[0143] For example, for each memory particle model in the function model, the expected offset value and the operation offset value of each memory particle model can be compared separately, so as to determine the offset error value of the physical layer interface for each memory particle model respectively.

[0144] For example, when the offset direction of a certain memory particle model is correct, the expected offset value and the operation offset value of this memory particle model can be compared to determine the offset error. For example, when the offset direction of a certain memory particle model is correct, the expected offset value is 38 ps and the operation offset value is 35 ps, then the offset error value is 38 ps - 35 ps = 3 ps.

[0145] For example, in response to the end (signal) of the training of the chip model, the offset error values of each memory particle model in the function model can be output. For example, the offset error values of all memory particle models in the function model can be output.

[0146] Although the timing offset (such as the offset error value) in data transmission does not exceed 1 / 2 ck clock cycles, the reading and writing of data are usually not affected. For example, within an error of 156 ps (within 1 / 2 ck clock cycles) at a frequency of 3200 Mbps. For example, when the offset error is 1 / 4 ck, the reading and writing are usually not affected. However, the method of the above embodiments of the present disclosure enables a higher precision in detecting errors at a frequency of 3200 Mbps (with a precision at the picosecond level, such as 5 ps), so that the chip verification method of the present disclosure can accurately calculate the compensation error (offset error value) of the PHY, realizing the detection of the offset error of the high-precision PHY before chip silicon, and can also evaluate in advance the quality of the data eye diagram of the real chip, avoiding possible problems of the post-silicon chip.

[0147] In some embodiments of the present disclosure, in the above chip verification method, step S33 further includes step S331:

[0148] Step S331, in response to the offset direction of the physical layer interface being incorrect, determining that there is an error in the internal logic or algorithm of the physical layer interface; in response to the offset direction of the physical layer interface being correct, outputting the offset error value of the physical layer interface.

[0149] For example, the training process of the PHY can be monitored in real time, so that the PHY gives a judgment on whether the offset direction is correct in real time and outputs the offset error value.

[0150] In some embodiments of the present disclosure, in the above chip verification method, in the training of the chip model, it includes step S312:

[0151] Step S312, in response to the chip model being in the retraining state or the normal working mode, sending an offset update instruction to the physical layer interface to update the operation offset obtained based on the training to the offset register of the physical layer interface.

[0152] In the normal working mode, an offset update instruction can be sent to update the operation offset to the delay register of the PHY.

[0153] In some embodiments of the present disclosure, before starting the training of the above chip verification method for the chip model, it further includes step S46:

[0154] Step S46, configuring the precision mode of the chip model to configure the training step size.

[0155] Before starting the training of the chip model, the precision mode of the chip model can be configured. For example, the configured training step can be 1 / 128ck (clock cycle), 1 / 64ck (clock cycle), or 40 / 128ck (clock cycle), etc. The embodiments of the present disclosure do not limit the size of the training step. For example, training (including initialization training and retraining) can be performed according to the training step, and the training step will affect the training speed and the adjusted precision.

[0156] Figure 6 The flowchart showing an example of a chip verification method provided by at least one embodiment of the present disclosure is as follows. Below, some embodiments of the present disclosure will be described by taking the Figure 6 example process shown as an example.

[0157] As Figure 6 shown, the process of retraining (RETRAIN) of the write operation will be used as an example for illustration.

[0158] First, obtain the offset reference value.

[0159] This offset reference value can be the offset value (golden value) DQS2DQ_base of the reference of the data strobe signal (DQS) and the data signal (DQ) during the initialization training (TRAIN) phase. For each retraining (RETRAIN) after the initialization training (TRAIN), this value can be used as the offset reference value. For example, the offset reference value (such as DQS2DQ_base) can be recorded in a corresponding register of the PHY.

[0160] After that, make the PHY of the chip model enter the normal working mode, and perform normal access operations (such as read operations or write operations) with the functional model to perform normal data reading and writing transmissions. During this process, as the voltage and temperature change, access errors will occur, such as incorrect read and write data.

[0161] Then, send a retraining start instruction.

[0162] When an access error occurs, the timing offset of the read / write link of the read / write operation has occurred. At this time, a retraining start instruction can be sent. For example, the retraining start instruction can also be sent at any time or periodically before the timing offset for calibrating the read / write link of the read / write operation. For example, it can be sent periodically by the DDR controller or the PHY. For example, taking the write operation as an example, the calibration of the write link can be performed. For example, the retraining start instruction sent can be the MPC_DQS_START instruction.

[0163] After that, an expected offset value is randomly generated and an expected offset direction is randomly generated, and the randomly generated expected offset value and expected offset direction are applied to the read / write link connection interface, also known as the connection interface (in the chip model).

[0164] For the retraining (RETRAIN) process, after the chip model has been initialized and trained (TRAIN), the offset reference value of the PHY is obtained according to the result of the initialization training (TRAIN). For example, based on the offset reference value obtained from the initialization training (TRAIN), the expected offset value and expected offset direction of each memory particle model in the functional model can be determined within a predetermined offset range. For example, the expected offset value can be obtained by increasing based on the offset reference value, or the expected offset value can be obtained by decreasing based on the offset reference value.

[0165] After sending the retraining start instruction, the expected offset is written into the destination register in the functional model; then the PHY reads the destination register in the functional model to obtain the obtained expected offset.

[0166] After that, the PHY calculates according to the obtained expected offset.

[0167] For example, after the PHY obtains the obtained expected offset, the obtained expected offset can be converted into the absolute value of the offset value of the current data strobe signal (DQS) and data signal (DQ) (DQS2DQ_now), and the absolute value of the offset value of the obtained expected offset (DQS2DQ_now) and the offset reference value (DQS2DQ_base) are operated to obtain the value that needs to be compensated for the offset between the data strobe signal (DQS) and data signal (DQ) (DQS2DQ_delay) as the operation offset.

[0168] After that, the operation offset is updated to the delay register of the PHY.

[0169] In the normal working mode, an offset update instruction can be sent to update the operation offset to the delay register of the PHY.

[0170] After that, the expected offset and the operation offset are compared to determine whether the expected offset and the operation offset are the same, so as to determine the offset adjustment ability of the physical layer interface.

[0171] The way of comparing the expected offset and the operation offset is the same as the description of the above chip verification method of the present disclosure, so it will not be repeated here.

[0172] Figure 7 The block diagram of a chip verification device provided by at least one embodiment of the present disclosure is shown.

[0173] At least one embodiment of the present disclosure further provides a chip verification device for verifying a chip model, such as Figure 7 As shown, the corresponding chip model 810 includes a physical layer interface and a functional model, for example, which can refer to the above description; the chip verification device 700 includes an expected offset module 710 and an inspection module 720.

[0174] The expected offset module 710 is configured to write an expected offset for simulating the timing offset during the access operation between the physical layer interface and the functional model into the chip model 810, so that the physical layer interface trains the timing of the access operation between the physical layer interface and the functional model based on the expected offset.

[0175] The inspection module 720 is configured to, in response to the end of the training of the chip model 810, obtain the operation offset for compensation obtained by the physical layer interface based on the training; determine the offset adjustment ability of the physical layer interface according to the operation offset and the expected offset.

[0176] In some embodiments of the present disclosure, the above chip verification device 700 further includes a configuration module 730.

[0177] The configuration module 730 is configured to perform one or more of the following configurations: configuring the training mode of the chip model 810 so that the chip model 810 is trained in a set working mode; configuring the working frequency of the chip model 810 to determine the expected offset according to the set working frequency; configuring the precision mode of the chip model 810 to configure the training step size; and / or, configuring the particle encoding rule of the chip model 810 so that each memory particle model in the functional model is encoded according to the set particle encoding rule.

[0178] For example, the expected offset module 710 is further configured to write the expected offset into a target register in the chip model for the physical layer interface to read for training.

[0179] For example, the expected offset module 710 is further configured to, in response to the start of the training of the chip model, enable the physical layer interface to obtain the expected offset written into the chip model and use it as the current offset between the physical layer interface and the functional model for training.

[0180] For example, the functional model includes multiple memory particle models; the expected offset module 710 is further configured to, before the start of the training of the chip model, obtain the encoding of each memory particle model in the functional model according to the set particle encoding rule and the encoding requirements of the physical layer interface; determine the expected offset corresponding to each memory particle model in the functional model according to the encoding of each memory particle model in the functional model and the set working frequency.

[0181] For example, the expected offset includes an expected offset value and an expected offset direction. The expected offset module 710 is further configured to determine a predetermined offset range corresponding to a set operating frequency according to a storage standard protocol supported by the functional model; and determine the expected offset value and the expected offset direction of each storage particle model in the functional model according to the predetermined offset range.

[0182] For example, the expected offset module 710 is further configured to obtain an offset reference value; in response to the start of training of the chip model, determine the expected offset value and the expected offset direction of each storage particle model in the functional model according to the offset reference value and the predetermined offset range.

[0183] For example, the inspection module 720 is further configured to obtain an operating offset according to the offset reference value and the absolute value of the offset value of the expected offset obtained by the physical layer interface.

[0184] For example, the expected offset module 710 is further configured to store the corresponding expected offset value and expected offset direction of each storage particle model in the functional model into the target register corresponding to each storage particle model according to the expected offset.

[0185] For example, the inspection module 720 is further configured to respectively obtain the expected offset value and the expected offset direction stored in the target register corresponding to each storage particle model according to the physical layer interface, and cause the physical layer interface to perform offset calculation based on the obtained expected offset value and the obtained expected offset direction, so as to obtain the offset value of the operating offset for compensation and the offset direction of the operating offset of each storage particle model.

[0186] For example, the inspection module 720 is further configured to compare the expected offset direction and the operating offset direction to determine whether the offset direction of the physical layer interface is correct; compare the expected offset value and the operating offset value to determine the offset error value of the physical layer interface.

[0187] For example, the inspection module 720 is further configured to determine that there is an error in the internal logic or algorithm of the physical layer interface in response to the incorrect offset direction of the physical layer interface; output the offset error value of the physical layer interface in response to the correct offset direction of the physical layer interface.

[0188] For example, the detection module 720 is further configured to send an offset update instruction to the physical layer interface in response to the chip model being in a retraining state or a normal operating mode, and update the operating offset for compensation obtained based on training to the offset register of the physical layer interface.

[0189] For example, in the above example, the chip simulated by the chip model is a DDR chip, and the functional model is a DRAM model.

[0190] Figure 8A schematic diagram showing an example of a chip verification device provided by at least one embodiment of the present disclosure.

[0191] As Figure 8 shown, the chip verification device 700 may include an expected offset module 710, an inspection module 720, and a configuration module 730. The chip verification device 700 is applied to verify or test a corresponding chip model 810.

[0192] The chip model 810 includes a physical layer interface (PHY), a functional model, and a read / write link connection interface (hereinafter also referred to as a connection interface) between the two. For example, the write link in the chip model 810 is Physical Layer Interface (PHY) -> Connection Interface -> Functional Model, and the read link in the chip model 810 is Functional Model -> Connection Interface -> Physical Layer Interface (PHY).

[0193] For example, the expected offset module 710 includes a particle number (the number of each storage particle model in the functional model), an offset direction (the expected offset direction), and an offset value (the expected offset value).

[0194] For example, the particle numbers of multiple storage particle models are DRAM(0) to DRAM(n), where n is a positive integer. Different expected offset directions and expected offset values can be randomly generated for each storage particle model. For example, in the offset direction, +++ can represent the expected offset direction of increasing offset, and --- can represent the expected offset direction of decreasing offset. For example, the expected offset values corresponding to multiple storage particle models DRAM(0) to DRAM(n) are Delay 0 to Delay n, where n is a positive integer.

[0195] The inspection module 720 includes functions of obtaining the operation offset, comparing the offset direction, and calculating the offset error.

[0196] For example, the inspection module 720 can respectively obtain the operation offset of each storage particle model in the functional model from the chip model 810. For example, the operation offsets corresponding to multiple storage particle models DRAM(0) to DRAM(n) are 0 to operation offset n, and the operation offset includes an operation offset value and an operation offset direction. Compare the expected offset direction and the operation offset direction to determine whether the offset direction of the physical layer interface is correct; compare the expected offset value and the operation offset value, and calculate the offset error value of the physical layer interface.

[0197] The configuration module 730 may include one or more of the four modules: particle encoding, clock frequency, training mode, and precision mode.

[0198] For example, for the training mode, after configuring the training mode of the chip model 810, the configuration module 730 can monitor the start and end of training by monitoring the flags of the PHY training process during real-time training. For example, the real-time training monitoring can be implemented by a real-time training monitoring module. For example, the start of training can be monitored by identifying the training start flag, and the training start flag can be sent to the expected offset module 710 when the start of training is detected. For example, the end of training can be monitored by identifying the training end flag, and the training end flag can be sent to the inspection module 720 when the end of training is detected.

[0199] For example, for the precision mode, the configuration module 730 can configure the precision mode of the chip model 810 before the start of training of the chip model 810.

[0200] For example, for the granular coding, the configuration module 730 can configure the granular coding rules of the chip model 810 so that each memory granular model in the functional model is encoded according to the set granular coding rules. For example, the granular coding rules can be to encode each of the multiple memory granular models in the functional model (such as DRAM) in the PDA (Per DRAM Addressability) mode according to the requirements of the PHY. For example, the configuration module 730 can send the granular coding rules to the expected offset module 710. For example, in the PDA mode, the DDR controller or the PHY can encode each DRAM granular model separately by sending specific commands. The specific encoding method for the multiple memory granular models is not limited in this disclosure.

[0201] For example, for the clock frequency, before the start of training, the working frequency of the chip model 810 can be configured by the configuration module 730. The configuration module 730 supports switching between multiple different working frequencies. For example, 4 working frequencies. The embodiments of this disclosure do not limit the number of supported working frequencies.

[0202] For example, after configuring the working frequency of the chip model 810 or after switching the working frequency, the set working frequency is used as the current working frequency. For example, in response to the start of training (signal) of the chip model 810, the configuration module 730 transmits the set working frequency to the expected offset module 710.

[0203] The functional model includes multiple memory granular models; the expected offset module 710 is further configured to, before the start of training of the chip model 810, obtain the encoding of each memory granular model in the functional model according to the set granular coding rules and the coding requirements of the physical layer interface; and determine the expected offset corresponding to each memory granular model in the functional model according to the encoding of each memory granular model in the functional model and the set working frequency.

[0204] For example, the expected offset module 710 may set different offsets for different memory die models according to the set operating frequency and the encoding of each memory die model.

[0205] For example, after receiving the die encoding rule sent by the configuration module 730, the expected offset module 710 may encode each memory die model according to the encoding requirements of the physical layer interface (e.g., numbering). For example, the encoding requirements of the physical layer interface may be determined according to the layout of the memory modules (e.g., memory modules) on the real chip.

[0206] For example, the expected offset includes an expected offset value and an expected offset direction. The expected offset module 710 is further configured to determine a predetermined offset range corresponding to the set operating frequency according to the storage standard protocol supported by the functional model; and determine the expected offset value and the expected offset direction of each memory die model in the functional model according to the predetermined offset range.

[0207] For example, the expected offset module 710 is further configured to obtain an offset reference value; in response to the start of training of the chip model 810, determine the expected offset value and the expected offset direction of each memory die model in the functional model according to the offset reference value and the predetermined offset range.

[0208] For example, the expected offset module 710 is further configured to store the corresponding expected offset value and expected offset direction of each memory die model in the functional model into the target register corresponding to each memory die model according to the expected offset.

[0209] For example, each memory die model in the functional model corresponds to its own target register, and the expected offset value and the expected offset direction of each memory die model in the functional model can be stored in the target register corresponding to its own memory die model respectively.

[0210] For example, the expected offset module 710 may randomly generate the corresponding expected offset direction and expected offset value for different memory die models in the functional model in a random generation manner within the predetermined offset range. The expected offset direction and expected offset value corresponding to each memory die model are applied to the chip model 810 to simulate the irregular timing offsets of each memory die caused by the different layouts and wire routings of different memory dies in the memory module in the real chip and the different influences of temperature and voltage changes.

[0211] For example, the expected offset direction and expected offset value generated by the expected offset module 710 may be applied at the connection interface of the chip model 810.

[0212] It should be noted that Figure 8The offset direction and offset size in [ ] are only examples, and the present disclosure does not limit the expected offset direction and expected offset size for different memory die models. In addition to the random generation method, other methods can also be used to generate the expected offset direction and expected offset size, and the present disclosure does not limit the specific expected offset generation method.

[0213] For example, the check module 720 can enable the PHY to respectively obtain the expected offset value and expected offset direction stored in the target register of each memory die model in the function model. The PHY performs offset calculation based on the obtained expected offset value and the obtained expected offset direction, so as to obtain the respective corresponding operation offset value and operation offset direction of each memory die model.

[0214] It should be noted that the offset calculation is performed by the PHY according to its own internal logic or algorithm. The obtained expected offset value and the obtained expected offset direction are obtained by the analog PHY peeking (obtaining) according to the command stream related to the expected offset obtaining instruction, which are different from the expected offset value and expected offset direction.

[0215] For example, the operation offset value and operation offset direction of each memory die model can be respectively stored in the delay register of the PHY. For example, the data of the delay register includes a delay size field and a delay direction field; for example, the operation offset value can be stored in the storage delay size field of the delay register, and the operation offset direction can be stored in the storage delay direction field of the delay register.

[0216] For example, the check module 720 can respectively obtain the expected offset value and expected offset direction corresponding to each memory die model in the function model from the expected offset module 710.

[0217] For example, the check module 720 can read the storage delay size field of the operation offset value and the storage delay direction field of the operation offset direction of each memory die model stored in the delay register of the PHY.

[0218] For example, the check module 720 can respectively compare the expected offset direction and the operation offset direction of each memory die model in the function model, so as to determine whether the offset direction of the PHY is correct for each memory die model. For example, if the expected offset direction of a certain memory die model is the direction of increasing offset, while the operation offset direction is the direction of decreasing offset, then the offset direction of the PHY of this memory die model is incorrect.

[0219] For example, the check module 720 can respectively compare the expected offset value and the operation offset value of each memory die model in the function model, so as to respectively determine the offset error value of the physical layer interface for each memory die model.

[0220] For example, when the offset direction of a certain memory cell model is correct, the checking module 720 can compare the expected offset value and the operating offset value of the memory cell model to determine the offset error.

[0221] For example, in response to the end of training (signal) of the chip model 810, the checking module 720 can output the offset error values of each memory cell model in the functional model. For example, the offset error values of all memory cell models in the functional model can be output.

[0222] For example, the checking module 720 is further configured to determine that there is an error in the internal logic or algorithm of the physical layer interface in response to an incorrect offset direction of the physical layer interface; and output the offset error value of the physical layer interface in response to a correct offset direction of the physical layer interface.

[0223] For example, the detection module 720 is further configured to send an offset update instruction to the physical layer interface in response to the chip model 810 being in a retraining state or a normal operating mode, and update the operating offset for compensation obtained based on training to the offset register of the physical layer interface.

[0224] For example, in the above example, the chip simulated by the chip model is a DDR chip, and the functional model is a DRAM model.

[0225] For example, the checking module 720 can monitor the training process of the PHY in real time, so that the PHY can give a judgment on whether the offset direction is correct in real time and output the offset error value.

[0226] The chip model 810 corresponding to the chip verification device 700 in the embodiments of the present disclosure, as well as the expected offset module 710, the checking module 720, and the configuration module 730 in the chip verification device 700, are the same as those described in the embodiments of the above chip verification method of the present disclosure, and thus will not be elaborated herein.

[0227] The technical effects of the chip verification device in the above embodiments of the present disclosure are the same as those of the above chip verification method, and thus will not be elaborated herein.

[0228] Figure 9 The block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0229] At least one embodiment of the present disclosure further provides an electronic device, as Figure 9 shown, the electronic device 600 includes at least one memory 610 and at least one processor 620.

[0230] The above memory 610 is configured to store computer-executable instructions.

[0231] The above-mentioned processor 620 is configured to execute computer-executable instructions, and when the computer-executable instructions are executed by at least one processor, the chip verification method provided by any embodiment of the present disclosure is implemented.

[0232] For example, the memory 610 can be any memory capable of storing computer-executable instructions. For example, the memory can be a dynamic random access memory (DRAM, Dynamic Random Access Memory), a random access memory (RAM, Random Access Memory), or a static random access memory (SRAM, Static Random Access Memory), etc. The memory can be a cache (Cache) or a memory (Memory), etc. The present disclosure does not make any restrictions.

[0233] For example, the processor 620 can be any processor capable of executing computer-executable instructions. For example, a central processing unit (CPU, Central Processing Unit), a microcontroller unit (MCU, Microcontroller Unit), or a digital signal processor (DSP, Digital Signal Processor), etc. The present disclosure does not make any restrictions.

[0234] The technical effects of the electronic device in the above embodiments of the present disclosure are the same as those of the above chip verification method, and thus will not be elaborated herein.

[0235] Figure 10 It is a block diagram of an electronic device provided by at least one embodiment of the present disclosure.

[0236] The electronic device in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Tablet Computers), PMPs (Portable Multimedia Players), in-vehicle terminals (such as in-vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 10 The illustrated electronic device 1000 is merely an example and should not impose any limitations on the functions and usage scope of the embodiments of the present disclosure.

[0237] For example, refer to Figure 10, in some examples, the electronic device 1000 includes a processing device (such as a central processing unit, a graphics processing unit, etc.) 1001, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1002 or the program loaded from the storage device 1008 into the random access memory (RAM) 1003. For example, the processing device 1001 can be at least one processor in any embodiment of the present disclosure. In the RAM 1003, various programs and data required for the operation of the computer system are also stored. For example, the RAM 1003 can be at least one memory in any embodiment of the present disclosure. The processing device 1001, the ROM 1002, and the RAM 1003 are connected to each other through the interconnection network 1004. The input / output (I / O) interface 1005 is also connected to the interconnection network 1004.

[0238] For example, the following components can be connected to the I / O interface 1005: an input device 1006 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1007 including, such as a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1008 including, for example, a magnetic tape, a hard disk, etc.; a communication device 1009 including, for example, a network interface card such as a LAN card, a modem, etc. The communication device 1009 can allow the electronic device 1000 to communicate with other devices wirelessly or wiredly to exchange data and perform communication processing via a network such as the Internet. The drive 1010 is also connected to the I / O interface 1005 as needed. A removable medium 1011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1010 as needed so that the computer program read from it can be installed into the storage device 1008 as needed. Although Figure 10 an electronic device 1000 including various devices is shown, it should be understood that it is not required to implement or include all the shown devices. Instead, more or fewer devices can be implemented or included.

[0239] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 1009 may communicate with the network and other devices through wireless communication. The network may be, for example, the Internet, an intranet, and / or a wireless network such as a cellular phone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). The wireless communication may use any one of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), WiMAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0240] For example, the electronic device 1000 may be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, etc., or may be a combination of an operating device and hardware of any chip verification device. The embodiments of the present disclosure are not limited thereto.

[0241] At least one embodiment of the present disclosure further provides a non-transitory storage medium that non-transitorily stores computer-executable instructions. For example, when the computer-executable instructions are executed by a processor, the chip verification method provided by at least one embodiment of the present disclosure is implemented.

[0242] Figure 11 is a schematic diagram of a non-transitory storage medium provided by some embodiments of the present disclosure. As Figure 11 shown, the non-transitory storage medium 900 may non-transitorily store computer-executable instructions 910, and the computer-executable instructions 910 implement the chip verification method provided by any embodiment of the present disclosure when executed by a computer.

[0243] Regarding the present disclosure, the following points need to be noted:

[0244] (1) In the accompanying drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures may refer to the general design.

[0245] (2) Without conflict, the features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0246] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A chip verification method, comprising: Acquire a chip model of the chip, wherein the chip model includes a physical layer interface and a functional model; Writing an expected offset for simulating the timing offset during the access operation between the physical layer interface and the functional model into the chip model, so that the physical layer interface trains the timing of the access operation between the physical layer interface and the functional model based on the expected offset; In response to completion of the training of the chip model, obtaining an operation offset of the physical layer interface for compensation obtained based on the training; An offset adjustment capability of the physical layer interface is determined based on the operating offset and the expected offset.

2. The chip verification method according to claim 1, wherein: The step of writing the expected offset used to simulate the timing offset during the access operation between the physical layer interface and the functional model into the chip model comprises: The expected offset is written into a target register in the chip model to be read by the physical layer interface for the training.

3. The chip verification method according to claim 1 or 2, wherein: The enabling the physical layer interface to train the timing of access operations performed between the physical layer interface and the functional model based on the expected offset comprises: In response to the start of training of the chip model, the physical layer interface is enabled to obtain the expected offset written into the chip model and use the expected offset as the current offset between the physical layer interface and the functional model to perform the training.

4. The chip verification method according to claim 3, wherein: Before starting the training of the chip model, the chip verification method further includes: The training mode of the chip model is configured so that the chip model is trained under the set working mode.

5. The chip verification method according to claim 3, wherein: Before starting the training of the chip model, the chip verification method includes: The operating frequency of the chip model is configured to determine the expected offset according to the set operating frequency.

6. The chip verification method according to claim 5, wherein: The functional model includes a plurality of storage particle models; before starting the training of the chip model, the chip verification method further includes: According to the set particle encoding rule and the encoding requirement of the physical layer interface, the encoding of each storage particle model in the functional model is obtained; According to the encoding of each storage particle model in the functional model and the set working frequency, the expected offset corresponding to each storage particle model in the functional model is determined.

7. The chip verification method according to claim 6, wherein: The expected offset includes an expected offset value and an expected offset direction, and determining the expected offset corresponding to each stored particle model in the functional model includes: Determining a predetermined offset range corresponding to the set operating frequency according to a storage standard protocol supported by the functional model; The expected offset value and the expected offset direction of each stored particle model in the functional model are determined according to the predetermined offset range.

8. The chip verification method according to claim 7, wherein: The step of determining the expected offset value and the expected offset direction of each stored particle model in the functional model according to the predetermined offset range comprises: Get the offset reference value; In response to the start of training of the chip model, the expected offset value and the expected offset direction of each storage particle model in the functional model are determined according to the offset reference value and the predetermined offset range.

9. The chip verification method according to claim 7, wherein: The step of causing the physical layer interface to obtain the expected offset written into the chip model and using the expected offset as the current offset between the physical layer interface and the functional model for training comprises: The operation offset is obtained according to the offset reference value and the absolute value of the offset value of the expected offset acquired by the physical layer interface.

10. The chip verification method according to claim 7, wherein the step of writing the expected offset into a target register in the chip model comprises: According to the expected offset, for each storage particle model in the functional model, the corresponding expected offset value and the expected offset direction are respectively stored in a target register corresponding to each storage particle model.

11. The chip verification method according to claim 10, wherein the step of causing the physical layer interface to obtain the expected offset written into the chip model and using the expected offset as the current offset between the physical layer interface and the functional model for the training further comprises: The expected offset value and the expected offset direction stored in the target register corresponding to each storage particle model are respectively obtained according to the physical layer interface, so that the physical layer interface performs an offset calculation based on the obtained expected offset value and the obtained expected offset direction, and obtains the offset value of the operation offset for compensating the operation offset and the offset direction of the operation offset of each storage particle model.

12. The chip verification method according to claim 10, wherein determining the offset adjustment capability of the physical layer interface according to the operating offset and the expected offset comprises: Comparing the expected offset direction with the operational offset direction to determine whether the offset direction of the physical layer interface is correct; The expected offset value and the operational offset value are compared to determine an offset error value of the physical layer interface.

13. The chip verification method according to claim 12, wherein determining the offset adjustment capability of the physical layer interface according to the operating offset and the expected offset further comprises: In response to an offset direction error of the physical layer interface, determining that an internal logic or algorithm of the physical layer interface is erroneous; In response to the offset direction of the physical layer interface being correct, the offset error value of the physical layer interface is output.

14. The chip verification method according to claim 1, wherein: The training of the chip model includes: In response to the chip model being in a retraining state or a normal operating mode, an offset update instruction is sent to the physical layer interface to update the operating offset for compensation obtained based on the training into an offset register of the physical layer interface.

15. The chip verification method according to claim 1, wherein: The chip is a DDR chip, and the functional model is a DRAM model.

16. The chip verification method according to claim 1, wherein: Before starting the training of the chip model, the chip verification method further includes: Configure the accuracy mode of the chip model to configure the training step size of the training.

17. A chip verification device, wherein: The chip model corresponding to the chip includes a physical layer interface and a functional model, wherein the chip verification device includes: An expected offset module is configured to write an expected offset used to simulate the timing offset during the access operation between the physical layer interface and the functional model into the chip model, so that the physical layer interface trains the timing of the access operation between the physical layer interface and the functional model based on the expected offset; The checking module is configured to obtain the operation offset of the physical layer interface for compensation based on the training in response to the completion of the training of the chip model; and determine the offset adjustment capability of the physical layer interface according to the operation offset and the expected offset.

18. The chip authentication device according to claim 17, further comprising: The configuration module is configured to perform one or more of the following configurations: Configuring a training mode of the chip model so that the chip model is trained in a set working mode; Configuring the operating frequency of the chip model to determine the expected offset according to the set operating frequency; Configuring the precision mode of the chip model to configure the training step size of the training; The particle encoding rule of the chip model is configured so that each storage particle model in the functional model is encoded according to the set particle encoding rule.

19. An electronic device comprising: at least one memory configured to store computer-executable instructions; as well as at least one processor configured to execute the computer executable instructions, Wherein, when the computer executable instructions are executed by the at least one processor, the chip verification method according to any one of claims 1-16 is implemented.

20. A non-transitory storage medium that non-transitorily stores computer-executable instructions, wherein: When the computer executable instructions are executed by at least one processor, the chip verification method according to any one of claims 1-16 is implemented.

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