Defect analysis method, electronic device, storage medium and program product based on wafer image overlay

Abstract

The present application provides a defect analysis method, electronic device, storage medium and program product based on wafer image overlay. It relates to the field of image processing technology. The method includes: obtaining multiple wafer images; extracting calibration features on each wafer image; aligning the multiple wafer images based on the calibration features to obtain multiple aligned wafer images; superimposing the multiple aligned wafer images according to preset superposition rules to obtain a superimposed image; extracting defect features on the superimposed image; analyzing the defect features in combination with the status information of each component in the production process during operation to obtain the factors that cause the defects. The present application performs wafer image overlay processing and performs defect analysis based on the superimposed images. It can accurately locate the factors that cause defects, and can also statistically analyze the frequency and distribution of defects, thereby improving the reliability of defect detection results.

Description

Technical Field

[0001] The present application relates to the field of image processing technology, and in particular to a defect analysis method based on wafer image overlay, an electronic device, a storage medium, and a program product. Background Art

[0002] In the field of industrial manufacturing, for example, in the process of wafer generation, the process is complex. In order to ensure production quality, wafer images need to be collected at multiple nodes during the production process to provide data for subsequent defect detection.

[0003] The purpose of defect analysis is to identify and locate the cause of product defects by mining and analyzing product defect information and other production information. Specifically, the process where the defect occurs, as well as the specific equipment, raw materials, process parameters, production personnel, and other production factors, can be located.

[0004] Currently, defect analysis relies on manual comparison of multiple images to determine the root cause of defects. This manual analysis method relies on human experience, which, if insufficient, makes it difficult to accurately determine the cause of the defect. Furthermore, humans can only compare and analyze features of general areas based on intuition, which lacks precision. When there are tens of thousands of images, it is difficult for humans to conduct a comprehensive comparison and analysis, and some defect information may be overlooked, resulting in inaccurate defect analysis. Summary of the Invention

[0005] The purpose of the embodiments of the present application is to provide a defect analysis method, electronic device, storage medium and program product based on wafer image overlay, so as to improve the accuracy of defect analysis.

[0006] In a first aspect, an embodiment of the present application provides a defect analysis method based on wafer image overlay, comprising:

[0007] Obtaining multiple wafer images; the multiple wafer images are images corresponding to the same wafer in different production processes, or images of different wafers in the same production process;

[0008] Extracting calibration features on each wafer image. Calibration features are features used for positioning when aligning multiple wafer images.

[0009] Aligning the multiple wafer images based on the calibration features to obtain the aligned multiple wafer images;

[0010] According to a preset superposition rule, the aligned multiple wafer images are superimposed to obtain a superimposed image;

[0011] Extract defect features on the superimposed image;

[0012] According to the defect characteristics, combined with the status information of each component in the production process during operation, the factors causing the defect are analyzed.

[0013] In the embodiments of the present application, because different production processes may introduce different types of defects, images of the same wafer from different production processes are overlaid, and defect analysis is then performed based on the overlaid images. This allows for more accurate identification of the specific process link where the defect occurred, and thus, precise location of the defect source. Furthermore, by overlaying and analyzing images of different wafers from the same production process, the frequency and distribution of defects can be statistically analyzed, reducing the probability of misjudgment due to accidental factors on a single wafer and improving the reliability of defect detection results.

[0014] In a possible implementation of the first aspect, the wafer image is an AOI image; the wafer image defect information includes a defect type and a defect location; the overlay image includes a first single-defect overlay image; and the method includes overlaying the aligned multiple wafer images according to a preset overlay rule to obtain the overlay image, including:

[0015] Based on the defect type, a defect image containing a single defect type is extracted from the wafer image;

[0016] For defect images of the same defect type, count the number of first defect images with defects at the same pixel position;

[0017] A first single-defect superimposed image is generated according to the number of first defect images.

[0018] The embodiment of the present application extracts defect images containing a single defect type from wafer images based on the defect type, so that subsequent defect analysis can focus on a specific type of defect and can clearly reflect the frequency of a certain defect occurring at each pixel position, providing data support for accurately locating high defect risk areas.

[0019] In a possible implementation of the first aspect, the superimposed image further includes a multi-defect superimposed image, and the method further includes:

[0020] The number of second defect images of the first target defect type at the same pixel position in the first single-defect overlay image is counted, and a multi-defect overlay image is generated based on the number of second defect images; wherein the first target defect type is all defect types or some defect types selected from all defect types.

[0021] When superimposing images of a single defect, the embodiment of the present application can more accurately quantify the severity of the defect by counting the number of second defect images with the first target defect type at the same pixel position.

[0022] In a possible implementation of the first aspect, generating a first single-defect superimposed image according to the number of first defect images includes:

[0023] Determining a color parameter corresponding to each pixel position according to the number of first defect images corresponding to each pixel position;

[0024] A first single defect overlay image is generated based on color parameter rendering.

[0025] The embodiment of the present application is based on the number of images with defects at each pixel position and is rendered with corresponding colors, so that the defect distribution of the first single-defect superimposed image is displayed more intuitively.

[0026] In a possible implementation of the first aspect, the wafer image is an AOI image; the wafer image defect information includes a defect type and a defect location; the overlay image includes a second single-defect overlay image; and the aligned multiple wafer images are overlaid according to a preset overlay rule to obtain the overlay image, including:

[0027] Based on the defect type, a defect image containing a single defect type is extracted from the wafer image;

[0028] Gridding the defect image corresponding to each defect type to obtain multiple grid images;

[0029] For each defect type, count the number of defective chips in each grid image of the corresponding defect image;

[0030] Based on the statistically obtained number of defective chips contained in each grid image, the overlay value corresponding to the grid image at the same position in multiple defect images of the same defect type is calculated according to a preset overlay algorithm, and a second single defect overlay image is generated based on the overlay value.

[0031] In a possible implementation of the first aspect, the superimposed image further includes a second multi-defect superimposed image, and the method further includes:

[0032] The number of chips with the second target defect type on the same grid image in the second single-defect overlay image is counted, and a second multi-defect overlay image is generated based on the number of chips; wherein the second target defect type is all defect types or some defect types selected from all defect types.

[0033] This embodiment of the application counts the number of defective chips in each grid image, quantifying the number of defects and facilitating comparison of defect densities in different regions. The second single-defect overlay images corresponding to the second target defect type are then superimposed to obtain a final overlay image. This allows for simultaneous observation of the distribution of multiple defect types across the wafer, facilitating analysis of whether there are correlations between different defect types.

[0034] In a possible implementation of the first aspect, the image type of the wafer image is a mapping image; the wafer image is generated based on a target measurement parameter value of each pixel point of the wafer; and a stacking operation is performed on the aligned multiple wafer images according to a preset stacking rule to obtain a stacked image, including:

[0035] Superimposing and calculating the target measurement parameter values at the same pixel position in the plurality of wafer images according to a preset superposition algorithm to obtain a first superposition parameter value; the preset superposition algorithm includes summing, averaging, variance, and standard deviation;

[0036] An overlay image is generated according to the first overlay parameter value.

[0037] The embodiment of the present application obtains a first superposition parameter value by superimposing and calculating multiple wafer mapping images generated based on the target measurement parameter value at each pixel point position according to a preset superposition algorithm, thereby achieving accurate quantification of the target measurement parameter value. The generated superposition image can intuitively display the overall distribution and changes of the wafer measurement parameters.

[0038] In a possible implementation of the first aspect, the image type of the wafer image is a mapping image; the wafer image is generated based on a target measurement parameter value of each pixel point of the wafer; and a stacking operation is performed on the aligned multiple wafer images according to a preset stacking rule to obtain a stacked image, including:

[0039] Dividing each wafer image into a grid to obtain a plurality of second grid images corresponding to each wafer image;

[0040] Calculating the mean of the target measurement parameter values in each second grid image to obtain the parameter mean corresponding to each second grid image;

[0041] According to a preset superposition algorithm, the parameter mean values of the second grid images at the same position of the multiple wafer images are superimposed and calculated to obtain a second superposition parameter value;

[0042] An overlay image is generated according to the second overlay parameter value.

[0043] In the embodiment of the present application, after the wafer image is divided into grids, the target measurement parameter value in each second grid image is calculated as a mean value to represent the parameter level of the grid. On the one hand, the defect conditions of each grid area of the wafer can be obtained, and on the other hand, the amount of data processing is reduced.

[0044] In a possible implementation of the first aspect, the superposition rule includes:

[0045] Parameters involved in the overlay operation in the wafer image;

[0046] The preset overlay algorithm corresponding to the overlay operation;

[0047] Rendering rules for overlay images.

[0048] The embodiment of the present application sets overlay rules so that, for different analysis purposes and data characteristics, image overlay is performed according to preset overlay rules, and the parameter selection, overlay algorithm and rendering rules involved in the overlay operation are clarified, so that the entire overlay process is highly targeted and presented to the staff more clearly and intuitively.

[0049] In a possible implementation of the first aspect, before overlaying the aligned multiple wafer images according to a preset overlay rule, the method further includes:

[0050] If the wafer image contains a linear defect, a linear defect image is intercepted from the wafer image according to the position of the linear defect;

[0051] Extracting the skeleton of the linear defect according to the linear defect image to obtain a skeleton image;

[0052] Accordingly, the aligned multiple wafer images are superimposed according to the preset superposition rules, including:

[0053] According to the preset superposition rules, the skeleton image is superimposed.

[0054] In an embodiment of the present application, after superimposing multiple defective wafer images, the defects may cover the entire wafer image, making it difficult to analyze information such as the defect location and direction. Therefore, before superimposing, the skeleton of the defect in each wafer image can be extracted to obtain a skeleton image containing the defect skeleton, and then the skeleton images can be superimposed to facilitate subsequent analysis of the defects.

[0055] In a possible implementation of the first aspect, factors causing the defect are obtained by analyzing the defect characteristics in combination with status information of each component during operation in the production process, including:

[0056] According to the defect characteristics, combined with the status information of each component in the production process during operation, analysis is performed to obtain the process information and component information that cause the defect.

[0057] In the embodiment of the present application, the presence of defects on a single wafer image and the location of the defects are accidental. By superimposing multiple wafer images, the distribution of defects becomes dense, and then the defect features can be extracted, and the causes of the defects can be analyzed based on the defect features.

[0058] In one possible implementation of the first aspect, the defect characteristics include distribution characteristics of needle mark defects. Analysis is performed based on the defect characteristics in combination with status information of each component during operation in the production process, including:

[0059] The minimum spacing of the needle marks in the superimposed image is obtained based on the distribution characteristics of the needle mark defects. The needle mark defects are caused by abnormal working conditions of the probes during the wafer production process.

[0060] The process information and probe information that cause the needle mark defect are determined based on the minimum spacing and the actual spacing of the probes in each production process.

[0061] In an embodiment of the present application, since the actual spacing of the probes corresponding to different production processes is different, after superimposing multiple wafer images, the minimum spacing of the needle marks in the wafer image can be found. Based on the minimum spacing, the production process information and probe information that cause the needle mark defect can be quickly located, which facilitates subsequent maintenance.

[0062] In a possible implementation of the first aspect, superimposing the aligned multiple wafer images according to a preset superposition rule to obtain a superimposed image includes:

[0063] In the case where multiple wafer images are images of the same wafer at different processes, the wafer image corresponding to the current process is superimposed with the wafer image before the current process to obtain a process superimposed image corresponding to the current process;

[0064] Based on the defect characteristics and combined with the status information of each component in the production process, the factors causing the defect are analyzed, including:

[0065] Calculate the difference between the process superposition images corresponding to adjacent processes;

[0066] Determine the process information of the defect occurrence based on the difference, and / or determine the evolution information of the defect along the production process.

[0067] In this embodiment of the present application, by superimposing the wafer image corresponding to the current process with the previous wafer image and calculating the difference between the superimposed process images corresponding to adjacent processes, the impact of the current process on the wafer can be clearly observed. If new defect features appear in the superimposed image, it can be accurately determined that these defects were caused by the current process.

[0068] In a second aspect, an embodiment of the present application provides a defect analysis device based on wafer image overlay, comprising:

[0069] An image acquisition module is used to obtain multiple wafer images; the multiple wafer images are images corresponding to the same wafer in different production processes, or images of different wafers in the same production process;

[0070] A feature extraction module is used to extract calibration features on each wafer image. Calibration features are features used for positioning when aligning multiple wafer images.

[0071] An image alignment module is used to align multiple wafer images based on calibration features to obtain multiple aligned wafer images;

[0072] An image overlay module is used to overlay the aligned multiple wafer images according to a preset overlay rule to obtain an overlay image;

[0073] A defect feature extraction module, used to extract defect features on the superimposed image;

[0074] The defect analysis module is used to analyze the defect characteristics in combination with the status information of each component in the production process during the operation to obtain the factors that cause the defect.

[0075] In a third aspect, an embodiment of the present application provides an electronic device, including: a processor, a memory, and a bus, wherein:

[0076] The processor and memory communicate with each other through the bus;

[0077] The memory stores program instructions that can be executed by the processor, and the processor calls the program instructions to execute the method of the first aspect.

[0078] In a fourth aspect, an embodiment of the present application provides a non-transitory computer-readable storage medium, comprising:

[0079] The non-transitory computer-readable storage medium stores computer instructions, which enable a computer to execute the method in each possible implementation manner of the first aspect.

[0080] In a fifth aspect, an embodiment of the present application provides a computer program product, comprising computer program instructions, which, when read and executed by a processor, execute the methods in each possible implementation of the first aspect.

[0081] By aligning each wafer image before overlaying it for analysis, the present embodiment completes the correlation analysis of all defects on the image at once, reducing complexity. Furthermore, the use of multiple colors to distinguish the number of defects after overlaying is more intuitive, considering not only the correlation of a single type of defect but also the unified correlation of all defects. When image resolutions vary, grid division and then overlaying can be used to uniformly consider the data within each grid, making defect analysis more effective and better assisting personnel in defect analysis.

[0082] Other features and advantages of the present application will be described in the following description and, in part, will become apparent from the description or be understood by practicing the embodiments of the present application. The objectives and other advantages of the present application can be achieved and obtained through the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0084] Figure 1 A schematic flow chart of a defect analysis method based on wafer image overlay provided in an embodiment of the present application;

[0085] Figure 2 A schematic diagram of a wafer image provided in an embodiment of the present application;

[0086] Figure 3 An example diagram of grid division provided in an embodiment of the present application;

[0087] Figure 4 This is an example of a mapping image provided in the embodiments of the present application;

[0088] Figure 5 Three defect area maps provided for the embodiments of this application;

[0089] Figure 6 Three skeleton diagrams provided for the embodiments of this application;

[0090] Figure 7A schematic diagram of a direct overlay provided in an embodiment of the present application;

[0091] Figure 8 A schematic diagram of the skeleton image superimposed according to an embodiment of the present application;

[0092] Figure 9 Three schematic diagrams of needle mark defects provided in the embodiments of this application;

[0093] Figure 10 A schematic diagram of superimposing multiple wafer images provided in an embodiment of the present application;

[0094] Figure 11 A schematic structural diagram of a defect analysis device based on wafer image overlay provided in an embodiment of the present application;

[0095] Figure 12 A schematic diagram of the physical structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0096] The following embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application and are therefore only examples and are not intended to limit the scope of protection of the present application.

[0097] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.

[0098] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0099] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0100] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0101] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0102] In the description of the embodiments of the present application, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components or interactions between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application based on specific circumstances.

[0103] In advanced manufacturing fields such as photovoltaics and semiconductor chips, low product yield is a major factor limiting profits and hindering business development. The manufacturing process is long and complex, and defects can occur at every stage of the process, from raw materials to intermediate products to the final product. The accumulation of defects at each stage leads to a low final yield. Product defects can arise from two sources: accidental factors and abnormal factors. Accidental factors are inherent, always present, have a minor impact on quality, but are difficult to eliminate. Abnormal factors, on the other hand, appear and disappear, have a greater impact on quality, and are easily eliminated. Abnormal factors often cause batch-wide quality issues.

[0104] The goal of defect analysis is to identify and locate the causes of product defects by mining and analyzing product defect information and other production data. Specifically, the process, equipment, raw materials, process parameters, and other production factors that cause the defect can be located. This allows for subsequent maintenance based on the cause of the defect, improving product yield.

[0105] Wafer production requires multiple production processes, each of which may produce defects. To perform quality inspections on the production process, an image acquisition device can be set up during the production process to capture wafer images after the production process is completed. Due to the large number of production processes, many wafer images will be obtained after a wafer is produced. In addition, the production line will produce continuously, so a large number of wafer images will be generated in each production process. When the number and type of wafer defects are large, manual analysis based on experience is inefficient and prone to overlooking key points, resulting in low accuracy.

[0106] To address the aforementioned technical issues, embodiments of the present application provide a defect analysis method based on wafer image overlay. Before defect analysis, multiple images are overlaid according to preset overlay rules to obtain an overlaid image. Wafer defect analysis is then performed based on this overlaid image. By analyzing defect overlay images, correlations between defects can be identified, facilitating the identification and timely troubleshooting of defects that frequently occur in the same location.

[0107] Figure 1 A schematic flow chart of a defect analysis method based on wafer image overlay provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the method includes:

[0108] Step 101: obtaining a plurality of wafer images; the plurality of wafer images are images corresponding to the same wafer in different production processes, or images of different wafers in the same production process;

[0109] Step 102: extracting calibration features on each wafer image, where the calibration features are features used for positioning when aligning multiple wafer images;

[0110] Step 103: aligning the multiple wafer images based on the calibration features to obtain multiple aligned wafer images;

[0111] Step 104: superimposing the aligned multiple wafer images according to a preset superposition rule to obtain a superimposed image;

[0112] Step 105: extracting defect features on the superimposed image;

[0113] Step 106: Analyze the defect characteristics in combination with the status information of each component during the production process to obtain the factors that cause the defect.

[0114] In step 101, the wafer undergoes multiple production processes, such as oxidation, photolithography, etching, doping, and metallization. After each key process is completed, the wafer is imaged using optical inspection equipment (e.g., an optical microscope, scanning electron microscope, etc.) to obtain an image of the wafer during that process. For example, after the photolithography process, an image of the wafer surface is taken to observe the formation of the photolithographic pattern; after the etching process, the wafer image is taken again to check the depth and shape of the etching.

[0115] Due to various factors in the wafer manufacturing process (such as raw material differences, equipment fluctuations, and process parameter changes), differences may exist between different wafers. By analyzing images of the same process across multiple wafers, we can assess the stability and consistency of that process across different wafers and promptly identify potential batch-to-batch quality issues.

[0116] In step 102, calibration features are used to align multiple wafer images. Typically, these are patterns or marks on the wafer that have distinct positional features and remain relatively stable across different process steps. For example, within the chip arrangement pattern on the wafer, a chip corner, center point, or specific alignment mark (such as an alignment mark or overlay mark) can be selected as calibration features. These calibration features have clear boundaries and easily recognizable shapes in the wafer images, facilitating subsequent image alignment operations.

[0117] Figure 2 A schematic diagram of a wafer image provided in an embodiment of the present application is shown as follows: Figure 2 As shown in the figure, there is a flat edge on each wafer image, so the flat edge can be used as a calibration feature. There are also depressions on both sides of the flat edge, and the flat edge and the two depressions can also be used as calibration features. These calibration features have clear boundaries and easily recognizable shapes in the wafer image, which facilitates subsequent image alignment operations. In addition, Figure 2 2 squares and 5 dots are also shown in FIG. , which are calibration points on the wafer image. These calibration points can also be used as calibration features for subsequent alignment. Figure 2 The calibration features shown above are only examples. In practice, the number and position of the squares and dots can be set on the wafer according to actual conditions, and this embodiment of the application does not specifically limit this. Furthermore, wafer image alignment can also be performed based on only squares or only dots.

[0118] Image processing algorithms can be used to extract calibration features from wafer images. These algorithms can include edge detection algorithms (such as the Canny edge detection algorithm), corner detection algorithms (such as the Harris corner detection algorithm), and template matching algorithms. These algorithms can accurately locate the position of calibration features in wafer images, providing precise reference points for subsequent image alignment.

[0119] Furthermore, image acquisition devices used in different production processes may employ different acquisition accuracies, resulting in different resolutions on wafer images. Therefore, image resolution must be standardized. For example, adjacent data from the high-resolution image can be merged based on the coordinate granularity of the low-resolution image (this can be done by taking the average or the minimum value based on business needs) to achieve the same resolution as the high-resolution image. Alternatively, the low-resolution image can be adjusted to the same resolution as the high-resolution image through interpolation or other methods, and then image alignment can be performed.

[0120] It should be noted that if the wafer image is an AOI image, the wafer image may be preprocessed before alignment, wherein the specific preprocessing operations include at least one of the following:

[0121] (1) Convert the wafer image into a grayscale image;

[0122] (2) Use the threshold segmentation algorithm to binarize the grayscale image;

[0123] (3) Image inversion;

[0124] (4) Perform closing operation on the AOI image;

[0125] (5) Find the maximum value of the minimum bounding rectangle after binarization.

[0126] For example, you can select (1), (2), and (5) from the preprocessing operations listed above for preprocessing, or you can perform (1), (2), (4), and (5) preprocessing on the wafer image.

[0127] During alignment, the four corner points of the smallest bounding rectangle can be found, and the largest circular outline area in the original image can be perspectively projected onto a rectangular area of a fixed size. The perspective width and height are the width and height of the largest circular outline area in the original image. After perspective, the circular outline areas of all AOI images are aligned to the same-sized rectangular area, and the flat edges are also aligned.

[0128] In step 103, the image acquisition equipment for the same process may be offset due to external factors, making it impossible for multiple wafer images captured by the same image acquisition equipment to completely overlap. Image acquisition equipment for different processes may have different device parameters, resulting in different information such as image resolution. This makes it impossible to directly overlay the multiple wafer images. The multiple wafer images must first be aligned and then overlaid.

[0129] Based on the extracted calibration features, a spatial correspondence is established between the multiple wafer images. Specifically, by calculating geometric transformations (such as translation, rotation, and scaling) between the calibration features in different images, the multiple wafer images are spatially aligned. For example, if one wafer image is translated and / or rotated relative to another, alignment can be used to reconcile the translated and / or rotated image with the other wafer images.

[0130] When aligning multiple wafer images based on calibration features, a suitable alignment algorithm can be used. For example, a matching-based alignment algorithm can be used, which matches calibration features between different images and then determines the geometric transformation relationship. Alignment algorithms based on image content similarity, or first positioning using the Hough transform and then aligning using perspective alignment can also be used.

[0131] In step 104, multiple superposition rules may be pre-set according to different analysis requirements. The superposition rules may include:

[0132] (1) Parameters involved in the overlay operation in the wafer image;

[0133] Different overlay rules can be set for different overlay operation parameters. The parameters involved in the overlay operation can refer to the measurement parameters of the mapping image involved in the overlay, or they can refer to the defect type in the AOI image. The defect type can include multiple types of defects in the wafer image. By setting the overlay rule, the defect type involved in the overlay can be determined. The measurement parameter refers to the wafer image composed of a measurement parameter in the wafer mapping data, and the wafer image is overlaid.

[0134] (2) a preset superposition algorithm corresponding to the superposition operation;

[0135] Overlay algorithms can include summation, averaging, variance calculation, and standard deviation calculation. The summation algorithm can be used to calculate the cumulative effect of defects across multiple wafer images. The averaging algorithm can affect the average defect level. The variance and standard deviation algorithms can assess the degree of discreteness and stability of defects. For example, to understand the overall distribution of defects on a wafer surface after a certain production process, the averaging algorithm can be used to perform overlay operations, resulting in an overlay image reflecting the average defect count distribution.

[0136] (3) Rendering rules for superimposed images;

[0137] The rendering rule refers to the correspondence between the number of defects and the color rendered into the superimposed image.

[0138] It should be understood that during actual superposition, any one or more of the above superposition rules may be used. For example, parameters and superposition algorithms may be selected for superposition operations without color rendering, or all three of the above rules may be used.

[0139] When superimposing multiple wafer images, wafer images of the same wafer under different production processes can be superimposed one by one in sequence according to the order of the production processes. Wafer images of different wafers under the same production process can be superimposed one by one in sequence according to the order in which the wafers are completed under the production process. All wafer images involved in the superposition can also be superimposed at one time. Moreover, when superimposing wafer images, only a certain type of defect on the wafer image can be superimposed. Therefore, the superimposed image obtained by superimposing the wafer images can be a single defect superimposed image; it can also be superimposed for certain types of defects on the wafer image, or all defects on the wafer image can be superimposed. In this case, the superimposed image obtained is a multi-defect superimposed image. It is understandable that when superimposing images, a single defect can be superimposed first to obtain a single defect superimposed image, and then the single defect superimposed image can be superimposed again to obtain a multi-defect superimposed image. Therefore, the superimposed image can include a single defect superimposed image and a multi-defect superimposed image.

[0140] In step 105, after obtaining the overlay image, it can be analyzed. Because the overlay image integrates information from multiple wafer images, the defective area will appear in the overlay image as a feature that is significantly different from the surrounding normal areas. Therefore, defect features can be extracted from the overlay image. For example, if the color or grayscale value of a certain area in the overlay image is significantly different from the surrounding area, it indicates that this area may have a defect. In addition, based on the coordinate information in the overlay image, the position of the defect on the wafer image can be located, providing data for subsequent analysis of the cause of the defect.

[0141] When analyzing wafer defects, the defect type can also be determined. Specifically, defects can be classified based on their appearance in the overlay image. For example, based on characteristics such as shape, size, and distribution, defects can be categorized as particle contamination, scratches, pattern loss, pattern shorts, and hidden cracks. Furthermore, by analyzing the defect area in the overlay image, the severity of the defect can be assessed. For example, parameters such as the area, depth, and height of the defect area can be calculated and compared with pre-set defect tolerances to determine whether the defect will affect wafer performance and quality.

[0142] In step 106, the factors causing defects are analyzed by combining the operating status information of various components in the production process (such as process parameters, equipment status, and raw material quality). By analyzing the distribution and evolution trends of defects in the superimposed image, the key processes or factors that lead to defects can be identified. For example, if scratch defects on the wafer surface increase significantly after a certain process, in-depth analysis can be conducted on the process parameters (such as etching depth, photoresist coating uniformity, etc.) and equipment operating conditions (such as tool wear and conveyor vibration) of that process. Targeted optimization measures can be taken, such as adjusting process parameters and improving equipment maintenance plans, to reduce defects and improve wafer yield.

[0143] In the embodiments of the present application, because different production processes may introduce different types of defects, images of the same wafer from different production processes are overlaid, and defect analysis is then performed based on the overlaid images. This allows for more accurate identification of the specific process link where the defect occurred, and thus, precise location of the defect source. Furthermore, by overlaying and analyzing images of different wafers from the same production process, the frequency and distribution of defects can be statistically analyzed, reducing the probability of misjudgment due to accidental factors on a single wafer and improving the reliability of defect detection results.

[0144] Based on the above embodiment, the image type of the wafer image may include an AOI image and a mapping image. When the image type of the wafer image is an AOI image, the wafer image includes defect information, and the defect information includes a defect type and a defect location. The overlay image includes a first single defect overlay image. According to a preset overlay rule, the aligned multiple wafer images are overlaid to obtain the overlay image, including:

[0145] Based on the defect type, a defect image containing a single defect type is extracted from the wafer image;

[0146] For defect images of the same defect type, the number of first defect images with defects at the same pixel position is counted, and a first single-defect superimposed image is generated according to the number of first defect images.

[0147] In practice, automated optical inspection (AOI) technology plays a key role in wafer inspection. Using high-resolution cameras, AOI systems scan and image the wafer surface, capturing subtle defect features. These features are then processed using image processing and analysis algorithms to identify and classify them into different defect types, such as scratches, cracks, and cut lines.

[0148] Before overlaying, each wafer image can be pre-determined for defect detection to determine whether each pixel in the wafer image contains a defect. If so, the defect type is further determined. While a wafer image may contain multiple defect types, a pixel may only contain one defect type.

[0149] For single-defect overlays, for example, to overlay a pin mark defect, the pin mark defects can be extracted from multiple wafer images to create a defect image containing only the pin mark defect. This can also be understood as removing all defects from the wafer images except the pin mark defect. It is understood that if some wafer images do not contain pin mark defects, these wafer images will not be included in the subsequent overlay process.

[0150] After obtaining defect images containing a single defect type, when overlaying the images, the number of first defect images containing defects at the same pixel location in the multiple defect images can be counted, and the counted number of first defect images can be stored at the corresponding pixel location to obtain a first single-defect overlay image. It will be understood that the overlay method described above can be used for each defect type to obtain a single defect overlay image of the corresponding defect type, i.e., an overlay image.

[0151] It should be noted that before extracting defect images containing a single defect type, the color space of the aligned AOI image can be converted from RGB to HSV. This is because in the RGB color space, color is determined by the three channels R, G, and B. In the HSV space, color is determined solely by the H channel, where S represents saturation and V represents brightness. Therefore, converting to the HSV color space makes it easier for back-end developers to set colors.

[0152] Based on the above embodiment, the superimposed image further includes a first multi-defect superimposed image. After obtaining a single defect superimposed image, single defect superimposed images corresponding to some or all defect types can be selected from multiple defect types for re-superimposition. The superimposition method is similar to the superimposition method for single defect types. That is, the number of second defect images with defects at the same pixel position in the first single defect superimposed images corresponding to multiple defect types is counted, and defect parameters corresponding to each pixel position are obtained according to a preset superimposition algorithm (e.g., summation). The first multi-defect superimposed image is generated based on the defect parameters.

[0153] In another embodiment, when overlaying images of multiple defect types, it is also possible to directly overlay the obtained wafer image containing multiple defect types without overlaying the first single defect overlay image. The specific operation method is as follows:

[0154] Extract multiple defect types that are to be involved in subsequent superposition from the obtained wafer image to obtain a wafer image with multiple defect types, or remove defect types that are not required to be involved in subsequent superposition from the obtained wafer image to obtain a wafer image with multiple defect types. It is understandable that the multiple defect types involved in subsequent superposition can be all defect types contained in the wafer image, or multiple defect types selected from all defect types. The specific setting can be based on actual needs, and the embodiment of the present application does not specifically limit this. If a wafer image does not contain any defect type that is to be involved in subsequent superposition, the wafer image is removed and does not participate in subsequent superposition. In addition, the obtained multi-defect type image may contain all defect types in the third target defect type, may also contain some defect types in the third target defect type, or may only contain one defect in the third target defect type. For example: for wafer image 1, it contains defect types A, defect B, defect C, defect D and defect E; the defect types contained in wafer image 2 are defect A, defect B and defect C; the defect types contained in wafer image 3 are defect C, defect D and defect E. Assuming that the third target defect type includes defect A, defect B and defect C, then the multi-defect type image obtained after defect extraction on wafer image 1 contains defect A, defect B and defect C; the multi-defect type image obtained after defect extraction on wafer image 2 contains defect B and defect C; and the multi-defect type image obtained after defect extraction on wafer image 3 contains defect C.

[0155] After obtaining the multi-defect type images, the multiple multi-defect type images are superimposed. Specifically, the number of defects at the same pixel position in the multiple multi-defect type wafer images is counted, and the number of defects is stored at the pixel position to obtain a superimposed image. Color rendering can also be performed according to the number of defects to obtain a superimposed image.

[0156] This embodiment of the application extracts defect images containing a single defect type from wafer images based on defect type, allowing subsequent defect analysis to focus on specific defects and clearly reflecting the frequency of a particular defect at each pixel location, providing data support for accurately locating high-defect risk areas. Furthermore, by comprehensively overlaying multiple defect types, correlations between different defect types can be discovered.

[0157] On the basis of the above embodiment, generating a first single defect superimposed image according to the number of first defect images includes:

[0158] Determining a color parameter corresponding to each pixel position according to the number of first defect images corresponding to each pixel position;

[0159] A first single defect overlay image is generated based on color parameter rendering.

[0160] In a specific implementation process, after obtaining the first single defect superimposed image, in order to more intuitively display the distribution of defects, a correspondence between the number of first defect images at each pixel position and the rendering color may be established.

[0161] Color models can include the RGB (Red, Green, Blue) model and the HSV (Hue, Saturation, and Transparency) model. For example, the RGB model allows various colors to be represented using different combinations of red, green, and blue channels. For the first single-defect overlay image, a uniform color scheme (e.g., red) can be used to represent the correspondence between the number of first defect images at each pixel location and their color. For example, lighter red indicates fewer first defect images at the corresponding pixel location, while darker red indicates more first defect images at the corresponding pixel location. Of course, different color schemes can also be used to represent the correspondence between the number of first defect images at each pixel location and their color. For example, when the number of first defect images is small, the corresponding color is light blue (RGB value (0, 191, 255)); when the number is moderate, it corresponds to green (RGB value (0, 255, 0)); when the number is large, it corresponds to yellow (RGB value (255, 255, 0)); and when the number is very large, it corresponds to red (RGB value (255, 0, 0)). This mapping rule can intuitively reflect the frequency of defects. The greater the number, the more eye-catching the color.

[0162] Alternatively, a grayscale image can be used for color rendering, establishing a correspondence between the grayscale value and the number of first defect images. For example, a smaller grayscale value indicates a greater number of first defect images at the corresponding pixel location, while a larger grayscale value indicates a smaller number of first defect images at the corresponding pixel location. Alternatively, a larger grayscale value indicates a greater number of first defect images at the corresponding pixel location, while a smaller grayscale value indicates a smaller number of first defect images at the corresponding pixel location.

[0163] Similarly, the superimposed image obtained by superimposing multiple defect type images can also be rendered using the above-mentioned similar color rendering method, which will not be described in detail here.

[0164] The embodiment of the present application is based on the number of images with defects at each pixel position and is rendered with corresponding colors, so that the defect distribution of the first single-defect superimposed image is displayed more intuitively.

[0165] Based on the above embodiment, the image type of the wafer image is an AOI image; the wafer image defect information includes the defect type and defect location; the overlay image includes a second single defect overlay image; and according to a preset overlay rule, the aligned multiple wafer images are overlaid to obtain the overlay image, including:

[0166] Based on the defect type, a defect image containing a single defect type is extracted from the wafer image;

[0167] Gridding the defect image corresponding to each defect type to obtain multiple grid images;

[0168] For each defect type, count the number of defective chips in each grid image of the corresponding defect image;

[0169] Based on the statistically obtained number of defective chips contained in each grid image, the overlay value corresponding to the grid image at the same position in multiple defect images of the same defect type is calculated according to a preset overlay algorithm, and a second single defect overlay image is generated based on the overlay value.

[0170] In a specific implementation, before overlaying, each wafer image can be pre-determined for defect detection to determine whether each pixel in the wafer image contains a defect. If a defect is present, the defect type is further determined. While a wafer image may contain multiple defect types, a pixel may only contain one defect type.

[0171] For single-defect overlays, for example, to overlay a pin mark defect, the pin mark defects can be extracted from multiple wafer images to create a defect image containing only the pin mark defect. This can also be understood as removing all defects from the wafer images except the pin mark defect. It is understood that if some wafer images do not contain pin mark defects, these wafer images will not be included in the subsequent overlay process.

[0172] After obtaining a defect image containing a single defect type, grid division can be performed according to a preset size. For example, the grid size can be 20 pixels or 30 pixels. Grid division can also be performed according to the chip size. For example, each grid can contain 5 chips or 10 chips, etc. The grid size can be set according to actual needs, and this embodiment of the present application does not make specific restrictions on this. In addition, the defect image can also be divided according to a preset number of grids. The number of grids can be set according to actual needs, and this embodiment of the present application does not make specific restrictions on this. In the grid image obtained after grid division, each grid can include multiple chips. It should be noted that the grid division method for each wafer image should be consistent. Figure 3 This is an example diagram of grid division provided in an embodiment of the present application. Figure 3The black dots in the wafer image are used to represent defect information. In practical applications, Figure 3 A color map can be used to represent the number of defects at the pixel location. Figure 3 The background grid in does not participate in the subsequent superposition calculation.

[0173] When overlaying grid images of a defect type, the number of defective chips in each grid can be counted. It should be noted that defective chips can be identified by determining whether a pixel at the chip's location contains a defect. If so, the chip can be determined to be a defective chip.

[0174] Based on the statistically determined number of defective chips in each grid image, a preset overlay algorithm is used to calculate the overlay value corresponding to the grid images at the same location across multiple defect images of the same defect type. Preset overlay algorithms can include summation, averaging, variance calculation, and standard deviation calculation. For example, if the averaging algorithm is selected, for multiple defect images of the same defect type (such as scratches), the average number of defective chips at each grid location is calculated as the overlay value for that grid location.

[0175] The overlay value can be stored as a defect attribute for the grid or represented using color. That is, a second single-defect overlay image is generated according to the set color rendering rules. Color coding can be used to assign different colors based on the overlay value. For example, areas with low overlay values are represented in green, indicating a small number of defective chips; areas with medium overlay values are represented in yellow, indicating a moderate number of defective chips; and areas with high overlay values are represented in red, indicating a large number of defective chips. In this way, the overlay value of each grid is converted into color information, and a second single-defect overlay image is drawn, visually demonstrating the distribution and severity of the same defect type across multiple wafer images.

[0176] In another embodiment, the overlay image may further include a second multi-defect overlay image. After obtaining the second single-defect overlay image, the second single-defect overlay images corresponding to the multiple defect types may be overlaid again. In this embodiment of the present application, the defect type selected for overlay is referred to as a second target defect type. The second curve target defect may be all defect types included in the multiple wafer images, or at least two defect types selected from all defect types.

[0177] When performing image superposition of multiple defect types, re-superposition can be performed based on the second single-defect superposition image that stores the superposition value. The superposition method is similar to the above-mentioned wafer image superposition method for a single defect, that is, the number of defective chips on the same grid in the second single-defect superposition image corresponding to the second target defect type is superimposed and calculated according to the preset superposition algorithm to obtain a second multi-defect superposition image.

[0178] The second single defect superposition images corresponding to the second target defect type are superimposed again to obtain a final superposition image. The second target defect type can be all defect types or some defect types selected from all defect types. For example, particle contamination and scratches are selected as the second target defect types, and their corresponding second single defect superposition images are superimposed again. During the superposition process, transparency superposition can be used so that the distribution of different defect types can be simultaneously presented in the final superposition image. The final superposition image can comprehensively display the distribution of multiple defect types on the entire wafer, providing comprehensive and intuitive visual information for wafer defect analysis, helping technicians quickly locate defect areas, analyze the causes and evolution of defects, and take corresponding measures to optimize production processes and improve wafer quality.

[0179] In another embodiment, when overlaying images of multiple defect types, it is also possible to directly overlay the obtained wafer image containing multiple defect types without overlaying the images based on the second single defect overlay image. The specific operation method is as follows:

[0180] Extract multiple defect types that will participate in subsequent superposition from the obtained wafer image to obtain a wafer image with multiple defect types, or remove defect types that do not need to participate in subsequent superposition from the obtained wafer image to obtain a wafer image with multiple defect types. It is understandable that if a certain wafer image does not contain any defect type that will participate in subsequent superposition, the wafer image will be removed and will not participate in subsequent superposition. Then, the wafer image with multiple defect types is grid-divided to obtain a grid image, and the multiple grid images with multiple defect types obtained are superimposed. Specifically, the number of defective chips contained in the same grid in the multiple wafer images with multiple defect types is counted, and the number of defective chips contained is stored in the grid as a defect attribute of the grid to obtain a superimposed image. Color rendering can also be performed according to the number of defects to obtain a superimposed image.

[0181] This embodiment of the application counts the number of defective chips in each grid image, quantifying the number of defects and facilitating comparison of defect densities in different regions. The second single-defect overlay images corresponding to the second target defect type are then superimposed to obtain a final overlay image. This allows for simultaneous observation of the distribution of multiple defect types across the wafer, facilitating analysis of whether there are correlations between different defect types.

[0182] On the basis of the above embodiment, when the image type of the wafer image is a mapping image; the wafer image is generated based on the target measurement parameter value of each pixel position of the wafer; according to the preset overlay rule, the aligned multiple wafer images are overlaid to obtain the overlaid image, including:

[0183] Superimposing and calculating the target measurement parameter values at the same pixel position in the plurality of wafer images according to a preset superposition algorithm to obtain a first superposition parameter value; the preset superposition algorithm includes summing, averaging, variance, and standard deviation;

[0184] An overlay image is generated according to the first overlay parameter value.

[0185] During the implementation, obtain a CSV data set for overlay mapping. This data set can contain anywhere from a few to several thousand data points, depending on the specific scenario. The CSV data set contains chip data, such as current and voltage data, obtained through measurement methods during the chip production process.

[0186] Based on the overlay requirements, the corresponding target measurement parameters are selected from the CSV data. The target measurement parameters corresponding to each pixel position in the CSV data set are extracted and plotted at the corresponding pixel position to obtain the mapping. Therefore, the mapping image is generated based on the target measurement parameter values of the wafer at each pixel position. Figure 4 This is an example of a mapping image provided in the embodiment of the present application. The black dots in the image are used to represent defect information. In practical applications, Figure 4 A color map may be used for representation, with different colors representing the number of defects at the pixel location.

[0187] After obtaining the mapping image, multiple mapping images are overlaid according to the preset overlay rules. The preset overlay algorithm includes various mathematical calculation methods, such as finding the mean, variance, and standard deviation.

[0188] The averaging algorithm calculates the average value of the target measurement parameter at the same pixel location across multiple wafer images. This method reflects the average physical parameter level at that location across multiple wafers, helping to understand the overall parameter distribution during wafer production and eliminate the impact of individual differences. For example, when analyzing the reflectivity of a batch of wafers, averaging can provide the average reflectivity at each location across the batch, which can be used to assess the stability of the production process.

[0189] Variance and Standard Deviation Algorithms: The variance and standard deviation are calculated to measure the dispersion of the target measurement parameter values. Larger variances and standard deviations indicate greater fluctuations in the physical parameters at the same pixel location across different wafers. This is crucial for assessing the uniformity and stability of the production process. For example, in wafer doping concentration control, a large variance in doping concentration in a specific area indicates instability in the doping process, necessitating process optimization.

[0190] The corresponding color can be rendered based on the first overlay parameter value at each pixel location, thereby obtaining an overlay image that uses different colors to represent the distribution of the first overlay parameter values. During rendering, a standard value for the target measurement parameter can be pre-set. The greater the deviation from the standard value, the darker the color used to represent it. Thus, the color in the overlay image can be used to identify abnormal locations on the wafer image.

[0191] The embodiment of the present application obtains a first superposition parameter value by superimposing and calculating multiple wafer mapping images generated based on the target measurement parameter value at each pixel point position according to a preset superposition algorithm, thereby achieving accurate quantification of the target measurement parameter value. The generated superposition image can intuitively display the overall distribution and changes of the wafer measurement parameters.

[0192] Based on the above embodiment, the image type of the wafer image is a mapping image; the wafer image is generated based on the target measurement parameter value of each pixel point of the wafer; according to the preset overlay rule, the aligned multiple wafer images are overlaid to obtain the overlaid image, including:

[0193] Dividing each wafer image into a grid to obtain a plurality of second grid images corresponding to each wafer image;

[0194] Calculating the mean of the target measurement parameter values in each second grid image to obtain the parameter mean corresponding to each second grid image;

[0195] According to a preset superposition algorithm, the parameter mean values of the second grid images at the same position of the multiple wafer images are superimposed and calculated to obtain a second superposition parameter value;

[0196] An overlay image is generated according to the second overlay parameter value.

[0197] In the specific implementation process, after obtaining the mapping image, it is divided into a grid based on the coordinate positions to obtain a second grid image. The grid size can be determined based on the requirements and the resolution of the wafer image. For example, a 2048×2048 pixel wafer image can be divided into 64×64 grids, with each grid image being 32×32 pixels in size.

[0198] The target measurement parameter values within each grid are averaged to obtain the parameter mean corresponding to each grid. According to the preset overlay rules, the parameters of multiple mapping images under the same grid are overlaid to obtain the second overlay parameter value of each grid object.

[0199] After obtaining the second overlay parameter value, the second overlay parameter value can be stored as an attribute of the corresponding grid under the grid to obtain an overlay image. Alternatively, the corresponding grid can be rendered with a corresponding color according to the second overlay parameter value to obtain an overlay image.

[0200] In the embodiment of the present application, after the wafer image is divided into grids, the target measurement parameter value in each second grid image is calculated as a mean value to represent the parameter level of the grid. On the one hand, the defect conditions of each grid area of the wafer can be obtained, and on the other hand, the amount of data processing is reduced.

[0201] Based on the above embodiment, before superimposing the aligned multiple wafer images according to the preset superposition rule, the method further includes:

[0202] If the wafer image contains a linear defect, a linear defect image is intercepted from the wafer image according to the position of the linear defect;

[0203] Extracting the skeleton of the linear defect according to the linear defect image to obtain a skeleton image;

[0204] Accordingly, the aligned multiple wafer images are superimposed according to the preset superposition rules, including:

[0205] According to the preset superposition rules, the skeleton image is superimposed.

[0206] In the specific implementation process, for linear defects such as scratches, cracks, and cut lines, after defect detection and classification, methods such as the mask_rcnn deep learning model or threshold segmentation can be used to accurately extract the defect area along the defect contour. Small discrete areas are removed, retaining the main defect area. Then, image morphological closing operations are performed on the area to eliminate internal holes, and the maximum outer contour is calculated to obtain a connected area. Figure 5The three defect area maps provided in the embodiment of the present application are used to extract the skeleton of the connected areas in the defect area map. Specifically, the skeleton can be extracted using the fire model or the maximum disk method to obtain a skeleton image with a width of only one pixel. Figure 6 The three skeleton diagrams provided for the embodiments of this application are Figure 5 The skeleton is extracted from the three defect area images (a), (b), and (c). Figure 6 The three skeleton images (d), (e), and (f) highlight the main features of the defect, allowing us to calculate fine features such as the relative position of the defect to the product's important structure, the defect length, and the bifurcation situation. This helps analyze the cause of the defect.

[0207] Graphite disk scratches are a common defect in semiconductor wafer production. In chemical vapor deposition equipment, wafers are placed on a graphite disk in the reaction chamber. When the disk is damaged, a comet-shaped defect extending from the edge to the center appears on the wafer. Since graphite disks are reused, "graphite disk scratch" defects appearing in the same disk slot have similar location and morphological characteristics. Graphite disk scratch defects have a certain width, and directly stacking multiple images could cover the entire wafer, making it difficult to analyze the consistency of the defect's location and direction. Figure 7 A schematic diagram of a direct overlay provided in an embodiment of the present application, from Figure 7 As can be seen from the figure, after the image is overlaid, the defect almost covers the entire wafer image. Therefore, skeleton extraction is performed first, and the center line along the length of the defect is used to depict the main features of the defect, and then the image is overlaid. Figure 8 This is a schematic diagram of the skeleton image overlay provided in an embodiment of the present application. After overlaying, the intersection position, length, and direction of each defect skeleton with the wafer edge can be calculated. After statistical analysis, a quantitative feature description of the graphite disk breakage defects can be generated.

[0208] In an embodiment of the present application, after superimposing multiple defective wafer images, the defects may cover the entire wafer image, making it difficult to analyze information such as the defect location and direction. Therefore, before superimposing, the skeleton of the defect in each wafer image can be extracted to obtain a skeleton image containing the defect skeleton, and then the skeleton images can be superimposed to facilitate subsequent analysis of the defects.

[0209] On the basis of the above embodiment, according to the defect characteristics, combined with the status information of each component in the production process during operation, analysis is performed to obtain the factors causing the defect, including:

[0210] According to the defect characteristics, combined with the status information of each component in the production process during operation, analysis is performed to obtain the process information and component information that cause the defect.

[0211] During the specific implementation process, the superimposed image can present image features that are not present in a single wafer image. Matching analysis is performed based on the image features on the superimposed image and the element information in the production process. When the defect features on the superimposed image have a certain degree of consistency with the features required for production, the possible cause of the defect is prompted.

[0212] Defect features can include geometric features, statistical features, and color features. Geometric features include the defect's shape, size, area, perimeter, aspect ratio, location, direction, and periodicity. For example, a circular or elliptical defect may indicate particle contamination, while an irregularly shaped defect may indicate a scratch or missing pattern. Area and perimeter can be used to measure the scale of the defect, while aspect ratio can help distinguish different types of linear defects. Statistical features reflect the distribution of defects in the overlay image. These include the frequency of defect occurrence (i.e., the number of defects per unit area) and the degree of defect clustering (e.g., whether the distribution of defects in the image is random, clustered, or uniform). For example, if defects exhibit a clustered distribution, this may indicate specific problems in certain localized areas during the production process. Based on the color coding rules of the overlay image, the color or grayscale value of the defect area can provide information on its severity or the degree to which a physical parameter deviates from the normal range. For example, in a thickness mapping overlay image, red areas may represent defects with thickness outside the normal range, while blue areas may represent defects with insufficient thickness. The information of production factors includes the shape, size, processing position, movement path, processing time, batch, equipment number, physical and chemical principles of production and processing, and geometric properties of production equipment parts.

[0213] When extracting defect features, image segmentation methods can be used, such as threshold segmentation, region growing segmentation, edge detection segmentation, etc., to segment the defect area from the overlay image. For example, for a color-coded overlay image, a threshold can be set based on a specific range of the color channel to segment the defect color area. If the value of the red channel is high and the values of the green and blue channels are low, the area can be determined to be a red defect area.

[0214] Some defects are caused by the periodic movement of equipment parts. For such defects, the process information and abnormal component information that cause the defect can be determined based on the periodic characteristics of the defect location and the matching of the component's movement pattern. To this end, equipment operating parameters related to the production process can be collected, such as the number of probes in the production process, the actual gap between the probes, etc. A correlation model is established between the defect characteristics and the status information of the production process components. By analyzing a large number of superimposed images with defect characteristics and the corresponding production process component status data, the correlation between the defect characteristics and factors such as equipment parameters, component wear, and process recipes can be found. For example, when the exposure energy of the lithography machine exceeds a certain threshold, the frequency of defects of a certain shape and size appearing in the superimposed image increases significantly. Therefore, a correlation model between exposure energy and the defect can be established.

[0215] Based on the established correlation model, fault diagnosis and source tracing are performed for specific defects. Once defect features are detected in the new overlay image, the specific process steps and related components that caused the defect are determined through model calculations or lookup tables, combined with the status information of the components in the production process at that time. For example, if a scratch defect is found on the wafer surface, by analyzing the shape, direction, and distribution characteristics of the scratch, combined with the status information of the mechanical components of the equipment during the production process (such as the moving parts of the wafer conveyor system), it can be determined that the scratch defect was caused by wear or improper adjustment of a component of the conveyor belt, and the specific conveyor belt component can be located.

[0216] In the embodiment of the present application, the presence of defects on a single wafer image and the location of the defects are accidental. By superimposing multiple wafer images, the distribution of defects becomes dense, and then the defect features can be extracted, and the causes of the defects can be analyzed based on the defect features.

[0217] Based on the above embodiment, the defect characteristics include the distribution characteristics of the needle mark defect. According to the defect characteristics, combined with the status information of each component in the production process during operation, analysis is performed, including:

[0218] The minimum spacing of the needle marks in the superimposed image is obtained based on the distribution characteristics of the needle mark defects. The needle mark defects are caused by abnormal working conditions of the probes during the wafer production process.

[0219] The process information and probe information that cause the needle mark defect are determined based on the minimum spacing and the actual spacing of the probes in each production process.

[0220] In the specific implementation process, the position of the needle mark stripes on a single wafer is accidental, and the interval between the needle marks cannot be fully inferred, so it is impossible to determine which probe in which process caused the problem. Figure 9 Three schematic diagrams of needle mark defects are provided in the embodiments of this application, such as Figure 9As shown in Figure 1, (x), (y), and (z) are three schematic diagrams of needle mark defects generated on a wafer during a specific process. The needle mark defects in each diagram are relatively sparse, and it is impossible to determine the probe information for the corresponding process based on a single wafer defect. When wafer images from multiple wafers produced from the same batch and at the same production process are superimposed, the needle mark distribution becomes denser, allowing the spacing of the needle mark stripes to be calculated, and it can be calculated that the widest spacing is always a multiple of the narrowest spacing. Figure 10 A schematic diagram of superimposing multiple wafer images provided in an embodiment of the present application is shown in FIG. Figure 10 According to the spacing of the needle marks and the actual spacing of the probes in each process, it can be inferred which probe in which process caused the needle marks on this batch of products.

[0221] In an embodiment of the present application, since the actual spacing of the probes corresponding to different production processes is different, after superimposing multiple wafer images under the same process, the minimum spacing of the needle marks in the wafer image can be found. Based on the minimum spacing, the production process information and probe information that cause the needle mark defect can be quickly located, which facilitates subsequent maintenance.

[0222] On the basis of the above embodiment, the aligned multiple wafer images are superimposed according to a preset superposition rule to obtain a superimposed image, including:

[0223] In the case where multiple wafer images are images of the same wafer at different processes, the wafer image corresponding to the current process is superimposed with the wafer image before the current process to obtain a process superimposed image corresponding to the current process;

[0224] Based on the defect characteristics and combined with the status information of each component in the production process, the factors causing the defect are analyzed, including:

[0225] Calculate the difference between the process superposition images corresponding to adjacent processes;

[0226] Determine the process information of the defect occurrence based on the difference, and / or determine the evolution information of the defect along the production process.

[0227] In practice, the overlay operation requires aligning images of the same wafer from different process steps. This ensures the consistency of the wafer images' position and orientation across different process steps, enabling accurate overlay comparison. This alignment process typically determines geometric transformations between the images, such as translation, rotation, and scaling, based on specific markers on the wafer images (e.g., alignment marks and corner points of the die arrangement pattern).

[0228] On the aligned wafer images, an appropriate overlay algorithm is used to perform an overlay operation. That is, the wafer images can be overlaid in the order of the production processes. For example, there are four production processes, namely process 1, process 2, process 3, and process 4. When overlaying, the wafer image of process 1 and the wafer image of process 2 can be overlaid first to obtain overlay image 1; then overlay image 1 and the wafer image of process 3 are overlaid to obtain overlay image 2; then overlay image 2 and the wafer image of process 4 are overlaid to obtain the final overlay image. It should be noted that the overlay algorithm can be referred to in the above embodiment and will not be repeated here.

[0229] To quantify the variation between adjacent processes, the difference between the superimposed process images corresponding to each adjacent process is calculated. This difference can be calculated by comparing the image's grayscale values, color values, or specific feature parameters. For example, metrics such as the mean squared error (MSE) and the structural similarity index (SSIM) can be used to measure the difference between two images. The MSE reflects the average grayscale difference between images, while the SSIM considers the structural similarity of images and can better reflect the human eye's perception of image differences.

[0230] A difference threshold is set to determine whether a defect has occurred in the current process. When the difference between adjacent processes exceeds the set threshold, it can be considered that a significant defect or change has occurred in the current process. For example, if the difference threshold is set to T, when the calculated difference D between the current process and the previous process is greater than T, the current process is considered to be a key process where the defect may have occurred. The status information of each component during the operation of each process can be understood as whether the component is in working condition. Therefore, after determining the key process, it is possible to further determine whether the damage level of the components in the process is increasing, that is, whether the defect evolves with the damage of various components in the production process.

[0231] Furthermore, by calculating the differences between multiple adjacent processes, it's possible to track the evolution of defects throughout the production process. By plotting a difference curve, with the horizontal axis representing the process sequence and the vertical axis representing the difference value, this visually illustrates the evolution of defects over the process. For example, if the difference curve shows a clear upward trend after a certain process, it indicates that defects may begin to occur or intensify after that process.

[0232] Based on the difference curves and overlaid images, the evolution patterns of defects can be identified. For example, some defects may gradually appear and intensify after a specific process, which may indicate that factors in that process or subsequent processes are continuously influencing the development of defects. Other defects may suddenly appear after a certain process with a large difference, which may indicate that there are sudden quality issues in that process. By analyzing defect evolution patterns, we can better understand the formation mechanisms of defects and provide a basis for optimizing production processes and preventing defects.

[0233] It should be noted that the evolution of component damage during the production process can also be determined based on images of different wafers taken during the same process. The specific method can be found in the above embodiment. That is, a wafer overlay image is calculated by superimposing each wafer image with the previous wafer image. The difference between the wafer overlay images corresponding to two adjacent wafer images is then calculated. Based on this difference, the time point at which the defect occurred during the process can be determined. Furthermore, based on the components in working order during the process, the scope of the faulty components can be initially identified. Furthermore, as the difference increases, the evolution of component failure can be further determined.

[0234] In this embodiment of the present application, by superimposing the wafer image corresponding to the current process with the previous wafer image and calculating the difference between the superimposed process images corresponding to adjacent processes, the impact of the current process on the wafer can be clearly observed. If new defect features appear in the superimposed image, it can be accurately determined that these defects were caused by the current process.

[0235] Figure 11 This is a schematic diagram of a defect analysis device based on wafer image overlay provided in an embodiment of the present application. The device can be a module, program segment or code on an electronic device. It should be understood that the device is similar to the above-mentioned Figure 1 The method embodiment corresponds to the embodiment that can be executed Figure 1 The various steps involved in the method embodiment and the specific functions of the device can be found in the description above. To avoid repetition, detailed description is omitted here. The device includes: an image acquisition module 1101, a feature extraction module 1102, an image alignment module 1103, an image overlay module 1104, a defect feature extraction module 1105, and a defect analysis module 1106, wherein:

[0236] The image acquisition module 1101 is used to obtain multiple wafer images; the multiple wafer images are images corresponding to the same wafer in different production processes, or images of different wafers in the same production process;

[0237] The feature extraction module 1102 is used to extract calibration features on each wafer image. The calibration features are features used for positioning when aligning multiple wafer images.

[0238] The image alignment module 1103 is used to align multiple wafer images based on the calibration features to obtain multiple aligned wafer images;

[0239] The image overlay module 1104 is used to overlay the aligned multiple wafer images according to a preset overlay rule to obtain an overlay image;

[0240] The defect feature extraction module 1105 is used to extract the defect features on the superimposed image;

[0241] The defect analysis module 1106 is used to perform wafer defect analysis based on the overlay image.

[0242] Based on the above embodiment, the image type of the wafer image is an AOI image; the wafer image includes the defect information, and the defect information includes the defect type and defect location; the overlay image includes a first single-defect overlay image; and the image overlay module 1104 is specifically configured to:

[0243] extracting a defect image containing a single defect type from the wafer image based on the defect type;

[0244] For defect images of the same defect type, the number of first defect images having defects at the same pixel position is counted, and a first single-defect superimposed image is generated according to the number of the first defect images.

[0245] Based on the above embodiment, the superimposed image further includes a first multi-defect superimposed image, and the image superimposition module 1104 is further configured to:

[0246] Count the number of second defect images of the first target defect type at the same pixel position in the first single-defect overlay image, and generate the first multi-defect overlay image based on the number of second defect images; wherein the first target defect type is all defect types or some defect types selected from all defect types.

[0247] Based on the above embodiment, the image overlay module 1104 is specifically configured to:

[0248] The number of second defect images of the first target defect type existing at the same pixel position in the first single-defect superimposed image is counted, and the superimposed image is generated according to the number of the second defect images.

[0249] Based on the above embodiment, the image overlay module 1104 is specifically configured to:

[0250] Determining a color parameter corresponding to each pixel position according to the number of first defect images corresponding to the pixel position;

[0251] The first single-defect overlay image is generated by rendering based on the color parameter.

[0252] Based on the above embodiment, the image type of the wafer image is an AOI image; the wafer image includes the defect information, and the defect information includes the defect type and defect location; the overlay image includes a second single-defect overlay image; and the image overlay module 1104 is specifically configured to:

[0253] extracting a defect image containing a single defect type from the wafer image based on the defect type;

[0254] Performing grid division on the defect image corresponding to each defect type to obtain a plurality of grid images;

[0255] For each defect type, counting the number of defective chips in each grid image in the corresponding defect image;

[0256] Based on the statistically obtained number of defective chips contained in each of the grid images, the overlay value corresponding to the grid image at the same position in multiple defect images of the same defect type is calculated according to a preset overlay algorithm, and a second single defect overlay image is generated based on the overlay value.

[0257] Based on the above embodiment, the image overlay module 1104 is further configured to:

[0258] Count the number of chips with a second target defect type on the same grid image in the second single-defect overlay image, and generate the second multi-defect overlay image based on the number of chips; wherein the second target defect type is all defect types or some defect types selected from all defect types.

[0259] Based on the above embodiment, the image type of the wafer image is a mapping image; the wafer image is generated based on the target measurement parameter value of each pixel position of the wafer; the image overlay module 1104 is specifically used to:

[0260] Superimposing and calculating the target measurement parameter values at the same pixel position in the plurality of wafer images according to a preset superposition algorithm to obtain a first superposition parameter value; the preset superposition algorithm includes summing, averaging, variance, and standard deviation;

[0261] The overlay image is generated according to the first overlay parameter value.

[0262] Based on the above embodiment, the image type of the wafer image is a mapping image; the wafer image is generated based on the target measurement parameter value of each pixel position of the wafer; the image overlay module 1104 is specifically used to:

[0263] Dividing each wafer image into a grid to obtain a plurality of second grid images corresponding to each wafer image;

[0264] Calculating a mean of the target measurement parameter values in each of the second grid images to obtain a parameter mean corresponding to each of the second grid images;

[0265] According to a preset superposition algorithm, the parameter mean values of the second grid images at the same position of the plurality of wafer images are superimposed and calculated to obtain a second superposition parameter value;

[0266] The overlay image is generated according to the second overlay parameter value.

[0267] Based on the above embodiment, the superposition rules include:

[0268] Parameters involved in the overlay operation in the wafer image;

[0269] A preset superposition algorithm corresponding to the superposition operation;

[0270] The rendering rules of the overlay image.

[0271] Based on the above embodiment, the device further includes a skeleton extraction module for:

[0272] If the wafer image includes a linear defect, intercepting a linear defect image from the wafer image according to a position of the linear defect;

[0273] extracting a skeleton of the linear defect according to the linear defect image to obtain a skeleton image;

[0274] Accordingly, the image overlay module 1104 is specifically configured to:

[0275] The skeleton image is superimposed according to a preset superposition rule.

[0276] Based on the above embodiment, the defect analysis module 1106 is specifically configured to:

[0277] According to the defect characteristics, combined with the status information of each component in the working process of the production process, analysis is performed to obtain the process information and component information that cause the defect.

[0278] Based on the above embodiment, the defect characteristics include the distribution characteristics of the needle mark defect, and the defect analysis module 1106 is specifically used to:

[0279] Obtaining a minimum spacing of the needle marks in the superimposed image according to the distribution characteristics of the needle mark defects; wherein the needle mark defects are caused by an abnormal working state of the probe during the production process of the wafer;

[0280] The process information and probe information causing the needle mark defect are determined according to the minimum spacing and the actual spacing of the probes in each production process.

[0281] Based on the above embodiment, the image overlay module 1104 is specifically configured to:

[0282] In the case where the plurality of wafer images are images of the same wafer at different processes, the wafer image corresponding to the current process is superimposed with the wafer image before the current process to obtain a process superimposed image corresponding to the current process;

[0283] The defect analysis module 1106 is specifically used to:

[0284] Calculate the difference between the process superposition images corresponding to adjacent processes;

[0285] Determine the process information of the defect occurrence according to the difference, and / or determine the evolution information of the defect along the production process.

[0286] Figure 12 The physical structure diagram of the electronic device provided in the embodiment of the present application is as follows: Figure 12 As shown, the electronic device includes: a processor 1201, a memory 1202 and a bus 1203; wherein:

[0287] The processor 1201 and the memory 1202 communicate with each other via the bus 1203;

[0288] The processor 1201 is used to call the program instructions in the memory 1202 to execute the methods provided by the above-mentioned method embodiments, for example, including: obtaining multiple wafer images; the multiple wafer images are images corresponding to the same wafer in different production processes, or images of different wafers in the same production process; extracting calibration features on each of the wafer images, and the calibration features are features used for positioning when aligning the multiple wafer images; aligning the multiple wafer images based on the calibration features to obtain multiple aligned wafer images; superimposing the multiple aligned wafer images according to preset superposition rules to obtain a superimposed image; extracting defect features on the superimposed image; according to the defect features, combined with the status information of each component in the production process during operation, analyzing to obtain factors causing defects.

[0289] Processor 1201 can be an integrated circuit chip with signal processing capabilities. Processor 1201 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application. A general-purpose processor can be a microprocessor or any conventional processor.

[0290] The memory 1202 may include, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0291] The present embodiment discloses a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the methods provided by the above-mentioned method embodiments, for example, including: obtaining multiple wafer images; the multiple wafer images are images corresponding to the same wafer in different production processes, or images of different wafers in the same production process; extracting calibration features on each of the wafer images, the calibration features are features used for positioning when aligning the multiple wafer images; aligning the multiple wafer images based on the calibration features to obtain multiple aligned wafer images; superimposing the multiple aligned wafer images according to preset superposition rules to obtain a superimposed image; extracting defect features on the superimposed image; and analyzing the factors causing the defects based on the defect features in combination with the status information of each component in the production process during operation to obtain the factors causing the defects.

[0292] This embodiment provides a non-transitory computer-readable storage medium, which stores computer instructions, and the computer instructions enable the computer to execute the methods provided by the above-mentioned method embodiments, for example, including: obtaining multiple wafer images; the multiple wafer images are images corresponding to the same wafer in different production processes, or images of different wafers in the same production process; extracting calibration features on each of the wafer images, and the calibration features are features used for positioning when aligning the multiple wafer images; aligning the multiple wafer images based on the calibration features to obtain multiple aligned wafer images; superimposing the multiple aligned wafer images according to preset superposition rules to obtain a superimposed image; extracting defect features on the superimposed image; according to the defect features, combined with the status information of each component in the production process during operation, analyzing to obtain factors causing defects.

[0293] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interface, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0294] In addition, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0295] Furthermore, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0296] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0297] The above description is merely an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, various modifications and variations of the present application are possible. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A defect analysis method based on wafer image overlay, characterized in that: include: Acquire multiple wafer images; The multiple wafer images are images corresponding to the same wafer in different production processes, or images of different wafers in the same production process; Extracting a calibration feature on each of the wafer images, wherein the calibration feature is a feature used for positioning when aligning multiple wafer images; Aligning the plurality of wafer images based on the calibration features to obtain a plurality of aligned wafer images; According to a preset superposition rule, the aligned multiple wafer images are superimposed to obtain a superimposed image; extracting defect features from the superimposed image; Based on the defect characteristics, combined with the status information of each component in the production process during operation, the factors causing the defect are analyzed; In a case where the image type of the wafer image is an AOI image; the wafer image includes defect information, the defect information including the defect type and the defect location; the superimposed image includes a first single-defect superimposed image or a second single-defect superimposed image; and superimposing the aligned multiple wafer images according to a preset superimposition rule to obtain the superimposed image includes: extracting a defect image containing a single defect type from the wafer image based on the defect type; For defect images of the same defect type, count the number of first defect images with defects at the same pixel position; Generate a first single defect superposition image according to the number of the first defect images; or, extracting a defect image containing a single defect type from the wafer image based on the defect type; Performing grid division on the defect image corresponding to each defect type to obtain a plurality of grid images; For each defect type, counting the number of defective chips in each grid image in the corresponding defect image; Calculating, based on the statistically obtained number of defective chips in each of the grid images, an overlay value corresponding to the grid images at the same position in multiple defect images of the same defect type according to a preset overlay algorithm, and generating a second single-defect overlay image based on the overlay value; In a case where the image type of the wafer image is a mapping image; the wafer image is generated based on a target measurement parameter value of each pixel point of the wafer; and the stacking operation of the aligned multiple wafer images according to a preset stacking rule to obtain a stacked image includes: Superimposing and calculating the target measurement parameter values at the same pixel position in the plurality of wafer images according to a preset superposition algorithm to obtain a first superposition parameter value; the preset superposition algorithm includes summing, averaging, variance, and standard deviation; Generate the overlay image according to the first overlay parameter value; or, Dividing each wafer image into a grid to obtain a plurality of second grid images corresponding to each wafer image; Calculating a mean of the target measurement parameter values in each of the second grid images to obtain a parameter mean corresponding to each of the second grid images; According to a preset superposition algorithm, the parameter mean values of the second grid images at the same position of the plurality of wafer images are superimposed and calculated to obtain a second superposition parameter value; The overlay image is generated according to the second overlay parameter value.

2. The method according to claim 1, characterized in that In a case where the image type of the wafer image is an AOI image, the superimposed image further includes a first multi-defect superimposed image, and the method further includes: Count the number of second defect images of the first target defect type at the same pixel position in the first single-defect overlay image, and generate the first multi-defect overlay image based on the number of second defect images; wherein the first target defect type is all defect types or some defect types selected from all defect types.

3. The method according to claim 1, characterized in that The overlay image further includes a second multi-defect overlay image, and the method further includes: Count the number of chips with a second target defect type on the same grid image in the second single-defect overlay image, and generate the second multi-defect overlay image based on the number of chips; wherein the second target defect type is all defect types or some defect types selected from all defect types.

4. The method according to claim 1, wherein Before superimposing the aligned multiple wafer images according to a preset superposition rule, the method further includes: If the wafer image includes a linear defect, intercepting a linear defect image from the wafer image according to a position of the linear defect; extracting a skeleton of the linear defect according to the linear defect image to obtain a skeleton image; Accordingly, the stacking operation of the aligned multiple wafer images according to the preset stacking rule includes: The skeleton image is superimposed according to a preset superposition rule.

5. The method according to claim 1, wherein The analysis based on the defect characteristics and the status information of each component in the production process during operation is performed to obtain the factors causing the defect, including: According to the defect characteristics, combined with the status information of each component in the working process of the production process, analysis is performed to obtain the process information and component information that cause the defect.

6. The method according to any one of claims 1 to 5, characterized in that The method of superimposing the aligned multiple wafer images according to a preset superposition rule to obtain a superimposed image includes: In the case where the plurality of wafer images are images of the same wafer at different processes, the wafer image corresponding to the current process is superimposed with the wafer image before the current process to obtain a process superimposed image corresponding to the current process; The analysis based on the defect characteristics and the status information of each component in the production process during operation is performed to obtain the factors causing the defect, including: Calculate the difference between the process superposition images corresponding to adjacent processes; Determine the process information of the defect occurrence according to the difference, and / or determine the evolution information of the defect along the production process.

7. An electronic device, characterized in that: include: A processor, memory, and bus, where: The processor and the memory communicate with each other via the bus; The memory stores program instructions that can be executed by the processor, and the processor calls the program instructions to execute the method according to any one of claims 1 to 6.

8. A non-transitory computer-readable storage medium, characterized in that The non-transitory computer-readable storage medium stores computer instructions, which, when executed by a computer, enable the computer to perform the method according to any one of claims 1 to 6.

9. A computer program product, characterized in that The method comprises computer program instructions, and when the computer program instructions are read and executed by a processor, the method according to any one of claims 1 to 6 is executed.

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