Gate driving unit and display device

Abstract

The invention provides a gate driving unit and a display device. A plurality of cascaded gate driving circuits are electrically connected with a frequency division control line for transmitting a frequency division control signal; and the frequency division control module in each gate drive circuit controls signal transmission between the first power supply end and the first node or the second node according to the frequency division control signal, so that the level state of the gate control signals output by the first output module and the second output module is controlled.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and more particularly, to a gate driving unit and a display device. Background Art

[0002] The use of a variable refresh rate design can reduce the power consumption of a display panel. However, in some usage scenarios, the display panel corresponds to different display areas with different displayed picture contents. If the same refresh rate is still used to drive different display areas to display different display pictures, then the areas displaying static pictures and the areas displaying dynamic pictures are driven at the same refresh rate, which will also cause waste of resources. Summary of the Invention

[0003] Embodiments of the present invention provide a gate driving circuit and a display device, which can achieve partitioned and frequency-divided driving.

[0004] Embodiments of the present invention provide a gate driving unit, including a frequency division control line and a plurality of cascaded gate driving circuits. The frequency division control line is configured to transmit a frequency division control signal to the plurality of gate driving circuits. Each gate driving circuit includes a first control module, a first output module, a second output module, and a frequency division control module. The first control module is electrically connected to a first node of the current-stage gate driving circuit, and is configured to control the signal transmission between one of a first power supply terminal and a second power supply terminal and the first node according to a corresponding first clock signal, a start signal, and one of first gate control signals output by a previous-stage gate driving circuit. The first output module is at least electrically connected to the first node of the current-stage gate driving circuit, and is configured to control the electrical connection between a third power supply terminal and a first output terminal of the current-stage gate driving circuit according to the potential of the first node. The first output terminal outputs a first gate control signal of the current-stage gate driving circuit. The second output module is electrically connected to a second node and a third node of the current-stage gate driving circuit, and is configured to output a second gate control signal of the current-stage gate driving circuit according to the potential of the second node and the potential of the third node. The frequency division control module is electrically connected to the first node of the current-stage gate driving circuit, and is configured to control the signal transmission between the first power supply terminal and the first node or the second node according to the frequency division control signal.

[0005] An embodiment of the present invention further provides a display device, including any of the above-mentioned gate driving units and a display panel. The display panel includes a plurality of sub-pixels, and each sub-pixel includes a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light. The pixel driving circuit at least includes a driving transistor, a data transistor, and a compensation transistor. The driving transistor is configured to drive the light-emitting device to emit light according to a corresponding data signal. The input end of the compensation transistor is electrically connected to the output end of the driving transistor, the output end of the compensation transistor is electrically connected to the control end of the driving transistor, the input end of the data transistor is configured to receive the corresponding data signal, and the output end of the data transistor is electrically connected to the input end of the driving transistor. Among them, the first gate control signal generated by the plurality of gate driving circuits is output to the control ends of the compensation transistors of the plurality of sub-pixels, and the second gate control signal generated by the plurality of gate driving circuits is output to the control ends of the data transistors of the plurality of sub-pixels.

[0006] The gate driving unit and the display device provided by the embodiment of the present invention electrically connect a plurality of cascaded gate driving circuits to a frequency division control line for transmitting a frequency division control signal, so that the frequency division control module in each gate driving circuit controls the signal transmission between the first power supply terminal and the first node or the second node according to the frequency division control signal, thereby controlling the level states of the gate control signals output by the first output module and the second output module, so that the gate control signal output by at least one gate driving circuit always maintains an invalid level state. When the gate driving unit is used in a display device, the level states of the gate control signals output by a plurality of gate driving circuits are controlled through the frequency division control signal, so that the display panel realizes frequency division and zoning control. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0008] Figures 1A - 1B is a schematic structural diagram of the gate driving unit provided by the embodiment of the present invention;

[0009] Figures 2A - 2D is a circuit diagram of the gate driving circuit provided by the embodiment of the present invention;

[0010] Figures 3A - 3D is a timing diagram of the gate driving circuit provided by the embodiment of the present invention;

[0011] Figure 4It is a schematic structural diagram of a display device provided by an embodiment of the present invention;

[0012] Figure 5 It is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0013] Figures 6A - 6C It is a timing diagram corresponding to the display device provided by an embodiment of the present invention. Detailed implementation manners

[0014] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention. In addition, it should be understood that the specific implementation manners described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In the present invention, unless otherwise stated, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the accompanying drawings; and "inner" and "outer" refer to the outline of the device.

[0015] Specifically, Figures 1A - 1B It is a schematic structural diagram of a gate driving unit provided by an embodiment of the present invention. The present invention provides a gate driving unit, including a frequency division control line LFL and a plurality of cascaded gate driving circuits GDC. The plurality of cascaded gate driving circuits GDC are electrically connected to the frequency division control line LFL, and the frequency division control line LFL is configured to transmit a frequency division control signal FD to the plurality of gate driving circuits GDC.

[0016] Please continue to refer to Figures 1A - 1B , the gate driving unit is electrically connected to a plurality of clock lines. The plurality of clock lines provide the required first clock signal XCK and second clock signal CK for the plurality of gate driving circuits GDC, so that the plurality of gate driving circuits GDC share the clock signals transmitted by the plurality of clock lines, reducing the number of clock signals applied by the gate driving unit, and reducing the number of clock signal lines and the wiring space occupied by the clock signal lines.

[0017] Optionally, the plurality of clock lines include a first clock line CKL1 to a fourth clock line CKL4. The first clock signal XCK corresponding to the 4x+1-stage gate drive circuit GDC (4x+1) is provided by the second clock line CKL2, and the second clock signal CK corresponding to the 4x+1-stage gate drive circuit GDC (4x+1) is provided by the first clock line CKL1; the first clock signal XCK corresponding to the 4x+2-stage gate drive circuit GDC (4x+2) is provided by the third clock line CKL3, and the second clock signal CK corresponding to the 4x+2-stage gate drive circuit GDC (4x+2) is provided by the second clock line CKL2; The first clock signal XCK corresponding to the 4x+3-level gate drive circuit GDC (4x+3) is provided by the fourth clock line CKL4, and the second clock signal CK corresponding to the 4x+3-level gate drive circuit GDC (4x+3) is provided by the third clock line CKL3; the first clock signal XCK corresponding to the 4x+4-level gate drive circuit GDC (4x+4) is provided by the first clock line CKL1, and the second clock signal CK corresponding to the 4x+4-level gate drive circuit GDC (4x+4) is provided by the fourth clock line CKL4. Wherein, x≥0.

[0018] Figures 2A - 2D : is a circuit diagram of a gate driving circuit provided by an embodiment of the present invention, and is described by taking the n-th gate driving circuit GDC(n) as an example. Wherein, Nout(n) represents the first output terminal of the n-th gate driving circuit GDC(n), Pout(n) represents the second output terminal of the n-th gate driving circuit GDC(n), and P(n) represents the third node of the n-th gate driving circuit GDC(n).

[0019] Each gate driving circuit GDC includes a first control module 10 , a second control module 20 , a first output module 30 , a second output module 40 and a frequency division control module 50 .

[0020] The first control module 10 is electrically connected to the first node K1 of the gate driving circuit GDC at this level, and is configured to control the signal transmission between the first node K1 and one of the first power supply terminal PVGL and the second power supply terminal PVGH according to the corresponding first clock signal XCK and the start signal STV.

[0021] Optionally, the first-level gate driving circuit GDC among the multiple gate driving circuits GDC uses the start signal stv as the start signal STV, so that the first-level gate driving circuit GDC(1) controls the signal transmission between one of the first power supply terminal PVGL and the second power supply terminal PVGH and the first node K1 of the first-level gate driving circuit GDC(1) according to the corresponding first clock signal XCK and the start signal stv.

[0022] Optionally, the n-th gate driving circuit GDC(n) among the multiple gate driving circuits GDC uses the nA-th first gate control signal Nscan(nA) output by the nA-th gate driving circuit GDC(nA) as the start signal STV, so that the n-th gate driving circuit GDC(n) controls the signal transmission between one of the first power supply terminal PVGL and the second power supply terminal PVGH and the first node K1 of the n-th gate driving circuit GDC(n) according to the corresponding first clock signal XCK and the nA-th first gate control signal Nscan(nA) output by the nA-th gate driving circuit GDC(nA). Where n>1, A≥1.

[0023] Optionally, in order to reduce the load corresponding to the first output terminal Nout of the gate drive circuit GDC, the n-th level gate drive circuit GDC(n) among the multiple gate drive circuits GDC controls the signal transmission between one of the first power supply terminal PVGL and the second power supply terminal PVGH and the first node K1 of the n-th level gate drive circuit GDC(n) according to the corresponding first clock signal XCK and the potential of the third node P of the nA-th level gate drive circuit GDC(nA).

[0024] Optionally, see Figures 2A - 2D , the first control module 10 includes a first transistor T1, a second transistor T2 and a third transistor T3.

[0025] The first control terminal and the second control terminal of the first transistor T1 are configured to receive a start signal STV, and the input terminal of the first transistor T1 is electrically connected to the first power terminal PVGL.

[0026] The control end of the second transistor T2 is electrically connected to the first control end of the first transistor T1 , the input end of the second transistor T2 is electrically connected to the second power supply end PVGH, and the output end of the second transistor T2 is electrically connected to the output end of the first transistor T1 .

[0027] The control end of the third transistor T3 is configured to receive the corresponding first clock signal XCK, the input end of the third transistor T3 is electrically connected to the output end of the first transistor T1 , and the output end of the third transistor T3 is electrically connected to the first node K1 .

[0028] Optionally, the first control module 10 is also electrically connected to the third node P of the gate drive circuit GDC at this level, and the first control module 10 is configured to control the electrical connection between the second power terminal PVGH or the third power terminal NVGL and the first node K1 according to the potential of the third node P.

[0029] Optionally, see Figures 2A - 2D, the first control module 10 includes a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6.

[0030] The first control terminal and the second control terminal of the fourth transistor T4 are configured to receive the corresponding first clock signal XCK, and the output terminal of the fourth transistor T4 is electrically connected to the first node K1. The control terminal of the fifth transistor T5 and the first control terminal and the second control terminal of the sixth transistor T6 are electrically connected to the third node P, the input terminal of the fifth transistor T5 is electrically connected to the second power supply terminal PVGH, the output terminal of the fifth transistor T5 is electrically connected to the input terminal of the fourth transistor T4, the input terminal of the sixth transistor T6 is electrically connected to the third power supply terminal NVGL, and the output terminal of the sixth transistor T6 is electrically connected to the first node K1.

[0031] Please continue reading Figures 2A - 2D The second control module 20 is electrically connected to the first node K1 of the gate driving circuit GDC of this level and the third node P of the gate driving circuit GDC of this level. The second control module 20 is configured to control the signal transmission between the first power supply terminal PVGL or the second power supply terminal PVGH and the third node P according to the potential of the first node K1.

[0032] Optionally, see Figures 2A - 2D , the gate driving unit also includes a seventh transistor T7 and an eighth transistor T8.

[0033] The first control terminal and the second control terminal of the seventh transistor T7 are electrically connected to the first node K1, the input terminal of the seventh transistor T7 is electrically connected to the first power supply terminal PVGL, the output terminal of the seventh transistor T7 is electrically connected to the third node P, the control terminal of the eighth transistor T8 is electrically connected to the first node K1, the input terminal of the eighth transistor T8 is electrically connected to the second power supply terminal PVGH, and the output terminal of the eighth transistor T8 is electrically connected to the third node P.

[0034] Please continue reading Figures 2A - 2D The first output module 30 is electrically connected to at least the first node K1 of the gate driving circuit GDC of this stage. The first output module 30 is configured to control the electrical connection between the third power supply terminal NVGL and the first output terminal Nout of the gate driving circuit GDC of this stage according to the potential of the first node K1. The first output terminal Nout outputs the first gate control signal Nscan of the gate driving circuit GDC of this stage.

[0035] The second output module 40 is electrically connected to the second node K2 of the gate drive circuit GDC at this level and the third node P of the gate drive circuit GDC at this level. The second output module 40 is configured to output the second gate control signal Pscan of the gate drive circuit GDC at this level according to the potential of the second node K2 and the potential of the third node P.

[0036] The frequency division control module 50 is electrically connected to the first node K1 of the gate driving circuit GDC at this stage, and is configured to control signal transmission between the first power supply terminal PVGL and the first node K1 or the second node K2 according to the frequency division control signal LF.

[0037] By setting up the frequency division control module 50, each gate driving circuit GDC can control the level state of the first gate control signal Nscan and the second gate control signal Pscan according to the frequency division control signal LF, so that when the gate driving unit is used in a display device, the level of the first gate control signal Nscan and the second gate control signal Pscan output by the corresponding gate driving circuit GDC is controlled to remain in an invalid level state, so that the display panel can achieve frequency division and partition control.

[0038] Since each gate drive circuit GDC can output the first gate control signal Nscan and the second gate control signal Pscan at the same time, the same frequency-divided control signal LF can be used to control the level state of the first gate control signal Nscan and the second gate control signal Pscan, or two frequency-divided control signals LF can be used to respectively control the level state of the first gate control signal Nscan and the second gate control signal Pscan.

[0039] Accordingly, if Figure 1A As shown, the plurality of gate driving circuits GDC are electrically connected to the same frequency division control line LFL, so as to control the level states of the first gate control signal Nscan and the second gate control signal Pscan output by the plurality of gate driving circuits GDC through the frequency division control signal LF transmitted by the frequency division control line LFL. Figure 1B As shown, the frequency division control line LFL includes a first frequency division control line LFL1 and a second frequency division control line LFL2, and a plurality of gate driving circuits GDC are electrically connected to the first frequency division control line LFL1 and the second frequency division control line LFL2, so as to control the level states of the first gate control signal Nscan and the second gate control signal Pscan output by the plurality of gate driving circuits GDC through the first frequency division control signal NLF transmitted by the first frequency division control line LFL1 and the second frequency division control signal PLF transmitted by the second frequency division control line LFL2.

[0040] The following first takes the example of multiple gate drive circuits GDC being controlled by the same frequency division control line LFL to explain the circuit structure of the gate drive circuit GDC. Figures 2A - 2C The frequency division control module 50 is electrically connected to the first control module 10 , and the frequency division control module 50 controls the signal transmission between the first power supply terminal PVGL and the first node K1 according to the frequency division control signal LF.

[0041] Optionally, the frequency division control module 50 is electrically connected to the first transistor T1 or the third transistor T3 to achieve electrical connection with the first control module 10.

[0042] Optionally, please continue to refer to Figure 2A , the frequency division control module 50 includes a frequency division transistor Tf. The control end of the frequency division transistor Tf is configured to receive a frequency division control signal LF. The input end of the frequency division transistor Tf is electrically connected to the output end of the third transistor T3, and the output end of the frequency division transistor Tf is electrically connected to the first node K1. The frequency division transistor Tf is configured to control the signal transmission between the first node K1 and the output end of the third transistor T3 according to the frequency division control signal LF, so as to disconnect the signal transmission between the first node K1 and the first power supply terminal PVGL when the frequency division transistor Tf is turned off. When the frequency division transistor Tf is turned on, the electrical connection between the first node K1 and the output end of the third transistor T3 is realized, so that there is signal transmission between the first power supply terminal PVGL and the first node K1, thereby realizing the control of the signal transmission between the first node K1 and the first power supply terminal PVGL.

[0043] Optionally, please continue to refer to Figure 2B , the frequency division control module 50 includes a frequency division transistor Tf. The control end of the frequency division transistor Tf is configured to receive a frequency division control signal LF, the input end of the frequency division transistor Tf is configured to receive a corresponding first clock signal XCK, and the output end of the frequency division transistor Tf is electrically connected to the control end of the third transistor T3. The frequency division transistor Tf is configured to control the conduction state of the third transistor T3 according to the frequency division control signal LF, thereby realizing the control of the signal transmission between the first node K1 and the first power supply terminal PVGL.

[0044] Optionally, please continue to refer to Figure 2C , the frequency division control module 50 includes a frequency division transistor Tf. The control end of the frequency division transistor Tf is configured to receive a frequency division control signal LF, the input end of the frequency division transistor Tf is configured to receive a start signal stv or a first gate control signal Nscan output by a previous-stage gate drive circuit GDC, and the output end of the frequency division transistor Tf is electrically connected to the first control end of the first transistor T1. The frequency division transistor Tf is configured to control the conduction states of the first transistor T1 and the second transistor T2 according to the frequency division control signal LF, thereby realizing the control of the signal transmission between the first node K1 and the first power supply terminal PVGL.

[0045] Please continue to refer to Figures 2A - 2C , the first output module 30 is configured to control the signal transmission between the third power supply terminal NVGL or the fourth power supply terminal NVGH and the first output terminal Nout according to the potential of the first node K1.

[0046] Optionally, the first output module 30 includes a first output transistor To1 and a second output transistor To2.

[0047] The first control terminal, the second control terminal of the first output transistor To1 and the control terminal of the second output transistor To2 are electrically connected to the first node K1. The input terminal of the first output transistor To1 is electrically connected to the third power supply terminal NVGL, the input terminal of the second output transistor To2 is electrically connected to the fourth power supply terminal NVGH, and the output terminals of the second output transistor To2 and the first output transistor To1 are electrically connected to the first output terminal Nout of the local gate drive circuit GDC.

[0048] Optionally, the second output module 40 includes a third output transistor To3, a fourth output transistor To4 and a storage capacitor C0.

[0049] The control terminal of the third output transistor To3 is electrically connected to the second node K2. The input terminal of the third output transistor To3 is configured to receive the corresponding second clock signal CK. The control terminal of the fourth output transistor To4 is electrically connected to the third node P of the local gate drive circuit GDC. The input terminal of the fourth output transistor To4 is electrically connected to the second power supply terminal PVGH. The output terminals of the fourth output transistor To4 and the third output transistor To3 are electrically connected to the second output terminal Pout of the local gate drive circuit GDC.

[0050] The first end of the storage capacitor C0 is electrically connected to the control terminal of the third output transistor To3, and the second end of the storage capacitor C0 is electrically connected to the second output terminal Pout of the local gate drive circuit GDC.

[0051] Optionally, each gate drive circuit GDC further includes an output control module 60. The output control module 60 is electrically connected to the first node K1 and the second node K2, and is configured to control the signal transmission between the first node K1 and the second node K2 according to the output control signal ST.

[0052] Optionally, please continue to refer to Figure 2A and Figure 2C The output control module 60 includes a first switching transistor Ts1, a second switching transistor Ts2 and a third capacitor Cs.

[0053] The input terminal of the first switching transistor Ts1 is electrically connected to the first node K1. The input terminal of the second switching transistor Ts2 is electrically connected to the output terminal of the first switching transistor Ts1. The output terminal of the second switching transistor Ts2 is electrically connected to the second node K2.

[0054] The first terminal of the third capacitor Cs is electrically connected to the control terminal of the first switching transistor Ts1, and the second terminal of the third capacitor Cs is electrically connected to the output terminal of the first switching transistor Ts1.

[0055] Wherein, the control terminal of the first switching transistor Ts1 is configured to receive a first output control signal ST1, the control terminal of the second switching transistor Ts2 is configured to receive a second output control signal ST2, and the output control signal ST includes the first output control signal ST1 and the second output control signal ST2.

[0056] Optionally, the control terminal of the first switching transistor Ts1 of the nth-stage gate driving circuit GDC(n) is configured to receive the (n-B)th-stage first gate control signal Nscan(n-B) output by the (n-B)th-stage gate driving circuit GDC(n-B) as the first output control signal ST1, and the control terminal of the second switching transistor Ts2 of the nth-stage gate driving circuit GDC(n) is configured to receive the (n-C)th-stage first gate control signal Nscan(n-C) output by the (n-C)th-stage gate driving circuit GDC(n-C) as the second output control signal ST2. Wherein, B>0, C>0.

[0057] Optionally, to reduce the load of the gate driving circuit GDC, the control terminal of the first switching transistor Ts1 of the nth-stage gate driving circuit GDC(n) is electrically connected to the third node P(n-B) of the (n-B)th-stage gate driving circuit GDC(n-B), so that the first switching transistor Ts1 of the nth-stage gate driving circuit GDC(n) is turned on or off according to the potential of the third node P of the (n-B)th-stage gate driving circuit GDC(n-B) (i.e., corresponding to the first output control signal ST1). The control terminal of the second switching transistor Ts2 of the nth-stage gate driving circuit GDC(n) is electrically connected to the third node P(n-C) of the (n-C)th-stage gate driving circuit GDC(n-C), so that the second switching transistor Ts2 of the nth-stage gate driving circuit GDC(n) is turned on or off according to the potential of the third node P of the (n-C)th-stage gate driving circuit GDC(n-C) (i.e., corresponding to the second output control signal ST2).

[0058] Optionally, in some embodiments, A = 1, B = 10, C = 2, so that the pulse width of the effective pulse of the first gate control signal Nscan is greater than the pulse width of the effective pulse of the second gate control signal Pscan.

[0059] Accordingly, the control terminal of the second transistor T2 of the first-stage gate driving circuit GDC(1) is configured to receive the start signal stv, and the control terminals of the second transistors T2 of the subsequent stages of gate driving circuits GDC after the first-stage gate driving circuit GDC(1) are configured to receive the first gate control signal Nscan output by the previous-stage gate driving circuit GDC (for example, the control terminal of the second transistor T2 of the nth-stage gate driving circuit GDC(n) is configured to receive the first gate control signal Nscan(n - 1) output by the (n - 1)th-stage gate driving circuit GDC(n - 1)). The first output control signal ST1 received by the control terminals of the first switching transistors Ts1 of the first-stage gate driving circuit GDC(1) to the tenth-stage gate driving circuit GDC(10) corresponds to a low-level signal VGL, and the control terminals of the first switching transistors Ts1 of the subsequent stages of gate driving circuits after the tenth-stage gate driving circuit GDC(10) are configured to receive the first gate control signal Nscan output by the previous 10-stage gate driving circuit (for example, the control terminal of the first switching transistor Ts1 of the nth-stage gate driving circuit GDC(n) is configured to receive the (n - 10)th-stage first gate control signal Nscan(n - 10) output by the (n - 10)th-stage gate driving circuit GDC(n - 10)); the second output control signal ST2 received by the control terminals of the second switching transistors Ts2 of the first-stage gate driving circuit GDC(1) to the second-stage gate driving circuit GDC(2) corresponds to a low-level signal VGL, and the control terminals of the second switching transistors Ts2 of the subsequent stages of gate driving circuits after the second-stage gate driving circuit GDC(2) are configured to receive the first gate control signal Nscan output by the previous 2-stage gate driving circuit (the control terminal of the second switching transistor Ts2 of the nth-stage gate driving circuit GDC(n) is configured to receive the (n - 2)th-stage first gate control signal Nscan(n - 2) output by the (n - 2)th-stage gate driving circuit GDC(n - 2)), as Figure 1A shown.

[0060] Taking the example that multiple gate driving circuits GDC adopt a two-frequency control signal LF to respectively control the level states of the first gate control signal Nscan and the second gate control signal Pscan, the circuit structure of the gate driving circuit GDC will be described below. Please continue to refer to Figure 2D , the frequency division control module 50 is designed corresponding to the first output module 30 and the second output module 40, and the frequency division control module 50 controls the signal transmission between the first power supply terminal PVGL and the second node K2 according to the frequency division control signal LF.

[0061] Please continue to refer to Figure 2DThe second node K2 includes a first sub-node K21 and a second sub-node K22 , the frequency division control signal LF includes a first frequency division control signal NLF and a second frequency division control signal PLF, and the frequency division control module 50 includes a first frequency division control module 501 and a second frequency division control module 502 .

[0062] The first frequency division control module 501 is electrically connected to the first node K1 and the first sub-node K21 , and is configured to control signal transmission between the first power terminal PVGL and the first sub-node K21 according to a first frequency division control signal NLF.

[0063] The second frequency division control module 502 is electrically connected to the first node K1 and the second sub-node K22 , and is configured to control signal transmission between the first power terminal PVGL and the second sub-node K22 according to a second frequency division control signal PLF.

[0064] The first output module 30 is electrically connected to the first sub-node K21, and is configured to output the first gate control signal Nscan of the gate drive circuit GDC of this stage according to the potential of the first node K1 and the potential of the first sub-node K21. The second output module 40 is electrically connected to the second sub-node K22, and is configured to output the second gate control signal Pscan of the gate drive circuit GDC of this stage according to the potential of the second sub-node K22 and the potential of the third node P.

[0065] The first frequency division control module 501 is set to control the signal transmission between the first node K1 and the first subnode K21, thereby controlling the level state of the first gate control signal Nscan. The second frequency division control module 502 is set to control the signal transmission between the first node K1 and the second subnode K22, thereby controlling the level state of the second gate control signal Pscan. The first frequency division control module 501 and the second frequency division control module 502 cooperate with each other to realize the control of the level state of the first gate control signal Nscan and the second gate control signal Pscan.

[0066] Optionally, see Figure 2D The first frequency division control module 501 includes a first frequency division transistor Tf1, a second frequency division transistor Tf2 and a first capacitor C1.

[0067] The control end of the first frequency-dividing transistor Tf1 is electrically connected to the third node P of the current-stage gate driving circuit GDC, and the input end of the first frequency-dividing transistor Tf1 is configured to receive the first frequency-dividing control signal NLF.

[0068] The control end of the second frequency dividing transistor Tf2 is electrically connected to the output end of the first frequency dividing transistor Tf1 , the input end of the second frequency dividing transistor Tf2 is electrically connected to the first node K1 , and the output end of the second frequency dividing transistor Tf2 is electrically connected to the first sub-node K21 .

[0069] A first end of the first capacitor C1 is electrically connected to the control end of the second frequency-dividing transistor Tf2 , and a second end of the first capacitor C1 is electrically connected to the first sub-node K21 .

[0070] Optionally, see Figure 2D The second frequency division control module 502 includes a third frequency division transistor Tf3, a fourth frequency division transistor Tf4 and a second capacitor C2.

[0071] The control end of the third frequency-dividing transistor Tf3 is electrically connected to the third node P of the gate driving circuit GDC at the same stage, and the input end of the third frequency-dividing transistor Tf3 is configured to receive the second frequency-dividing control signal PLF.

[0072] The control end of the fourth frequency dividing transistor Tf4 is electrically connected to the output end of the third frequency dividing transistor Tf3 , the input end of the fourth frequency dividing transistor Tf4 is electrically connected to the first node K1 , and the output end of the fourth frequency dividing transistor Tf4 is electrically connected to the second sub-node K22 .

[0073] A first end of the second capacitor C2 is electrically connected to the control end of the fourth frequency-dividing transistor Tf4 , and a second end of the second capacitor C2 is electrically connected to the second sub-node K22 .

[0074] By making the control end of the first frequency-dividing transistor Tf1 and the control end of the third frequency-dividing transistor Tf3 controlled by the third node P of the gate driving circuit GDC at this stage, when the level state of the first frequency-dividing control signal NLF and the second frequency-dividing control signal PLF of the gate driving unit changes, the gate control signal output by the corresponding multi-stage gate driving circuit GDC can still meet the design expectations, thereby reducing the probability of abnormality in the multi-stage first gate control signal Nscan and the second gate control signal Pscan output by the gate driving unit.

[0075] Because the first frequency-division control module 501 is designed corresponding to the first output module 30, and the second frequency-division control module 502 is designed corresponding to the second output module 40, therefore, when the multi-stage gate drive circuit GDC is controlled by the first frequency-division control signal NLF and the second frequency-division control signal PLF, the connection relationship between the first output module 30 and the second output module 40 is different from the connection relationship between the first output module 30 and the second output module 40 when the multi-stage gate drive circuit GDC is controlled by a frequency-division control signal LF.

[0076] Accordingly, please continue to refer to Figure 2D, the first output module 30 includes a first output transistor To1 and a second output transistor To2.

[0077] The first control terminal and the second control terminal of the first output transistor To1 are electrically connected to the first node K1 , and the input terminal of the first output transistor To1 is electrically connected to the third power terminal NVGL.

[0078] The control end of the second output transistor To2 is electrically connected to the first subnode K21, the input end of the second output transistor To2 is electrically connected to the fourth power supply end NVGH, and the output end of the second output transistor To2 and the output end of the first output transistor To1 are electrically connected to the first output end Nout of the gate drive circuit GDC at this level.

[0079] Please continue reading Figure 2D The second output module 40 includes a third output transistor To3, a fourth output transistor To4 and a storage capacitor C0.

[0080] The control end of the third output transistor To3 is electrically connected to the second sub-node K22 , and the input end of the third output transistor To3 is configured to receive the corresponding second clock signal CK.

[0081] The control end of the fourth output transistor To4 is electrically connected to the third node P, the input end of the fourth output transistor To4 is electrically connected to the second power supply end PVGH, and the output end of the fourth output transistor To4 and the output end of the third output transistor To3 are electrically connected to the second output end Pout of the gate drive circuit GDC at this level.

[0082] A first end of the storage capacitor C0 is electrically connected to the control end of the third output transistor To3 , and a second end of the storage capacitor C0 is electrically connected to the second output end Pout of the current-stage gate driving circuit GDC.

[0083] That is, when the multi-stage gate drive circuit GDC is controlled by the first frequency division control signal NLF and the second frequency division control signal PLF, the control end of the second output transistor To2 is electrically connected to the first sub-node K21, and the control end of the third output transistor To3 is electrically connected to the second sub-node K22, so that the conduction and cutoff of the second output transistor To2 are controlled by the potential of the first sub-node K21, and the conduction and cutoff of the third output transistor To3 are controlled by the potential of the second sub-node K22.

[0084] Optionally, in some embodiments, at least one gate driving circuit GDC further includes a third control module 801. The third control module 801 is electrically connected to a third node P of the current-stage gate driving circuit GDC and a first sub-node K21 of the current-stage gate driving circuit GDC. The third control module 801 is configured to control signal transmission between a second power supply terminal PVGH and the first sub-node K21 according to a corresponding first clock signal XCK and the potential of the third node P.

[0085] Optionally, please continue to refer to Figure 2D , the third control module 801 includes a ninth transistor T9 and a tenth transistor T10.

[0086] A first control end and a second control end of the ninth transistor T9 are configured to receive a corresponding first clock signal XCK, and an output end of the ninth transistor T9 is electrically connected to the first sub-node K21.

[0087] A control end of the tenth transistor T10 is electrically connected to the third node P of the current-stage gate driving circuit GDC. An input end of the tenth transistor T10 is electrically connected to the second power supply terminal PVGH, and an output end of the tenth transistor T10 is electrically connected to an input end of the ninth transistor T9.

[0088] Optionally, in some embodiments, at least one gate driving circuit GDC further includes a switch module 90. The switch module 90 is electrically connected between a second frequency division control module 502 and a second sub-node K22. The switch module 90 is configured to control the electrical connection between the second frequency division control module 502 and the second sub-node K22 according to a corresponding switch control signal SC.

[0089] Optionally, please continue to refer to Figure 2D , the switch module 90 includes an eleventh transistor T11. A control end of the eleventh transistor T11 is configured to receive a switch control signal SC. An input end of the eleventh transistor T11 is electrically connected to an output end of a third frequency division transistor Tf3, and an output end of the eleventh transistor T11 is electrically connected to the second sub-node K22.

[0090] Optionally, a control end of the eleventh transistor T11 of the nth-stage gate driving circuit GDC(n) is configured to receive an (n-C)th-stage first gate control signal Nscan(n-C) output by the (n-C)th-stage gate driving circuit GDC(n-C), so as to use the (n-C)th-stage first gate control signal Nscan(n-C) output by the (n-C)th-stage gate driving circuit GDC(n-C) as the switch control signal SC received by the control end of the eleventh transistor T11 of the nth-stage gate driving circuit GDC(n).

[0091] Optionally, the switch control signal SC received by the control end of the eleventh transistor T11 of the first-stage gate driving circuit GDC(1) to the second-stage gate driving circuit GDC(2) corresponds to the low-level signal VGL, and the control end of the eleventh transistor T11 of each stage of the gate driving circuit after the second-stage gate driving circuit GDC(2) is configured to receive the first gate control signal Nscan output by the first two stages of the gate driving circuit (e.g., the control end of the eleventh transistor T11 of the n-stage gate driving circuit GDC(n) is configured to receive the n-2-stage first gate control signal Nscan(n-2) output by the n-2-stage gate driving circuit GDC(n-2)). Figure 1B shown.

[0092] Optionally, the control terminal of the eleventh transistor T11 is electrically connected to the third node P of the previous gate driving circuit GDC, so that the potential of the third node P of the previous gate driving circuit GDC is used as the switch control signal SC to control the working state of the eleventh transistor T11 and reduce the load carried by the first output terminal Nout of the gate driving circuit GDC. For example, the control terminal of the eleventh transistor T11 of the n-th gate driving circuit GDC(n) is electrically connected to the third node P of the nC-th gate driving circuit GDC(nC), so that the potential of the third node P of the nC-th gate driving circuit GDC(nC) is used as the switch control signal SC received by the control terminal of the eleventh transistor T11 of the n-th gate driving circuit GDC(n).

[0093] Optionally, in some embodiments, at least one gate driving circuit GDC further includes a fourth control module 802 .

[0094] The fourth control module 802 is electrically connected to the third node P of the gate drive circuit GDC of this level and the second sub-node K22 of the gate drive circuit GDC of this level, and the fourth control module 802 is configured to control the signal transmission between the second power supply terminal PVGH and the second sub-node K22 according to the corresponding first clock signal XCK and the potential of the third node P.

[0095] Optionally, see Figure 2D , the fourth control module 802 includes a twelfth transistor T12 and a thirteenth transistor T13.

[0096] The first control terminal and the second control terminal of the twelfth transistor T12 are configured to receive the corresponding first clock signal XCK, and the output terminal of the twelfth transistor T12 is electrically connected to the input terminal of the eleventh transistor T11.

[0097] The control terminal of the thirteenth transistor T13 is electrically connected to the third node P of the local gate driving circuit GDC. The input terminal of the thirteenth transistor T13 is electrically connected to the second power supply terminal PVGH. The output terminal of the thirteenth transistor T13 is electrically connected to the input terminal of the twelfth transistor T12.

[0098] Optionally, please continue to refer to Figures 2A - 2D , at least one gate driving circuit GDC further includes a reset module 70. The reset module 70 is electrically connected to the first node K1 and is configured to control the signal transmission between the second power supply terminal PVGH and the first node K1 according to a reset control signal Ctl.

[0099] Optionally, the reset module 70 includes a reset transistor Tr. The control terminal of the reset transistor Tr is configured to receive the reset control signal Ctl. The input terminal of the reset transistor Tr is electrically connected to the second power supply terminal PVGH. The output terminal of the reset transistor Tr is electrically connected to the first node K1.

[0100] Optionally, when the gate driving unit is applied to a display device, the reset module 70 is configured to be enabled when the display device is powered on and / or during a blanking interval.

[0101] Optionally, in some embodiments, the voltage corresponding to the first power supply terminal PVGL is less than the voltage corresponding to the second power supply terminal PVGH, and the voltage corresponding to the third power supply terminal NVGL is less than the voltage corresponding to the fourth power supply terminal NVGH.

[0102] Optionally, in some embodiments, at least one of the first transistor T1, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the twelfth transistor T12, and the first output transistor To1 may correspondingly have only one control terminal.

[0103] It can be understood that each transistor included in the gate driving circuit GDC can be one of a P-type transistor and an N-type transistor. The semiconductor of each transistor included in the gate driving circuit GDC can be one of a silicon semiconductor and an oxide semiconductor.

[0104] As Figures 3A - 3D is the timing diagram of the gate driving circuit provided by the embodiment of the present invention. Among them, Figure 3A corresponds to Figures 2A - 2C the gate driving circuit GDC shown, Figures 3B - 3C corresponds to Figure 2D the gate driving circuit GDC shown.

[0105] First, taking the example that multiple gate driving circuits GDC are controlled by the same frequency division control signal LF, the working principle of the gate driving unit will be described. That is, the second transistor T2, the third transistor T3, the fifth transistor T5, the eighth transistor T8, the first switching transistor Ts1, the second switching transistor Ts2, the second output transistor To2 to the fourth output transistor To4, and the frequency division transistor Tf are P-type transistors, the first transistor T1, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the first output transistor To1 are N-type transistors, the frequency division control signal LF has a transition from a low level state to a high level state in the p-th stage gate driving circuit GDC to the (p + q)-th stage gate driving circuit GDC(p + q) of the corresponding gate driving unit, the first clock signal XCK corresponding to the (p + 4x)-th stage gate driving circuit GDC is provided by the second clock line CKL2, the second clock signal CK corresponding to the (p + 4x)-th stage gate driving circuit GDC is provided by the first clock line CKL1, the first clock signal XCK corresponding to the (p + (4x + 1))-th stage gate driving circuit GDC is provided by the third clock line CKL3, the second clock signal CK corresponding to the (p + (4x + 1))-th stage gate driving circuit GDC is provided by the second clock line CKL2, the first clock signal XCK corresponding to the (p + (4x + 2))-th stage gate driving circuit GDC is provided by the fourth clock line CKL4, the second clock signal CK corresponding to the (p + (4x + 2))-th stage gate driving circuit GDC is provided by the third clock line CKL3, the first clock signal XCK corresponding to the (p + (4x + 3))-th stage gate driving circuit GDC is provided by the first clock line CKL1, and the second clock signal CK corresponding to the (p + (4x + 3))-th stage gate driving circuit GDC is provided by the fourth clock line CKL4 as an example, for the gate driving unit including Figures 2A - 2C the shown gate driving circuit GDC, and when the multiple gate driving circuits GDC of the gate driving unit are cascaded in the Figure 1A shown cascading manner, the working principle will be described. Among them, p ≥ 1, q ≥ 1, x ≥ 0.

[0106] Please continue to refer to Figures 2A - 2C and Figure 3A, in the first stage t1, the first clock signal CK1 provided by the first clock line CKL1 has a high level state, the second clock signal CK2 provided by the second clock line CKL2 has a low level state, the third clock signal CK3 provided by the third clock line CKL3 has a high level state, and the fourth clock signal CK4 provided by the fourth clock line CKL4 has a high level state. The (p - 10)-th stage first gate control signal Nscan(p - 10) output by the (p - 10)-th stage gate driving circuit GDC(p - 10) to the (p - 4)-th stage first gate control signal Nscan(p - 4) output by the (p - 4)-th stage gate driving circuit GDC(p - 4) have a high level state, and the (p - 3)-th stage first gate control signal Nscan(p - 3) output by the (p - 3)-th stage gate driving circuit GDC(p - 3) to the (p - 1)-th stage first gate control signal Nscan(p - 1) output by the (p - 1)-th stage gate driving circuit GDC(p - 1) have a low level state; the frequency division control signal LF has a low level state.

[0107] In the p-th stage gate driving circuit GDC(p) and the (p + 4)-th stage gate driving circuit GDC(p + 4), the second transistor T2, the third transistor T3, the second switching transistor Ts2, and the frequency division transistor Tf are turned on, and the fourth transistor T4 and the first switching transistor Ts1 are turned off. The second power supply terminal PVGH is electrically connected to the first node K1, the seventh transistor T7, the first output transistor To1, and the fourth output transistor To4 are turned on, the third power supply terminal NVGL is electrically connected to the first output terminal Nout, and the second power supply terminal PVGH is electrically connected to the second output terminal Pout. The first power supply terminal PVGL is electrically connected to the third node P, the fifth transistor T5 is turned on, and the sixth transistor T6, the eighth transistor T8, the second output transistor To2, and the third output transistor To3 are turned off.

[0108] In the (p + 1)-th stage gate driving circuit GDC(p + 1) to the (p + 3)-th stage gate driving circuit GDC(p + 3) and the (p + 5)-th stage gate driving circuit GDC(p + 5) to the (p + 7)-th stage gate driving circuit GDC(p + 7), the second transistor T2 is turned on and the third transistor T3 is turned off. Therefore, the (p + 1)-th stage first gate control signal Nscan(p + 1) to the (p + 3)-th stage first gate control signal Nscan(p + 3) and the (p + 5)-th stage first gate control signal Nscan(p + 5) to the (p + 7)-th stage first gate control signal Nscan(p + 7) maintain a low level state, and the (p + 1)-th stage second gate control signal Pscan(p + 1) to the (p + 3)-th stage second gate control signal Pscan(p + 3) and the (p + 5)-th stage second gate control signal Pscan(p + 5) to the (p + 7)-th stage second gate control signal Pscan(p + 7) maintain a high level state.

[0109] In the (p + 8)-th stage gate driving circuit GDC(p + 8), the second transistor T2, the third transistor T3, the first switching transistor Ts1, the second switching transistor Ts2, and the frequency dividing transistor Tf are turned on, the fifth transistor T5, the seventh transistor T7, the first output transistor To1, and the fourth output transistor To4 are turned on, and the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the second output transistor To2, and the third output transistor To3 are turned off.

[0110] The gate driving circuit GDC, which is located after the (p + 8)-th stage gate driving circuit GDC(p + 8) and for which the first clock signal XCK is correspondingly provided by the second clock line CKL2 and the second clock signal CK is correspondingly provided by the first clock line CKL1, performs an operation similar to that of the (p + 8)-th stage gate driving circuit GDC(p + 8) in the first stage t1. The gate driving circuit GDC, which is located after the (p + 8)-th stage gate driving circuit GDC(p + 8) and for which the first clock signal XCK is not correspondingly provided by the second clock line CKL2 and the second clock signal CK is not correspondingly provided by the first clock line CKL1, performs an operation similar to that of the (p + 7)-th stage gate driving circuit GDC(p + 7) in the first stage t1.

[0111] Please continue to refer to Figures 2A - 2C and Figure 3A , in the second stage t2, the first clock signal CK1 provided by the first clock line CKL1 has a low level state, the second clock signal CK2 provided by the second clock line CKL2 has a high level state, the third clock signal CK3 provided by the third clock line CKL3 has a high level state, and the fourth clock signal CK4 provided by the fourth clock line CKL4 has a high level state. The (p - 10)-th stage first gate control signal Nscan(p - 10) output by the (p - 10)-th stage gate driving circuit GDC(p - 10) to the (p - 9)-th stage first gate control signal Nscan(p - 9) output by the (p - 9)-th stage gate driving circuit GDC(p - 9) have a low level state, and the (p - 8)-th stage first gate control signal Nscan(p - 8) output by the (p - 8)-th stage gate driving circuit GDC(p - 8) to the (p - 1)-th stage first gate control signal Nscan(p - 1) output by the (p - 1)-th stage gate driving circuit GDC(p - 1) have a high level state; the frequency division control signal LF has a low level state.

[0112] In the p-th stage gate driving circuit GDC(p), the first switching transistor Ts1, the first transistor T1, and the frequency dividing transistor Tf are turned on, while the second switching transistor Ts2, the second transistor T2, and the third transistor T3 are turned off. The fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the first output transistor To1, and the fourth output transistor To4 remain turned on, while the sixth transistor T6, the eighth transistor T8, the second output transistor To2, and the third output transistor To3 remain turned off.

[0113] In the p+1-th stage gate driving circuit GDC(p+1) to the p+q-th stage gate driving circuit GDC(p+q), since the start signal STV received by the control terminal of the second transistor T2 has a low level state corresponding to the second stage t2, the second transistor T2 is turned on. In the gate driving circuit GDC located after the p-th stage gate driving circuit GDC(p), where the first clock signal XCK is provided by the first clock line CKL1 and the second clock signal CK is provided by the fourth clock line CKL4, the third transistor T3 is turned on, and the second power supply terminal PVGH is electrically connected to the first node K1. In the gate driving circuit GDC located after the p-th stage gate driving circuit GDC(p), where the first clock signal XCK is not provided by the first clock line CKL1 and the second clock signal CK is not provided by the fourth clock line CKL4, the third transistor T3 is turned off. The first gate control signals Nscan(p+1) to Nscan(p+q) of the p+1-th stage to the p+q-th stage remain in the low level state, and the second gate control signals Pscan(p+1) to Pscan(p+q) of the p+1-th stage to the p+q-th stage remain in the high level state.

[0114] Please continue to refer to Figures 2A - 2C and Figure 3A, in the third stage t3, the first clock signal CK1 provided by the first clock line CKL1 has a high level state, the second clock signal CK2 provided by the second clock line CKL2 has a low level state, the third clock signal CK3 provided by the third clock line CKL3 has a high level state, and the fourth clock signal CK4 provided by the fourth clock line CKL4 has a high level state. The p-10th stage first gate control signal Nscan(p-10) output by the p-10th stage gate drive circuit GDC(p-10) to the p-8th stage first gate control signal Nscan(p-8) output by the p-8th stage gate drive circuit GDC(p-8) have a low level state, and the p-7th stage first gate control signal Nscan(p-7) output by the p-7th stage gate drive circuit GDC(p-7) to the p-1st stage first gate control signal Nscan(p-1) output by the p-1st stage gate drive circuit GDC(p-1) have a high level state; the frequency division control signal LF has a low level state.

[0115] In the pth stage gate drive circuit GDC(p), the first switching transistor Ts1, the first transistor T1, the third transistor T3, and the frequency division transistor Tf are turned on, and the second switching transistor Ts2, the second transistor T2, and the fourth transistor T4 are turned off. The first power supply terminal PVGL and the first node K1 are electrically connected, the sixth transistor T6, the eighth transistor T8, and the second output transistor To2 are turned on, the fifth transistor T5, the seventh transistor T7, the first output transistor To1, and the fourth output transistor To4 are turned off, and the third output transistor To3 remains turned off. The first output terminal Nout is electrically connected to the third power supply terminal NVGL, and the second output terminal Pout maintains the output state of the first stage t1.

[0116] The (p + 1)th stage gate drive circuit GDC(p + 1) performs actions similar to those performed by the pth stage gate drive circuit GDC(p) in the second stage t2 in the third stage t3. The (p + 2)th stage gate drive circuit GDC(p + 2) performs actions similar to those performed by the (p + 1)th stage gate drive circuit GDC(p + 1) in the second stage t2 in the third stage t3, and so on to obtain the actions performed by the (p + 3)th stage gate drive circuit GDC(p + 3) to the (p + q)th stage gate drive circuit GDC(p + q) in the third stage t3.

[0117] Please continue to refer to Figures 2A - 2C and Figure 3A, in the fourth stage t4, the first clock signal CK1 provided by the first clock line CKL1 has a high level state, the second clock signal CK2 provided by the second clock line CKL2 has a high level state, the third clock signal CK3 provided by the third clock line CKL3 has a low level state, and the fourth clock signal CK4 provided by the fourth clock line CKL4 has a high level state. The first gate control signal Nscan(p - 10) output by the (p - 10)-th stage gate drive circuit GDC(p - 10) to the first gate control signal Nscan(p - 7) output by the (p - 7)-th stage gate drive circuit GDC(p - 7) have a low level state, and the first gate control signal Nscan(p - 6) output by the (p - 6)-th stage gate drive circuit GDC(p - 6) has a high level state; the frequency division control signal LF has a low level state.

[0118] In the p-th stage gate drive circuit GDC(p), the first switching transistor Ts1, the first transistor T1, the frequency division transistor Tf, the sixth transistor T6, the eighth transistor T8, and the second output transistor To2 remain conducting, the fourth transistor T4 conducts, the third transistor T3 cuts off, and the second switching transistor Ts2, the second transistor T2, the fifth transistor T5, the seventh transistor T7, the first output transistor To1, the fourth output transistor To4, and the third output transistor To3 remain cut off. The first output terminal Nout is electrically connected to the third power supply terminal NVGL, and the second output terminal Pout maintains the output state of the third stage t3.

[0119] The (p + 1)-th stage gate drive circuit GDC(p + 1) performs actions similar to those performed by the p-th stage gate drive circuit GDC(p) in the third stage t3 in the fourth stage t4. The (p + 2)-th stage gate drive circuit GDC(p + 2) performs actions similar to those performed by the (p + 1)-th stage gate drive circuit GDC(p + 1) in the third stage t3 in the fourth stage t4, and so on to obtain the actions performed by the (p + 3)-th stage gate drive circuit GDC(p + 3) to the (p + q)-th stage gate drive circuit GDC(p + q) in the fourth stage t4.

[0120] Please continue to refer to Figures 2A - 2C and Figure 3A, in the fifth stage t5, the first clock signal CK1 provided by the first clock line CKL1 has a high level state, the second clock signal CK2 provided by the second clock line CKL2 has a high level state, the third clock signal CK3 provided by the third clock line CKL3 has a high level state, and the fourth clock signal CK4 provided by the fourth clock line CKL4 has a low level state. The first gate control signals Nscan(p - 10) of the (p - 10)-th stage gate drive circuit GDC(p - 10) to the first gate control signal Nscan(p - 2) of the (p - 2)-th stage gate drive circuit GDC(p - 2) have a low level state, and the first gate control signal Nscan(p - 1) of the (p - 1)-th stage gate drive circuit GDC(p - 1) has a high level state; the frequency division control signal LF has a low level state.

[0121] In the p-th stage gate drive circuit GDC(p), the first switching transistor Ts1, the first transistor T1, and the frequency division transistor Tf remain conducting, the second switching transistor Ts2 conducts, so that the third output transistor To3 conducts, and the corresponding first clock signal XCK is transmitted to the second output terminal Pout. The second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the first output transistor To1, and the fourth output transistor To4 remain cut off. The fourth transistor T4 conducts, the sixth transistor T6, the eighth transistor T8, and the second output transistor To2 remain conducting, and the first output terminal Nout is electrically connected to the third power supply terminal NVGL.

[0122] In the (p + 1)-th stage gate drive circuit GDC(p + 1), the (p + 3)-th stage gate drive circuit GDC(p + 3) to the (p + 5)-th stage gate drive circuit GDC(p + 5), the corresponding first clock signal XCK has a high level state, the third transistor T3 is cut off, and the second output transistor To2 remains conducting. In the (p + 2)-th stage gate drive circuit GDC(p + 2), the corresponding first clock signal XCK has a low level state, the third transistor T3 conducts, the second switching transistor Ts2 is cut off, the first power supply terminal PVGL is electrically connected to the first node K1, and the second output transistor To2 remains conducting. The (p + 6)-th stage gate drive circuit GDC(p + 6) performs actions similar to those performed by the p-th stage gate drive circuit GDC(p) in the third stage t3 in the fifth stage t5, the (p + 7)-th stage gate drive circuit GDC(p + 7) performs actions similar to those performed by the (p + 1)-th stage gate drive circuit GDC(p + 1) in the third stage t3 in the fifth stage t5, and so on to obtain the actions performed by the (p + 8)-th stage gate drive circuit GDC(p + 8) to the (p + q)-th stage gate drive circuit GDC(p + q) in the fifth stage t5.

[0123] Please continue to refer to Figures 2A - 2C and Figure 3A In the sixth stage t6, the first clock signal CK1 provided by the first clock line CKL1 has a low level state, the second clock signal CK2 provided by the second clock line CKL2 has a high level state, the third clock signal CK3 provided by the third clock line CKL3 has a high level state, and the fourth clock signal CK4 provided by the fourth clock line CKL4 has a high level state. The first gate control signal Nscan(p - 10) output by the (p - 10)-th stage gate drive circuit GDC(p - 10) to the first gate control signal Nscan(p - 1) output by the (p - 1)-th stage gate drive circuit GDC(p - 1) have a low level state, and the frequency division control signal LF has a low level state.

[0124] In the p-th stage gate drive circuit GDC(p), the second transistor T2 is turned on, the first switching transistor Ts1, the second switching transistor Ts2, the frequency division transistor Tf, and the third output transistor To3 remain turned on, and the corresponding first clock signal XCK is transmitted to the second output terminal Pout, so that the second gate control signal Pscan(p) of the p-th stage has a low level state. The third transistor T3, the fifth transistor T5, the seventh transistor T7, the first output transistor To1, and the fourth output transistor To4 remain turned off. The fourth transistor T4, the sixth transistor T6, the eighth transistor T8, and the second output transistor To2 remain turned on, and the first output terminal Nout is electrically connected to the third power supply terminal NVGL.

[0125] The (p + 1)-th stage gate drive circuit GDC(p + 1) performs an action similar to that performed by the p-th stage gate drive circuit GDC(p) in the fifth stage t5 in the sixth stage t6. The (p + 2)-th stage gate drive circuit GDC(p + 2) performs an action similar to that performed by the (p + 1)-th stage gate drive circuit GDC(p + 1) in the fifth stage t5 in the sixth stage t6, and so on to obtain the actions performed by the (p + 3)-th stage gate drive circuit GDC(p + 3) to the (p + q)-th stage gate drive circuit GDC(p + q) in the sixth stage t6.

[0126] Please continue to refer to Figures 2A - 2C and Figure 3A, in the seventh stage t7, the first clock signal CK1 provided by the first clock line CKL1 has a high level state, the second clock signal CK2 provided by the second clock line CKL2 has a low level state, the third clock signal CK3 provided by the third clock line CKL3 has a high level state, and the fourth clock signal CK4 provided by the fourth clock line CKL4 has a high level state. The first gate control signals Nscan(p - 10) output by the (p - 10)-th stage gate drive circuit GDC(p - 10) to the first gate control signal Nscan(p - 1) output by the (p - 1)-th stage gate drive circuit GDC(p - 1) have a low level state, and the frequency division control signal LF has a low level state.

[0127] In the p-th stage gate drive circuit GDC(p), the second transistor T2, the third transistor T3, the first switching transistor Ts1, the second switching transistor Ts2, and the frequency division transistor Tf are turned on, the second power supply terminal PVGH is electrically connected to the first node K1, the fifth transistor T5, the seventh transistor T7, the first output transistor To1, and the fourth output transistor To4 are turned on, and the first transistor T1, the fourth transistor T4, the sixth transistor T6, the second output transistor To2, and the third output transistor To3 are turned off. The third power supply terminal NVGL and the first output terminal Nout are electrically connected, and the second power supply terminal PVGH and the second output terminal Pout are electrically connected.

[0128] The (p + 1)-th stage gate drive circuit GDC(p + 1) performs an action similar to the action performed by the p-th stage gate drive circuit GDC(p) in the sixth stage t6 in the seventh stage t7, and the second gate control signal Pscan(p + 1) of the (p + 1)-th stage has a low level state. The (p + 2)-th stage gate drive circuit GDC(p + 2) performs an action similar to the action performed by the (p + 1)-th stage gate drive circuit GDC(p + 1) in the sixth stage t6 in the seventh stage t7, and so on to obtain the actions performed by the (p + 3)-th stage gate drive circuit GDC(p + 3) to the (p + q)-th stage gate drive circuit GDC(p + q) in the seventh stage t7.

[0129] Please continue to refer to Figures 2A - 2C and Figure 3A, in the eighth stage t8, the first clock signal CK1 provided by the first clock line CKL1 has a high level state, the second clock signal CK2 provided by the second clock line CKL2 has a high level state, the third clock signal CK3 provided by the third clock line CKL3 has a low level state, and the fourth clock signal CK4 provided by the fourth clock line CKL4 has a high level state. The first gate control signals Nscan(p - 10) of the (p - 10)-th stage gate driving circuit GDC(p - 10) to the first gate control signal Nscan(p - 1) of the (p - 1)-th stage gate driving circuit GDC(p - 1) have a low level state, and the frequency division control signal LF has a high level state.

[0130] In the p-th stage gate driving circuit GDC(p), the second transistor T2, the first switching transistor Ts1, the second switching transistor Ts2, the fifth transistor T5, the seventh transistor T7, the first output transistor To1, and the fourth output transistor To4 remain conducting, the third transistor T3 and the frequency division transistor Tf are cut off, the fourth transistor T4 is conducting, and the first transistor T1, the sixth transistor T6, the second output transistor To2, and the third output transistor To3 remain cut off.

[0131] In the (p + 1)-th to (p + q)-th level gate driving circuits GDC(p + 1) to GDC(p + q), since the frequency dividing transistor Tf is cut off, the potential of the first node K1 maintains the state of the seventh stage t7, causing the second output transistors To2 in the (p + 1)-th to (p + 8)-th level gate driving circuits GDC(p + 1) to GDC(p + 8) to conduct, so that the first output terminals Nout of the (p + 1)-th to (p + 8)-th level gate driving circuits GDC(p + 1) to GDC(p + 8) are electrically connected to the fourth power supply terminal NVGH. The second switching transistors Ts2 and the second output transistors To2 in the (p + 1)-th to (p + 2)-th level gate driving circuits GDC(p + 1) to GDC(p + 2) conduct, the second output terminals Pout of the (p + 1)-th to (p + 2)-th level gate driving circuits GDC(p + 1) to GDC(p + 2) receive the corresponding second clock signal CK, and the (p + 2)-th second gate control signal Pscan(p + 2) has a low level state. In the (p + 9)-th to (p + q)-th level gate driving circuits GDC(p + 9) to GDC(p + q), the first output transistors To1 and the fourth output transistors To4 conduct, so that the first output terminals Nout of the (p + 9)-th to (p + q)-th level gate driving circuits GDC(p + 9) to GDC(p + q) are electrically connected to the third power supply terminal NVGL, and the second output terminals Pout are electrically connected to the second power supply terminal PVGH. Therefore, no effective pulse is output from the (p + 9)-th first gate control signal Nscan(p + 9) of the (p + 9)-th level gate driving circuit GDC(p + 9).

[0132] Please continue to refer to Figures 2A - 2C and Figure 3A In the ninth stage t9, the first clock signal CK1 provided by the first clock line CKL1 has a high level state, the second clock signal CK2 provided by the second clock line CKL2 has a high level state, the third clock signal CK3 provided by the third clock line CKL3 has a high level state, and the fourth clock signal CK4 provided by the fourth clock line CKL4 has a low level state. The (p - 10)-th first gate control signal Nscan(p - 10) output by the (p - 10)-th level gate driving circuit GDC(p - 10) to the (p - 1)-th first gate control signal Nscan(p - 1) output by the (p - 1)-th level gate driving circuit GDC(p - 1) have low level states, and the frequency dividing control signal LF has a high level state.

[0133] The p-th stage gate drive circuit GDC(p) maintains the same state as that in the eighth stage t8 during the ninth stage t9. In the (p + 1)-th stage gate drive circuit GDC(p + 1) to the (p + q)-th stage gate drive circuit GDC(p + q), since the frequency division transistor Tf is cut off, the potential of the first node K1 maintains the state of the eighth stage t8, resulting in the conduction of the second output transistor To2 and the third output transistor To3 in the (p + 1)-th stage gate drive circuit GDC(p + 1) to the (p + 8)-th stage gate drive circuit GDC(p + 8), so that the first output terminal Nout of the (p + 1)-th stage gate drive circuit GDC(p + 1) to the (p + 8)-th stage gate drive circuit GDC(p + 8) is electrically connected to the fourth power supply terminal NVGH. The second switching transistor Ts2 and the second output transistor To2 in the (p + 1)-th stage gate drive circuit GDC(p + 1) to the (p + 2)-th stage gate drive circuit GDC(p + 2) are conducting, and the second output terminal Pout of the (p + 1)-th stage gate drive circuit GDC(p + 1) to the (p + 2)-th stage gate drive circuit GDC(p + 2) receives the corresponding second clock signal CK. The second switching transistor Ts2 and the second output transistor To2 in the (p + 3)-th stage gate drive circuit GDC(p + 3) are cut off, and there is no valid pulse in the (p + 3)-th stage second control signal of the (p + 3)-th stage gate drive circuit GDC(p + 3). In the (p + 9)-th stage gate drive circuit GDC(p + 9) to the (p + q)-th stage gate drive circuit GDC(p + q), the first output transistor To1 and the fourth output transistor To4 are conducting, so that the first output terminal Nout of the (p + 9)-th stage gate drive circuit GDC(p + 9) to the (p + q)-th stage gate drive circuit GDC(p + q) is electrically connected to the third power supply terminal NVGL, and the second output terminal Pout is electrically connected to the second power supply terminal PVGH. Therefore, there is no valid pulse output in the (p + 9)-th stage first gate control signal Nscan(p + 9) output by the (p + 9)-th stage gate drive circuit GDC(p + 9) to the (p + 10)-th stage first gate control signal Nscan(p + 10) output by the (p + 10)-th stage gate drive circuit GDC(p + 10).

[0134] After that, the frequency division control signal LF maintains a high level state, the first clock signal CK1 to the fourth clock signal CK4 have a switching between a high level state and a low level state, there is no valid pulse output in the (p + 9)-th stage first gate control signal Nscan(p + 9) output by the (p + 9)-th stage gate drive circuit GDC(p + 9) to the (p + q)-th stage first gate control signal Nscan(p + q) output by the (p + q)-th stage gate drive circuit GDC(p + q), and there is no valid pulse output in the (p + 9)-th stage second gate control signal Pscan(p + 9) output by the (p + 9)-th stage gate drive circuit GDC(p + 9) to the (p + q)-th stage second gate control signal Pscan(p + q) output by the (p + q)-th stage gate drive circuit GDC(p + q).

[0135] Among them, in the eighth stage t8 and the ninth stage t9, Figure 2A the electrical connection between the third transistor T3 and the first node K1 of the shown gate driving circuit GDC is disconnected. Figure 2B the control terminal of the first transistor T1 of the shown gate driving circuit GDC does not receive the corresponding start signal STV. Figure 2C the control terminal of the third transistor T3 of the shown gate driving circuit GDC does not receive the corresponding first clock signal XCK.

[0136] Therefore, by controlling the frequency division control signal LF, the level states of the gate control signals output by multiple gate driving circuits GDC can be controlled, so that when the gate driving unit is applied to a display panel, it is beneficial for the display panel to implement frequency division and zoning settings.

[0137] Next, taking multiple gate driving circuits GDC being controlled by the first frequency division control signal NLF and the second frequency division control signal PLF as an example, the working principle of the gate driving unit will be described. That is, taking the second transistor T2, the third transistor T3, the fifth transistor T5, the eighth transistor T8, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency division transistor Tf1 to the fourth frequency division transistor Tf4, the second output transistor To2 to the fourth output transistor To4 as P-type transistors, the first transistor T1, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the twelfth transistor T12 and the first output transistor To1 as N-type transistors, the first clock signal XCK corresponding to the p + 4x -th stage gate driving circuit GDC is provided by the second clock line CKL2, the second clock signal CK corresponding to the p + 4x -th stage gate driving circuit GDC is provided by the first clock line CKL1, the first clock signal XCK corresponding to the p + (4x + 1)-th stage gate driving circuit GDC is provided by the third clock line CKL3, the second clock signal CK corresponding to the p + (4x + 1)-th stage gate driving circuit GDC is provided by the second clock line CKL2, the first clock signal XCK corresponding to the p + (4x + 2)-th stage gate driving circuit GDC is provided by the fourth clock line CKL4, the second clock signal CK corresponding to the p + (4x + 2)-th stage gate driving circuit GDC is provided by the third clock line CKL3, the first clock signal XCK corresponding to the p + (4x + 3)-th stage gate driving circuit GDC is provided by the first clock line CKL1, the second clock signal CK corresponding to the p + (4x + 3)-th stage gate driving circuit GDC is provided by the fourth clock line CKL4 as an example, for the gate driving unit including Figure 2D the shown gate driving circuit GDC, and multiple gate driving circuits GDC of the gate driving unit adopt Figure 1BThe operating principle when cascading in the shown cascading manner will be described. Here, p ≥ 1, q ≥ 1, and x ≥ 0.

[0138] Please continue to refer to Figure 2D and Figure 3B , and first, take the example where the first frequency division control signal NLF has a transition from a low level state to a high level state in the p-th stage gate driving circuit GDC(p) to the (p + q)-th stage gate driving circuit GDC(p + q) of the corresponding gate driving unit for explanation.

[0139] In the first stage t1, the first clock signal CK1 has a high level state, the second clock signal CK2 has a low level state, the third clock signal CK3 has a high level state, and the fourth clock signal CK4 has a high level state. The (p - 2)-th stage first gate control signal Nscan(p - 2) output by the (p - 2)-th stage gate driving circuit GDC(p - 2) to the (p - 1)-th stage first gate control signal Nscan(p - 1) output by the (p - 1)-th stage gate driving circuit GDC(p - 1) have a low level state. The first frequency division control signal NLF has a low level state, and the second frequency division control signal PLF has a low level state.

[0140] In the p-th stage gate driving circuit GDC(p), the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency division transistor Tf1 to the fourth frequency division transistor Tf4, the first output transistor To1, and the fourth output transistor To4 are turned on, and the first transistor T1, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, the second output transistor To2, and the third output transistor To3 are turned off. The third power supply terminal NVGL is electrically connected to the first output terminal Nout, and the second power supply terminal PVGH is electrically connected to the second output terminal Pout.

[0141] In the (p + 1)-th stage gate driving circuit GDC(p + 1) to the (p + 3)-th stage gate driving circuit GDC(p + 3), the second transistor T2 is turned on, and the third transistor T3 is turned off. Therefore, the (p + 1)-th stage first gate control signal Nscan(p + 1) to the (p + 3)-th stage first gate control signal Nscan(p + 3) maintain a low level state, and the (p + 1)-th stage second gate control signal Pscan(p + 1) to the (p + 3)-th stage second gate control signal Pscan(p + 3) maintain a high level state. In the first stage t1, the (p + 4)-th stage gate driving circuit GDC(p + 4) performs actions similar to those of the p-th stage gate driving circuit GDC(p).

[0142] After the gate driving circuit GDC(p + 4) at the (p + 4)-th level, and the first clock signal XCK is correspondingly provided by the second clock line CKL2, and the second clock signal CK is correspondingly provided by the first clock line CKL1, the gate driving circuit GDC performs actions similar to those of the gate driving circuit GDC(p) at the p-th level in the first stage t1. After the gate driving circuit GDC(p + 4) at the (p + 4)-th level, and the first clock signal XCK is not correspondingly provided by the second clock line CKL2, and the second clock signal CK is not correspondingly provided by the first clock line CKL1, the gate driving circuit GDC performs actions similar to those of the gate driving circuit GDC(p + 1) to GDC(p + 3) at the (p + 1)-th to (p + 3)-th levels in the first stage t1.

[0143] In the second stage t2, the first clock signal CK1 has a high level state, the second clock signal CK2 has a low level state, the third clock signal CK3 has a high level state, and the fourth clock signal CK4 has a high level state. The (p - 1)-th first gate control signal Nscan(p - 1) output by the gate driving circuit GDC(p - 1) to the (p - 2)-th first gate control signal Nscan(p - 2) output by the gate driving circuit GDC(p - 2) have high level states. The first frequency division control signal NLF has a low level state, and the second frequency division control signal PLF has a low level state.

[0144] In the gate driving circuit GDC(p), the first transistor T1, the third transistor T3, the sixth transistor T6, the eighth transistor T8, and the second output transistor To2 are turned on, the second frequency division transistor Tf2 and the fourth frequency division transistor Tf4 remain turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the first frequency division transistor Tf1, the third frequency division transistor Tf3, the first output transistor To1, the third output transistor To3, and the fourth output transistor To4 are turned off. The fourth power supply terminal NVGH is electrically connected to the first output terminal Nout, and the (p)-th second gate control signal Pscan output by the second output terminal Pout maintains a high level state.

[0145] In the (p + 1)-th stage gate driving circuit GDC(p + 1), the first transistor T1 is turned on, the third transistor T3 is turned off, the (p + 1)-th stage first gate control signal Nscan(p + 1) maintains a low level state, and the (p + 1)-th stage second gate control signal Pscan(p + 1) maintains a high level state. In the (p + 2)-th stage gate driving circuit GDC(p + 2), the second transistor T2 is turned on, the third transistor T3 is turned off, the (p + 2)-th stage first gate control signal Nscan(p + 2) maintains a low level state, and the (p + 2)-th stage second gate control signal Pscan(p + 2) maintains a high level state.

[0146] The gate driving circuit GDC, which is located after the (p + 2)-th stage gate driving circuit GDC(p + 2) and for which the first clock signal XCK is correspondingly provided by the second clock line CKL2 and the second clock signal CK is correspondingly provided by the first clock line CKL1, performs actions similar to those performed by the p-th stage gate driving circuit GDC(p) in the first stage t1 in the second stage t2. The gate driving circuit GDC, which is located after the (p + 2)-th stage gate driving circuit GDC(p + 2) and for which the first clock signal XCK is not correspondingly provided by the second clock line CKL2 and the second clock signal CK is not correspondingly provided by the first clock line CKL1, performs actions similar to those performed by the (p + 1)-th stage gate driving circuit GDC(p + 1) to the (p + 3)-th stage gate driving circuit GDC(p + 3) in the first stage t1 in the second stage t2.

[0147] In the third stage t3, the first clock signal CK1 has a high level state, the second clock signal CK2 has a high level state, the third clock signal CK3 has a low level state, and the fourth clock signal CK4 has a high level state. The (p - 1)-th stage first gate control signal Nscan(p - 1) output by the (p - 1)-th stage gate driving circuit GDC(p - 1) to the (p - 2)-th stage first gate control signal Nscan(p - 2) output by the (p - 2)-th stage gate driving circuit GDC(p - 2) have a high level state. The first frequency division control signal NLF has a low level state, and the second frequency division control signal PLF has a low level state.

[0148] In the p-th stage gate driving circuit GDC(p), the first transistor T1, the sixth transistor T6, the eighth transistor T8, the second output transistor To2, the second frequency-dividing transistor Tf2, and the fourth frequency-dividing transistor Tf4 remain conducting, the fourth transistor T4, the ninth transistor T9, and the twelfth transistor T12 conduct, the third transistor T3 is cut off, and the second transistor T2, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the first output transistor To1, the third output transistor To3, and the fourth output transistor To4 remain cut off. The fourth power supply terminal NVGH is electrically connected to the first output terminal Nout, and the p-th stage second gate control signal Pscan output from the second output terminal Pout remains at a high level state.

[0149] The (p + 1)-th stage gate driving circuit GDC(p + 1) performs an action similar to the action performed by the p-th stage gate driving circuit GDC(p) in the second stage t2 during the third stage t3, so that the fourth power supply terminal NVGH of the (p + 1)-th stage gate driving circuit GDC(p + 1) is electrically connected to the first output terminal Nout, and the (p + 1)-th stage second gate control signal Pscan(p + 1) remains at a high level state. The (p + 2)-th stage gate driving circuit GDC(p + 2) performs an action similar to the action performed by the (p + 1)-th stage gate driving circuit GDC(p + 1) in the second stage t2 during the third stage t3. And so on, the actions performed by the (p + 3)-th stage gate driving circuit GDC(p + 3) to the (p + q)-th stage gate driving circuit GDC(p + q) during the third stage t3 are obtained.

[0150] Fourth stage t4: The first clock signal CK1 has a low level state, the second clock signal CK2 has a high level state, the third clock signal CK3 has a high level state, and the fourth clock signal CK4 has a high level state. The (p - 1)-th stage first gate control signal Nscan(p - 1) output from the (p - 1)-th stage gate driving circuit GDC(p - 1) to the (p - 2)-th stage first gate control signal Nscan(p - 2) output from the (p - 2)-th stage gate driving circuit GDC(p - 2) have low level states. The first frequency-dividing control signal NLF has a low level state, and the second frequency-dividing control signal PLF has a low level state.

[0151] In the p-th stage gate driving circuit GDC(p), the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, the second frequency-dividing transistor Tf2, the fourth frequency-dividing transistor Tf4, the second output transistor To2, and the third output transistor To3 are turned on, while the first transistor T1, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the first output transistor To1, and the fourth output transistor To4 are turned off. The fourth power supply terminal NVGH is electrically connected to the first output terminal Nout, and the p-th stage second gate control signal Pscan output from the second output terminal Pout has a low level state.

[0152] In the (p + 1)-th stage gate driving circuit GDC(p + 1) to the (p + 2)-th stage gate driving circuit GDC(p + 2) and the (p + 4)-th stage gate driving circuit GDC(p + 4) to the (p + 5)-th stage gate driving circuit GDC(p + 5), the third transistor T3 is turned off. Therefore, the potentials of the first node K1 and the third node P in the (p + 1)-th stage gate driving circuit GDC(p + 1) to the (p + 2)-th stage gate driving circuit GDC(p + 2) and the (p + 4)-th stage gate driving circuit GDC(p + 4) to the (p + 5)-th stage gate driving circuit GDC(p + 5) maintain the same state as that in the third stage t3. In the (p + 3)-th stage gate driving circuit GDC(p + 3), the first transistor T1 and the third transistor T3 are turned on, and the first power supply terminal PVGL is electrically connected to the first node K1. Therefore, the (p + 1)-th stage first gate control signal Nscan(p + 1) to the (p + 5)-th stage first gate control signal Nscan(p + 5) maintain a high level state, and the (p + 1)-th stage first gate control signal Nscan(p + 1) to the (p + 5)-th stage first gate control signal Nscan(p + 5) maintain a high level state.

[0153] The (p + 6)-th stage gate driving circuit GDC(p + 6) performs an operation similar to that performed by the p-th stage gate driving circuit GDC(p) in the third stage t3 in the fourth stage t4. The (p + 7)-th stage gate driving circuit GDC(p + 7) performs an operation similar to that performed by the (p + 1)-th stage gate driving circuit GDC(p + 1) in the third stage t3 in the fourth stage t4. And so on, the operations performed by the (p + 8)-th stage gate driving circuit GDC(p + 8) to the (p + q)-th stage gate driving circuit GDC(p + q) in the fourth stage t4 are obtained.

[0154] Fifth stage t5: The first clock signal CK1 has a high level state, the second clock signal CK2 has a low level state, the third clock signal CK3 has a high level state, and the fourth clock signal CK4 has a high level state. The (p - 1)-th stage first gate control signal Nscan(p - 1) output by the (p - 1)-th stage gate driving circuit GDC(p - 1) to the (p - 2)-th stage first gate control signal Nscan(p - 2) output by the (p - 2)-th stage gate driving circuit GDC(p - 2) have a low level state. The first frequency division control signal NLF has a low level state, and the second frequency division control signal PLF has a low level state.

[0155] In the p-th stage gate driving circuit GDC(p), the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency division transistor Tf1 to the fourth frequency division transistor Tf4, the first output transistor To1, and the fourth output transistor To4 are turned on, and the first transistor T1, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, the second output transistor To2, and the third output transistor To3 are turned off. The third power supply terminal NVGL is electrically connected to the first output terminal Nout, and the second power supply terminal PVGH is electrically connected to the second output terminal Pout.

[0156] The (p + 1)-th stage gate driving circuit GDC(p + 1) performs an action similar to the action performed by the p-th stage gate driving circuit GDC(p) in the fourth stage t4 in the fifth stage t5, so that the (p + 1)-th stage second gate control signal Pscan(p + 1) has a low level state. The (p + 2)-th stage gate driving circuit GDC(p + 2) performs an action similar to the action performed by the (p + 1)-th stage gate driving circuit GDC(p + 1) in the fourth stage t4 in the sixth stage t6. And so on, the actions performed by the (p + 3)-th stage gate driving circuit GDC(p + 3) to the (p + q)-th stage gate driving circuit GDC(p + q) in the fifth stage t5 are obtained.

[0157] Sixth stage t6: The first clock signal CK1 has a high level state, the second clock signal CK2 has a high level state, the third clock signal CK3 has a low level state, and the fourth clock signal CK4 has a high level state. The (p - 1)-th stage first gate control signal Nscan(p - 1) output by the (p - 1)-th stage gate driving circuit GDC(p - 1) to the (p - 2)-th stage first gate control signal Nscan(p - 2) output by the (p - 2)-th stage gate driving circuit GDC(p - 2) have a low level state. The first frequency division control signal NLF has a low level state, and the second frequency division control signal PLF has a low level state.

[0158] In the p-th stage gate driving circuit GDC(p), the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the first frequency division transistor Tf1 to the fourth frequency division transistor Tf4, the first output transistor To1, and the fourth output transistor To4 are turned on, and the first transistor T1, the third transistor T3, the sixth transistor T6, the eighth transistor T8, the second output transistor To2, and the third output transistor To3 are turned off. The third power supply terminal NVGL is electrically connected to the first output terminal Nout, and the second power supply terminal PVGH is electrically connected to the second output terminal Pout.

[0159] The (p + 1)-th stage gate driving circuit GDC(p + 1) performs an operation similar to that performed by the p-th stage gate driving circuit GDC(p) in the fifth stage t5 in the sixth stage t6, so that the (p + 1)-th stage first gate control signal Nscan(p + 1) has a low level state. The (p + 2)-th stage gate driving circuit GDC(p + 2) performs an operation similar to that performed by the (p + 1)-th stage gate driving circuit GDC(p + 1) in the fifth stage t5 in the sixth stage t6, so that the (p + 2)-th stage second gate control signal Pscan(p + 2) has a low level state. And so on, the operations performed by the (p + 3)-th stage gate driving circuit GDC(p + 3) to the (p + q)-th stage gate driving circuit GDC(p + q) in the sixth stage t6 are obtained.

[0160] Seventh stage t7: The first clock signal CK1 has a high level state, the second clock signal CK2 has a high level state, the third clock signal CK3 has a high level state, and the fourth clock signal CK4 has a low level state. The (p - 1)-th stage first gate control signal Nscan(p - 1) output by the (p - 1)-th stage gate driving circuit GDC(p - 1) to the (p - 2)-th stage first gate control signal Nscan(p - 2) output by the (p - 2)-th stage gate driving circuit GDC(p - 2) have low level states. The first frequency division control signal NLF has a high level state, and the second frequency division control signal PLF has a low level state.

[0161] The p-th stage gate driving circuit GDC(p) maintains the same state in the seventh stage t7 as in the sixth stage t6. The (p + 1)-th stage gate driving circuit GDC(p + 1) performs an action similar to the action performed by the p-th stage gate driving circuit GDC(p) in the sixth stage t6 in the seventh stage t7. The (p + 2)-th stage gate driving circuit GDC(p + 2) performs an action similar to the action performed by the (p + 1)-th stage gate driving circuit GDC(p + 1) in the sixth stage t6 in the seventh stage t7. The (p + 3)-th stage gate driving circuit GDC(p + 3) performs an action similar to the action performed by the (p + 2)-th stage gate driving circuit GDC(p + 2) in the sixth stage t6 in the seventh stage t7, so that the second gate control signal Pscan(p + 3) of the (p + 3)-th stage has a low level state. And so on, the actions performed by the (p + 4)-th stage gate driving circuit GDC(p + 4) to the (p + 9)-th stage gate driving circuit GDC(p + 9) in the seventh stage t7 are obtained.

[0162] In the (p + 10)-th stage gate driving circuit GDC(p + 10), the first transistor T1, the third transistor T3, the sixth transistor T6, the eighth transistor T8, and the second output transistor To2 are turned on, the second frequency-dividing transistor Tf2 and the fourth frequency-dividing transistor Tf4 remain turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the first output transistor To1, the third output transistor To3, and the fourth output transistor To4 are turned off. The fourth power supply terminal NVGH is electrically connected to the first output terminal Nout, and the second gate control signal Pscan of the p-th stage output from the second output terminal Pout maintains a high level state.

[0163] In the (p + 11)-th stage gate driving circuit GDC(p + 11), the first transistor T1, the fourth transistor T4, the ninth transistor T9, the twelfth transistor T12, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, and the fourth frequency-dividing transistor Tf4 are turned on, and the second transistor T2, the third transistor T3, the eleventh transistor T11, and the second frequency-dividing transistor Tf2 are turned off. Therefore, the first gate control signal Nscan(p + 11) of the (p + 11)-th stage has a low level state, and the second gate control signal Pscan(p + 11) of the (p + 11)-th stage has a high level state.

[0164] In the (p + 12)-th stage gate driving circuit GDC(p + 12) to the (p + q)-th stage gate driving circuit GDC(p + q), the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, and the fourth frequency-dividing transistor Tf4 are turned on, and the second frequency-dividing transistor Tf2 is turned off.

[0165] Eighth stage t8: The first clock signal CK1 has a low level state, the second clock signal CK2 has a high level state, the third clock signal CK3 has a high level state, and the fourth clock signal CK4 has a high level state. The (p-1)th stage first gate control signal Nscan(p-1) output by the (p-1)th stage gate drive circuit GDC(p-1) to the (p-2)th stage first gate control signal Nscan(p-2) output by the (p-2)th stage gate drive circuit GDC(p-2) have a low level state. The first frequency division control signal NLF has a high level state, and the second frequency division control signal PLF has a low level state.

[0166] The pth stage gate drive circuit GDC(p) maintains the same state in the eighth stage t8 as in the seventh stage t7. The (p + 1)th stage gate drive circuit GDC(p + 1) performs an action similar to the action performed by the pth stage gate drive circuit GDC(p) in the seventh stage t7 in the eighth stage t8. The (p + 2)th stage gate drive circuit GDC(p + 2) performs an action similar to the action performed by the (p + 1)th stage gate drive circuit GDC(p + 1) in the seventh stage t7 in the eighth stage t8. The (p + 3)th stage gate drive circuit GDC(p + 3) performs an action similar to the action performed by the (p + 2)th stage gate drive circuit GDC(p + 2) in the seventh stage t7 in the eighth stage t8. The (p + 4)th stage gate drive circuit GDC(p + 4) performs an action similar to the action performed by the (p + 3)th stage gate drive circuit GDC(p + 3) in the seventh stage t7 in the eighth stage t8, so that the (p + 4)th stage second gate control signal Pscan(p + 4) has a low level state. And so on, the actions performed by the (p + 5)th stage gate drive circuit GDC(p + 5) to the (p + 9)th stage gate drive circuit GDC(p + 9) in the seventh stage t7 are obtained.

[0167] In the (p + 10)th stage gate drive circuit GDC(p + 10), the first transistor T1, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, and the second output transistor To2 are turned on. The second frequency division transistor Tf2 and the fourth frequency division transistor Tf4 remain turned on. The second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency division transistor Tf1, the third frequency division transistor Tf3, the first output transistor To1, the third output transistor To3, and the fourth output transistor To4 are turned off. The fourth power supply terminal NVGH is electrically connected to the first output terminal Nout. The (p)th stage second gate control signal Pscan output by the second output terminal Pout maintains a high level state.

[0168] In the (p + 11)-th stage gate driving circuit GDC(p + 11), the first transistor T1, the third transistor T3, the sixth transistor T6, the eighth transistor T8, and the fourth frequency-dividing transistor Tf4 are turned on, and the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the first frequency-dividing transistor Tf1 to the third frequency-dividing transistor Tf3, and the first output transistor To1 to the fourth output transistor To4 are turned off, so that the (p + 11)-th stage first gate control signal Nscan(p + 11) maintains a low level state, and the (p + 11)-th stage second gate control signal Pscan(p + 11) maintains a high level state.

[0169] In the (p + 12)-th stage gate driving circuit GDC(p + 12) to the (p + 13)-th stage gate driving circuit GDC(p + 13), the second transistor T2 is turned on and the third transistor T3 is turned off. Therefore, the (p + 12)-th stage first gate control signal Nscan(p + 12) and the (p + 13)-th stage second gate control signal Pscan(p + 13) maintain the same state as that in the seventh stage t7, and the (p + 12)-th stage second gate control signal Pscan(p + 12) and the (p + 13)-th stage second gate control signal Pscan(p + 13) maintain the same state as that in the seventh stage t7.

[0170] The (p + 14)-th stage gate driving circuit GDC(p + 14) performs an operation similar to that performed by the (p + 13)-th stage gate driving circuit GDC(p + 13) in the seventh stage t7 in the eighth stage t8, and the (p + 15)-th stage gate driving circuit GDC(p + 15) performs an operation similar to that performed by the (p + 14)-th stage gate driving circuit GDC(p + 14) in the seventh stage t7 in the eighth stage t8. By analogy, the operations performed by the (p + 16)-th stage gate driving circuit GDC(p + 16) to the (p + q)-th stage gate driving circuit GDC(p + q) in the eighth stage t8 are obtained.

[0171] Ninth stage t9: The first clock signal CK1 has a high level state, the second clock signal CK2 has a high level state, the third clock signal CK3 has a low level state, and the fourth clock signal CK4 has a high level state. The (p - 1)-th stage first gate control signal Nscan(p - 1) output by the (p - 1)-th stage gate driving circuit GDC(p - 1) to the (p - 2)-th stage first gate control signal Nscan(p - 2) output by the (p - 2)-th stage gate driving circuit GDC(p - 2) have a low level state. The first frequency-dividing control signal NLF has a high level state, and the second frequency-dividing control signal PLF has a low level state.

[0172] The p-th stage gate drive circuit GDC(p) to the (p + 3)-th stage gate drive circuit GDC(p + 3) maintain the same state as in the eighth stage t8 during the ninth stage t9. The first gate control signals Nscan(p + 4) to Nscan(p + 8) of the (p + 4)-th stage to the (p + 8)-th stage have a low level state, and the second gate control signals Pscan(p + 4) to Pscan(p + 8) of the (p + 4)-th stage to the (p + 8)-th stage have a high level state. The (p + 9)-th stage gate drive circuit GDC(p + 9) performs an action similar to the action performed by the (p + 3)-th stage gate drive circuit GDC(p + 3) in the eighth stage t8 during the ninth stage t9. The (p + 10)-th stage gate drive circuit GDC(p + 10) performs an action similar to the action performed by the (p + 4)-th stage gate drive circuit GDC(p + 4) in the eighth stage t8 during the ninth stage t9.

[0173] That is, in the (p + 9)-th stage gate drive circuit GDC(p + 9), the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency division transistor Tf1 to the fourth frequency division transistor Tf4, the first output transistor To1, and the fourth output transistor To4 are turned on, and the first transistor T1, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, the second output transistor To2, and the third output transistor To3 are turned off. The third power supply terminal NVGL is electrically connected to the first output terminal Nout, and the second power supply terminal PVGH is electrically connected to the second output terminal Pout.

[0174] In the (p + 10)-th stage gate drive circuit GDC, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, the second frequency division transistor Tf2, the fourth frequency division transistor Tf4, the second output transistor To2, and the third output transistor To3 are turned on, and the first transistor T1, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the thirteenth transistor T13, the first frequency division transistor Tf1, the third frequency division transistor Tf3, the first output transistor To1, and the fourth output transistor To4 are turned off. The fourth power supply terminal NVGH is electrically connected to the first output terminal Nout, and the second gate control signal Pscan(p + 10) output from the second output terminal Pout has a low level state.

[0175] In the (p + 11)-th stage gate driving circuit GDC(p + 11) to the (p + 12)-th stage gate driving circuit GDC(p + 12), the second transistor T2 is turned on and the third transistor T3 is turned off. Therefore, the (p + 11)-th stage first gate control signal Nscan(p + 11) and the (p + 12)-th stage first gate control signal Nscan(p + 12) maintain the same state as that in the eighth stage t8, and the (p + 11)-th stage second gate control signal Pscan(p + 11) and the (p + 12)-th stage second gate control signal Pscan(p + 12) maintain the same state as that in the eighth stage t8. In the (p + 11)-th stage gate driving circuit GDC(p + 11), the eleventh transistor T11 and the third output transistor To3 are turned on.

[0176] The (p + 13)-th stage gate driving circuit GDC(p + 13) performs an operation similar to that performed by the (p + 11)-th stage gate driving circuit GDC(p + 11) in the eighth stage t8 in the ninth stage t9, and the (p + 14)-th stage gate driving circuit GDC(p + 14) performs an operation similar to that performed by the (p + 12)-th stage gate driving circuit GDC(p + 12) in the eighth stage t8 in the ninth stage t9. By analogy, the operations performed by the (p + 15)-th stage gate driving circuit GDC(p + 15) to the (p + q)-th stage gate driving circuit GDC(p + q) in the ninth stage t9 are obtained.

[0177] Tenth stage t10: The first clock signal CK1 has a high level state, the second clock signal CK2 has a high level state, the third clock signal CK3 has a high level state, and the fourth clock signal CK4 has a low level state. The (p - 1)-th stage first gate control signal Nscan(p - 1) output by the (p - 1)-th stage gate driving circuit GDC(p - 1) to the (p - 2)-th stage first gate control signal Nscan(p - 2) output by the (p - 2)-th stage gate driving circuit GDC(p - 2) have low level states. The first frequency division control signal NLF has a high level state, and the second frequency division control signal PLF has a low level state.

[0178] The (p)-th stage gate driving circuit GDC(p) to the (p + 9)-th stage gate driving circuit GDC(p + 9) maintain the same state as that in the ninth stage t9 in the tenth stage t10, and the (p + 10)-th stage gate driving circuit GDC(p + 10) performs an operation similar to that performed by the (p + 9)-th stage gate driving circuit GDC(p + 9) in the ninth stage t9 in the tenth stage t10.

[0179] That is, in the p + 10 - stage gate driving circuit GDC, the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency - dividing transistor Tf1 to the fourth frequency - dividing transistor Tf4, the first output transistor To1, and the fourth output transistor To4 are turned on, and the first transistor T1, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, the second output transistor To2, and the third output transistor To3 are turned off. The third power supply terminal NVGL is electrically connected to the first output terminal Nout, and the second power supply terminal PVGH is electrically connected to the second output terminal Pout.

[0180] In the p + 11 - stage gate driving circuit GDC(p + 11), the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, the fourth frequency - dividing transistor Tf4, and the third output transistor To3 are turned on, and the first transistor T1, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the thirteenth transistor T13, the first frequency - dividing transistor Tf1, the second frequency - dividing transistor Tf2, the third frequency - dividing transistor Tf3, the first output transistor To1, the second output transistor To2, and the fourth output transistor To4 are turned off. The p + 11 - stage first gate control signal Nscan(p + 11) maintains the state of the ninth stage t9, and the p + 11 - stage second gate control signal Pscan(p + 11) output from the second output terminal Pout has a low - level state.

[0181] In the p + 12 - stage gate driving circuit GDC to the p + 13 - stage gate driving circuit GDC, the third transistor T3 is turned off, the p + 12 - stage first gate control signal Nscan(p + 12) and the p + 13 - stage first gate control signal Nscan(p + 13) maintain the same state as the ninth stage t9, and the p + 12 - stage second gate control signal Pscan(p + 12) and the p + 13 - stage second gate control signal Pscan(p + 13) maintain the same state as the ninth stage t9.

[0182] The (p + 14)-th stage gate drive circuit GDC(p + 14) performs an action similar to that performed by the (p + 13)-th stage gate drive circuit GDC(p + 13) in the ninth stage t9 in the tenth stage t10. The (p + 15)-th stage gate drive circuit GDC(p + 15) performs an action similar to that performed by the (p + 14)-th stage gate drive circuit GDC(p + 14) in the ninth stage t9 in the tenth stage t10. And so on, the actions performed by the (p + 15)-th stage gate drive circuit GDC(p + 15) to the (p + q)-th stage gate drive circuit GDC(p + q) in the tenth stage t10 are obtained.

[0183] Eleventh stage t11: The first clock signal CK1 has a low level state, the second clock signal CK2 has a high level state, the third clock signal CK3 has a high level state, and the fourth clock signal CK4 has a high level state. The (p - 1)-th stage first gate control signal Nscan(p - 1) output by the (p - 1)-th stage gate drive circuit GDC(p - 1) to the (p - 2)-th stage first gate control signal Nscan(p - 2) output by the (p - 2)-th stage gate drive circuit GDC(p - 2) have low level states. The first frequency division control signal NLF has a high level state, and the second frequency division control signal PLF has a low level state.

[0184] The (p)-th stage gate drive circuit GDC(p) to the (p + 10)-th stage gate drive circuit GDC(p + 10) maintain the same state as in the tenth stage t10 in the eleventh stage t11.

[0185] In the (p + 11)-th stage gate drive circuit GDC(p + 11), the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency division transistor Tf1, the third frequency division transistor Tf3, the fourth frequency division transistor Tf4, the first output transistor To1, and the fourth output transistor To4 are turned on, and the first transistor T1, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, the second frequency division transistor Tf2, the second output transistor To2, and the third output transistor To3 are turned off. The third power supply terminal NVGL is electrically connected to the first output terminal Nout, and the second power supply terminal PVGH is electrically connected to the second output terminal Pout.

[0186] After that, if the corresponding start signals STV received by the first transistor T1 and the second transistor T2 of each gate driving circuit GDC are provided by the first output terminal Nout of the previous-stage gate driving circuit GDC, then, in the (p + 12)-th stage gate driving circuit GDC(p + 12) to the (p + q)-th stage gate driving circuit GDC(p + q), since the corresponding start signals STV received by the first transistor T1 and the second transistor T2 of each gate driving circuit GDC are both at low level, therefore, the (p + 12)-th stage first gate control signal Nscan(p + 12) to the (p + q)-th stage first gate control signal Nscan(p + q) output by the (p + 12)-th stage gate driving circuit GDC(p + 12) to the (p + q)-th stage gate driving circuit GDC(p + q) maintain a low level state, and the (p + 12)-th stage second gate control signal Pscan(p + 12) to the (p + q)-th stage second gate control signal Pscan(p + q) output by the (p + 12)-th stage gate driving circuit GDC(p + 12) to the (p + q)-th stage gate driving circuit GDC(p + q) maintain a high level state.

[0187] If the start signals STV received by the first transistor T1 and the second transistor T2 of each gate driving circuit GDC correspond to the potential of the third node P of the previous-stage gate driving circuit GDC, then, in the (p + 12)-th stage gate driving circuit GDC(p + 12) to the (p + q)-th stage gate driving circuit GDC(p + q), the (p + 12)-th stage first gate control signal Nscan(p + 12) to the (p + q)-th stage first gate control signal Nscan(p + q) output by the (p + 12)-th stage gate driving circuit GDC(p + 12) to the (p + q)-th stage gate driving circuit GDC(p + q) maintain a low level state, and the (p + 12)-th stage second gate control signal Pscan(p + 12) to the (p + q)-th stage second gate control signal Pscan(p + q) output by the (p + 12)-th stage gate driving circuit GDC(p + 12) to the (p + q)-th stage gate driving circuit GDC(p + q) will have a level state corresponding to the corresponding second clock signal CK in some periods.

[0188] Therefore, by controlling the first frequency division control signal NLF, the level states of the gate control signals output by multiple gate driving circuits GDC can be controlled, so as to facilitate the display panel to achieve frequency division and partition setting when the gate driving unit is applied to the display panel.

[0189] Please continue to refer to Figure 2D and Figure 3C , and take the example of the second frequency division control signal PLF having a jump from a low level state to a high level state in the p-th stage gate driving circuit GDC(p) to the (p + q)-th stage gate driving circuit GDC(p + q) of the corresponding gate driving unit for illustration.

[0190] Among them, when the first frequency division control signal NLF is in a low level state and the second frequency division control signal PLF is in a low level state, the working principles of the p-th stage gate driving circuit GDC(p) to the (p+q)-th stage gate driving circuit GDC(p+q) corresponding to the first stage t1 to the sixth stage t6 can be referred to the descriptions of the first stage t1 to the sixth stage t6 in the corresponding Figure 2D and Figure 3B . Therefore, the jump of the second frequency division control signal PLF from a low level state to a high level state in the p-th stage gate driving circuit GDC(p) to the (p+q)-th stage gate driving circuit GDC(p+q) of the corresponding gate driving unit will be described starting from the seventh stage t7.

[0191] Seventh stage t7: The first clock signal CK1 is in a high level state, the second clock signal CK2 is in a high level state, the third clock signal CK3 is in a high level state, and the fourth clock signal CK4 is in a low level state. The (p-1)-th stage first gate control signal Nscan(p-1) output by the (p-1)-th stage gate driving circuit GDC(p-1) to the (p-2)-th stage first gate control signal Nscan(p-2) output by the (p-2)-th stage gate driving circuit GDC(p-2) are in low level states. The first frequency division control signal NLF is in a low level state, and the second frequency division control signal PLF is in a low level state.

[0192] In the p-th stage gate driving circuit GDC(p) to the (p+1)-th stage gate driving circuit GDC(p+1), for the third transistor T3, the p-th stage first gate control signal Nscan(p) to the (p+1)-th stage first gate control signal Nscan(p+1) are in low level states, and the p-th stage second gate control signal Pscan to the (p+1)-th stage second gate control signal Pscan(p+1) are in high level states.

[0193] The (p+2)-th stage gate driving circuit GDC(p+2) performs an action similar to the action performed by the (p+1)-th stage gate driving circuit GDC(p+1) in the sixth stage t6 in the seventh stage t7, so that the (p+2)-th stage first gate control signal Nscan(p+2) is in a low level state. The (p+3)-th stage gate driving circuit GDC(p+3) performs an action similar to the action performed by the (p+2)-th stage gate driving circuit GDC(p+2) in the sixth stage t6 in the seventh stage t7, so that the (p+3)-th stage second gate control signal Pscan(p+3) is in a low level state. By analogy, the actions performed by the (p+4)-th stage gate driving circuit GDC(p+4) to the (p+q)-th stage gate driving circuit GDC(p+q) in the seventh stage t7 are obtained.

[0194] Eighth stage t8: The first clock signal CK1 has a low level state, the second clock signal CK2 has a high level state, the third clock signal CK3 has a high level state, and the fourth clock signal CK4 has a high level state. The (p - 1)-th stage first gate control signal Nscan(p - 1) output by the (p - 1)-th stage gate drive circuit GDC(p - 1) to the (p - 2)-th stage first gate control signal Nscan(p - 2) output by the (p - 2)-th stage gate drive circuit GDC(p - 2) have a low level state. The first frequency division control signal NLF has a low level state, and the second frequency division control signal PLF has a high level state.

[0195] The p-th stage gate drive circuit GDC(p) to the (p + 2)-th stage gate drive circuit GDC(p + 2) maintain the same state in the eighth stage t8 as in the seventh stage t7. The (p + 3)-th stage gate drive circuit GDC(p + 3) performs an action similar to the action performed by the (p + 2)-th stage gate drive circuit GDC(p + 2) in the seventh stage t7 in the eighth stage t8, so that the (p + 3)-th stage first gate control signal Nscan(p + 3) has a low level state. The (p + 4)-th stage gate drive circuit GDC(p + 4) performs an action similar to the action performed by the (p + 3)-th stage gate drive circuit GDC(p + 3) in the seventh stage t7 in the eighth stage t8, so that the (p + 4)-th stage second gate control signal Pscan(p + 4) has a low level state. And so on, the actions performed by the (p + 5)-th stage gate drive circuit GDC(p + 5) to the (p + 10)-th stage gate drive circuit GDC(p + 10) in the eighth stage t8 are obtained.

[0196] In the (p + 11)-th stage gate drive circuit GDC(p + 11), the first transistor T1, the third transistor T3, the sixth transistor T6, the eighth transistor T8, and the second output transistor To2 are turned on, the second frequency division transistor Tf2 and the fourth frequency division transistor Tf4 remain turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the first frequency division transistor Tf1, the third frequency division transistor Tf3, the first output transistor To1, the third output transistor To3, and the fourth output transistor To4 are turned off. The fourth power supply terminal NVGH is electrically connected to the first output terminal Nout, and the p-th stage second gate control signal Pscan output by the second output terminal Pout remains at a high level state.

[0197] In the (p + 12)-th stage gate driving circuit GDC(p + 12), the first transistor T1, the fourth transistor T4, the ninth transistor T9, the twelfth transistor T12, the first frequency-dividing transistor Tf1 to the third frequency-dividing transistor Tf3 are turned on, and the second transistor T2, the third transistor T3, the eleventh transistor T11, and the fourth frequency-dividing transistor Tf4 are turned off. Thus, the (p + 12)-th stage first gate control signal Nscan(p + 12) has a low level state, and the (p + 12)-th stage second gate control signal Pscan(p + 12) has a high level state.

[0198] In the (p + 13)-th stage gate driving circuit GDC(p + 13) to the (p + q)-th stage gate driving circuit GDC(p + q), the first frequency-dividing transistor Tf1 to the third frequency-dividing transistor Tf3 are turned on, and the fourth frequency-dividing transistor Tf4 is turned off.

[0199] Ninth stage t9: The first clock signal CK1 has a high level state, the second clock signal CK2 has a low level state, the third clock signal CK3 has a high level state, and the fourth clock signal CK4 has a high level state. The (p - 1)-th stage first gate control signal Nscan(p - 1) output by the (p - 1)-th stage gate driving circuit GDC(p - 1) to the (p - 2)-th stage first gate control signal Nscan(p - 2) output by the (p - 2)-th stage gate driving circuit GDC(p - 2) have low level states. The first frequency-dividing control signal NLF has a low level state, and the second frequency-dividing control signal PLF has a high level state.

[0200] The (p)-th stage gate driving circuit GDC(p) to the (p + 3)-th stage gate driving circuit GDC(p + 3) maintain the same state as in the eighth stage t8 in the ninth stage t9. The (p + 4)-th stage gate driving circuit GDC(p + 4) performs an action similar to the action performed by the (p + 3)-th stage gate driving circuit GDC(p + 3) in the eighth stage t8 in the ninth stage t9, so that the (p + 4)-th stage first gate control signal Nscan(p + 4) has a low level state. The (p + 5)-th stage gate driving circuit GDC(p + 5) performs an action similar to the action performed by the (p + 4)-th stage gate driving circuit GDC(p + 4) in the eighth stage t8 in the ninth stage t9, so that the (p + 5)-th stage second gate control signal Pscan(p + 5) has a low level state. And so on, the actions performed by the (p + 6)-th stage gate driving circuit GDC(p + 6) to the (p + 10)-th stage gate driving circuit GDC(p + 10) in the ninth stage t9 are obtained.

[0201] In the (p + 11)-th stage gate driving circuit GDC(p + 11), the first transistor T1, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, and the second output transistor To2 are turned on, the second frequency-dividing transistor Tf2 and the fourth frequency-dividing transistor Tf4 remain turned on, and the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the first output transistor To1, the third output transistor To3, and the fourth output transistor To4 are turned off. The fourth power supply terminal NVGH is electrically connected to the first output terminal Nout, and the p-th stage second gate control signal Pscan output from the second output terminal Pout remains at a high level state.

[0202] In the (p + 12)-th stage gate driving circuit GDC(p + 12), the first transistor T1, the third transistor T3, the sixth transistor T6, the eighth transistor T8, and the second frequency-dividing transistor Tf2 are turned on, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the fourth frequency-dividing transistor Tf4, the first output transistor To1, the third output transistor To3, and the fourth output transistor To4 are turned off, the fourth power supply terminal NVGH is electrically connected to the first output terminal Nout, and the (p + 12)-th stage second gate control signal Pscan(p + 12) remains at a high level state.

[0203] In the (p + 13)-th stage gate driving circuit GDC(p + 13) to the (p + 14)-th stage gate driving circuit GDC(p + 14), the third transistor T3 is turned off. Therefore, the (p + 13)-th stage first gate control signal Nscan(p + 13) and the (p + 14)-th stage second gate control signal Pscan(p + 14) remain in the same state as the ninth stage t9, and the (p + 13)-th stage second gate control signal Pscan(p + 13) and the (p + 14)-th stage second gate control signal Pscan(p + 14) remain in the same state as the ninth stage t9.

[0204] The (p + 15)-th stage gate driving circuit GDC(p + 15) performs an action similar to that performed by the (p + 14)-th stage gate driving circuit GDC(p + 14) in the eighth stage t8 in the ninth stage t9. The (p + 16)-th stage gate driving circuit GDC(p + 16) performs an action similar to that performed by the (p + 15)-th stage gate driving circuit GDC(p + 15) in the eighth stage t8 in the ninth stage t9. By analogy, the actions performed by the (p + 17)-th stage gate driving circuit GDC(p + 17) to the (p + q)-th stage gate driving circuit GDC(p + q) in the ninth stage t9 are obtained.

[0205] Tenth stage t10: The first clock signal CK1 has a high level state, the second clock signal CK2 has a high level state, the third clock signal CK3 has a high level state, and the fourth clock signal CK4 has a low level state. The (p - 1)-th stage first gate control signal Nscan(p - 1) output by the (p - 1)-th stage gate driving circuit GDC(p - 1) to the (p - 2)-th stage first gate control signal Nscan(p - 2) output by the (p - 2)-th stage gate driving circuit GDC(p - 2) have low level states. The first frequency division control signal NLF has a low level state, and the second frequency division control signal PLF has a high level state.

[0206] The (p)-th stage gate driving circuit GDC(p) to the (p + 4)-th stage gate driving circuit GDC(p + 4) maintain the same state as in the ninth stage t9 in the tenth stage t10. The (p + 5)-th stage first gate control signal Nscan(p + 5) to the (p + 9)-th stage first gate control signal Nscan(p + 9) have low level states, and the (p + 5)-th stage second gate control signal Pscan(p + 5) to the (p + 9)-th stage second gate control signal Pscan(p + 9) have high level states. The (p + 10)-th stage gate driving circuit GDC(p + 10) performs an action similar to that performed by the (p + 4)-th stage gate driving circuit GDC(p + 4) in the ninth stage t9 in the tenth stage t10 so that the (p + 10)-th stage first gate control signal Nscan(p + 10) has a low level state. The (p + 11)-th stage gate driving circuit GDC(p + 11) performs an action similar to that performed by the (p + 5)-th stage gate driving circuit GDC(p + 5) in the ninth stage t9 in the ninth stage t9 so that the (p + 11)-th stage second gate control signal Pscan(p + 11) has a low level state.

[0207] That is, in the p+11th stage gate driving circuit GDC, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, the second frequency-dividing transistor Tf2, the fourth frequency-dividing transistor Tf4, the second output transistor To2, and the third output transistor To3 are turned on, while the first transistor T1, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the thirteenth transistor T13, the first frequency-dividing transistor Tf1, the third frequency-dividing transistor Tf3, the first output transistor To1, and the fourth output transistor To4 are turned off. The fourth power supply terminal NVGH is electrically connected to the first output terminal Nout, and the p+11th stage second gate control signal Pscan(p+11) output from the second output terminal Pout has a low level state.

[0208] In the p+12th stage gate driving circuit GDC(p+12) to the p+13th stage gate driving circuit GDC(p+13), the third transistor T3 is turned off, the p+12th stage first gate control signal Nscan(p+12) and the p+13th stage first gate control signal Nscan(p+13) maintain the same state as the ninth stage t9, and the p+12th stage second gate control signal Pscan(p+12) and the p+13th stage second gate control signal Pscan(p+13) maintain the same state as the ninth stage t9. In the p+12th stage gate driving circuit GDC(p+12), the eleventh transistor T11 is turned on.

[0209] The p+14th stage gate driving circuit GDC(p+14) performs an operation similar to that performed by the p+8th stage gate driving circuit GDC(p+8) in the ninth stage t9 in the tenth stage t10, and the p+15th stage gate driving circuit GDC(p+15) performs an operation similar to that performed by the p+9th stage gate driving circuit GDC(p+9) in the ninth stage t9 in the tenth stage t10. By analogy, the operations performed by the p+16th stage gate driving circuit GDC(p+16) to the p+qth stage gate driving circuit GDC(p+q) in the tenth stage t10 are obtained.

[0210] The eleventh stage t11: The first clock signal CK1 has a low level state, the second clock signal CK2 has a high level state, the third clock signal CK3 has a high level state, and the fourth clock signal CK4 has a high level state. The (p - 1)-th stage first gate control signal Nscan(p - 1) output by the (p - 1)-th stage gate driving circuit GDC(p - 1) to the (p - 2)-th stage first gate control signal Nscan(p - 2) output by the (p - 2)-th stage gate driving circuit GDC(p - 2) have a low level state. The first frequency division control signal NLF has a low level state, and the second frequency division control signal PLF has a high level state.

[0211] The p-th stage gate driving circuit GDC(p) to the (p + 10)-th stage gate driving circuit GDC(p + 10) maintain the same state as in the tenth stage t10 in the eleventh stage t11. The (p + 11)-th stage gate driving circuit GDC(p + 11) performs an action similar to the action performed by the (p + 10)-th stage gate driving circuit GDC(p + 10) in the tenth stage t10 in the eleventh stage t11, so that the (p + 11)-th stage first gate control signal Nscan(p + 11) has a low level state.

[0212] In the (p + 12)-th stage gate driving circuit GDC(p + 12), the (p + 11)-th stage first gate control signal Nscan(p + 11) maintains the state of the tenth stage t10. Since the fourth frequency division transistor Tf4 is cut off, therefore, the (p + 11)-th stage second gate control signal Pscan(p + 11) maintains the state of the tenth stage t10.

[0213] Similarly, the working principles of the (p + 13)-th stage gate driving circuit GDC(p + 13) to the (p + q)-th stage gate driving circuit GDC(p + q) corresponding to the eleventh stage t11 can be obtained.

[0214] By analogy, after the eleventh stage t11, the working principles of the p-th stage gate driving circuit GDC(p) to the (p + q)-th stage gate driving circuit GDC(p + q) can be obtained with reference to the descriptions of the seventh stage t7 to the eleventh stage t11.

[0215] It can be understood that the moment of the level change of the first frequency division control signal NLF and the moment of the level change of the second frequency division control signal PLF can be the same or different.

[0216] It can be understood that the working principles of the first frequency division control signal NLF and the second frequency division control signal PLF when both have a jump from a low level state to a high level state in the p-th stage gate driving circuit GDC(p) to the (p + q)-th stage gate driving circuit GDC(p + q) of the corresponding gate driving unit can be referred to Figure 2D and Figures 3B - 3C to obtain the working principles.

[0217] It can be understood that by adjusting the change time of the level state of the first frequency division control signal NLF, it is possible to control that the multi-stage first gate control signal Nscan does not have an effective pulse at the start of corresponding different stages. By adjusting the change time of the level state of the second frequency division control signal PLF, it is possible to control that the multi-stage second gate control signal Pscan does not have an effective pulse at the start of corresponding different stages.

[0218] It can be understood that by adjusting the position of the change time of the level state of the first frequency division control signal NLF relative to the change time of the level state of the second frequency division control signal PLF, it is possible to make the display panel applying the gate driving unit have frequency reduction at different positions corresponding to the first gate control signal Nscan and the second gate control signal Pscan.

[0219] According to Figures 2A - 2C and Figure 3A the analyzed working principle, it can be known that applying the gate driving circuit GDC shown in Figures 2A - 2C cooperates with the frequency division control signal LF to control the level state of the gate control signal. When there is a change in the level state of the frequency division control signal LF, a transition will be achieved by some gate driving circuits GDC (for example, after the sixth stage t6, the first gate control signal Nscan(p + 1) to the first gate control signal Nscan(p + 8) of the (p + 1)-th stage always maintain a high level state. Correspondingly, the second gate control signal Pscan(p + 1) to the second gate control signal Pscan(p + 8) of the (p + 1)-th stage correspond to the state of the corresponding second clock signal CK), so that the gate control signals output by the subsequent gate driving circuits GDC (such as the gate driving circuit GDC(p + 9) to the gate driving circuit GDC(p + q) of the (p + q)-th stage) have no pulses.

[0220] And according to Figure 2D and Figures 3B - 3C the analyzed working principle, it can be known that applying the gate driving circuit GDC shown in Figure 2D cooperates with the two-frequency division control signal LF to control the level state of the gate control signal, which can make the multi-stage first gate control signal Nscan output by the gate driving unit no longer always be in a high level state, and the multi-stage second gate control signal no longer always correspond to the state of the second clock signal CK, and can improve the use of Figures 2A - 2CProblems that occur in the shown gate driving circuit GDC (i.e., after the sixth stage t6, the first gate control signals Nscan(p + 1) to Nscan(p + 8) of the (p + 1)-th to (p + 8)-th stages remain at a high level state. Correspondingly, the second gate control signals Pscan(p + 1) to Pscan(p + 8) of the (p + 1)-th to (p + 8)-th stages correspond to the states of the corresponding second clock signals CK).

[0221] In addition, when applying Figures 2A - 2C the shown gate driving circuit GDC in cooperation with the frequency division control signal LF to control the level state of the gate control signal, after the level state of the frequency division control signal LF jumps, the multi-stage first gate control signal Nscan will have a step problem due to the large capacitance value of the first capacitor C1 and insufficient conduction of the first switching transistor Ts1 (such as Figure 3D at point A' in). And the number of consecutive stages is equal to the number of row cycles in which the first gate control signal Nscan remains at a high level. Applying Figure 2D the shown gate driving circuit GDC can improve the step problem of the first gate control signal Nscan.

[0222] When applying Figures 2A - 2C the shown gate driving circuit GDC to a display panel to achieve low-frequency control, using the potential of the third node P as the start signal STV of the corresponding stage of the gate driving circuit GDC can make the potential of the third node P correspond to the function of the stage transmission signal, so that the display panel can achieve frequency reduction in any area.

[0223] Optionally, in some embodiments, when applying Figures 2A - 2C the shown gate driving circuit GDC in cooperation with the frequency division control signal LF to control the level state of the gate control signal, when the first gate control signal Nscan and the second gate control signal Pscan output by the frequency division control signal LF to control the corresponding stage of the gate driving circuit GDC do not have effective pulse outputs (such as after the ninth stage t9 corresponding to Figure 3A ), the first clock signal CK1 to the fourth clock signal CK4 can be controlled to be at a high level state, thereby reducing power consumption.

[0224] The present invention also provides a display device, including any of the above-mentioned gate driving units.

[0225] Figure 4 is a schematic structural diagram of the display device provided by the embodiment of the present invention. The display device includes a display panel and a gate driving unit.

[0226] The display panel includes a plurality of sub-pixels Spi, a plurality of scan lines, and a plurality of data lines DL. The plurality of scan lines and the plurality of data lines DL are electrically connected between the gate driving unit and the plurality of sub-pixels Spi. The plurality of data lines DL are configured to transmit a plurality of data signals.

[0227] Optionally, the plurality of scan lines include a plurality of first scan lines SL1 and a plurality of second scan lines SL2. The plurality of first scan lines SL1 are electrically connected between the first output terminals Nout of the plurality of gate driving circuits GDC and the plurality of sub-pixels Spi. The plurality of second scan lines SL2 are electrically connected between the second output terminals Pout of the plurality of gate driving circuits GDC and the plurality of sub-pixels Spi. The plurality of first scan lines SL1 are configured to transmit a plurality of first gate control signals Nscan, and the plurality of second scan lines SL2 are configured to transmit a plurality of second gate control signals Pscan.

[0228] Each sub-pixel Spi includes a light-emitting device Di and a pixel driving circuit for driving the light-emitting device Di to emit light.

[0229] Optionally, the light-emitting device Di includes an organic light-emitting diode, a submillimeter light-emitting diode, a micro light-emitting diode, etc.

[0230] As Figure 5 is a schematic structural diagram of the pixel driving circuit provided by an embodiment of the present invention.

[0231] The pixel driving circuit at least includes a driving transistor Tdr, a data transistor Tda, and a compensation transistor Tc.

[0232] The driving transistor Tdr is connected in series with the light-emitting device Di between the first voltage terminal VDD and the second voltage terminal VSS. The driving transistor Tdr is configured to generate a driving current according to the data signal Vdata transmitted by the corresponding data line DL to drive the light-emitting device Di to emit light.

[0233] The input terminal of the compensation transistor Tc is electrically connected to the output terminal of the driving transistor Tdr, and the output terminal of the compensation transistor Tc is electrically connected to the control terminal of the driving transistor Tdr.

[0234] The input terminal of the data transistor Tda is electrically connected to the corresponding data line DL. The input terminal of the data transistor Tda is configured to receive the corresponding data signal Vdata, and the output terminal of the data transistor Tda is electrically connected to the input terminal of the driving transistor Tdr.

[0235] Among them, the first gate control signal Nscan generated by multiple gate driving circuits GDC is output to the control ends of compensation transistors Tc of multiple sub-pixels Spi through multiple first scan lines SL1; the second gate control signal Pscan generated by multiple gate driving circuits GDC is output to the control ends of data transistors Tda of multiple sub-pixels Spi through multiple second scan lines SL2.

[0236] By controlling the data transistors Tda and compensation transistors Tc of multiple sub-pixels Spi to be controlled by the first gate control signal Nscan and the second gate control signal Pscan output by the gate driving unit, at the position where frequency division needs to be achieved on the display panel, the conduction state of at least one of the corresponding data transistors Tda and compensation transistors Tc is controlled, so as to control whether the content displayed by the corresponding sub-pixel Spi changes, enabling the display panel to achieve partitioned frequency division display.

[0237] Optionally, the compensation transistor Tc includes an oxide transistor or a silicon transistor.

[0238] Optionally, the compensation transistor Tc is a P-type transistor or an N-type transistor, and the data transistor Tda is a P-type transistor or an N-type transistor.

[0239] Optionally, in the gate driving unit, the voltage corresponding to the second power supply terminal PVGH is greater than the voltage corresponding to the first power supply terminal PVGL, the voltage corresponding to the fourth power supply terminal NVGH is greater than the voltage corresponding to the third power supply terminal NVGL, the compensation transistor Tc is an N-type transistor, and the data transistor Tda is a P-type transistor.

[0240] Optionally, the multiple scan lines further include a third scan line SL3. Please continue to refer to Figure 5 , the pixel driving circuit includes a first reset transistor Ti1. The control end of the first reset transistor Ti1 is electrically connected to the corresponding third scan line SL3. The input end of the first reset transistor Ti1 is configured to receive a first reset signal Vi1. The output end of the first reset transistor Ti1 is electrically connected to the control end of the driving transistor Tdr. The first reset transistor Ti1 is configured to transmit the first reset signal Vi1 to the control end of the driving transistor Tdr to reset the potential of the control end of the driving transistor Tdr.

[0241] Optionally, in some embodiments, the first gate control signal Nscan generated by multiple gate driving circuits GDC is output to the control ends of the first reset transistors Ti1 of multiple sub-pixels Spi through multiple first scan lines SL1, and the second gate control signal Pscan generated by multiple gate driving circuits GDC is output to the control ends of the data transistors Tda of multiple sub-pixels Spi through multiple second scan lines SL2, so as to control whether the content displayed by the corresponding sub-pixels Spi changes at the frequency division position where the display panel needs to be implemented by making the data transistors Tda and the first reset transistors Ti1 of multiple sub-pixels Spi be controlled by the first gate control signal Nscan and the second gate control signal Pscan output by the gate driving unit, so as to enable the display panel to achieve partitioned frequency division display.

[0242] Optionally, in some embodiments, multiple third scan lines SL3 are electrically connected between the control ends of the first reset transistors Ti1 of multiple sub-pixels Spi and the first output end Nout of the gate driving unit, so that the first gate control signal Nscan generated by multiple gate driving circuits GDC is output to the control ends of the compensation transistors Tc of multiple sub-pixels Spi through multiple first scan lines SL1; the second gate control signal Pscan generated by multiple gate driving circuits GDC is output to the control ends of the data transistors Tda of multiple sub-pixels Spi through multiple second scan lines SL2; the first gate control signal Nscan generated by multiple gate driving circuits GDC is output to the control ends of the first reset transistors Ti1 of multiple sub-pixels Spi through multiple third scan lines SL3, so as to enable the display panel to achieve partitioned frequency division display by making the data transistors Tda, the first reset transistors Ti1 and the compensation transistors Tc of multiple sub-pixels Spi be controlled by the first gate control signal Nscan and the second gate control signal Pscan output by the gate driving unit.

[0243] Optionally, when both the first reset transistor Ti1 and the compensation transistor Tc are controlled by the first gate control signal Nscan of the gate driving unit, the levels of the first gate control signal Nscan received by the control ends of the first reset transistor Ti1 and the compensation transistor Tc are different. For example, the control end of the first reset transistor Ti1 of the sub-pixel Spi located in the nth row receives the (n-D)th level of the first gate control signal Nscan, and the control end of the compensation transistor Tc of the sub-pixel Spi located in the nth row receives the (n+E)th level of the first gate control signal Nscan. Wherein, D≥1 and E≥1.

[0244] Optionally, the second gate control signal Pscan received by the control terminal of the data transistor Tda and the first gate control signal Nscan received by the control terminal of the compensation transistor Tc are provided by different gate driving circuits GDC. For example, the control terminal of the data transistor Tda of the sub-pixel Spi located in the nth row receives the nth-level second gate control signal Pscan, and the control terminal of the compensation transistor Tc of the sub-pixel Spi located in the nth row receives the (n + E)th-level first gate control signal Nscan.

[0245] Optionally, the control terminal of the first reset transistor Ti1 of the sub-pixel Spi located in the nth row receives the (n - 3)th-level first gate control signal Nscan(n - 3), the control terminal of the compensation transistor Tc of the sub-pixel Spi located in the nth row receives the (n + 1)th-level first gate control signal Nscan(n + 1), and the control terminal of the data transistor Tda of the sub-pixel Spi located in the nth row receives the nth-level second gate control signal Pscan(n).

[0246] Please continue to refer to Figure 5 , the pixel driving circuit of each sub-pixel Spi further includes a second reset transistor Ti2. The input terminal of the second reset transistor Ti2 is configured to receive a second reset signal Vi2. The output terminal of the second reset transistor Ti2 is electrically connected to the anode of the light-emitting device Di. The second reset transistor Ti2 is configured to transmit the second reset signal Vi2 to the anode of the light-emitting device Di to initialize the anode potential of the light-emitting device Di.

[0247] Optionally, in some embodiments, the control terminal of the second reset transistor Ti2 can be controlled by the second gate control signal Pscan. Optionally, the control terminal of the second reset transistor Ti2 is electrically connected to the control terminal of the data transistor Tda, and is electrically connected to the second output terminal Pout of the corresponding gate driving circuit GDC through a plurality of second scan lines SL2, so that the second reset transistor Ti2 is also controlled by the second gate control signal Pscan.

[0248] Optionally, in some embodiments, the control terminal of the second reset transistor Ti2 can be controlled by the first gate control signal Nscan. Optionally, the second reset transistor Ti2 and the compensation transistor Tc are both N-type transistors or both P-type transistors. The control terminal of the second reset transistor Ti2 is electrically connected to the control terminal of the compensation transistor Tc, and is electrically connected to the first output terminal Nout of the corresponding gate driving circuit GDC through a plurality of third scan lines SL3, so that the second reset transistor Ti2 is also controlled by the first gate control signal Nscan.

[0249] Optionally, the pixel driving circuit of each sub-pixel Spi further includes a light-emitting control transistor, which is electrically connected between the input end of the driving transistor Tdr and the first voltage terminal VDD, and / or electrically connected between the output end of the driving transistor Tdr and the light-emitting device Di.

[0250] Optionally, please continue to refer to Figure 4 , the display panel includes a plurality of light-emitting control lines EML, and the plurality of light-emitting control lines EML are configured to transmit a plurality of light-emitting control signals EMA.

[0251] Optionally, the light-emitting control transistor includes a first light-emitting control transistor Te1 and a second light-emitting control transistor Te2. The input end and the output end of the first light-emitting control transistor Te1 are electrically connected between the first voltage terminal VDD and the input end of the driving transistor Tdr. The input end and the output end of the second light-emitting control transistor Te2 are electrically connected between the light-emitting device Di and the output end of the driving transistor Tdr. The control ends of the first light-emitting control transistor Te1 and the second light-emitting control transistor Te2 are electrically connected to the corresponding light-emitting control line EML. The first light-emitting control transistor Te1 and the second light-emitting control transistor Te2 are configured to control the light-emitting period of the light-emitting device Di according to the light-emitting control signal EMA transmitted by the corresponding light-emitting control line EML.

[0252] Optionally, the pixel driving circuit of each sub-pixel Spi further includes a fourth capacitor Cst1, and the fourth capacitor Cst1 is connected in series between the first voltage terminal VDD and the control end of the driving transistor Tdr.

[0253] Optionally, in some embodiments, the pixel driving circuit of each sub-pixel Spi further includes a fifth capacitor Cst2, and the fifth capacitor Cst2 is connected in series between the control end of the driving transistor Tdr and the control end of the data transistor Tda.

[0254] Optionally, in some embodiments, the plurality of scan lines further include a fourth scan line SL4. The pixel driving circuit of each sub-pixel Spi further includes a third reset transistor Ti3. The control end of the third reset transistor Ti3 is electrically connected to the corresponding fourth scan line SL4. The input end of the third reset transistor Ti3 is configured to receive a third reset signal Vi3. The output end of the third reset transistor Ti3 is electrically connected to the input end of the driving transistor Tdr. The third reset transistor Ti3 is configured to transmit the third reset signal Vi3 to the input end of the driving transistor Tdr to reset the potential of the input end of the driving transistor Tdr.

[0255] Optionally, the control end of the second reset transistor Ti2 and the control end of the third reset transistor Ti3 are electrically connected so that the second reset transistor Ti2 and the third reset transistor Ti3 are controlled by the same reset control signal EMB, thereby achieving synchronous resetting of the anode potential of the light-emitting device Di and the input potential of the driving transistor Tdr.

[0256] Optionally, in some embodiments, the display panel further includes a first gate driving unit and a second gate driving unit, the first gate driving unit includes a plurality of first gate driving circuits, the plurality of first gate driving circuits are electrically connected to a plurality of sub-pixels Spi through a plurality of light emitting control lines EML, and the plurality of first gate driving circuits are configured to generate a plurality of light emitting control signals EMA. The plurality of second gate driving units include a plurality of second gate driving circuits, the plurality of second gate driving circuits are electrically connected to a control end of a third reset transistor Ti3 of a plurality of sub-pixels Spi through a plurality of fourth scanning lines SL4, and the plurality of second gate driving circuits GDC are configured to generate a plurality of reset control signals EMB.

[0257] Among them, the first gate driving circuit for generating the light emitting control signal EMA and the second gate driving circuit for generating the reset control signal EMB can be designed with reference to the commonly used circuit structures in the art, and will not be described in detail here.

[0258] Optionally, in some embodiments, the display panel includes a display area and a non-display area located on one side of the display area, wherein the gate driving unit, the first gate driving unit and the second gate driving unit are located in the non-display area.

[0259] Figures 6A - 6C This is a timing diagram corresponding to the display device provided by the embodiment of the present invention. Please continue to refer to Figure 4 , Figure 5 and Figures 6A - 6C When the display panel performs display, a display period may include a write frame WF and at least one hold frame HF.

[0260] In the write frame WF, in order to update the display panel, the Figures 2A - 2C When the gate driving unit shown controls a plurality of sub-pixels Spi, the frequency division control signal LF has an effective level state (ie, a level state that controls the frequency division transistor Tf to be turned on). Figure 2D When the gate driving unit shown controls the plurality of sub-pixels Spi, the first frequency division control signal NLF and the second frequency division control signal PLF both have an effective level state.

[0261] In the blanking interval after the writing frame WF or in at least one holding frame HF after the writing frame WF, in order to keep the image of some rows of the display panel the same as the image displayed in the writing frame WF, Figures 2A - 2CWhen the gate driving unit shown controls a plurality of sub-pixels Spi, the frequency division control signal LF has a transition from an active level state to an inactive level state (i.e., a level state that controls the frequency division transistor Tf to be turned off). When using Figure 2D When the gate driving unit shown controls a plurality of sub-pixels Spi, at least one of the first frequency division control signal NLF and the second frequency division control signal PLF has a transition from an active level state to an inactive level state, so that some of the gate control signals generated by the gate control unit do not have active pulses.

[0262] Optionally, the blanking interval includes a horizontal blanking interval and a vertical blanking interval.

[0263] Optionally, when the display panel adopts Figures 2A - 2C the gate driving unit shown, the moment when the frequency division control signal LF jumps from the active level state to the inactive level state for each holding frame HF can be the same or different. When the display panel adopts Figure 2D the gate driving unit shown, the moment when the first frequency division control signal NLF jumps from the active level state to the inactive level state for each holding frame HF can be the same or different, and the moment when the second frequency division control signal PLF jumps from the active level state to the inactive level state for each holding frame HF can be the same or different.

[0264] Since the frequency division control signal LF, the first frequency division control signal NLF, and the second frequency division control signal PLF can control the first gate control signal Nscan and the second gate control signal Pscan generated by some of the gate driving circuits GDC not to have active pulses when corresponding to the inactive level state; and the frequency division control signal LF, the first frequency division control signal NLF, and the second frequency division control signal PLF can control the first gate control signal Nscan and the second gate control signal Pscan generated by some of the gate driving circuits GDC to have active pulses when corresponding to the active level state. Therefore, by controlling the frequency division control signal LF, the first frequency division control signal NLF, and the second frequency division control signal PLF to jump from the active level state to the inactive level state at different times within different holding frames HF, the display area of the display panel can be divided into a plurality of sub-display areas with different frequencies, and the display panel can be divided into frequencies at any position in the display area, realizing the partition frequency division control of the display area of the display panel.

[0265] Taking the sub-pixel Spi located in the n-th row, the control terminal of the first reset transistor Ti1 receiving the first gate control signal Nscan(n - 3) of the (n - 3)-th level, the control terminal of the compensation transistor Tc receiving the first gate control signal Nscan(n + 1) of the (n + 1)-th level, the control terminal of the data transistor Tda receiving the second gate control signal Pscan(n) of the n-th level, the light-emitting control transistor receiving the light-emitting control signal EMA, and the second reset transistor Ti2 and the third reset transistor Ti3 receiving the reset control signal EMB as an example, the principle of frequency-divided display of the display panel in a display cycle is described.

[0266] Among them, in the write frame WF, in order to enable the control terminal data of the multiple driving transistors Tdr included in the display panel to be reset and updated, the frequency-divided control signal LF, or the first frequency-divided control signal NLF and the second frequency-divided control signal PLF have an effective level state, so that the gate driving unit can output the first gate control signal Nscan and the second gate control signal Pscan with multi-level effective pulses within the write frame WF. Therefore, in the write frame WF, each row of sub-pixels SpiPi correspondingly experiences a first reset stage ta1, a second reset stage ta2, a data writing stage ta3, a third reset stage ta4, and a light-emitting stage ta5, as Figure 6A shown.

[0267] In the first reset stage ta1, the first gate control signal Nscan(n - 3) of the (n - 3)-th level has a high level state, the second gate control signal Pscan(n) of the n-th level has a high level state, the first gate control signal Nscan(n + 1) of the (n + 1)-th level has a low level state, the reset control signal EMB has a high level state, the light-emitting control signal EMA has a high level state, and the first reset transistor Ti1 is turned on, and the first reset signal Vi1 resets the potential of the control terminal of the driving transistor Tdr.

[0268] In the second reset stage ta2, the first gate control signal Nscan(n - 3) of the (n - 3)-th level has a high level state, the second gate control signal Pscan(n) of the n-th level has a high level state, the first gate control signal Nscan(n + 1) of the (n + 1)-th level has a high level state, the reset control signal EMB has a high level state, the light-emitting control signal EMA has a high level state, and the first reset transistor Ti1 and the compensation transistor Tc are turned on, so that the potentials of the output terminal and the control terminal of the driving transistor Tdr are reset according to the first reset signal.

[0269] During the data writing stage ta3, the first gate control signal Nscan(n - 3) of the (n - 3)-th stage has a low level state, the second gate control signal Pscan(n) of the n-th stage has a low level state, the first gate control signal Nscan(n + 1) of the (n + 1)-th stage has a high level state, the reset control signal EMB has a high level state, the light emission control signal EMA has a high level state, the data transistor Tda and the compensation transistor Tc are turned on, and the control terminal of the driving transistor Tdr is written with the information of the data signal.

[0270] During the third reset stage ta4, the first gate control signal Nscan(n - 3) of the (n - 3)-th stage has a low level state, the second gate control signal Pscan(n) of the n-th stage has a high level state, the first gate control signal Nscan(n + 1) of the (n + 1)-th stage has a low level state, the reset control signal EMB has a low level state, the light emission control signal EMA has a high level state, the second reset transistor Ti2 and the third transistor T3 are turned on, the anode of the light emitting device Di is reset according to the second reset signal Vi2, and the input terminal of the driving transistor Tdr is reset according to the third reset signal Vi3.

[0271] During the light emission stage ta5, the first gate control signal Nscan(n - 3) of the (n - 3)-th stage has a low level state, the second gate control signal Pscan(n) of the n-th stage has a high level state, the first gate control signal Nscan(n + 1) of the (n + 1)-th stage has a low level state, the reset control signal EMB has a high level state, the light emission control signal EMA has a low level state, the first light emission control transistor Te1 and the second light emission control transistor Ts1 are turned on according to the light emission control signal EMA, so that the driving transistor Tdr generates a driving current to drive the corresponding light emitting device Di to emit light.

[0272] In the holding frame HF, the sub-pixels Spi of some rows can display the same picture as the display picture of the writing frame WF. Therefore, the sub-pixels Spi corresponding to these rows do not need to go through the first reset stage ta1, the second reset stage ta2, and the data writing stage ta3 again.

[0273] As shown in Figure 6B , the gate driving unit applied to the display panel includes a gate driving circuit GDC that adopts Figures 2A - 2C the design that for a holding frame HF (such as the first holding frame HF1), the frequency division control signal LF has a transition from an effective level state to an invalid level state corresponding to the p-th stage gate driving circuit GDC(p) to the (p + q)-th stage gate driving circuit GDC(p + q) of the gate driving unit. Then, combined with Figure 3AAnalysis shows that the multi-level first gate control signal Nscan and the second gate control signal Pscan output by the multi-level gate driving circuit GDC before the p-th level gate driving circuit GDC(p) and the p-th level gate driving circuit GDC(p) both have effective pulses, so that the data transistors Tda and the compensation transistors Tc in the multiple sub-pixels Spi electrically connected to the multi-level gate driving circuit GDC before the p-th level gate driving circuit GDC(p) and the multiple sub-pixels Spi electrically connected to the p-th level gate driving circuit GDC(p) can be turned on during the corresponding period (such as during the data writing stage ta3 of the corresponding writing frame WF), so that the information of the corresponding data signal is transmitted to the control terminal of the driving transistor Tdr, thereby controlling the change of the driving current generated by the driving transistor Tdr, and realizing the display update of the multiple sub-pixels Spi electrically connected to the multi-level gate driving circuit GDC before the p-th level gate driving circuit GDC(p) and the multiple sub-pixels Spi electrically connected to the p-th level gate driving circuit GDC(p).

[0274] However, the multi-level first gate control signal Nscan and the second gate control signal Pscan output by the multi-level gate driving circuit GDC after the (p + 9)-th level gate driving circuit GDC(p + 9) and the (p + 9)-th level gate driving circuit GDC(p + 9) do not have effective pulses. Therefore, the data transistors Tda and the compensation transistors Tc in the multiple sub-pixels Spi electrically connected to the multi-level gate driving circuit GDC after the (p + 9)-th level gate driving circuit GDC(p + 9) and the multiple sub-pixels Spi electrically connected to the (p + 9)-th level gate driving circuit GDC(p + 9) will not be turned on during the holding frame HF. Therefore, in the multiple sub-pixels Spi electrically connected to the multi-level gate driving circuit GDC after the (p + 9)-th level gate driving circuit GDC(p + 9) and the multiple sub-pixels Spi electrically connected to the (p + 9)-th level gate driving circuit GDC(p + 9), the control terminal of the driving transistor Tdr retains the information written in the writing frame WF, so that the multiple sub-pixels Spi electrically connected to the multi-level gate driving circuit GDC after the (p + 9)-th level gate driving circuit GDC(p + 9) and the multiple sub-pixels Spi electrically connected to the (p + 9)-th level gate driving circuit GDC(p + 9) still display the same content as the writing frame WF during the holding frame HF.

[0275] Due to the change in the level state of the corresponding frequency division control signal LF, the first gate control signals Nscan(p + 1) to Nscan(p + 8) of the (p + 1)-th stage to the (p + 8)-th stage remain at a high level state all the time, and the second gate control signals Pscan(p + 1) to Pscan(p + 8) of the (p + 1)-th stage to the (p + 8)-th stage correspond to the corresponding second clock signal CK. At least one of the devices such as the central processing unit, the graphics processing unit, and the timing controller can control a plurality of sub-pixels Spi electrically connected to the gate driving circuits GDC of the (p + 1)-th stage to GDC(p + 8)-th stage to fixedly display a black screen, so as to improve the problem of easily detectable display anomalies in the plurality of sub-pixels Spi electrically connected to the gate driving circuits GDC of the (p + 1)-th stage to GDC(p + 8)-th stage.

[0276] As shown in Figure 6C , the gate driving unit applied to the display panel includes a gate driving circuit GDC that adopts Figure 2D a design. Corresponding to a hold frame HF (such as the first hold frame HF1), the first frequency division control signal NLF and the second frequency division control signal PLF have a transition from an effective level state to an invalid level state at the p-th stage to (p + q)-th stage gate driving circuits GDC(p) to GDC(p + q) of the gate driving unit. Then, combining Figures 3B - 3C the analysis, it can be seen that the multi-stage first gate control signals Nscan and second gate control signals Pscan output by the multi-stage gate driving circuits GDC before the (p + 11)-th stage gate driving circuit GDC(p + 11) all have effective pulses, so that in a plurality of sub-pixels Spi electrically connected to the multi-stage gate driving circuits GDC before the (p + 11)-th stage gate driving circuit GDC(p + 11), both the data transistor Tda and the compensation transistor Tc can be turned on during the corresponding period (such as during the data writing stage ta3 of the corresponding writing frame WF), so that the information of the corresponding data signal is transmitted to the control end of the driving transistor Tdr, thereby controlling the change of the driving current generated by the driving transistor Tdr, and realizing the display update of the plurality of sub-pixels Spi electrically connected to the multi-stage gate driving circuits GDC before the (p + 11)-th stage gate driving circuit GDC(p + 11).

[0277] The multi-level first gate control signal Nscan output by the multi-level gate drive circuit GDC located after the (p + 10)-th level gate drive circuit GDC(p + 10) does not have an effective pulse, and the multi-level second gate control signal Pscan output by the multi-level gate drive circuit GDC located after the (p + 11)-th level gate drive circuit GDC(p + 11) does not have an effective pulse. Therefore, among the multiple sub-pixels Spi electrically connected to the multi-level gate drive circuit GDC located after the (p + 10)-th level gate drive circuit GDC(p + 10), the data transistor Tda will not conduct during the holding frame HF; among the multiple sub-pixels Spi electrically connected to the multi-level gate drive circuit GDC located after the (p + 11)-th level gate drive circuit GDC(p + 11), the compensation transistor Tc does not conduct during the holding frame HF. The (p + 10)-th level second gate control signal Pscan(p + 10) output by the (p + 10)-th level gate drive circuit GDC(p + 10) has an effective pulse, but the compensation transistor Tc in the multiple sub-pixels Spi electrically connected to the (p + 10)-th level gate drive circuit GDC(p + 10) is cut off because it receives the (p + 11)-th level first gate control signal Nscan(p + 11). Therefore, the control terminals of the drive transistors Tdr in the multiple sub-pixels Spi electrically connected to the (p + 10)-th level gate drive circuit GDC(p + 10) do not receive new data information during the holding frame HF.

[0278] If the first frequency division control signal NLF transitions from the active level state to the inactive level state earlier than the second frequency division control signal PLF, and the first reset transistor Ti1 and the compensation transistor Tc of the sub-pixel Spi are both controlled by the first gate control signal Nscan (for example, the control terminal of the first reset transistor Ti1 located in the n-th row is controlled by the (n - 3)-th level first gate control signal Nscan(n - 3), and the control terminal of the compensation transistor Tc located in the n-th row is controlled by the (n + 1)-th level first gate control signal Nscan(n + 1)), then, during the hold frame HF, although the sub-pixels Spi of some rows of the display panel are controlled not to receive new data signals, since the first reset transistors Ti1 in multiple sub-pixels Spi will be turned on under the control of the corresponding first gate control signal Nscan, the potential at the control terminal of the driving transistor Tdr of the sub-pixels Spi in some rows is reset (for example, during the hold frame HF, the (p)-th level first gate control signal Nscan(p) to the (p + 10)-th level first gate control signal Nscan(p + 10) have active pulse outputs, and the (p)-th level second gate control signal Pscan to the (p + 11)-th level second gate control signal Pscan(p + 11) have active pulse outputs. Then, the first reset transistors Ti1 in multiple sub-pixels Spi located in the (p + 10)-th to (p + 13)-th rows receive the (p + 8)-th level first gate control signal Nscan(p + 8) to the (p + 10)-th level first gate control signal Nscan(p + 10) and turn on, achieving the reset of the potential at the control terminal of the driving transistor Tdr of multiple sub-pixels Spi in the (p + 10)-th to (p + 13)-th rows. However, since the compensation reset transistors in multiple sub-pixels Spi in the (p + 10)-th to (p + 13)-th rows receive the (p + 11)-th level first gate control signal Nscan(p + 11) to the (p + 14)-th level first gate control signal Nscan(p + 14) and are turned off, therefore, multiple sub-pixels Spi in the (p + 10)-th to (p + 13)-th rows achieve the reset of the potential at the control terminal of the driving transistor Tdr, but no new data information is stored at the control terminal of the driving transistor Tdr, nor is the original data signal retained at the control terminal of the driving transistor Tdr). Thus, display problems may occur.

[0279] To improve the problem that during the hold frame HF, the sub-pixels Spi of some rows of the display panel do not receive new data signals and the potential at the control terminal of the driving transistor Tdr of the sub-pixels Spi in these rows is reset, the second frequency division control signal PLF can be controlled to transition from the active level state to the inactive level state earlier than the first frequency division control signal NLF.

[0280] Therefore, in the display panel, Figure 2DWhen the shown gate driving circuit GDC realizes zoned and frequency-divided display, by controlling the relative moments at which the first frequency-dividing control signal NLF and the second frequency-dividing control signal PLF jump from the effective level state to the invalid level state, a plurality of sub-pixels Spi electrically connected to multiple levels of gate driving circuits GDC after the (p + 11)-th level gate driving circuit GDC(p + 11) can keep displaying the same content as that in the write frame WF within the frame HF.

[0281] It can be understood that within each hold frame HF, the frequency-dividing control signal LF, the first frequency-dividing control signal NLF, and the second frequency-dividing control signal PLF are not limited to having a jump from the effective level state to the invalid level state corresponding to the p-th level gate driving circuit GDC(p) to the (p + q)-th level gate driving circuit GDC(p + q) of the gate driving unit. By controlling the frequency-dividing control signal LF, the first frequency-dividing control signal NLF, and the second frequency-dividing control signal PLF to have a jump from the effective level state to the invalid level state corresponding to different levels of gate driving circuits GDC in different hold frames HF, the display area of the display panel can be divided into multiple sub-display areas with different refresh frequencies, realizing the zoned and frequency-divided setting of the display panel.

[0282] In this article, specific examples are used to elaborate on the principles and implementation manners of the present invention. The descriptions of the above embodiments are only used to help understand the method and its core idea of the present invention; at the same time, for those skilled in the art, based on the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A gate driving unit, characterized in that, It includes a frequency division control line and a plurality of cascaded gate drive circuits. The frequency division control line is configured to transmit a frequency division control signal to the plurality of gate drive circuits. Each of the gate drive circuits includes: A first control module, electrically connected to a first node of the current-stage gate drive circuit, and configured to control the signal transmission between one of a first power supply terminal and a second power supply terminal and the first node according to a corresponding first clock signal and one of a start signal and a first gate control signal output by the previous-stage gate drive circuit; A first output module, at least electrically connected to the first node of the current-stage gate drive circuit, and configured to control the electrical connection between a third power supply terminal and a first output terminal of the current-stage gate drive circuit according to the potential of the first node. The first output terminal outputs the first gate control signal of the current-stage gate drive circuit; A second output module, electrically connected to a second node and a third node of the current-stage gate drive circuit, and configured to output a second gate control signal of the current-stage gate drive circuit according to the potential of the second node and the potential of the third node; and A frequency division control module, electrically connected to the first node of the current-stage gate drive circuit, and configured to control the signal transmission between the first power supply terminal and the first node or the second node according to the frequency division control signal.

2. The gate driving unit according to claim 1, characterized in that, The first control module includes: A first transistor, a first control end and a second control end of the first transistor are configured to receive one of the start signal and the first gate control signal output by the previous-stage gate drive circuit, and an input end of the first transistor is electrically connected to the first power supply terminal; A second transistor, a control end of the second transistor is electrically connected to the first control end of the first transistor, an input end of the second transistor is electrically connected to the second power supply terminal, and an output end of the second transistor is electrically connected to the output end of the first transistor; and A third transistor, a control end of the third transistor is configured to receive the corresponding first clock signal, an input end of the third transistor is electrically connected to the output end of the first transistor, and an output end of the third transistor is electrically connected to the first node; Wherein, the frequency division control module is electrically connected to the first transistor or the third transistor.

3. The gate driving unit according to claim 2, wherein The frequency division control module includes: A frequency division transistor, a control end of the frequency division transistor is configured to receive the frequency division control signal, an input end of the frequency division transistor is electrically connected to the output end of the third transistor, and an output end of the frequency division transistor is electrically connected to the first node.

4. The gate driving unit according to claim 2, wherein The frequency division control module includes: A frequency division transistor, a control end of the frequency division transistor is configured to receive the frequency division control signal, an input end of the frequency division transistor is configured to receive the corresponding first clock signal, and an output end of the frequency division transistor is electrically connected to the control end of the third transistor.

5. The gate driving unit according to claim 2, characterized in that, The frequency division control module includes: A frequency-dividing transistor, wherein a control terminal of the frequency-dividing transistor is configured to receive the frequency-dividing control signal, an input terminal of the frequency-dividing transistor is configured to receive the start signal or the first gate control signal output by the previous-stage gate driving circuit, and an output terminal of the frequency-dividing transistor is electrically connected to a first control terminal of the first transistor.

6. The gate driving unit according to any one of claims 1 to 5, characterized in that The first output module includes a first output transistor and a second output transistor. A first control terminal, a second control terminal of the first output transistor and a control terminal of the second output transistor are electrically connected to the first node. An input terminal of the first output transistor is electrically connected to the third power supply terminal. An input terminal of the second output transistor is electrically connected to the fourth power supply terminal. An output terminal of the second output transistor and an output terminal of the first output transistor are electrically connected to the first output terminal of the gate driving circuit of this stage; The second output module includes a third output transistor, a fourth output transistor and a storage capacitor. A control terminal of the third output transistor is electrically connected to the second node. An input terminal of the third output transistor is configured to receive a corresponding second clock signal. A control terminal of the fourth output transistor is electrically connected to the third node. An input terminal of the fourth output transistor is electrically connected to the second power supply terminal. An output terminal of the fourth output transistor and an output terminal of the third output transistor are electrically connected to the second output terminal of the gate driving circuit of this stage; A first end of the storage capacitor is electrically connected to the control terminal of the third output transistor, and a second end of the storage capacitor is electrically connected to the second output terminal of the gate driving circuit of this stage.

7. The gate driving unit according to claim 1, wherein The second node includes a first sub-node and a second sub-node, and the frequency-dividing control signal includes a first frequency-dividing control signal and a second frequency-dividing control signal; The frequency-dividing control module includes: A first frequency-dividing control module, electrically connected to the first node and the first sub-node, and configured to control signal transmission between the first power supply terminal and the first sub-node according to the first frequency-dividing control signal; and A second frequency-dividing control module, electrically connected to the first node and the second sub-node, and configured to control signal transmission between the first power supply terminal and the second sub-node according to the second frequency-dividing control signal; Wherein, the first output module is electrically connected to the first sub-node, and the first output module is configured to output the first gate control signal of the gate driving circuit of this stage according to the potential of the first node and the potential of the first sub-node; the second output module is electrically connected to the second sub-node, and the second output module is configured to output the second gate control signal of the gate driving circuit of this stage according to the potential of the second sub-node and the potential of the third node.

8. The gate driving unit according to claim 7, characterized in that, The first frequency division control module includes a first frequency division transistor, a second frequency division transistor, and a first capacitor. The control terminal of the first frequency division transistor is electrically connected to the third node of the gate driving circuit at this stage, and the input terminal of the first frequency division transistor is configured to receive the first frequency division control signal; The control terminal of the second frequency division transistor is electrically connected to the output terminal of the first frequency division transistor. The input terminal of the second frequency division transistor is electrically connected to the first node, and the output terminal of the second frequency division transistor is electrically connected to the first sub-node. The first end of the first capacitor is electrically connected to the control terminal of the second frequency division transistor, and the second end of the first capacitor is electrically connected to the first sub-node; The second frequency division control module includes a third frequency division transistor, a fourth frequency division transistor, and a second capacitor. The control terminal of the third frequency division transistor is electrically connected to the third node of the gate driving circuit at this stage, and the input terminal of the third frequency division transistor is configured to receive the second frequency division control signal; The control terminal of the fourth frequency division transistor is electrically connected to the output terminal of the third frequency division transistor. The input terminal of the fourth frequency division transistor is electrically connected to the first node, and the output terminal of the fourth frequency division transistor is electrically connected to the second sub-node. The first end of the second capacitor is electrically connected to the control terminal of the fourth frequency division transistor, and the second end of the second capacitor is electrically connected to the second sub-node.

9. The gate driving unit according to claim 8, wherein The first output module includes a first output transistor and a second output transistor. The first control terminal and the second control terminal of the first output transistor are electrically connected to the first node. The input terminal of the first output transistor is electrically connected to the third power supply terminal. The control terminal of the second output transistor is electrically connected to the first sub-node. The input terminal of the second output transistor is electrically connected to the fourth power supply terminal. The output terminal of the second output transistor and the output terminal of the first output transistor are electrically connected to the first output terminal of the gate driving circuit at this stage; The second output module includes a third output transistor, a fourth output transistor, and a storage capacitor. The control terminal of the third output transistor is electrically connected to the second sub-node. The input terminal of the third output transistor is configured to receive the corresponding second clock signal. The control terminal of the fourth output transistor is electrically connected to the third node. The input terminal of the fourth output transistor is electrically connected to the second power supply terminal. The output terminal of the fourth output transistor and the output terminal of the third output transistor are electrically connected to the second output terminal of the gate driving circuit at this stage. The first end of the storage capacitor is electrically connected to the control terminal of the third output transistor, and the second end of the storage capacitor is electrically connected to the second output terminal of the gate driving circuit at this stage.

10. The gate driving unit according to claim 1, wherein The first control module further includes a fourth transistor, a fifth transistor, and a sixth transistor. The first control terminal and the second control terminal of the fourth transistor are configured to receive the corresponding first clock signal. The output terminal of the fourth transistor is electrically connected to the first node. The control terminal of the fifth transistor, the first control terminal and the second control terminal of the sixth transistor are electrically connected to the third node. The input terminal of the fifth transistor is electrically connected to the second power supply terminal. The output terminal of the fifth transistor is electrically connected to the input terminal of the fourth transistor. The input terminal of the sixth transistor is electrically connected to the third power supply terminal. The output terminal of the sixth transistor is electrically connected to the first node; The gate driving unit further includes a seventh transistor and an eighth transistor. The first control terminal and the second control terminal of the seventh transistor are electrically connected to the first node. The input terminal of the seventh transistor is electrically connected to the first power supply terminal. The output terminal of the seventh transistor is electrically connected to the third node. The control terminal of the eighth transistor is electrically connected to the first node. The input terminal of the eighth transistor is electrically connected to the second power supply terminal. The output terminal of the eighth transistor is electrically connected to the third node.

11. The gate driving unit according to claim 6, wherein The gate driving circuit further includes: A first switching transistor, the input terminal of the first switching transistor is electrically connected to the first node; A second switching transistor, the input terminal of the second switching transistor is electrically connected to the output terminal of the first switching transistor, and the output terminal of the second switching transistor is electrically connected to the second node; and A third capacitor, the first terminal of the third capacitor is electrically connected to the control terminal of the first switching transistor, and the second terminal of the third capacitor is electrically connected to the output terminal of the first switching transistor; Wherein, the control terminal of the first switching transistor of the nth-stage gate driving circuit is configured to receive the first gate control signal output by the (n-10)th-stage gate driving circuit, and the control terminal of the second switching transistor of the nth-stage gate driving circuit is configured to receive the first gate control signal output by the (n-2)th-stage gate driving circuit.

12. The gate driving unit according to claim 9, characterized in that, The gate driving circuit further includes: A ninth transistor, the first control terminal and the second control terminal of the ninth transistor are configured to receive the corresponding first clock signal, and the output terminal of the ninth transistor is electrically connected to the first sub-node; A tenth transistor, the control terminal of the tenth transistor is electrically connected to the third node of the current-stage gate driving circuit, the input terminal of the tenth transistor is electrically connected to the second power supply terminal, and the output terminal of the tenth transistor is electrically connected to the input terminal of the ninth transistor; An eleventh transistor, the control terminal of the eleventh transistor is electrically connected to the third node of the previous-stage gate driving circuit, the input terminal of the eleventh transistor is electrically connected to the output terminal of the third frequency-dividing transistor, and the output terminal of the eleventh transistor is electrically connected to the second sub-node; A twelfth transistor, a first control terminal and a second control terminal of the twelfth transistor are configured to receive the corresponding first clock signal, and an output terminal of the twelfth transistor is electrically connected to an input terminal of the eleventh transistor; A thirteenth transistor, a control terminal of the thirteenth transistor is electrically connected to the third node of the gate driving circuit of this stage, an input terminal of the thirteenth transistor is electrically connected to the second power supply terminal, and an output terminal of the thirteenth transistor is electrically connected to the input terminal of the twelfth transistor.

13. A display device, characterized in that, Comprising: The gate driving unit according to any one of claims 1 to 12; A display panel, including a plurality of sub-pixels, each sub-pixel includes a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light, and the pixel driving circuit at least includes a driving transistor, a data transistor and a compensation transistor; the driving transistor is configured to drive the light-emitting device to emit light according to the corresponding data signal, an input terminal of the compensation transistor is electrically connected to an output terminal of the driving transistor, an output terminal of the compensation transistor is electrically connected to a control terminal of the driving transistor, an input terminal of the data transistor is configured to receive the corresponding data signal, and an output terminal of the data transistor is electrically connected to the input terminal of the driving transistor; Wherein, the first gate control signals generated by the plurality of gate driving circuits are output to the control terminals of the compensation transistors of the plurality of sub-pixels, and the second gate control signals generated by the plurality of gate driving circuits are output to the control terminals of the data transistors of the plurality of sub-pixels.

Images