Method for manufacturing mask and integrated circuit

Abstract

Embodiments of the present disclosure relate to semiconductor manufacturing technology and provide methods for manufacturing masks and integrated circuits. The mask manufacturing method includes: dividing a layout pattern of an active layer of an integrated circuit into a first pattern portion and a second pattern portion; modifying the first pattern portion and the second pattern portion; and determining manufacturing data for a first mask and a second mask based on the modified first pattern portion and the modified second pattern portion, respectively, wherein the first mask and the second mask form light-transmitting regions in the modified first pattern portion and the modified second pattern portion, respectively.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor manufacturing technology, and more particularly, to a method for manufacturing a mask, a method for manufacturing an integrated circuit, an electronic device, and a computer-readable storage medium. Background Art

[0002] Photolithography transfers the circuit pattern on the mask to the wafer surface through optical-chemical reactions and a series of etching steps, thereby forming an integrated circuit or chip with the desired functionality. Computational lithography is an additional method for photolithography, primarily using mathematical modeling, simulation, and algorithm optimization to reduce or eliminate pattern distortion caused by physical limitations such as the proximity effect during the photolithography process. Computational lithography has been a key driving force behind the continued advancement of pattern miniaturization technology in recent years. By using software technologies such as resolution enhancement to achieve minimum exposure dimensions beyond hardware limitations, while maintaining the hardware environment of existing lithography equipment, computational lithography has significantly advanced the development of advanced semiconductor processes.

[0003] In the photolithography process, masks carry specific design layouts or patterns that achieve the performance specified by the design. During the manufacturing process, masks must comply with mask rule checks (MRCs), for example, the spacing between two graphic blocks cannot be too small. Mask design using computational lithography is also typically subject to MRC constraints. However, some of the mask layouts required for some current advanced processes may not meet MRC requirements. There is currently no effective solution for this problem, and the only option is to forgo checks at certain locations through specific rules, and to tolerate the resulting mask defects. Summary of the Invention

[0004] Based on the above problems, according to example embodiments of the present disclosure, a method of manufacturing a mask, a method of manufacturing an integrated circuit, an electronic device, and a computer-readable storage medium are provided.

[0005] In a first aspect of the present disclosure, a method for manufacturing a mask is provided, comprising: dividing a layout pattern of an active layer of an integrated circuit into a first pattern portion and a second pattern portion; correcting the first pattern portion and the second pattern portion; and determining manufacturing data for a first mask and manufacturing data for a second mask based on the corrected first pattern portion and the second pattern portion, respectively, the first mask and the second mask forming light-transmitting areas at the corrected first pattern portion and the second pattern portion, respectively.

[0006] In a second aspect of the present disclosure, a method for manufacturing an integrated circuit is provided, comprising: performing a first photolithography exposure and a second photolithography exposure, respectively, on an integrated circuit substrate having an initial fin structure formed thereon using a first mask and a second mask manufactured according to the method of the first aspect; and after the second photolithography exposure, etching an unexposed area of ​​the integrated circuit substrate and retaining the fin structure of the exposed area.

[0007] In a third aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory coupled to the processor, the memory having instructions stored therein, which, when executed by the processor, cause the electronic device to perform actions, the actions comprising: dividing a layout graphic of an active layer of an integrated circuit into a first graphic portion and a second graphic portion; correcting the first graphic portion and the second graphic portion; and determining manufacturing data for a first mask and manufacturing data for a second mask based on the corrected first graphic portion and the second graphic portion, respectively, the first mask and the second mask forming light-transmitting areas at the corrected first graphic portion and the second graphic portion, respectively.

[0008] In some embodiments of the present disclosure, the layout graphic includes a first graphic block having at least one L-shaped corner, and wherein dividing the layout graphic of the active layer of the integrated circuit into a first graphic portion and a second graphic portion includes: dividing the first graphic block into at least two rectangular blocks; and dividing two adjacent rectangular blocks of the at least two rectangular blocks into the first graphic portion and the second graphic portion, respectively.

[0009] In some embodiments of the present disclosure, the layout graphic also includes at least one second graphic block, each second graphic block is a rectangular block, and wherein dividing the layout graphic of the active layer of the integrated circuit into a first graphic portion and a second graphic portion further includes: dividing at least one second graphic block into the first graphic portion or the second graphic portion, so that the spacing between adjacent graphic blocks in the first graphic portion and the second graphic portion is increased compared to the spacing between adjacent graphic blocks in the layout graphic.

[0010] In some embodiments of the present disclosure, modifying the first pattern portion and the second pattern portion includes: extending rectangular blocks in the first pattern portion and the second pattern portion by a first predetermined distance in a direction perpendicular to the fin.

[0011] In some embodiments of the present disclosure, the first predetermined distance is half of a distance between two adjacent fins.

[0012] In some embodiments of the present disclosure, two adjacent rectangular blocks of at least two rectangular blocks are arranged along the extension direction of the fin and have different boundary lengths from each other, and wherein modifying the first graphic portion and the second graphic portion includes: extending the rectangular block with the shorter boundary length of the two adjacent rectangular blocks by a second predetermined distance on one side of the boundary.

[0013] In some embodiments of the present disclosure, the second predetermined distance is half of the distance between two adjacent fins.

[0014] In some embodiments of the present disclosure, correcting the first graphic portion and the second graphic portion includes correcting corners of rectangular blocks in the first graphic portion and the second graphic portion using an optical proximity correction process.

[0015] In some embodiments of the present disclosure, the first mask and the second mask are used in a self-aligned double patterning process or a self-aligned quadruple patterning process.

[0016] In a fourth aspect of the present disclosure, a computer-readable storage medium is provided, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the method according to the first aspect and / or the second aspect of the present disclosure is implemented.

[0017] It should be understood that the contents described in the Summary of the Invention section are not intended to limit the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other features, advantages and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0019] Figure 1 A schematic diagram showing an exemplary layout of an integrated circuit is shown.

[0020] Figure 2 A schematic diagram showing a partial pattern block of an active layer of an integrated circuit and a partial pattern block of a horizontal clipping mask is shown.

[0021] Figure 3 A schematic flowchart of a method for manufacturing a mask according to an embodiment of the present disclosure is shown.

[0022] Figure 4 A schematic diagram of dividing a layout pattern of an active layer of an integrated circuit into a first pattern portion and a second pattern portion according to an embodiment of the present disclosure is shown.

[0023] Figure 5A and Figure 5B A schematic diagram illustrating a process of dividing a graphic block in a layout pattern of an active layer of an integrated circuit according to an embodiment of the present disclosure is shown.

[0024] Figure 6A and Figure 6BA schematic diagram illustrating a process of dividing another graphic block in a layout pattern of an active layer of an integrated circuit according to an embodiment of the present disclosure is shown.

[0025] Figure 7A and Figure 7B A schematic diagram illustrating a process of dividing another graphic block in a layout pattern of an active layer of an integrated circuit according to an embodiment of the present disclosure is shown.

[0026] Figure 8A and Figure 8B A schematic diagram illustrating a process of dividing a portion of graphic blocks in a layout pattern of an active layer of an integrated circuit according to an embodiment of the present disclosure is shown.

[0027] Figure 9A and Figure 9B A schematic diagram illustrating an exemplary process of dividing a layout pattern of an active layer of an integrated circuit into two mask layout patterns according to an embodiment of the present disclosure is shown.

[0028] Figure 10A and Figure 10B A schematic diagram illustrating a correction process of a pattern block in a first pattern portion or a second pattern portion of a first mask according to an embodiment of the present disclosure is shown.

[0029] Figure 11 A schematic diagram illustrating a modification process of a graphic block in a first graphic portion and a graphic block in a second graphic portion according to an embodiment of the present disclosure is shown.

[0030] Figure 12A and Figure 12B A schematic diagram of a pattern block formed on a substrate after a photolithography process according to an embodiment of the present disclosure is shown.

[0031] Figure 13 A schematic diagram illustrating a modification process of a graphic block in a first graphic portion and a graphic block in a second graphic portion according to an embodiment of the present disclosure is shown.

[0032] Figure 14 A schematic diagram illustrating a modification process of a graphic block in a first graphic portion and a graphic block in a second graphic portion according to an embodiment of the present disclosure is shown.

[0033] Figure 15 A schematic flow chart of a method for manufacturing an integrated circuit according to an embodiment of the present disclosure is shown.

[0034] Figure 16 A schematic diagram of an integrated circuit manufactured by a method according to an embodiment of the present disclosure is shown.

[0035] Figure 17 A schematic block diagram of an example device for implementing an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0036] The following describes embodiments of the present disclosure in more detail with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0037] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, i.e., "including but not limited to." The term "based on" should be understood as "based at least in part on." The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment." The terms "first," "second," etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0038] As mentioned earlier, some advanced process masks may not meet MRC requirements. For example, in the Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) processes, redundant pattern cut layer masks are required. The layout of these redundant pattern cut layer masks may not meet MRC requirements, such as the presence of point contact patterns.

[0039] Figure 1 A schematic diagram of a layout 100 of an integrated circuit is shown. The active area (AA) layer and the polysilicon (Poly) layer are shown in the layout 100. The AA layer refers to the transistor area formed on the silicon substrate after etching and doping. It defines the boundaries of the transistor source, drain and channel, and is the core area of ​​the transistor. In the case where the transistor is a fin field-effect transistor (FinFET), the fin will be formed in the area covered by the AA layer. The Poly layer is a material layer used to form the gate structure of the transistor. The Poly design direction is usually perpendicular to the extension direction of the fin. For ease of description, this article defines the extension direction of the fin covered by the AA layer as the X direction, and the Poly design direction of the Poly layer as the Y direction.

[0040] The integrated circuit corresponding to layout 100 can be manufactured using advanced processes such as SADP and SAQP. During the SADP process, a fin core structure can be formed on a substrate using a fin core mask. For example, a photoresist is applied to the substrate and photolithographic exposure is performed to form a set of parallel linear patterns (each linear pattern is referred to as a fin core). The spacing between these parallel linear patterns can be twice the fin pitch. Spacers are then deposited on both sides of each fin core, and the excess deposited material is removed, leaving only the spacers on both sides of the fin core. The fin core structure is then removed and the silicon substrate uncovered by the spacers is etched, forming a set of parallel fins in the silicon substrate with a spacing half the fin core pitch. In subsequent processing, the silicon substrate with the fins formed is further processed using an excess pattern shearing layer mask to remove the fin structure in areas not covered by the AA layer. For example, a horizontal shearing mask is used to perform photolithographic exposure on a silicon substrate covered with photoresist, and etching is performed to remove the fin structure outside the AA layer along the X direction, and a vertical shearing mask is used to perform photolithographic exposure on the silicon substrate, and etching is performed to remove the fin structure outside the AA layer along the Y direction. In other words, two photolithography steps and two etching steps are required to obtain the pattern corresponding to the AA layer of layout 100. The horizontal shearing mask and the vertical shearing mask are generated according to the pattern of the AA layer and based on certain specific rules. Therefore, even if the graphics of the AA layer meet the requirements of the Design Rule Check (DRC), the horizontal shearing mask and the vertical shearing mask may not comply with the DRC, and in some cases, may even not comply with the MRC, such as the appearance of a point contact pattern in the mask.

[0041] Figure 2 FIG. 1 shows a schematic diagram of a portion of the graphic blocks of the AA layer of the layout 100 and a portion of the graphic blocks of the horizontal clipping mask. Figure 2As shown, the AA layer includes pattern blocks 211, 212, and 213. As previously mentioned, the layout pattern of the horizontal shear mask needs to be designed based on the layout pattern of the AA layer and certain rules to remove the fin structure outside the AA layer along the X direction. Therefore, to obtain a pattern corresponding to pattern blocks 211, 212, and 213 in the AA layer, pattern blocks 221, 222, and 223 need to be arranged on the layout of the horizontal shear mask. However, in this horizontal shear mask design, point contacts D1 occur between pattern blocks 221 and 222. This point contact is the most unacceptable defect in the mask process, potentially causing electrostatic discharge (ESD) during mask fabrication, leading to manufacturing defects. Currently, to achieve advanced processes, the design layout of the horizontal shear mask inevitably contains a large number of point contacts, and MRC checks for the horizontal shear mask are foregone. The presence of a large number of point contacts and the abandonment of MRC checks can also mask or miss other serious mask design and manufacturing defects, adversely affecting the design and manufacture of integrated circuits.

[0042] Embodiments of the present disclosure provide improved mask manufacturing methods and integrated circuit manufacturing methods. In the improved scheme, by splitting the AA layer layout pattern into two pattern portions and correcting them, and then directly using the two corrected pattern portions to form the patterns of two masks, a new mask can be provided to replace the horizontal shear mask and the vertical shear mask. Because the AA layer layout design complies with design rules and its layout pattern does not have point contact, the pattern of the new mask formed by splitting the AA layer layout pattern will naturally comply with design rules and will not have the problem of point contact. When manufacturing the integrated circuit, the integrated circuit substrate with the initial fin structure can be exposed twice using a new mask using a process such as negative tone development (NTD), and the unexposed areas can be etched away, rather than etching away the exposed areas as in conventional schemes. As a result, the desired AA layer layout pattern consistent with the superimposed pattern of the two new masks can be formed on the substrate. In this way, the problem of mask pattern point contact that occurs in advanced processes such as SADP and SAQP can be eliminated. By eliminating numerous point contacts, the present invention also facilitates the detection of other defects that would otherwise be masked by these issues in conventional solutions, thereby improving and optimizing computational lithography processes and integrated circuit manufacturing efficiency. Furthermore, compared to conventional integrated circuit manufacturing solutions that use redundant pattern shearing layer masks, the disclosed embodiments can also eliminate one etching step, simplifying the process, reducing costs, and improving manufacturing efficiency.

[0043] Figure 3A schematic flow chart of a method 300 for manufacturing a mask according to an embodiment of the present disclosure is shown. Method 300 can be performed by a computing device, which can be any device with computing capabilities. In one example, the computing device used to perform method 300 can be any type of fixed, mobile, or portable computing device, such as a desktop computer, laptop computer, notebook computer, netbook computer, tablet computer, multimedia computer, mobile phone, etc. In another example, all or a portion of the components of the computing device used to perform method 300 can be distributed in the cloud.

[0044] At block 301, the layout pattern of the integrated circuit AA layer is divided into a first pattern portion and a second pattern portion. As an example, the layout pattern of the AA layer may include a set of multiple pattern blocks (e.g. Figure 1 ), the set of graphic blocks can be split into two subsets. For example, a basic splitting method similar to that used in Double Patterning Technology (DPT) can be employed to arrange these graphic blocks in two separate mask layouts, with the positions of the split graphic blocks remaining the same as in the AA layer layout. Furthermore, the splitting process can be used to split more complex graphic blocks into simpler ones, thus avoiding potential defects caused by complex graphic blocks during mask manufacturing and lithography.

[0045] At block 302, the first and second pattern portions are corrected. For example, the structure, shape, and size of the pattern blocks in the two pattern portions can be actively adjusted and corrected to eliminate or reduce manufacturing defects caused by deviations and errors that may exist during subsequent mask manufacturing and photolithography processes. These deviations and errors may include, for example, mask alignment deviations, errors caused by diffraction and interference of light used for photolithographic exposure, and errors caused by diffraction and interference of the electron beam used to manufacture the mask.

[0046] At block 303, based on the modified first pattern portion and the second pattern portion, manufacturing data for the first mask and manufacturing data for the second mask are determined, respectively, and the first mask and the second mask form light-transmitting areas at the modified first pattern portion and the second pattern portion, respectively. Specifically, in a conventional SADP process, the patterns of the light-transmitting areas of the horizontal shear mask and the vertical shear mask correspond to areas outside the layout pattern of the AA layer, for example Figure 2The areas of pattern blocks 221, 222, and 223 in the first and second masks are exposed to remove excess components outside the layout pattern of the AA layer (e.g., fin structures not covered by the AA layer pattern). Unlike horizontal and vertical shear masks, the pattern portions of the light-transmitting areas of the first and second masks directly correspond to a subset of the layout pattern of the AA layer. If the layout pattern of the AA layer complies with design rules, the layout patterns of the first and second masks, formed using the subset of the AA layer layout pattern, will also comply with design rules and will not cause point contact issues. During integrated circuit manufacturing, the first and second masks are used to perform a double exposure, overlapping the portions where the fin structure is to be retained. Combined with a process such as NTD photoresist, the fin structure in the unexposed areas can be removed while retaining the fin structure in the exposed areas, thereby preserving the fin structure covered by the AA layer layout pattern and forming the desired integrated circuit pattern. This approach avoids the problem of discarding inspection due to the excess pattern shear layer mask failing to comply with mask manufacturing rules in conventional solutions, effectively eliminating various defects in the mask process and optimizing the design and manufacturing of integrated circuits.

[0047] Figure 4 FIG. 1 shows a schematic diagram of dividing the layout pattern of the integrated circuit AA layer into a first pattern portion and a second pattern portion according to an embodiment of the present disclosure. Figure 4 As shown, the layout 400 of the integrated circuit AA layer includes a layout pattern 410. As described in block 301 of the method 300 above, the layout pattern 410 can be split into a first pattern portion 410A and a second pattern portion 410B, and the first pattern portion 410A is arranged in the first mask layout 400A, while the second pattern portion 410B is arranged in the second mask layout 400B.

[0048] Figure 5A and Figure 5B FIG. 4 is a schematic diagram showing a process of dividing a graphic block 411 in a layout graphic 410 of an AA layer according to an embodiment of the present disclosure. Figure 5A and Figure 5B As shown, the layout pattern 410 includes a graphic block 411 having an L-shaped corner, and in the process of dividing the layout pattern of the integrated circuit AA layer into the first graphic portion 410A and the second graphic portion 410B as described in method 300, the graphic block 411 can be divided into two rectangular blocks 411A and 411B, and the two rectangular blocks 411A and 411B are respectively divided into the first graphic portion 410A for the first mask layout 400A and the second graphic portion 410B for the second mask layout 400B.

[0049] Figure 6A and Figure 6BFIG. 4 is a schematic diagram showing a process of dividing another graphic block 412 in the layout 400 of the AA layer according to an embodiment of the present disclosure. Figure 6A and 6B As shown, the layout pattern 410 includes a pattern block 412 having two L-shaped corners. In the process of dividing the layout pattern 410 of the AA layer of the integrated circuit into the first pattern portion 410A and the second pattern portion 410B, the pattern block 412 can be divided into three rectangular blocks 412A, 412B, and 412C, and the rectangular block 412A is divided into the first pattern portion 410A for the first mask layout 400A, while the rectangular blocks 412B and 412C are divided into the second pattern portion 410B for the second mask layout 400B.

[0050] Figure 7A and Figure 7B FIG. 4 is a schematic diagram showing a process of dividing another graphic block 413 in the layout graphic 410 of the AA layer according to an embodiment of the present disclosure. Figure 7A and 7B As shown, the layout pattern of layout 400 includes a pattern block 413 having two L-shaped corners. In the process of dividing the layout pattern 410 of the AA layer of the integrated circuit into the first pattern portion 410A and the second pattern portion 410B as described in method 300, the pattern block 413 can be divided into three rectangular blocks 413A, 413B, and 413C, and rectangular block 413A is divided into the first pattern portion 410A for the first mask layout 400A, while rectangular blocks 413B and 413C are divided into the second pattern portion 410B for the second mask layout 400B.

[0051] Understandable, except Figure 5A 、 Figure 6A and Figure 7A In addition to graphic blocks 411, 412, and 413 in the layout pattern 410, some graphic blocks in the layout pattern 410 may also have more L-shaped corners (for example, three or four). When dividing a graphic block with at least one L-shaped corner, the graphic block may be divided into more rectangular blocks (for example, four or five). Furthermore, the direction or method of dividing the graphic block may be other than those shown in the figure, as long as the graphic block can be divided into several rectangular blocks. However, dividing a graphic block with an L-shaped corner into several rectangular blocks arranged along the X-direction is more preferred because this type of division is simpler and allows for easier correction of any defects that may arise from the division in subsequent correction steps by offsetting the divided rectangular blocks in the X-direction.

[0052] In this way, manufacturing deviations or errors caused by L-shaped corners can be avoided when designing and manufacturing masks. Specifically, in the process of mask manufacturing and photolithography based on the pattern of the L-shaped corner, a pattern with rounded corners may be actually formed on the substrate due to diffraction and interference, rather than a right-angle pattern with L-shaped corners. This rounded corner pattern will expand the coverage area of ​​the graphic block, so that the coverage area exceeds the coverage area of ​​the layout design, resulting in part of the fin structure that needs to be removed not being removed. By dividing the graphic block with at least one L-shaped corner into several rectangular blocks, the L-shaped corner can be eliminated in the mask layout, thereby avoiding the appearance of rounded corner patterns that cause manufacturing defects in the subsequent manufacturing process.

[0053] Figure 8A and Figure 8B FIG. 4 is a schematic diagram showing a process of dividing a portion of graphic blocks in the layout graphic 410 of the AA layer according to an embodiment of the present disclosure. Figure 8A and Figure 8B As shown, the layout pattern 410 further includes a plurality of pattern blocks 4141, 4142, 4143, 4144, 4145, 4146, 4147, and 4148, each of which is a rectangular block. In the process of dividing the layout pattern 410 of the integrated circuit layer AA into the first pattern portion 410A and the second pattern portion 410B, the plurality of pattern blocks 4141, 4142, 4143, 4144, 4145, 4146, 4147, and 4148 can be respectively divided into the first pattern portion 410A for the first mask layout 400A or the second pattern portion 410B for the second mask layout 400B, such that the spacing between adjacent pattern blocks in the first pattern portion 410A and the second pattern portion 410B is increased compared to the spacing between adjacent pattern blocks in the layout pattern 410. For example, in subsequent correction steps, the size and shape of the pattern blocks may need to be changed, or even additional structures for auxiliary exposure may need to be placed. This requires occupying space near the pattern blocks, while still ensuring sufficient spacing between the pattern blocks. In this way, sufficient space for auxiliary exposure patterns and correction margins can be reserved for each mask layout.

[0054] Figure 9A and Figure 9B FIG. 1 is a schematic diagram showing an exemplary process of dividing the layout pattern of the integrated circuit AA layer into two mask layout patterns according to an embodiment of the present disclosure. Figure 9A and Figure 9BAs shown, the layout patterns in layout 400 include pattern blocks 411 to 413, pattern blocks 4141 to 4148, and pattern blocks 4151 to 4154. After the layout patterns are divided, pattern blocks 411A, 412A, 413A, 4142, 4144, 4145, 4147, 4151, 4153, and 4154 are arranged in the first mask layout 400A, and pattern blocks 411B, 412B, 412C, 413B, 413C, 4141, 4143, 4146, 4148, and 4152 are arranged in the second mask layout 400B. Obviously, the pattern blocks in the first mask layout 400A and the second mask layout 400B are relatively simple rectangular blocks without L-shaped corners, thereby avoiding the defects caused by L-shaped corners. In addition, the spacing between graphic blocks of the first mask layout 400A and the second mask layout 400B is larger than that of the graphic blocks of the AA layer layout, which reserves a large enough space for subsequent corrections.

[0055] Figure 10A and Figure 10B FIG. 1 is a schematic diagram showing a correction process of a pattern block 4144 in a first pattern portion 410A of a first mask 400A according to an embodiment of the present disclosure. Figure 10A and Figure 10B As shown, during the modification of the first pattern portion 410A and the second pattern portion 410B described in method 300, the rectangular block 4144 in the first pattern portion 410A may be extended by a first predetermined distance B1 in a direction perpendicular to the fin 1001. Similarly, the other rectangular blocks in the first pattern portion 410A and the second pattern portion 410B may also be extended by the first predetermined distance B1 in a direction perpendicular to the fin 1001.

[0056] According to design rules, fins 1001 are typically formed on both sides of the pattern block in the AA layer. In this case, if the alignment of the first or second mask is misaligned, the entire or a portion of the fin that should be retained may not be covered by the pattern block and thus removed, resulting in missing fin structures. By expanding or offsetting the pattern blocks or rectangular blocks of the first and second mask layouts in the Y direction, the coverage of the pattern blocks can be appropriately expanded. This ensures that the pattern blocks cover the fins that need to be retained even with slight misalignment, improving the integrated circuit manufacturing process. In some embodiments, the first predetermined distance B1 is half the spacing between two adjacent fins. If the first predetermined distance B1 is too small, it can only address scenarios with small misalignment. If the first predetermined distance B1 is too large, the pattern block may cover fin structures that should not be covered due to misalignment. By setting the first predetermined distance B1 to half the fin spacing, the adverse effects of misalignment can be minimized.

[0057] Figure 11 A schematic diagram of the correction process of the graphic block 411A in the first graphic portion 410A and the graphic block 411B in the second graphic portion 410B according to an embodiment of the present disclosure is shown. The graphic block 411 with an L-shaped corner is divided into rectangular blocks 411A and 411B. The two rectangular blocks 411A and 411B are arranged along the extension direction of the fin (i.e., the X direction) and have different boundary lengths. The rectangular block 411A belongs to the first graphic portion 410A of the first mask 400A, while the rectangular block 411B belongs to the second graphic portion 410B of the second mask 400B. Figure 11 As shown, during the correction of the first graphic portion 410A and the second graphic portion 410B as described in method 300, the rectangular block 411A with the shorter boundary length of the two rectangular blocks 411A and 411B can be extended by a second predetermined distance B2 on one side of the boundary. In other words, the rectangular block 411A is offset by the second predetermined distance B2 in the direction toward the other rectangular block 411B. By offsetting the rectangular block 411A with the shorter boundary length, the defect caused by splitting the graphic block 411 with the L-shaped corner can be eliminated. Figure 12A and Figure 12B to describe.

[0058] Figure 12A Schematic diagram of graphic blocks 411A' and 411B' formed on a substrate after a photolithography process is shown, and graphic blocks 411A' and 411B' correspond to rectangular blocks 411A and 411B that are not expanded or offset. Rectangular blocks 411A and 411B are formed by splitting graphic block 411 with an L-shaped corner. After two photolithography processes, graphic block 411A' corresponding to rectangular block 411A and graphic block 411B' corresponding to rectangular block 411B are formed on the substrate. Graphic blocks 411A' and 411B' corresponding to the two rectangular blocks 411A and 411B respectively should be recombined into graphic blocks with L-shaped corners. However, as Figure 12A As shown, due to the diffraction and interference effects of light and electron beams, pattern blocks 411A' and 411B' become rounded at their corners, resulting in defects D2 and D3 at their intersections. Defects D2 and D3 cause portions of the area that should be covered by the pattern blocks to be uncovered, resulting in the removal of the fin structure that should be retained in these portions, thus causing a manufacturing defect.

[0059] Figure 12B A schematic diagram of pattern blocks 411A'' and 411B'' formed on a substrate after a photolithography process is shown, and the pattern blocks 411A'' and 411B'' correspond to the expanded or offset rectangular blocks 411A and 411B. Figure 11 As described above, the rectangular block 411A is extended or offset by a second predetermined distance B2 in the direction toward the rectangular block 411B. Figure 12B As shown, pattern block 411A″ formed on the substrate after photolithography corresponds to the expanded or offset rectangular block 411A and is also offset by a second predetermined distance B2. Thus, even if rounded corners appear at the corners of pattern blocks 411A″ and 411B″ due to diffraction and interference, the two rounded corners of pattern block 411A″ facing pattern block 411B″ are completely covered by pattern block 411B″, effectively eliminating defects D2 and D3.

[0060] Figure 13 A schematic diagram of the correction process of the graphic block 412A in the first graphic portion 410A and the graphic blocks 412B and 412C in the second graphic portion 410B according to an embodiment of the present disclosure is shown. The graphic block 412 having two L-shaped corners is divided into rectangular blocks 412A, 412B, and 412C. The three rectangular blocks 412A, 412B, and 412C are arranged along the extension direction of the fin (i.e., the X direction) and have different boundary lengths. The rectangular block 412A belongs to the first graphic portion 410A of the first mask 400A, while the rectangular blocks 412B and 412C belong to the second graphic portion 410B of the second mask 400B. Figure 13 As shown, during the correction of first graphic portion 410A and second graphic portion 410B as described in method 300, rectangular block 412B with the shorter boundary length among two adjacent rectangular blocks 412A and 412B can be extended by a second predetermined distance B2 on one side of the boundary, and rectangular block 412C with the shorter boundary length among two adjacent rectangular blocks 412A and 412C can be extended by a second predetermined distance B2 on one side of the boundary. In other words, rectangular blocks 412B and 412C are both offset by a second predetermined distance B2 in a direction toward the other rectangular block 412B. By offsetting rectangular blocks 412B and 412C with the shorter boundary length, the defect caused by splitting the graphic block 412 having two L-shaped corners can be eliminated. The principle of this can be seen in FIG. Figure 12A and Figure 12B The content described is therefore not repeated here.

[0061] Figure 14A schematic diagram of the correction process of the graphic block 413A in the first graphic portion 410A and the graphic blocks 413B and 413C in the second graphic portion 410B according to an embodiment of the present disclosure is shown. The graphic block 413 having two L-shaped corners is divided into rectangular blocks 413A, 413B, and 413C. The three rectangular blocks 413A, 413B, and 413C are arranged along the extension direction of the fin (i.e., the X direction) and have different boundary lengths. The rectangular block 413A belongs to the first graphic portion 410A of the first mask 400A, while the rectangular blocks 413B and 413C belong to the second graphic portion 410B of the second mask 400B. Figure 14 As shown, during the process of correcting the first graphic portion 410A and the second graphic portion 410B as described in method 300, the rectangular block 413A with the shorter boundary length among the two adjacent rectangular blocks 413A and 413B can be extended by a second predetermined distance B2 on one side of the boundary, and the rectangular block 413C with the shorter boundary length among the two adjacent rectangular blocks 413A and 413C can be extended by a second predetermined distance B2 on one side of the boundary. In other words, the rectangular block 413A is offset by the second predetermined distance B2 in the direction toward the adjacent rectangular block 413B, and the rectangular block 413C is offset by the second predetermined distance B2 in the direction toward the adjacent rectangular block 413A. By offsetting the rectangular blocks 413A and 413C with the shorter boundary length, the defect caused by splitting the graphic block 413 having two L-shaped corners can be eliminated. The principle thereof refers to FIG. Figure 12A and Figure 12B The content described is therefore not repeated here.

[0062] In some embodiments of the present disclosure, the second predetermined distance B2 is half the distance between two adjacent fins. By offsetting the rectangular block with a shorter boundary length by half the distance between the fins, a sufficiently large area can be expanded to effectively eliminate potential defects D2 and D3 at the boundary between the two split rectangular blocks.

[0063] In some embodiments of the present disclosure, correcting the first graphic portion 410A and the second graphic portion 410B further includes correcting the corners of each rectangular block in the first graphic portion 410A and the second graphic portion 410B using an optical proximity correction (OPC) process. For example, the OPC process can be used to correct the corners of each rectangular block in the first graphic portion 410A and the second graphic portion 410B. Figure 12BThe rounded corner patterns at the remaining corners of pattern blocks 411A'' and 411B'' in the image are pre-corrected. These rounded corner patterns are caused by diffraction and interference of light and electron beams. By adjusting the corners of the rectangular blocks, for example, by adding raised or recessed auxiliary structures at right-angled corners, the rounded corner patterns can be corrected. Consequently, when the first and second pattern portions obtained by splitting the layout pattern of the AA layer are used to manufacture the first and second masks, potential defects that may be caused by the first and second pattern portions can be eliminated or reduced, thereby improving integrated circuit manufacturing processes, such as SADP and SAQP processes.

[0064] Figure 15 A schematic flow chart of a method 1500 for manufacturing an integrated circuit according to an embodiment of the present disclosure is shown. Method 1500 may be executed by a computing device, which may be any device with computing capabilities, such as the computing device used to execute method 300 described above.

[0065] At block 1503, a first photolithographic exposure and a second photolithographic exposure are performed on the integrated circuit substrate having the initial fin structure formed thereon, using the first mask and the second mask manufactured by method 300, respectively. Specifically, the first photolithographic exposure is performed using the first mask including the first pattern portion 410A to form a pattern corresponding to the first pattern portion 410A on the substrate. Then, the second photolithographic exposure is performed using the second mask including the second pattern portion 410B to form a pattern corresponding to the second pattern portion 410B on the substrate. The patterns formed by the two exposures are superimposed to form the layout pattern of the AA layer.

[0066] At box 1504, after the second exposure, the unexposed area of ​​the integrated circuit substrate is etched and the fin structure of the exposed area is retained. Specifically, the substrate can be processed using a process such as NTD photoresist to remove the fin structure of the unexposed area and retain the fin structure of the exposed area. For example, before exposure, the photoresist material covering the silicon substrate is soluble in an organic solvent, and after exposure, a chemical reaction occurs in the exposed area, causing the photoresist material to change to no longer be soluble in the organic solvent. Thus, after the second exposure, an organic solvent can be used to dissolve the unexposed area and etch it, thereby forming a pattern identical to the layout pattern of the AA layer. It can be seen that method 1500 can complete the manufacture of the integrated circuit with only two photolithography steps and one etching, while the conventional scheme using redundant pattern shear layer mask requires two photolithography steps and two etching steps. In this way, the process of integrated circuit manufacturing can be simplified, costs can be reduced, and overall efficiency can be improved.

[0067] In some embodiments of the present disclosure, method 1500 may further include blocks 1501 and 1502. At block 1501, a plurality of fin cores arranged in parallel are formed on an integrated circuit substrate using a third mask. For example, the third mask may be a fin core mask having a fin core pattern formed thereon. Using the fin core mask and photolithographic exposure, a fin core structure is formed on the substrate. The fin core structure is formed over the entire substrate and comprises a set of parallel linear patterns extending along the X-direction. The parallel linear patterns are spaced apart from each other in the Y-direction and have a pitch twice the fin pitch. At block 1502, an initial fin structure is formed on both sides of each of the plurality of fin cores. For example, a series of processes, including spacer deposition and etching, may be used to form fins on both sides of the fin core. Since the initial fin structure is formed based on the fin core structure, it also comprises a set of parallel linear patterns formed over the entire substrate. Each fin extends in the X-direction and is spaced apart from other fins in the Y-direction. The fin pitch is half the fin core pitch. In this manner, integrated circuits with higher pattern density can be manufactured at lower photolithographic resolution.

[0068] Figure 16 FIG1 shows a schematic diagram of an integrated circuit manufactured by method 1500 according to an embodiment of the present disclosure. Figure 16 As shown, after the initial fin structure is formed on the substrate, a negative development process is used and two photolithography steps and only one etching step are performed to ensure that the fin structure covered by the AA layer of the layout can be retained without defects.

[0069] Figure 17 FIG17 is a schematic block diagram of an example device 1700 that can be used to implement embodiments of the present disclosure. The device 1700 can be implemented as a computing device for performing methods 300 and 1500.

[0070] As shown, device 1700 includes a central processing unit (CPU) 1701, which can perform various appropriate actions and processes according to computer program instructions stored in a read-only memory (ROM) 1702 or loaded from a storage unit 1708 into a random access memory (RAM) 1703. RAM 1703 may also store various programs and data required for the operation of device 1700, such as the measurement data mentioned above. CPU 1701, ROM 1702, and RAM 1703 are interconnected via a bus 1704. An input / output (I / O) interface 1705 is also connected to bus 1704.

[0071] Various components in device 1700 are connected to I / O interface 1705, including an input unit 1706, such as a keyboard, mouse, etc.; an output unit 1707, such as various types of displays, speakers, etc.; a storage unit 1708, such as a magnetic disk, optical disk, etc.; and a communication unit 1709, such as a network card, modem, wireless communication transceiver, etc. The communication unit 1709 allows device 1700 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0072] Processing unit 1701 performs the methods or processes described above, methods 300 and 1500. For example, in some embodiments, methods 300 and 1500 may be implemented as a computer software program or computer program product tangibly embodied on a machine-readable medium, such as a non-transitory computer-readable medium, such as storage unit 1708. In some embodiments, part or all of the computer program may be loaded and / or installed onto device 1700 via ROM 1702 and / or communication unit 1709. When the computer program is loaded into RAM 1703 and executed by CPU 1701, one or more steps of methods 300 and 1500 described above may be performed. Alternatively, in other embodiments, CPU 1701 may be configured to perform methods 300 and 1500 in any other suitable manner (e.g., via firmware).

[0073] Those skilled in the art will appreciate that the various steps of the method disclosed above can be implemented by a general-purpose computing device. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they can be implemented using program code executable by a computing device, which can then be stored in a storage device and executed by the computing device. Alternatively, they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present disclosure is not limited to any particular combination of hardware and software.

[0074] It should be understood that although the detailed description above mentions several devices or sub-devices of a device, this division is merely exemplary and not mandatory. In fact, according to embodiments of the present disclosure, the features and functions of two or more devices described above may be embodied in a single device. Conversely, the features and functions of a single device described above may be further divided and embodied by multiple devices.

[0075] The foregoing description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that the present disclosure is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A method for manufacturing a mask, comprising: Dividing the layout pattern of the integrated circuit active layer into a first pattern portion and a second pattern portion; modifying the first graphic portion and the second graphic portion; as well as Based on the corrected first and second graphic portions, manufacturing data for a first mask and manufacturing data for a second mask are determined respectively, and the first and second masks form light-transmitting areas at the corrected first and second graphic portions respectively.

2. The method according to claim 1, wherein the layout pattern comprises a first pattern block having at least one L-shaped corner, and wherein dividing the layout pattern of the active layer of the integrated circuit into the first pattern portion and the second pattern portion comprises: Dividing the first graphic block into at least two rectangular blocks; as well as Two adjacent rectangular blocks among the at least two rectangular blocks are divided into the first graphic part and the second graphic part respectively.

3. The method according to claim 2, wherein the layout pattern further comprises at least one second pattern block, each second pattern block is a rectangular block, and The method of dividing the layout pattern of the integrated circuit active layer into the first pattern portion and the second pattern portion further comprises: The at least one second graphic block is divided into the first graphic portion or the second graphic portion respectively, so that the spacing between adjacent graphic blocks in the first graphic portion and the second graphic portion is increased compared to the spacing between adjacent graphic blocks in the layout graphic.

4. The method of claim 3 , wherein modifying the first graphic portion and the second graphic portion comprises: The rectangular blocks in the first pattern portion and the second pattern portion are extended by a first predetermined distance in a direction perpendicular to the fin. 5 . The method according to claim 4 , wherein the first predetermined distance is half of a distance between two adjacent fins.

6. The method according to claim 2 or 4, wherein two adjacent rectangular blocks of the at least two rectangular blocks are arranged along the extension direction of the fin and have different boundary lengths from each other, and The modifying of the first graphic portion and the second graphic portion includes: The rectangular block with the shorter boundary length among the two adjacent rectangular blocks is extended by a second predetermined distance on one side of the boundary. The method according to claim 6 , wherein the second predetermined distance is half of a distance between two adjacent fins.

8. The method of claim 6, wherein modifying the first graphic portion and the second graphic portion comprises: The corners of the rectangular blocks in the first graphic portion and the second graphic portion are corrected using an optical proximity correction process. 9 . The method according to claim 1 , wherein the first mask and the second mask are used in a self-aligned double patterning process or a self-aligned quadruple patterning process.

10. A method of manufacturing an integrated circuit, comprising: Using the first mask and the second mask manufactured by the method according to any one of claims 1 to 9, respectively, to perform a first photolithography exposure and a second photolithography exposure on the integrated circuit substrate having the initial fin structure formed thereon; and After the second photolithography exposure, the unexposed area of ​​the integrated circuit substrate is etched and the fin structure of the exposed area is retained.

11. The method of manufacturing an integrated circuit according to claim 10, further comprising: forming a plurality of fin cores arranged in parallel on the integrated circuit substrate using a third mask; as well as The initial fin structure is formed on both sides of a corresponding fin core of the plurality of fin cores.

12. An electronic device comprising: processor; as well as A memory coupled to the processor, the memory having instructions stored therein, the instructions causing the electronic device to perform actions when executed by the processor, the actions comprising: Dividing the layout pattern of the integrated circuit active layer into a first pattern portion and a second pattern portion; modifying the first graphic portion and the second graphic portion; and Based on the corrected first and second graphic portions, manufacturing data for a first mask and manufacturing data for a second mask are determined respectively, and the first and second masks form light-transmitting areas at the corrected first and second graphic portions respectively.

13. The electronic device of claim 12, wherein the actions further comprise: Using the first mask and the second mask, respectively, a first exposure and a second exposure are performed on the integrated circuit substrate having the initial fin structure formed thereon; as well as After the second exposure, the unexposed area of ​​the integrated circuit substrate is etched and the fin structure of the exposed area is retained.

14. A computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the method according to any one of claims 1 to 11 is implemented.

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