Operational amplifier with compensation circuit, chip and electronic equipment

Abstract

The invention provides an operational amplifier with a compensation circuit, a chip and electronic equipment, and the amplifier comprises a differential pair module which is connected with two input signals and is used for carrying out the differential processing of the two input signals, and generating a differential signal; the folded cascode circuit comprises two stages of operational amplifiers; the bias current mirror circuit is respectively connected with the two stages of operational amplifiers and is used for providing bias current; the folded cascode circuit is used for performing two-stage amplification on the differential signal to obtain an output signal; wherein the RC network is connected between the positive output end and the negative output end of the auxiliary operational amplifier, and the phase margin of the folded cascode circuit is compensated by adding a pair of zero poles. The RC network is added to the output end of the auxiliary operational amplifier, and a pair of zero poles is added, so that the phase margin of the system becomes better, and the small signal establishment speed is also increased; meanwhile, the newly added RC network design method does not need to optimize the performance by increasing the size of the auxiliary operational amplifier, so that the size of the auxiliary operational amplifier is reduced, and the area and the power consumption are also reduced.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and more particularly to an operational amplifier, a chip, and an electronic device having a compensation circuit. Background Art

[0002] In integrated circuits, operational amplifiers, as key units, are widely used in various analog and mixed-signal integrated circuits. In pipelined analog-to-digital converters, there are many switched-capacitor amplifier circuits centered around operational amplifiers, and the performance of the operational amplifier also affects the performance of the converter.

[0003] In switched-capacitor amplifier circuits, the design specifications of operational amplifiers include gain, gain-bandwidth product, stability (phase margin), and slew rate, etc. When the gain meets certain requirements, the time-domain response of the operational amplifier is designed. Here, only the small-signal time-domain establishment is concerned, and the corresponding concept is the phase margin. However, in previous designs, the small-signal time-domain establishment speed was optimized by adjusting the sizes of the auxiliary operational amplifier and the main operational amplifier. However, for a fixed process, the upper limit of its optimization is almost fixed, which has limitations. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present application is to provide an operational amplifier, a chip, and an electronic device having a compensation circuit, which are used to solve the problem of breaking through the limitations introduced by the structure and process in the prior art to improve the phase margin.

[0005] In a first aspect, to achieve the above object and other related objects, the present application provides an operational amplifier having a compensation circuit, including: a differential pair module, which accesses two input signals and is used to perform differential processing on the two input signals to generate a differential signal; a folded cascode circuit including a two-stage operational amplifier; a bias current mirror circuit, which is respectively connected to the two-stage operational amplifier to provide a bias current; a folded cascode circuit, which is used to amplify the differential signal in two stages to obtain an output signal; wherein, an RC network is connected between the positive and negative output terminals of the auxiliary operational amplifier, and a pair of zero-poles is added to compensate the phase margin of the folded cascode circuit. The auxiliary operational amplifier is the first operational amplifier in the first stage of the operational amplifier.

[0006] In an embodiment of the present application, the RC network includes a first resistor, a second resistor, and a capacitor, and the capacitor is connected in series between the first resistor and the second resistor.

[0007] In an embodiment of the present application, the two-stage operational amplifier includes a first-stage operational amplifier and a second-stage operational amplifier; the first-stage operational amplifier includes a first operational amplifier, a first transistor, and a second transistor. The first transistor and the second transistor are in a cascode structure. The positive input terminal of the auxiliary operational amplifier is connected to the source of the first transistor, and the negative output terminal is connected to the gate of the first transistor; the negative input terminal of the auxiliary operational amplifier is connected to the source of the second transistor, and the positive output terminal is connected to the gate of the second transistor; the second-stage operational amplifier includes a second operational amplifier, a third transistor, and a fourth transistor. The third transistor and the fourth transistor are in a cascode structure. The positive input terminal of the second operational amplifier is connected to the source of the third transistor, and the negative output terminal is connected to the gate of the third transistor; the negative input terminal of the second operational amplifier is connected to the source of the fourth transistor, and the positive output terminal is connected to the gate of the fourth transistor; wherein, the drains of the first transistor and the third transistor are connected together as the first output voltage, and the drains of the second transistor and the fourth transistor are connected together as the second output voltage.

[0008] In an embodiment of the present application, the bias current mirror circuit includes a first bias current mirror circuit and a second bias current mirror circuit; the first bias current mirror circuit includes a fifth transistor and a sixth transistor. The gates of the fifth transistor and the sixth transistor are connected to the first bias voltage. The sources of the fifth transistor and the sixth transistor are grounded. The drain of the fifth transistor is connected to the source of the first transistor, and the drain of the sixth transistor is connected to the source of the second transistor; the second bias current mirror circuit includes a seventh transistor and an eighth transistor. The gates of the seventh transistor and the eighth transistor are connected to the second bias voltage. The sources of the seventh transistor and the eighth transistor are connected to the power supply voltage. The drain of the seventh transistor is connected to the source of the third transistor, and the drain of the eighth transistor is connected to the source of the fourth transistor.

[0009] In an embodiment of the present application, the first transistor, the second transistor, the fifth transistor, and the sixth transistor are NMOS transistors; the third transistor, the fourth transistor, the seventh transistor, and the eighth transistor are PMOS transistors.

[0010] In an embodiment of the present application, the differential pair module includes a ninth transistor and a tenth transistor; the gate of the ninth transistor is connected to the negative input signal, and the drain of the ninth transistor is connected to the negative input terminal of the auxiliary operational amplifier; the gate of the tenth transistor is connected to the positive input signal, and the drain of the tenth transistor is connected to the positive input terminal of the auxiliary operational amplifier. The sources of the ninth transistor and the tenth transistor are connected together.

[0011] In an embodiment of the present application, the sources of the ninth transistor and the tenth transistor are connected to one end of a current source, and the other end of the current source is connected to the power supply voltage.

[0012] In an embodiment of the present application, the ninth transistor and the tenth transistor are PMOS transistors.

[0013] In a second aspect, the present application provides a chip, including the operational amplifier with a compensation circuit as described above.

[0014] In a third aspect, the present application provides an electronic device, including the operational amplifier with a compensation circuit as described above.

[0015] As described above, the operational amplifier, chip and electronic device with a compensation circuit of the present application have the following beneficial effects:

[0016] First, after the differential signal is amplified by two stages of the folded cascode circuit, an amplified output signal is obtained; since the bias current mirror circuit provides a stable bias current, the operating point of the operational amplifier is ensured to be stable; the RC network compensates the phase margin of the folded cascode circuit by introducing a pair of zero-poles, improving the stability of the system.

[0017] Second, by adding an RC network at the output end of the auxiliary operational amplifier, a pair of zero-poles are added, making the phase margin of the system better and also improving the small-signal establishment speed; at the same time, the design method of the newly added RC network does not need to optimize the performance by increasing the size of the auxiliary operational amplifier, reducing the size of the auxiliary operational amplifier, and also reducing the area and power consumption of the operational amplifier. Description of the Drawings

[0018] Figure 1 It shows a block diagram of an operational amplifier with a compensation circuit provided by an embodiment of the present application;

[0019] Figure 2 It shows a circuit diagram of an operational amplifier with a compensation circuit provided by an embodiment of the present application;

[0020] Figure 3 It shows a circuit diagram of the zero-pole distribution of an operational amplifier with a compensation circuit before compensation provided by an embodiment of the present application;

[0021] Figure 4 It shows a circuit diagram of the zero-pole distribution of an operational amplifier with a compensation circuit after compensation provided by an embodiment of the present application.

[0022] Description of Component Labels:

[0023] 1: Differential pair module, 2: Folded cascode circuit, 3: Bias current mirror circuit, 4: RC network, M1 to M10: First transistor to tenth transistor, Au1: First operational amplifier, Au2: Second operational amplifier, V b1 : First bias voltage, V b2 : Second bias voltage, V ON : First output voltage, V OP : Second output voltage, R1: First resistor, R2: Second resistor, C: Capacitor. Detailed Implementation Modes

[0024] The following specific examples illustrate the implementation modes of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific implementation modes. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0025] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present application in a schematic manner. Therefore, only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0026] Please refer to Figure 1 , which shows a structural block diagram of an operational amplifier with a compensation circuit provided by an embodiment of the present application, including:

[0027] A differential pair module 1, which accesses two input signals and is used to perform differential processing on the two input signals to generate a differential signal;

[0028] The folded cascode circuit 2 includes two-stage operational amplifiers; a bias current mirror circuit 3, which is respectively connected to the two-stage operational amplifiers to provide bias current; the folded cascode circuit is used to amplify the differential signal in two stages to obtain an output signal;

[0029] Among them, an RC network 4 is connected between the positive and negative output terminals of the auxiliary operational amplifier to compensate for the phase margin of the folded cascode circuit by adding a pair of zero-poles. The auxiliary operational amplifier is the first operational amplifier in the first stage of operational amplifiers.

[0030] Exemplarily, the differential pair module can suppress common-mode noise and improve the anti-interference ability of the signal. When there are the same noise components in the two input signals, the noise components are cancelled out during the differential processing. For example, different types of differential pairs, such as complementary metal oxide semiconductor (CMOS) differential pairs or bipolar junction transistor (BJT) differential pairs, can also be used, and the appropriate type can be selected according to the specific application scenario to improve the signal-to-noise ratio of the signal. Differential processing means taking the voltage difference between the two input signals as the output signal. The folded cascode structure can provide a high output impedance and gain, while reducing the power supply voltage consumption.

[0031] Through two-stage amplification, the gain of the signal is further improved. The folded cascode circuit consists of two-stage operational amplifiers, which perform two-stage amplification on differential signals. The first-stage operational amplifier receives the differential signal, and the second-stage operational amplifier further amplifies the output of the first stage. The bias current mirror circuit generates the required bias current by copying a reference current. This structure can ensure the stability and consistency of the current. The bias current mirror circuit is connected to the two-stage operational amplifiers respectively to provide stable bias current for each stage of the operational amplifier.

[0032] Exemplarily, the RC network can adjust the phase margin of the circuit by introducing additional frequency response characteristics. When the frequency response of the circuit approaches the unstable region, the RC network can provide necessary phase compensation to ensure the stability of the circuit. By adjusting the parameters of the RC network, a pair of zero-poles can be added to compensate the phase margin of the folded cascode circuit. Of course, other types of phase compensation methods, such as Miller compensation or nested Miller compensation, can be used to select a suitable compensation strategy according to specific requirements. Improve the phase margin of the circuit to ensure that the circuit can operate stably at various frequencies.

[0033] In some embodiments, the RC network 4 includes a first resistor R1, a second resistor R2 and a capacitor C, and the capacitor C is connected in series between the first resistor R1 and the second resistor R2.

[0034] Among them, an RC series network is added at the output end of the auxiliary operational amplifier (i.e., the first operational amplifier Au1). Through theoretical analysis, it can be known that this RC series network will add a pair of zero-pole pairs to the system and change the overall zero-pole distribution.

[0035] In the above way, on the one hand, by adjusting the values of R1, R2 and C, precise control of the frequency components of the signal can be achieved, such as attenuating high-frequency components, enhancing low-frequency components, etc.; on the other hand, the introduction of the capacitor C can change the phase of the signal, so that the signal maintains a certain phase relationship during the processing; in addition, the stability of the circuit can be improved through the RC network, and reduce the circuit oscillation or instability phenomenon caused by frequency changes.

[0036] In some embodiments, please refer to Figure 2 , for the circuit diagram of an operational amplifier with a compensation circuit provided by an embodiment of the present application, which is described in detail as follows:

[0037] The two-stage operational amplifier includes a first-stage operational amplifier and a second-stage operational amplifier;

[0038] The first - stage operational amplifier includes a first operational amplifier Au1 (auxiliary operational amplifier), a first transistor M1, and a second transistor M2. The first transistor M1 and the second transistor M2 form a cascode structure. The positive input terminal of the auxiliary operational amplifier is connected to the source of the first transistor M1, and the negative output terminal is connected to the gate of the first transistor M1; the negative input terminal of the auxiliary operational amplifier is connected to the source of the second transistor M2, and the positive output terminal is connected to the gate of the second transistor M2;

[0039] The second - stage operational amplifier includes a second operational amplifier Au2, a third transistor M3, and a fourth transistor M4. The third transistor M3 and the fourth transistor M4 form a cascode structure. The positive input terminal of the second operational amplifier Au2 is connected to the source of the third transistor M3, and the negative output terminal is connected to the gate of the third transistor M3; the negative input terminal of the second operational amplifier Au2 is connected to the source of the fourth transistor M4, and the positive output terminal is connected to the gate of the fourth transistor M4;

[0040] Among them, the drains of the first transistor M1 and the third transistor M3 are connected together as the first output voltage V ON ; the drains of the second transistor M2 and the fourth transistor M4 are connected together as the second output voltage V OP .

[0041] Exemplarily, the cascode structure increases the equivalent transconductance and output impedance through the cascade of two transistors, thereby increasing the gain; the negative - feedback mechanism helps to stabilize the output of the amplifier and reduce the non - linear distortion; the second stage further amplifies the output signal of the first stage, increasing the total gain.

[0042] In the above - mentioned manner, through the design of two - stage cascode operational amplifiers, the technical problems of improving the gain, stability, and output impedance are effectively solved; where each stage adopts a cascode structure with negative - feedback control, which not only increases the gain but also improves the stability of the circuit; in addition, this application has a certain degree of flexibility and can adjust the transistor type and operational - amplifier type according to specific application requirements; finally, this design presents technical effects of high gain, low noise, and high stability, and is suitable for application scenarios that require high - precision and high - performance amplification.

[0043] In some embodiments, the bias current - mirror circuit 3 includes a first bias current - mirror circuit and a second bias current - mirror circuit;

[0044] The first bias current - mirror circuit includes a fifth transistor M5 and a sixth transistor. The gates of the fifth transistor M5 and the sixth transistor M6 are connected to the first bias voltage V b1 , the sources of the fifth transistor M5 and the sixth transistor M6 are grounded, the drain of the fifth transistor M5 is connected to the source of the first transistor, and the drain of the sixth transistor M6 is connected to the source of the second transistor;

[0045] The second bias current mirror circuit includes a seventh transistor M7 and an eighth transistor M8. The gates of the seventh transistor M7 and the eighth transistor M8 are connected to a second bias voltage V b2 , the sources of the seventh transistor M7 and the eighth transistor M8 are connected to the power supply voltage, the drain of the seventh transistor M7 is connected to the source of the third transistor, and the drain of the eighth transistor M8 is connected to the source of the fourth transistor.

[0046] It should be noted that the first transistor, the second transistor, the fifth transistor M5 and the sixth transistor M6 are NMOS transistors; the third transistor, the fourth transistor, the seventh transistor M7 and the eighth transistor M8 are PMOS transistors.

[0047] In the above manner, by adopting a bias current mirror circuit, it can be ensured that each transistor operates stably within its normal operating region, thereby improving the stability of the entire circuit. At the same time, the stable bias current helps to improve the performance of the circuit, such as gain, linearity, noise, etc.; by precisely controlling the size and bias voltage of the transistor, the magnitude of the bias current can be precisely controlled, thereby meeting the requirements of the circuit for the accuracy of the bias current.

[0048] In some embodiments, the differential pair module includes a ninth transistor M9 and a tenth transistor M10; the gate of the ninth transistor M9 is connected to the negative input signal, and the drain of the ninth transistor M9 is connected to the negative input terminal of the auxiliary operational amplifier; the gate of the tenth transistor M10 is connected to the positive input signal, and the drain of the tenth transistor M10 is connected to the positive input terminal of the auxiliary operational amplifier. The sources of the ninth transistor M9 and the tenth transistor M10 are connected together.

[0049] Among them, the sources of the ninth transistor M9 and the tenth transistor M10 are connected to one end of a current source, the other end of the current source is connected to the power supply voltage, and the ninth transistor M9 and the tenth transistor M10 are PMOS transistors.

[0050] It should be noted that the auxiliary operational amplifier is used to further amplify the current difference generated by the differential pair and convert it into a voltage output. Due to the high input impedance and low output impedance of the auxiliary operational amplifier, it can effectively isolate the differential pair and the subsequent circuit, and at the same time provide a stable gain.

[0051] In the above manner, through the design of the differential pair module, precise amplification of the differential signal is achieved, improving the accuracy and stability of signal processing; the differential signal itself has the characteristic of strong anti-interference ability, and the differential pair module further enhances this ability, enabling the circuit to still operate normally in a noisy environment.

[0052] Please refer to Figure 3 , which is the zero-pole distribution circuit diagram before compensation of an operational amplifier with a compensation circuit provided by an embodiment of the present application; please refer to Figure 4, which is the circuit diagram of the zero-pole distribution after compensation of an operational amplifier with a compensation circuit provided by an embodiment of the present application.

[0053] The present application introduces a pair of additional zero-pole pairs for the operational amplifier to adjust the phase margin of the system, so as to improve the establishment of small-signal in the time domain, which is mainly applicable to folded cascode and telescopic operational amplifiers with a gain-boost structure.

[0054] Specifically, since the circuit is a fully differential structure, for the convenience of description, 2a and 2b are collectively referred to as node 2, and 3a and 3b are collectively referred to as node 3. In this structure, the main pole is at the output node, that is, the second output voltage V OP , the first output voltage V ON . The second pole appears at the output node of the auxiliary operational amplifier, that is, node 2, which depends on the gain-bandwidth product of the auxiliary operational amplifier, and the third pole appears at node 3. Due to the parasitic capacitance between nodes 2 and 3, a left-half plane zero will be introduced into the system. At this time, there are mainly three poles and one zero in the system, all in the left-half plane. Adjusting the phase margin of the system is equivalent to adjusting the distribution of these zeros and poles.

[0055] Through theoretical analysis, it can be known that this RC series network will add a pair of zero-pole pairs to the system and change the overall zero-pole distribution; the zero-pole distributions before and after adding the compensation network are respectively as Figure 3 and Figure 4 shown; among them, Figure 3 has three poles (P1, P2, P3) and one zero (Z1), all in the left-half plane. The main pole P1 is at the output node, that is, the second output voltage V OP , the first output voltage V ON . Node 2 corresponds to pole P2, and node 3 corresponds to pole P3. Pole P2 and pole P3 will form a pair of conjugate complex poles.

[0056] Figure 4 In

[0057] , after introducing the RC network, new poles P4 and zero Z2 are generated. If the frequency of pole P4 is greater than that of pole P2, then pole P4 will replace pole P2 and form a pair of conjugate complex poles with pole P3 at a higher frequency. Since the real part of the complex pole pair is pushed to a higher frequency and the imaginary part remains almost unchanged, the phase margin of the system is improved. At this time, pole P2 and zero Z2 can be regarded as a pair of zero-pole pairs, and the effects introduced into the frequency response can almost cancel each other. The relative position of pole P2 and zero Z2 can be achieved by adjusting the capacitance value. The frequency of pole P2 needs to be greater than that of zero Z2, otherwise, the system will have a Droop effect.

[0058] In this embodiment, since any of the above operational amplifiers is included, it is beneficial to improve the phase margin of the product to a certain extent and enhance the stability of the system.

[0059] In a third aspect, the present application provides an electronic device including the above operational amplifier with a compensation circuit.

[0060] In this embodiment, since any of the above operational amplifiers is included, it is beneficial to improve the phase margin of the product to a certain extent and enhance the stability of the system.

[0061] In summary, the operational amplifier, chip, and electronic device with a compensation circuit in the present application have the following technical effects:

[0062] First, after the differential signal is amplified by two stages of the folded cascode circuit, an amplified output signal is obtained; since the bias current mirror circuit provides a stable bias current, the operating point of the operational amplifier is ensured to be stable; the RC network compensates for the phase margin of the folded cascode circuit by introducing a pair of zero-poles, enhancing the stability of the system; second, by adding an RC network at the output of the auxiliary operational amplifier, a pair of zero-poles are added, making the system phase margin better and also improving the small-signal establishment speed; at the same time, the design method of the newly added RC network does not require optimizing the performance by increasing the size of the auxiliary operational amplifier, reducing the size of the auxiliary operational amplifier, as well as the area and power consumption of the operational amplifier.

[0063] The above embodiments merely illustrate the principles and effects of the present application and are not intended to limit the present application. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present application should still be covered by the claims of the present application.

Claims

1. An operational amplifier with a compensation circuit, characterized in that: include: A differential pair module receives two input signals and is used to perform differential processing on the two input signals to generate a differential signal; The folded cascode circuit includes two stages of operational amplifiers; A bias current mirror circuit is connected to the two-stage operational amplifiers to provide a bias current; The folded cascode circuit is used to perform two-stage amplification on the differential signal to obtain an output signal; The RC network is connected between the positive and negative output terminals of the auxiliary operational amplifier, and compensates for the phase margin of the folded common-source and common-gate circuit by adding a pair of zero poles. The auxiliary operational amplifier is the first operational amplifier in the first-stage operational amplifier.

2. The operational amplifier with compensation circuit according to claim 1, characterized in that: The RC network includes a first resistor, a second resistor and a capacitor, and the capacitor is connected in series between the first resistor and the second resistor.

3. The operational amplifier with compensation circuit according to claim 2, characterized in that: The two-stage operational amplifier comprises a first-stage operational amplifier and a second-stage operational amplifier; The first-stage operational amplifier includes a first operational amplifier, a first transistor and a second transistor, the first transistor and the second transistor are in a common-source common-gate structure, the positive input terminal of the auxiliary operational amplifier is connected to the source of the first transistor, and the negative output terminal is connected to the gate of the first transistor; the negative input terminal of the auxiliary operational amplifier is connected to the source of the second transistor, and the positive output terminal is connected to the gate of the second transistor; The second-stage operational amplifier includes a second operational amplifier, a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are of a common-source common-gate structure, a positive input terminal of the second operational amplifier is connected to a source of the third transistor, and a negative output terminal is connected to a gate of the third transistor; The negative input terminal of the second operational amplifier is connected to the source of the fourth transistor, and the positive output terminal is connected to the gate of the fourth transistor; The drains of the first transistor and the third transistor are connected to serve as a first output voltage, and the drains of the second transistor and the fourth transistor are connected to serve as a second output voltage.

4. The operational amplifier with compensation circuit according to claim 3, characterized in that: The bias current mirror circuit includes a first bias current mirror circuit and a second bias current mirror circuit; the first bias current mirror circuit includes a fifth transistor and a sixth transistor, the gates of the fifth transistor and the sixth transistor are connected to a first bias voltage, the sources of the fifth transistor and the sixth transistor are grounded, the drain of the fifth transistor is connected to the source of the first transistor, and the drain of the sixth transistor is connected to the source of the second transistor; The second bias current mirror circuit includes a seventh transistor and an eighth transistor, wherein the gates of the seventh transistor and the eighth transistor are connected to a second bias voltage, the sources of the seventh transistor and the eighth transistor are connected to a power supply voltage, the drain of the seventh transistor is connected to the source of the third transistor, and the drain of the eighth transistor is connected to the source of the fourth transistor.

5. The operational amplifier with compensation circuit according to claim 4, characterized in that: The first transistor, the second transistor, the fifth transistor and the sixth transistor are NMOS transistors; the third transistor, the fourth transistor, the seventh transistor and the eighth transistor are PMOS transistors.

6. The operational amplifier with compensation circuit according to claim 3, characterized in that: The differential pair module includes a ninth transistor and a tenth transistor; the gate of the ninth transistor is connected to a negative input signal, and the drain of the ninth transistor is connected to a negative input terminal of the auxiliary operational amplifier; the gate of the tenth transistor is connected to a positive input signal, and the drain of the tenth transistor is connected to a positive input terminal of the auxiliary operational amplifier, and the ninth transistor is connected to a source of the tenth transistor.

7. The operational amplifier with compensation circuit according to claim 6, characterized in that: The source of the ninth transistor and the source of the tenth transistor are connected to one end of a current source, and the other end of the current source is connected to a power supply voltage.

8. The operational amplifier with compensation circuit according to claim 6, characterized in that: The ninth transistor and the tenth transistor are PMOS transistors.

9. A chip, characterized in that: The invention comprises an operational amplifier with a compensation circuit as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that: The invention comprises an operational amplifier with a compensation circuit as claimed in any one of claims 1 to 8.

Images