Signal transmission circuit, signal transmission circuit generation method, signal transmission circuit generation device and chip
By introducing a bypass module into the chip signal transmission circuit, providing bypass paths at specific clock frequency, the problem of large signal delay in high-performance chips is solved, and the signal transmission delay reduction and establishment time are achieved at high operating frequency.
Patent Information
- Application Number
- CN202510344282.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-21
- Publication Date
- 2025-06-27
AI Technical Summary
In high-performance chips, the physical distance of signal transmission is long, resulting in a large signal delay. Especially at high operating frequency, the signal cannot meet the establishment time requirements in time, resulting in sampling errors.
A signal transmission circuit is designed, including a plurality of relay modules and at least one bypass module. The relay module transmits the target signal in sequence based on the clock signal, and the bypass module provides a bypass path for the target signal at a specific clock frequency to reduce the signal transmission clock period.
Through the bypass path, the target signal reduces the clock cycle during the transmission process, effectively reduces the signal delay, improves the efficiency of signal transmission, and meets the establishment time requirements at high operating frequency.
Smart Images
Figure CN120223030A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit technology, and in particular, to a signal transmission circuit, a generation method, a device, and a chip thereof. Background Art
[0002] In high-performance chips, there is often a situation where the physical distance of signal transmission is relatively long. In this case, the signal generally needs to experience a long time delay to reach the next register (such as the destination register) from one register (such as the source register). If the operating frequency of the circuit is relatively high, it is very likely that the signal arrives too late to meet the setup time requirement at this operating frequency, resulting in the signal being unable to be correctly sampled at the current operating frequency.
[0003] In the related art, in order to maintain the operating frequency without reduction, a repeater can be inserted into the signal transmission path so that the setup time requirement at the current operating frequency can be met between every two adjacent registers. However, the cost of doing so is that the signal needs to pass through multiple clock cycles to reach the destination register from the source register, so the signal delay will be relatively large.
[0004] Specifically, the higher the operating frequency of the circuit, the less time is available for signal transmission after deducting the setup time within one cycle. When the signal transmission speed is constant, the shorter the signal transmission distance, the denser the inserted repeaters. Therefore, in chip design, the insertion scheme of repeaters is usually planned according to the maximum value of the operating frequency (i.e., the highest frequency). However, in this way, when the operating frequency is lower than the highest frequency, the signal also has to pass through so many clock cycles from the source register to the destination register, resulting in an unnecessarily large signal delay. Summary of the Invention
[0005] In view of this, embodiments of the present invention provide a signal transmission circuit, a generation method, a device, a chip, an electronic device, and a storage medium, which can effectively reduce signal delay.
[0006] In a first aspect, an embodiment of the present invention provides a signal transmission circuit, including: a plurality of relay modules configured to sequentially transmit a target signal based on a clock signal, where the plurality of relay modules include a first relay module and a second relay module arranged along the transmission direction of the target signal; at least one bypass module, where the at least one bypass module includes a first bypass module, and an input end of the first bypass module is electrically connected to the first relay module and the second relay module respectively; the first bypass module is configured to provide a bypass path for the target signal passing through the first relay module when the frequency of the clock signal is a first frequency.
[0007] In one embodiment, the plurality of relay modules further includes a third relay module arranged along the target signal transmission direction, and an output end of the first bypass module is electrically connected to the third relay module.
[0008] In one embodiment, the at least one bypass module further includes a second bypass module. An input end of the second bypass module is electrically connected to an output end of the first bypass module and an output end of the third relay module respectively. The second bypass module is configured to provide a bypass path for the target signal passing through the first bypass module when the frequency of the clock signal is the first frequency.
[0009] In one embodiment, the number of the second bypass modules is at least one, and the number of the third relay modules is equal to the number of the second bypass modules; the third relay modules and the second bypass modules are in one-to-one correspondence, and each second bypass module and the corresponding third relay module form a first combination, and the first combinations are connected in series in sequence along the target signal transmission direction at the output end of the first bypass module.
[0010] In one embodiment, the input end of the first bypass module includes a first input end and a second input end. The first input end is electrically connected to an output end of the first relay module, and the second input end is electrically connected to an output end of the second relay module.
[0011] In one embodiment, the number of the first bypass modules is at least one, and the number of the first relay modules and the number of the second relay modules are both equal to the number of the first bypass modules; the first bypass modules, the first relay modules, and the second relay modules are in one-to-one correspondence, and each first bypass module and the corresponding first relay module and the corresponding second relay module form a second combination, and the second combinations are connected in series with each other along the target signal transmission direction.
[0012] In one embodiment, the plurality of relay modules further includes a fourth relay module, and the fourth relay module is connected in series between any two adjacent second combinations.
[0013] In one embodiment, the signal transmission circuit further includes: a control module, electrically connected to the at least one bypass module, and configured to control each of the first bypass modules to provide a bypass path for the target signal when the frequency of the clock signal is at the first frequency.
[0014] In one embodiment, the control module is further configured to control the target signal to sequentially pass through the first relay module, the second relay module, and the first bypass module when the frequency of the clock signal is at a second frequency, where the second frequency is greater than the first frequency.
[0015] In one embodiment, the first frequency is one Nth of the second frequency, where N is an integer greater than 1.
[0016] In one embodiment, the control module includes: a determination sub-module configured to determine whether the frequency of the clock signal is the first frequency; a sending sub-module electrically connected to the determination sub-module and configured to send a first control signal to the first bypass module so that the first bypass module receiving the first control signal provides a bypass path for the target signal.
[0017] In one embodiment, the sending sub-module is further configured to send a second control signal to other bypass modules in the at least one bypass module except the bypass module for receiving the first control signal, so that the bypass module receiving the second control signal refuses to provide a bypass path for the target signal.
[0018] In one embodiment, the first bypass module includes a multiplexer, and the multiplexer includes a control end, and the control module is configured to be electrically connected to the control ends of the respective multiplexers.
[0019] In one embodiment, the relay module includes at least one of the following: a flip-flop, a register.
[0020] In a second aspect, an embodiment of the present invention further provides a chip, and the chip includes any signal transmission circuit provided by the embodiment of the present invention.
[0021] In a third aspect, an embodiment of the present invention further provides a method for generating a signal transmission circuit, including: obtaining a relay circuit, where the relay circuit includes a plurality of relay modules; the plurality of relay modules are configured to sequentially transmit a target signal based on a clock signal; where the plurality of relay modules include a first relay module and a second relay module arranged along the transmission direction of the target signal; setting at least one bypass module for the relay circuit to obtain the signal transmission circuit; where the at least one bypass module includes a first bypass module, and the input end of the first bypass module is electrically connected to the first relay module and the second relay module respectively; the first bypass module is configured to provide a bypass path for the target signal passing through the first relay module when the frequency of the clock signal is the first frequency.
[0022] In one embodiment, before obtaining the relay circuit, the method further includes: obtaining a second frequency of the clock signal and a setup time corresponding to a preset signal transmission module; determining, according to the second frequency, a maximum transmission distance for each of the preset transmission modules to perform signal transmission on a preset type of line when the setup time is satisfied, to obtain a second distance; laying out the preset type of line and setting the preset transmission module as the relay module on the line to obtain the relay circuit, where, in the relay circuit, the length of the line between any two adjacent relay modules is less than or equal to the second distance.
[0023] In one embodiment, the first frequency is one Nth of the second frequency, where N is an integer greater than 1.
[0024] In one embodiment, the number of the first relay modules is at least two; setting at least one bypass module for the relay circuit includes: obtaining a first frequency of the clock signal; determining, according to the first frequency, a maximum transmission distance for each of the relay modules to perform signal transmission when the setup time of the relay module is satisfied, to obtain a first distance; setting the at least one bypass module for the relay circuit according to the distribution of the relay modules and the first distance, so that the length of the line between two adjacent first relay modules is greater than the second distance and less than or equal to the first distance.
[0025] In one embodiment, after setting at least one bypass module for the relay circuit, the method further includes: setting a control module for the at least one bypass module, where the control module is electrically connected to the at least one bypass module and is configured to send a control signal to the first bypass module when the clock signal is at the first frequency, so as to control the first bypass module to provide a bypass path for the target signal.
[0026] In a fourth aspect, an embodiment of the present invention further provides a generating device for a signal transmission circuit, including: a first obtaining unit, configured to obtain a relay circuit, where the relay circuit includes a plurality of relay modules; the plurality of relay modules are configured to sequentially transmit a target signal based on a clock signal; where the plurality of relay modules include a first relay module and a second relay module arranged along the transmission direction of the target signal; a first setting unit, configured to set at least one bypass module for the relay circuit to obtain the signal transmission circuit; where the at least one bypass module includes a first bypass module, and an input end of the first bypass module is electrically connected to the first relay module and the second relay module respectively; the first bypass module is configured to provide a bypass path for the target signal passing through the first relay module when the frequency of the clock signal is a first frequency.
[0027] In one embodiment, the device further includes: a second acquisition unit, configured to acquire a second frequency of the clock signal and a setup time corresponding to a preset signal transmission module; a determination unit, configured to determine, according to the second frequency, a maximum transmission distance for each of the preset transmission modules to perform signal transmission on a preset type of line when the setup time is satisfied, so as to obtain a second distance; a second setting unit, configured to lay out the preset type of line and set the preset transmission module as the relay module on the line, so as to obtain the relay circuit, where, in the relay circuit, the length of the line between any two adjacent relay modules is less than or equal to the second distance.
[0028] In one embodiment, the first frequency is one Nth of the second frequency, where N is an integer greater than 1.
[0029] In one embodiment, the number of the first relay modules is at least two; the first setting unit is specifically configured to: acquire a first frequency of the clock signal; determine, according to the first frequency, a maximum transmission distance for each of the relay modules to perform signal transmission when the setup time of the relay module is satisfied, so as to obtain a first distance; and set the at least one bypass module for the relay circuit according to the distribution of the relay modules and the first distance, so that the length of the line between two adjacent first relay modules is greater than the second distance and less than or equal to the first distance.
[0030] In one embodiment, the device further includes: a third setting unit, configured to, after setting the at least one bypass module for the relay circuit, set a control module for the at least one bypass module, where the control module is electrically connected to the at least one bypass module and is configured to send a control signal to the first bypass module to control the first bypass module to provide a bypass path for the target signal when the clock signal is at the first frequency.
[0031] In a fifth aspect, an embodiment of the present invention further provides an electronic device, where the electronic device includes: a processor and a memory, where the processor is electrically connected to the memory; the memory is used to store an executable program code; and the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to implement any one of the signal transmission circuit generation methods provided by the embodiments of the present invention.
[0032] In a sixth aspect, an embodiment of the present invention further provides a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement any of the signal transmission circuit generation methods provided by the embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0034] Figure 1 FIG. 9 is a schematic structural diagram of a signal transmission circuit provided by an embodiment of the present invention; Figure 2 FIG. 12 is another schematic structural diagram of a signal transmission circuit provided by an embodiment of the present invention; Figure 3 FIG. 15 is still another schematic structural diagram of a signal transmission circuit provided by an embodiment of the present invention; Figure 4 FIG. 18 is yet another schematic structural diagram of a signal transmission circuit provided by an embodiment of the present invention; Figure 5 FIG. 21 is yet another schematic structural diagram of a signal transmission circuit provided by an embodiment of the present invention; Figure 6 FIG. 24 is yet another schematic structural diagram of a signal transmission circuit provided by an embodiment of the present invention; Figure 7 FIG. 27 is yet another schematic structural diagram of a signal transmission circuit provided by an embodiment of the present invention; Figure 8 FIG. 30 is a schematic structural diagram of a control module in a signal transmission circuit provided by an embodiment of the present invention; Figure 9 FIG. 33 is a schematic structural diagram of a chip provided by an embodiment of the present invention; Figure 10 FIG. 36 is a flowchart of a method for generating a signal transmission circuit provided by an embodiment of the present invention; Figure 11 FIG. 39 is a schematic structural diagram of a relay circuit generated in an embodiment of the present invention; Figure 12 FIG. 42 is a schematic structural diagram of a signal transmission circuit generated in an embodiment of the present invention; Figure 13 FIG. 45 is a schematic structural diagram of a signal transmission circuit generation device provided by an embodiment of the present invention; Figure 14 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. Detailed implementation manners
[0035] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0036] It should be clear that the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.
[0037] As Figure 1 shown, an embodiment of the present invention provides a signal transmission circuit, and the signal transmission circuit may include: A plurality of relay modules 11, configured to sequentially transmit a target signal based on a clock signal, wherein the plurality of relay modules 11 include a first relay module 111 and a second relay module 112 arranged along the transmission direction of the target signal; At least one bypass module 12, the at least one bypass module 12 includes a first bypass module 121, and the input end of the first bypass module 121 is electrically connected to the first relay module 111 and the second relay module 112 respectively; the first bypass module 121 is configured to provide a bypass path for the target signal passing through the first relay module 111 when the frequency of the clock signal is a first frequency.
[0038] The signal transmission circuit provided by the embodiment of the present invention includes a plurality of relay modules 11 and at least one bypass module 12. The plurality of relay modules 11 are configured to sequentially transmit a target signal based on a clock signal. The plurality of relay modules 11 include a first relay module 111 and a second relay module 112 arranged along the transmission direction of the target signal; the at least one bypass module 12 includes a first bypass module 121, and the input end of the first bypass module 121 is electrically connected to the first relay module 111 and the second relay module 112 respectively; the first bypass module 121 is configured to provide a bypass path for the target signal passing through the first relay module 111 when the frequency of the clock signal is a first frequency. In this way, when the frequency of the clock signal is the first frequency, the bypass module 12 can provide a bypass path for the target signal passing through the first relay module 111, so that the target signal is transmitted through the bypass path without passing through the second relay module 112. Therefore, the target signal will use one less clock cycle during the transmission process, thereby effectively reducing signal delay.
[0039] In an embodiment of the present invention, the relay module 11 may be a sequential circuit module capable of relaying and transmitting a target signal based on a clock signal. Exemplarily, in one example, the relay module 11 may include registers and / or flip-flops, etc. The first relay module 111 and the second relay module 112 may be any two adjacent relay modules among the multiple relay modules 11. Among them, the first relay module 111 and the second relay module 112 are arranged along the transmission direction of the target signal. That is to say, the second relay module 112 is located in the downstream direction of the first relay module 111.
[0040] The bypass module 12 may be a circuit module capable of providing a bypass path for the target signal. Here, providing a bypass path means providing another path so that the original path is not used. In an embodiment of the present invention, the bypass module 12 may include a first bypass module 121. The input end of the first bypass module 121 may include a first input end and a second input end. The first input end may be electrically connected to the output end of the first relay module 111, and the second input end may be electrically connected to the output end of the second relay module 112, so as to provide a bypass path for the target signal passing through the first relay module 111. This bypass path may be used to bypass the second relay module 112, that is, to make the target signal not pass through the second relay module 112 for transmission.
[0041] Further, in addition to the first relay module 111 and the second relay module 112, as Figure 2 shown, in an embodiment of the present invention, the multiple relay modules 11 may further include a third relay module 113 arranged along the transmission direction of the target signal. The output end of the first bypass module 121 may be electrically connected to the third relay module 113. That is to say, after the first bypass module 121 provides a bypass path for the target signal, the target signal may bypass the second relay module 112 via the bypass path and continue to be transmitted by the third relay module 113.
[0042] As Figure 3As shown, in another embodiment of the present invention, the bypass module 12 may further include a second bypass module 122. The input end of the second bypass module 122 may be electrically connected to the output end of the first bypass module 121 and the output end of the third relay module 113 respectively. The second bypass module 122 may be configured to provide a bypass path for the target signal passing through the first bypass module 121 when the frequency of the clock signal is the first frequency. That is to say, in the embodiment of the present invention, in addition to being electrically connected to the third relay module 112, the output end of the first bypass module 121 may also be electrically connected to the second bypass module 122. In this way, after passing through the bypass path provided by the first bypass module 121, the target signal can continue to be transmitted through the bypass path provided by the second bypass module 122, thereby continuously bypassing two relay modules, namely the second relay module 112 and the third relay module 113. Therefore, the transmission time of two clock cycles can be saved.
[0043] In the embodiment of the present invention, the second bypass module 122 may have the same circuit structure as the first bypass module 121, but the specific circuit connection relationship is different. For example, in one example, both the first bypass module 121 and the second bypass module 122 may be multiplexers (MUX).
[0044] Based on this, as Figure 4 shown, in one implementation, the number of the second bypass modules 122 may be at least one, and the number of the third relay modules 113 may be equal to the number of the second bypass modules 122; the third relay modules 113 and the second bypass modules 122 are in one-to-one correspondence, and each second bypass module 122 and the corresponding third relay module 113 form a first combination 41. The first combinations 41 are connected in series to the output end of the first bypass module 121 in sequence along the transmission direction of the target signal. In this way, after the bypass path is provided by the first bypass module 121, the target signal can continue to have the bypass paths provided by the second bypass modules 122 in sequence, so as to bypass the corresponding third relay modules 113, saving more transmission time of clock cycles. Among them, for each bypass path provided by a second bypass module 122 that the target signal passes through, the transmission of the target signal can be reduced by one clock cycle.
[0045] In the foregoing embodiment, after passing through the first relay module 111, the target signal can continuously pass through the bypass path provided by the first bypass module 121 and the bypass paths provided by the second bypass modules 122 in each first combination 41. However, the embodiment of the present invention is not limited thereto. In other embodiments of the present invention, the bypass path may have other forms.
[0046] For example, as Figure 5As shown in the figure, in an embodiment of the present invention, the number of the first bypass modules 121 may be at least one, and the numbers of the first relay module 111 and the second relay module 112 are both equal to the number of the first bypass modules 121; the first bypass modules 121, the first relay modules 111, and the second relay modules 112 are in one-to-one correspondence, and each first bypass module 121 and the corresponding first relay module 111 and the corresponding second relay module 112 form a second combination 42, and the second combinations 42 are connected in series with each other along the transmission direction of the target signal. In this way, the target signal can pass through the bypass path after passing through a first relay module 111, and after passing through the bypass path, it can be transmitted through another first relay module 111, and so on.
[0047] Further, as Figure 6 shown, in an implementation manner, the plurality of relay modules 11 may further include a fourth relay module 114, and the fourth relay module 114 may be connected in series between any two adjacent second combinations 42. In this way, the target signal can be transmitted through the first relay module 111, the bypass path, the fourth relay module 114, and the next first relay module 111. In the embodiments of the present invention, between any two adjacent second combinations 42, the number of the fourth relay modules 114 is not limited and may be one or more.
[0048] Further, as Figure 7 shown, in an implementation manner of the present invention, in addition to the relay module 11 and the bypass module 12, the signal transmission circuit may further include a control module 13. The control module 13 may be electrically connected to the first bypass module 121 of the bypass module 12 and is configured to control each first bypass module 121 to provide a bypass path for the target signal when the frequency of the clock signal is at a first frequency.
[0049] In another implementation manner, the control module 13 may further be configured to control the target signal to sequentially pass through the first relay module 111, the second relay module 112, and the first bypass module 121 when the frequency of the clock signal is at a second frequency, where the second frequency is greater than the first frequency. That is to say, when the frequency of the clock signal is the second frequency, the first bypass module 121 does not provide a bypass path for the target signal passing through the first relay module 111, but enables the target signal passing through the first relay module 111 to continue to be transmitted through the second relay module 112.
[0050] In an embodiment of the present invention, the second frequency is greater than the first frequency. When the frequency of the clock signal is the first frequency, since the first frequency is relatively small, the period of the corresponding clock signal is relatively long. Therefore, within one period, after reserving the necessary setup time, there is a longer time available for the transmission of the target signal, enabling the target signal to be transmitted over a longer distance. Thus, even if the bypass path provided by the first bypass module 121 causes the target signal not to pass through the second relay module anymore, the setup time requirement can still be met.
[0051] When the frequency of the clock signal is the second frequency, since the second frequency is relatively large, the period of the corresponding clock signal is relatively short. Therefore, within one period, after reserving the necessary setup time, there is only a short time available for the transmission of the target signal. As a result, the target signal can only be transmitted over a short distance. The target signal passing through the first relay module 111 needs to be relayed in a timely manner by the second relay module 112 to meet the setup time requirement. Therefore, when the clock signal is at the second frequency, the first bypass module 121 does not need to provide a bypass path for the target signal passing through the first relay module 111. Instead, it makes full use of each relay module 11 to relay and transmit the target signal in a timely manner, thereby meeting the setup time requirement.
[0052] Specifically, in one implementation, as Figure 8 shown, the control module 13 may include: a determination sub-module 131 configured to determine whether the frequency of the clock signal is the first frequency; a transmission sub-module 132 electrically connected to the determination sub-module 131 and configured to send a first control signal to the first bypass module 121, so that the first bypass module 121 that receives the first control signal provides a bypass path for the target signal.
[0053] In an embodiment of the present invention, the clock signal of the signal transmission circuit may be fixed or variable. Regardless of which one it is, the determination sub-module 131 can compare the frequency of the clock signal with the first frequency to determine whether the clock frequency is the first frequency.
[0054] In an embodiment of the present invention, the first frequency may be a preset frequency value. The number of first frequencies may be one or multiple. The first frequency may be related to the second frequency of the clock signal. For example, in one example, the first frequency may be one Nth of the second frequency, where N is an integer greater than 1. For instance, in one example, if the second frequency is 120 MHz and N is 2, then the first frequency is 60 MHz; if N is 3, then the first frequency is 40 MHz.
[0055] In another embodiment, the sending sub-module 132 is further configured to send a second control signal to other bypass modules in at least one bypass module 12 except the bypass module for receiving the first control signal, so that the bypass module receiving the second control signal refuses to provide a bypass path for the target signal.
[0056] In an embodiment of the present invention, the first bypass module 121 may include a multiplexer MUX, the multiplexer MUX may include a control end, and the control module 13 may be configured to be electrically connected to the control ends of the respective multiplexers MUX.
[0057] Correspondingly, as Figure 9 shown, an embodiment of the present invention further provides a chip 1, and the chip 1 includes any one of the signal transmission circuits 2 provided in the foregoing embodiments. Therefore, the corresponding beneficial technical effects can also be achieved, which have been described in detail above and will not be elaborated here.
[0058] Correspondingly, an embodiment of the present invention further provides a method for generating a signal transmission circuit, which can effectively reduce the signal delay of the signal transmission circuit.
[0059] As Figure 10 shown, an embodiment of the present invention provides a method for generating a signal transmission circuit, and the method may include: S31, obtaining a relay circuit, where the relay circuit includes a plurality of relay modules; the plurality of relay modules are configured to sequentially transmit a target signal based on a clock signal; wherein, the plurality of relay modules include a first relay module and a second relay module arranged along the transmission direction of the target signal; S32, setting at least one bypass module for the relay circuit to obtain the signal transmission circuit; wherein, the at least one bypass module includes a first bypass module, and an input end of the first bypass module is electrically connected to the first relay module and the second relay module respectively; the first bypass module is configured to provide a bypass path for the target signal passing through the first relay module when the frequency of the clock signal is a first frequency.
[0060] The method for generating a signal transmission circuit provided by an embodiment of the present invention can obtain a relay circuit, where the relay circuit includes a plurality of relay modules; the plurality of relay modules are configured to sequentially transmit a target signal based on a clock signal; among them, the plurality of relay modules include a first relay module and a second relay module arranged along the transmission direction of the target signal; at least one bypass module is set for the relay circuit to obtain the signal transmission circuit; among them, the at least one bypass module includes a first bypass module, and the input end of the first bypass module is electrically connected to the first relay module and the second relay module respectively; the first bypass module is configured to provide a bypass path for the target signal passing through the first relay module when the frequency of the clock signal is a first frequency. In this way, when the frequency of the clock signal is the first frequency, the bypass module can provide a bypass path for the target signal passing through the first relay module, so that the target signal is transmitted through the bypass path instead of passing through the second relay module. Therefore, the target signal will use one less clock cycle during the transmission process, effectively reducing signal delay.
[0061] Optionally, in an embodiment of the present invention, the relay circuit obtained in step S31 can either be a relay circuit that has been designed by obtaining a design document or a newly designed relay circuit according to specific signal transmission requirements. The embodiments of the present invention do not limit this.
[0062] Specifically, in one implementation manner, before step S31 of obtaining the relay circuit, the method for generating a signal transmission circuit provided by an embodiment of the present invention may further include: obtaining a second frequency of the clock signal and a setup time corresponding to a preset signal transmission module; according to the second frequency, determining the farthest transmission distance for each preset transmission module to perform signal transmission on a preset type of line when the setup time is satisfied, to obtain a second distance; laying out the preset type of line and setting the preset transmission module as the relay module on the line to obtain the relay circuit, where the length of the line between any two adjacent relay modules 11 in the relay circuit is less than or equal to the second distance.
[0063] In this embodiment, first, the second frequency of the clock signal and the setup time corresponding to the preset signal transmission module can be obtained. The second frequency may be the highest frequency of the clock signal. For example, in one example, the frequency of the clock signal may vary between 500 MHz and 2 GHz, then the second frequency is 2 GHz. The preset signal transmission module may include any timing circuit with signal transmission capabilities, such as a register for a certain signal. Depending on the circuit structure and manufacturing process, different types of signal transmission modules may correspond to different setup times. In the embodiments of the present invention, the setup time corresponding to the preset signal transmission module can be obtained in advance. For example, in one example, the setup time corresponding to the preset signal transmission module may be 20 picoseconds.
[0064] After obtaining the second frequency and the setup time of the preset signal transmission module, the farthest transmission distance for each preset transmission module to transmit signals on a preset type of line can be determined according to the second frequency, to obtain a second distance. Specifically, since frequency is the reciprocal of the period, the clock period corresponding to the second frequency can be determined, for example, as the second period. Within one second period, the target signal needs to be transmitted from one relay module 11 to the input end of the next relay module 11 and reach a stable state at this input end in advance by a certain time (where the shortest advance time is the setup time). Therefore, within each clock period, the remaining time after deducting the setup time is the longest time that the signal can spend during transmission (without considering the transmission time of the target signal inside the relay module).
[0065] Here, the circuit of the preset type may include at least one transmission unit, and the transmission units may be connected in series with each other. Among them, each transmission unit may include a driving device and a metal wire with a fixed length electrically connected to the output end of the driving device. In one example, the driving device may include, for example, a buffer or an inverter. Since the process parameters of different types of circuits are different, the transmission speed of signals on different types of circuits is also correspondingly different. Therefore, within the same time, the distances traveled by signals on different types of circuits are also correspondingly different. Based on this, in this embodiment, it is possible to determine the maximum time available for the transmission of the target signal within each second period when the setup time is satisfied, so as to determine the farthest transmission distance of signal transmission by each of the preset transmission modules on the circuit of the preset type during this period, and obtain the second distance. Exemplarily, in one implementation manner, the period of the clock signal is T2, and the setup time of the preset transmission module is Tsetup, then the second distance is equal to the distance traveled by the target signal on the circuit of the preset type within the time of (T2 - Tsetup). In one example, the second distance can be specifically measured by the number of transmission units passed by the signal during transmission on the circuit. For example, the second distance may include 1 transmission unit or 2 transmission units, etc.
[0066] After obtaining the second distance, the circuit of the preset type can be laid out, and the preset transmission module can be set as the relay module on the circuit to obtain the relay circuit. Exemplarily, a schematic structural diagram of a relay circuit may be as Figure 11 shown. In the relay circuit, the length L1 of the circuit between any two adjacent relay modules is less than or equal to the second distance. That is to say, after laying out the circuit of the preset type and inserting the preset transmission module as the relay module, the length of the circuit between adjacent relay modules is less than or equal to the second distance, so that it can be ensured that the signal transmission circuit can transmit the target signal when the clock signal is at the second frequency while satisfying the setup time.
[0067] After obtaining the relay circuit, at least one bypass module can be set for the relay circuit in step S32 to obtain a signal transmission circuit. Specifically, in an embodiment of the present invention, setting at least one bypass module for the relay circuit may include: obtaining a first frequency of the clock signal; determining, according to the first frequency, a farthest transmission distance for each relay module to transmit a signal when the setup time of the relay module is satisfied, to obtain a first distance; and setting the bypass module for the relay circuit according to the distribution of each relay module and the first distance, so that the length L2 of the line between two adjacent first relay modules is greater than a second distance and less than or equal to the first distance. Exemplarily, a schematic structural diagram of the signal transmission circuit may be as shown in Figure 12 shown.
[0068] In this embodiment, first, a first frequency of the clock signal can be obtained. In an embodiment of the present invention, the first frequency may be a preset frequency value. The number of first frequencies may be one or multiple. In one implementation manner, the first frequency may be related to a second frequency of the clock signal. For example, in an example, the first frequency may be one Nth of the second frequency, where N is an integer greater than 1. For example, in an example, the second frequency is 120 MHz. If N is 2, the first frequency is 60 MHz. If N is 3, the first frequency is 40 MHz.
[0069] After obtaining the first frequency, the farthest transmission distance for each relay module to transmit a signal when the setup time of the relay module is satisfied can be determined according to the first frequency, to obtain a first distance. Specifically, since the frequency is the reciprocal of the period, the clock period corresponding to the first frequency, such as a first period, can be determined. Since the first frequency is one Nth of the second frequency and N is an integer greater than 1, the first frequency is less than the second frequency. Correspondingly, the first period is greater than the second period. In a first period, the target signal needs to be transmitted from one relay module to the input end of the next relay module and reach a stable state at the input end in advance for a certain time (where the shortest advance time is the setup time). Therefore, in each first period, the remaining time after deducting the setup time is the longest time that the signal can spend in transmission (without considering the transmission time of the target signal inside the relay module). Since the first period is greater than the second period, the remaining time after deducting the setup time in the first period is longer, and the time that the signal can spend in transmission is also longer, that is, the first distance is greater than the second distance. In one implementation manner, if the first period is T1 and the setup time of the preset transmission module is Tsetup, the first distance is equal to the distance that the target signal transmits on a preset type of line within the time of (T1 - Tsetup).
[0070] After obtaining the first distance, a bypass module can be set for the relay circuit according to the distribution of each of the relay modules and the first distance, so that the length of the line between two adjacent first relay modules is greater than the second distance and less than or equal to the first distance. That is to say, after setting the bypass module for the relay circuit, when the clock frequency is the first frequency, except for two adjacent first relay modules for transmitting the target signal, other relay modules between the adjacent first relay modules can be bypassed by the bypass path. Therefore, the transmission time of the target signal can be reduced by the corresponding number of clock cycles.
[0071] Further, in an embodiment of the present invention, after step S32 of setting the bypass module for the relay circuit, the method for generating a signal transmission circuit provided by the embodiment of the present invention may further include: setting a control module for the at least one bypass module, the control module being electrically connected to the first bypass module and configured to send a control signal to the first bypass module when the clock signal is the first frequency to control the first bypass module to provide a bypass path for the target signal.
[0072] In the embodiment of the present invention, the specific control method and principle of the control module for the bypass module have been described in detail in the foregoing signal transmission circuit and will not be elaborated here.
[0073] Correspondingly, as Figure 13 shown, the embodiment of the present invention further provides a device for generating a signal transmission circuit, and the device may include: A first acquisition unit 51, configured to acquire a relay circuit, where the relay circuit includes a plurality of relay modules; the plurality of relay modules are configured to sequentially transmit a target signal based on a clock signal; wherein, the plurality of relay modules include a first relay module and a second relay module arranged along the transmission direction of the target signal; A first setting unit 52, configured to set at least one bypass module for the relay circuit to obtain the signal transmission circuit; wherein, the at least one bypass module includes a first bypass module, and the input end of the first bypass module is electrically connected to the first relay module and the second relay module respectively; the first bypass module is configured to provide a bypass path for the target signal passing through the first relay module when the frequency of the clock signal is the first frequency.
[0074] The generating device of the signal transmission circuit provided by the embodiment of the present invention can obtain a relay circuit, where the relay circuit includes a plurality of relay modules; the plurality of relay modules are configured to sequentially transmit a target signal based on a clock signal; among them, the plurality of relay modules include a first relay module and a second relay module arranged along the transmission direction of the target signal; at least one bypass module is set for the relay circuit to obtain the signal transmission circuit; among them, the at least one bypass module includes a first bypass module, and the input end of the first bypass module is electrically connected to the first relay module and the second relay module respectively; the first bypass module is configured to provide a bypass path for the target signal passing through the first relay module when the frequency of the clock signal is a first frequency. In this way, when the frequency of the clock signal is the first frequency, the bypass module can provide a bypass path for the target signal passing through the first relay module, so that the target signal is transmitted through the bypass path without passing through the second relay module. Therefore, the target signal will use one less clock cycle during the transmission process, effectively reducing the signal delay.
[0075] In one implementation manner, the generating device of the signal transmission circuit provided by the embodiment of the present invention may further include: a second obtaining unit, configured to obtain a second frequency of the clock signal and a setup time corresponding to a preset signal transmission module; a determining unit, configured to determine, according to the second frequency, a farthest transmission distance for each of the preset transmission modules to perform signal transmission on a preset type of line when the setup time is satisfied, to obtain a second distance; a second setting unit, configured to lay out the preset type of line and set the preset transmission module as the relay module on the line to obtain the relay circuit, where the length of the line between any two adjacent relay modules in the relay circuit is less than or equal to the second distance.
[0076] In one implementation manner, the first frequency is one Nth of the second frequency, where N is an integer greater than 1.
[0077] In one implementation manner, the number of the first relay modules is at least two; the first setting unit is specifically configured to: obtain the first frequency of the clock signal; determine, according to the first frequency, a farthest transmission distance for each of the relay modules to perform signal transmission when the setup time of the relay module is satisfied, to obtain a first distance; according to the distribution of each of the relay modules and the first distance, set the at least one bypass module for the relay circuit, so that the length of the line between two adjacent first relay modules is greater than the second distance and less than or equal to the first distance.
[0078] In one embodiment, the generating device of the signal transmission circuit provided by the embodiment of the present invention may further include a third setting unit, configured to, after setting at least one bypass module for the relay circuit, set a control module for the at least one bypass module. The control module is electrically connected to the at least one bypass module and is configured to send a control signal to the first bypass module when the clock signal is at the first frequency, so as to control the first bypass module to provide a bypass path for the target signal.
[0079] Correspondingly, the embodiment of the present invention further provides an electronic device, such as Figure 14 As shown, the electronic device provided by the embodiment of the present invention may include: a processor 71 and a memory 72, and the processor 71 is electrically connected to the memory 72; the memory 72 is used to store executable program codes; the processor 71 runs a program corresponding to the executable program codes by reading the executable program codes stored in the memory 72, so as to implement any one of the signal transmission circuit generating methods provided by the foregoing embodiments.
[0080] For the specific execution process of the processor 71 for the above steps and the further steps executed by the processor 71 by running the executable program codes, reference may be made to the descriptions of the foregoing embodiments and will not be elaborated herein.
[0081] Correspondingly, the embodiment of the present invention further provides a computer-readable storage medium, which stores one or more programs, and the one or more programs can be executed by one or more processors to implement any one of the signal transmission circuit generating methods provided by the foregoing embodiments, and thus can also achieve corresponding technical effects. Details have been described in the foregoing and will not be elaborated herein.
[0082] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.
[0083] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.
[0084] In particular, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple. For the relevant parts, please refer to the partial description of the method embodiments.
[0085] For the convenience of description, the above device is described by dividing it into various units / modules according to functions. Of course, when implementing the present invention, the functions of each unit / module can be realized in the same or multiple software and / or hardware.
[0086] Those of ordinary skill in the art can understand that all or part of the processes in the above method embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the above method embodiments. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc.
[0087] As mentioned above, the above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims
1. A signal transmission circuit, characterized in that: include: A plurality of relay modules are configured to sequentially transmit a target signal based on a clock signal, wherein the plurality of relay modules include a first relay module and a second relay module arranged along a transmission direction of the target signal; At least one bypass module, the at least one bypass module includes a first bypass module, the input end of the first bypass module is electrically connected to the first relay module and the second relay module respectively; the first bypass module is configured to provide a bypass path for the target signal passing through the first relay module when the frequency of the clock signal is a first frequency.
2. The signal transmission circuit according to claim 1, characterized in that: The plurality of relay modules further include a third relay module arranged along a target signal transmission direction, and an output end of the first bypass module is electrically connected to the third relay module.
3. The signal transmission circuit according to claim 2, characterized in that: The at least one bypass module also includes a second bypass module, an input end of the second bypass module is electrically connected to the output end of the first bypass module and the output end of the third relay module, respectively, and the second bypass module is configured to provide a bypass path for the target signal passing through the first bypass module when the frequency of the clock signal is the first frequency.
4. The signal transmission circuit according to claim 3, characterized in that: The number of the second bypass modules is at least one, and the number of the third relay modules is equal to the number of the second bypass modules; The third relay modules correspond to the second bypass modules one by one, each of the second bypass modules forms a first combination with the corresponding third relay module, and each of the first combinations is serially connected to the output end of the first bypass module in sequence along the target signal transmission direction.
5. The signal transmission circuit according to claim 1, characterized in that: The input end of the first bypass module includes a first input end and a second input end, the first input end is electrically connected to the output end of the first relay module, and the second input end is electrically connected to the output end of the second relay module.
6. The signal transmission circuit according to any one of claims 1 to 5, characterized in that: The number of the first bypass modules is at least one, and the number of the first relay modules and the number of the second relay modules are both equal to the number of the first bypass modules; The first bypass module, the first relay module, and the second relay module correspond one to one, each of the first bypass modules forms a second combination with the corresponding first relay module and the corresponding second relay module, and each of the second combinations is connected in series with each other along the transmission direction of the target signal.
7. The signal transmission circuit according to claim 6, characterized in that: The plurality of relay modules further include a fourth relay module, and the fourth relay module is serially connected between any two adjacent second combinations.
8. The signal transmission circuit according to any one of claims 1 to 5, characterized in that: Also includes: The control module is electrically connected to the at least one bypass module and is configured to control each of the first bypass modules to provide a bypass path for the target signal when the frequency of the clock signal is at a first frequency.
9. The signal transmission circuit according to claim 8, characterized in that: The control module is also configured to control the target signal to pass through the first relay module, the second relay module and the first bypass module in sequence when the frequency of the clock signal is at a second frequency, wherein the second frequency is greater than the first frequency.
10. The signal transmission circuit according to claim 9, characterized in that: The first frequency is one Nth of the second frequency, where N is an integer greater than 1.
11. A chip, characterized in that: The chip includes the signal transmission circuit according to any one of claims 1 to 10.
12. A method for generating a signal transmission circuit, characterized in that: include: Acquire a relay circuit, the relay circuit comprising a plurality of relay modules; the plurality of relay modules are configured to sequentially transmit a target signal based on a clock signal; wherein the plurality of relay modules comprise a first relay module and a second relay module arranged along a transmission direction of the target signal; At least one bypass module is set for the relay circuit to obtain the signal transmission circuit; wherein the at least one bypass module includes a first bypass module, and the input end of the first bypass module is electrically connected to the first relay module and the second relay module respectively; the first bypass module is configured to provide a bypass path for the target signal passing through the first relay module when the frequency of the clock signal is a first frequency.
13. The method according to claim 12, characterized in that Before obtaining the relay circuit, the method further includes: Obtaining a second frequency of the clock signal and a setup time corresponding to a preset signal transmission module; determining, based on the second frequency, a maximum transmission distance for each preset transmission module to perform signal transmission on a preset type of line when the setup time is met, to obtain a second distance; The preset type of line is laid out, and the preset transmission module is set as the relay module on the line to obtain the relay circuit, in which the length of the line between any two adjacent relay modules is less than or equal to the second distance.
14. The method according to claim 13, characterized in that The first frequency is one-Nth of the second frequency, where N is an integer greater than 1.
15. The method according to claim 13, characterized in that The number of the first relay modules is at least two; The step of providing at least one bypass module for the relay circuit comprises: Acquire a first frequency of the clock signal; Determine, according to the first frequency, a maximum transmission distance for each of the relay modules to transmit a signal when the establishment time of the relay module is met, and obtain a first distance; According to the distribution of each of the relay modules and the first distance, the at least one bypass module is set for the relay circuit so that the length of the line between two adjacent first relay modules is greater than the second distance and less than or equal to the first distance.
16. The method according to claim 12, characterized in that After providing at least one bypass module for the relay circuit, the method further includes: A control module is set for the at least one bypass module. The control module is electrically connected to the at least one bypass module and is configured to send a control signal to the first bypass module when the clock signal is the first frequency, so as to control the first bypass module to provide a bypass path for the target signal.
17. An electronic device, characterized in that: The electronic device includes: a processor and a memory, the processor is electrically connected to the memory; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to implement the method for generating a signal transmission circuit as described in any one of claims 12 to 16.
18. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the method for generating a signal transmission circuit according to any one of claims 12 to 16.