Multi-level decoder with adaptive learning

Abstract

A data storage device includes an error correction code (ECC) system and a decoder gear determination system. If a decoder of the ECC system is unable to decode a codeword, the decoder gear determination system dynamically enhances the error correction capability of the decoder. The decoder gear determination system enhances the error correction capability of the decoder prior to initiation of a gear switch in which the codeword is decoded using another decoder having a higher error correction capability. The decoder gear determination system enhances the error correction capability of the decoder by deriving information about failed decoding attempts. The derived information is used to generate updated decoding parameters provided to the decoder. The decoder attempts to perform a subsequent decoding process on the codeword using the updated decoding parameters.

Description

BACKGROUND OF THE INVENTION

[0001] When data is written to a data storage device such as a NAND data storage device, the data is associated with additional redundant bits or error correction code (ECC) bits. The data and ECC bits are used to generate a codeword stored in the data storage device. During a read operation, the codeword is retrieved and analyzed to determine if the codeword contains any errors. If an error is detected, the decoder is used to correct the error.

[0002] Some data storage devices use several different decoders, and each decoder has different error correction capabilities, power consumption profiles, latencies, and speeds. For example, an ultra-low power (ULP) decoder is generally faster compared to a low power (LP) decoder and a full power (FP) decoder. However, the error correction capability of the ULP decoder is more limited when compared to the correction capabilities of the LP and FP decoders.

[0003] In an example where a data storage device uses different decoders, the ULP decoder is used first. If the ULP decoder is unable to correct an error in the codeword, then a "gear shift" is made and the LP decoder is used to correct the error. If the LP decoder is also unable to correct the error in the codeword, then another gear shift is made and the FP decoder is used.

[0004] Although each gear shift increases the probability that an error in the codeword will be corrected, the latency and power consumption requirements also increase. As a result, the throughput and quality of service (QoS) metrics of the data storage device may be negatively affected.

[0005] Therefore, it would be beneficial to improve the error correction capability of a decoder with higher throughput and lower power requirements when decoding a codeword before performing a gear shift. SUMMARY OF THE INVENTION

[0006] Examples of the present disclosure describe a data storage device, such as a NAND data storage device, that includes a decoder gear determination system. If a first type of decoder is unable to decode / correct a codeword, the decoder gear determination system dynamically increases or enhances the error correction capability of the first type of decoder (e.g., an ultra-low power (ULP) decoder). If the enhanced first type of decoder is unable to decode / correct the codeword, the decoder gear determination system initiates a gear shift and uses a second type of decoder (e.g., a decoder with better error correction capability but increased latency and / or power consumption requirements compared to the first type of decoder) to decode / correct the codeword.

[0007] To enhance the calibration ability of a first type of decoder, a decoder gear determination system determines or identifies first decoding parameters used by the first type of decoder during a first decoding process. If the first decoding process is unsuccessful, the decoder gear determination system derives information regarding the unsuccessful decoding attempt. The derived information and information regarding the first decoding parameters used during the first decoding process are used to dynamically generate and / or determine updated decoding parameters.

[0008] The decoder gear determination system provides the updated decoding parameters to the first type of decoder, and a second decoding process is initiated. If the second decoding process is unsuccessful, the decoder gear determination system determines that a second type of decoder should be used for a third decoding process and initiates a gear shift. The second type of decoder is used for the third decoding process, and this process is repeated.

[0009] Accordingly, an example of the present disclosure describes a method that includes initiating a first decoding process on a codeword using a first type of decoder. In the example, the first decoding process utilizes first decoding parameters. Information associated with the first decoding process is derived at least in part based on determining that the first decoding process is unsuccessful. A second decoding process using a decoder is initiated. In the example, the second decoding process utilizes updated parameters that are at least in part based on information derived from the first decoding process.

[0010] Other examples describe a data storage device that includes a controller, a first decoder of a first type, and a second decoder of a second type different from the first type. The data storage device also includes a decoder gear determination system communicatively coupled to the controller and the first and second decoders. The decoder gear determination system derives decoding information from a failed codeword decoding process performed by the first decoder. In the example, the derived decoding information includes information regarding the failed codeword decoding process. The decoder gear determination system also generates decoding parameters at least in part based on the derived decoding information and causes the first decoder to initiate a codeword decoding process using the decoding parameters.

[0011] In yet another example, the present disclosure describes a data storage device that includes a control component and a decoder gear selection component communicatively coupled to the control component. The decoder gear selection component can be used to initiate a first decoding process on a codeword using a decoding component. In the example, the first decoding process utilizes first decoding parameters. Information associated with the first decoding process is derived at least in part based on determining that the first decoding process is unsuccessful. Second decoding parameters are generated at least in part based on information derived from the first decoding process. A second decoding process on the codeword is initiated using the decoding component. In the example, the second decoding process utilizes the second decoding parameters.

[0012] This summary is provided to introduce a series of concepts in a simplified form, which are further described in the detailed description below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Non-limiting and non-exhaustive examples are described with reference to the following figures.

[0014] Figure 1 is a block diagram of a system according to an example that includes a host device and a data storage device.

[0015] Figure 2 is a flowchart according to a first example showing how the error correction capability of a decoder is updated using derived information.

[0016] Figure 3 is a flowchart according to a second example showing how the error correction capability of a decoder is updated using derived information.

[0017] Figure 4 is a flowchart according to a third example showing how the error correction capability of a decoder is updated using derived information.

[0018] Figure 5 is a flowchart according to a fourth example showing how the error correction capability of a decoder is updated using derived information.

[0019] Figure 6 shows a method for enhancing the error correction capability of a decoder of a data storage device according to an example.

[0020] Figure 7 is a perspective view of a storage device according to an example that includes a three-dimensional (3D) stacked non-volatile memory.

[0021] Figure 8 is a block diagram of a storage device according to an example. DETAILED DESCRIPTION

[0022] In the following detailed description, reference is made to the accompanying drawings, which form a part of the present disclosure and illustrate specific embodiments or examples. These aspects may be combined, other aspects may be utilized, and structural changes may be made without departing from the present disclosure. Accordingly, the following detailed description should not be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims and their equivalents.

[0023] Some data storage devices, such as NAND data storage devices, utilize several different decoders during an error correction code (ECC) process. Each decoder has different error correction capabilities, power consumption profiles, latency profiles, and speeds. For example, an ultra-low power (ULP) decoder is faster when compared to a low power (LP) decoder and a full power (FP) decoder. However, the error correction capability of the ULP decoder is limited when compared to the error correction capabilities of the LP decoder and the FP decoder.

[0024] During a codeword decoding process, the ULP decoder is typically used first. However, if the ULP decoder is unable to decode and / or correct an error in the codeword, then the data storage device implements a shift and uses the LP decoder in subsequent codeword decoding processes. However, if the LP decoder is also unable to correct the error in the codeword, then another shift is made and the FP decoder is used.

[0025] Although each shift increases the probability that an error in the codeword will be corrected, the latency and power consumption requirements of the decoder also increase. As a result, the throughput and quality of service (QoS) metrics of the data storage device may be negatively affected.

[0026] To address the above problems, the present disclosure describes a decoder gear determination system for a data storage device. The decoder gear determination system (also referred to as a decoder gear selection system) monitors one or more decoding processes performed by different types of decoders. For example, the decoder gear determination system monitors a first decoding process performed by a first type of decoder (e.g., a ULP decoder). If the first decoding process is unsuccessful or fails, then the decoder gear determination system enhances or boosts the error correction capability of the first decoder. In an example, the decoder gear determination system enhances / boosts the error correction capability of the first decoder before initiating or enabling a shift, in which a second type of decoder (e.g., a decoder with better error correction capability but increased latency and / or power consumption requirements when compared to the first type of decoder) is used to decode the codeword.

[0027] For example, the decoder gear determination system determines or identifies a first parameter (or a first set of parameters) used by the first type of decoder during the first decoding process. If the first decoding process is unsuccessful, then the decoder gear determination system derives information regarding the unsuccessful attempt. The derived information, along with information regarding the first parameter (or the first set of parameters) used during the first decoding process, is used to dynamically generate and / or determine a second / updated parameter.

[0028] The decoder gear determination system provides second / updated parameters to a first type of decoder, and a second decoding process is initiated. If the second decoding process is still unsuccessful or fails, then the decoder gear determination system determines that a second type of decoder should be used for a third decoding process. Accordingly, the decoder gear determination system initiates a gear shift. The second type of decoder is used for the third decoding process, and this process is repeated.

[0029] Using the above, the decoder gear determination system can dynamically determine or learn how to improve decoders with fewer changes, lower latency, and lower power before performing a gear shift. For example, collecting data on each decoding attempt associated with a first decoder and subsequently providing the data to the first decoder can enhance the error correction capabilities of the first decoder. Although multiple decoding attempts are used, in some examples, multiple decoding attempts at a lower gear will outperform a data storage system that shifts gears when a previous gear fails.

[0030] According to the above, many technical benefits can be achieved, including but not limited to increasing the QoS and throughput of a data storage device, reducing the power requirements of the data storage device during the decoding process, and increasing the reliability and lifespan of the data storage device.

[0031] These benefits and other examples will be shown and described in more detail with respect to Figures 1 - 8 shown and described in more detail.

[0032] Figure 1 is a block diagram of a system 100 that includes a host device 105 and a data storage device 110 according to an example. In the example, the host device 105 includes a processor 115 and a memory 120 (e.g., main memory). The memory 120 may include, be associated with, or otherwise include an operating system 125, a kernel 130, and / or an application 135.

[0033] The processor 115 may execute various instructions, such as instructions from the operating system 125 and / or the application 135. The processor 115 includes circuitry, such as a microcontroller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), hardwired logic, analog circuitry, and / or various combinations thereof. In the example, the processor 115 includes a system on a chip (SoC).

[0034] In an example, the memory 120 is used by the host device 105 to store data that the processor 115 uses or otherwise executes. The data stored in the memory 120 includes instructions provided by the data storage device 110 via the communication interface 140. The data stored in the memory 120 also includes data for executing instructions from the operating system 125 and / or one or more application programs 135. In an example, the memory 120 is a single memory. In another example, the memory 120 includes multiple memories, such as one or more non-volatile memories, one or more volatile memories, or a combination thereof.

[0035] In an example, the operating system 125 creates a virtual address space for the application programs 135 and / or other processes executed by the processor 115. The virtual address space is mapped to locations in the memory 120. The operating system 125 also includes a kernel 130 that is otherwise associated therewith. In an example, the kernel 130 includes instructions for managing various resources of the host device 105 (e.g., memory allocation), handling read and write requests, and performing other operations.

[0036] The communication interface 140 communicatively couples the host device 105 and the data storage device 110. The communication interface 140 can be a Serial Advanced Technology Attachment (SATA), a PCI Express (PCIe) bus, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), Ethernet, Fibre Channel, or Wi-Fi. Thus, the host device 105 and the data storage device 110 do not need to be physically co-located and can communicate via a network such as a local area network (LAN) or a wide area network (WAN) such as the Internet. Additionally, the host device 105 interfaces with the data storage device 110 using a logical interface specification, such as Non-Volatile Memory Express (NVMe) or Advanced Host Controller Interface (AHCI).

[0037] The data storage device 110 also includes a controller 150 and a memory device 155. In an example, the controller 150 is communicatively coupled to the memory device 155. The memory device 155 includes one or more memory dies (e.g., a first memory die 165 and a second memory die 170). Although memory dies are specifically mentioned, the memory device 155 can include any non-volatile memory device, storage device, storage element, or storage medium that includes NAND flash memory cells and / or NOR flash memory cells.

[0038] The memory cells may be in the form of solid-state (e.g., flash) memory cells and may be single-programmable, multi-programmable a few times, or multi-programmable many times. Additionally, the memory cells may be single-level cells (SLCs), multi-level cells (MLCs), three-level cells (TLCs), four-level cells (QLCs), five-level cells (PLCs), and / or use any other memory technology. The memory cells are arranged in a two-dimensional configuration or a three-dimensional configuration.

[0039] In some examples, the data storage device 110 is attached to or embedded within the host device 105. In another example, the data storage device 110 is implemented as an external or portable device that can be communicatively or selectively coupled to the host device 105. In yet another example, the data storage device 110 is a component (e.g., a solid-state drive (SSD)) of a network-accessible data storage system, a network-attached storage system, a cloud data storage system, etc.

[0040] As noted above, the memory device 155 of the data storage device 110 includes a first memory die 165 and a second memory die 170. Although two memory dies are shown, the memory device 155 may include any number of memory dies (e.g., one memory die, two memory dies, eight memory dies, or another number of memory dies).

[0041] The memory device 155 also includes support circuitry. In an example, the support circuitry includes read / write circuitry 160. The read / write circuitry 160 supports the operation of the memory dies of the memory device 155. Although the read / write circuitry 160 is depicted as a single component, the read / write circuitry 160 may be divided into separate components, such as a read circuitry and a write circuitry. The read / write circuitry 160 may be external to the memory dies of the memory device 155. In another example, one or more of the memory dies include corresponding read / write circuitry 160 that can be used to read data from the storage elements of a single memory die and / or write data into the storage elements of a single memory die, without being affected by other read and / or write operations on any of the other memory dies.

[0042] In an example, one or more of the first memory die 165 and the second memory die 170 include one or more memory blocks. In an example, each memory block includes one or more memory cells. A memory cell block is the smallest number of memory cells that can be physically erased together. In an example, to increase parallelism, each block may be operated or organized into larger blocks or superblocks. For example, one block from different memory cell planes may be logically connected together to form a superblock.

[0043] As previously described, data storage device 110 also includes at least one controller 150. Controller 150 is communicatively coupled to memory device 155 via a bus, interface, or other communication circuitry. In an example, the communication circuitry includes one or more channels enabling controller 150 to communicate with first memory die 165 and / or second memory die 170 of memory device 155. In another example, the communication circuitry includes multiple different channels enabling controller 150 to communicate with first memory die 165 independently and / or in parallel with second memory die 170 of memory device 155.

[0044] Controller 150 receives data and / or instructions from host device 105. Controller 150 may also send data to host device 105. For example, controller 150 may send data to host device 105 and / or receive data from host device 105 via communication interface 140.

[0045] Controller 150 may also send data and / or commands to memory device 155 and / or receive data from memory device 155. For example, controller 150 sends data and a corresponding write command to memory device 155 to cause memory device 155 to store the data at a specified address of memory device 155. In an example, the write command specifies a physical address of a portion of memory device 155.

[0046] Controller 150 also sends data and / or commands associated with one or more background scan operations, garbage collection operations, and / or wear leveling operations. Controller 150 may also send one or more read commands to memory device 155. In an example, the read command specifies a physical address of a portion of memory device 155 storing data.

[0047] Controller 150 also includes or is otherwise associated with an error correction code (ECC) system 185. ECC system 185 receives data and generates one or more ECC codewords based at least in part on the received data. For example, ECC system 185 includes at least one encoder that encodes the received data using one or more encoding techniques.

[0048] The ECC system 185 also includes at least one decoder 190 that decodes data read from the memory device 155. In an example, the ECC system 185 includes multiple decoders 190. Some of the decoders 190 belong to a first type and have a first amount of error correction capability, speed, power requirement, and / or latency distribution, while some of the decoders 190 belong to a second type and / or a third type and have a second / third amount of error correction capability, speed, power requirement, and / or latency distribution. For example, the ECC system 185 includes one or more ultra-low power (ULP) decoders, one or more low power (LP) decoders, and one or more full power (FP) decoders. For example, the ECC system 185 includes two or more decoders of the same type and / or two or more decoders of different types. In such examples, the decoder 190 can be part of a decoder pool.

[0049] In an example, the ULP decoder is a bit flip decoder, and the LP decoder and the FP decoder are belief propagation (BP) decoders. Thus, the ULP decoder is more power and cost effective (in a relative bit error rate (BER) range) compared to the LP decoder and the FP decoder. Additionally, the ULP decoder can be used with a higher parallelism or a higher clock frequency compared to the LP decoder and the FP decoder. Thus, the ULP decoder achieves a higher decoding throughput while maintaining the power consumption relatively constant compared to the LP decoder and the FP decoder. However, as previously described, the ULP decoder has limited error correction capability compared to the LP decoder and the FP decoder.

[0050] When decoding a codeword, the ECC system 185 will attempt to decode the codeword using the ULP decoder. If the decoding is not successful, then the ECC system 185 implements a gear shift and uses a higher gear decoder, such as the LP decoder, to decode the codeword. Similarly, if the LP decoder cannot decode the codeword, then the ECC system 185 implements a gear shift again and uses the FP decoder to decode the codeword.

[0051] However, before implementing the gear shift, the decoder gear determination system 180 associated with the ECC system 185 enhances the error correction capability of the decoder (e.g., the ULP decoder) that is first used to decode the codeword. In an example, using the lower gear (e.g., faster) decoder multiple times, especially the decoder whose error correction capability has been enhanced, before switching to a higher gear decoder can be superior to a similar system that automatically switches to a higher gear decoder when the decoding operation fails.

[0052] To enhance decoder 190, decoder gear determination system 180 monitors, selects, identifies, and / or tracks one or more decoding parameters for use by the decoder during the codeword decoding process / operation. Decoder gear determination system 180 also monitors the result of the decoding process. Using the one or more decoding parameters and / or the result of the decoding process, decoder gear generation system 180 derives updated decoding parameters, which are provided to the same decoder for a second decoding process in case the first decoding process fails.

[0053] For example, using the information obtained from the first decoding process, decoder gear generation system 180 generates updated decoding parameters and provides the updated decoding parameters to decoder 190. During the second decoding process, decoder 190 uses the updated decoding parameters to enhance or improve its error correction ability. This process continues N times until the codeword is decoded or until decoder gear determination system 180 determines that it is time to implement a gear shift and switch to a different type of decoder 190 (e.g., an LP decoder).

[0054] In an example, the one or more decoding parameters for use by decoder 190 include but are not limited to a decoding schedule, a bit flip threshold, a log-likelihood ratio (LLR), a way to mark artificial soft bits (ASB), a dynamic bit skipping method (DBS), and a number of decoding iterations.

[0055] In an example, the decoding schedule specifies variables or equations of a low-density parity-check (LDPC) code to be used and / or executed at a specific time. For example, each variable in the LDPC code equation can be selected at any time. In some examples, changing the order of selection / execution of variables or equations affects the result of the decoding operation.

[0056] To determine the bit flip threshold, decoder gear determination system 180 monitors a specific variable (or bit) and determines how many equations (e.g., LDPC equations) associated with this specific variable are satisfied. For example, if more than a threshold number of equations associated with the specific variable are satisfied, then decoder gear determination system 180 determines that the specific variable is correct. However, if the number drops below the bit flip threshold (e.g., decoder gear determination system 180 determines that the threshold number of equations associated with this specific variable are not satisfied), then decoder gear determination system 180 determines that the specific variable is incorrect.

[0057] In an example, each variable is associated with or correlated to the same number of equations or a different number of equations. Thus, each variable can have the same bit flip threshold or a different bit flip threshold. In an example, the bit flip threshold of a specific variable is at least partially based on the number of equations associated with or otherwise correlated to the specific variable.

[0058] In another example, the bit flip threshold for the specific variable is at least partially based on the number of decoding attempts that have occurred on the specific variable. For example, when the specific variable is decoded for the first time, a first bit flip threshold may be used. However, during one or more subsequent decoding attempts, the bit flip threshold may be decreased (or increased).

[0059] In an example, the LLR decoding parameter is a value assigned to a variable or bit that indicates the confidence level of the decoder gear determination system 180. The confidence level is a value that indicates whether the variable or bit is correct. For example, a high magnitude may indicate that the bit is correct, while a low magnitude may indicate that the bit is incorrect, where the sign will indicate whether the bit is a "0" or a "1". In an example, the value of the LLR decoding parameter may also be changed to change the characteristics of the decoder 190.

[0060] In another example, the way of marking ASB is a decoding parameter that indicates a variable or bit that is suspected of bit flipping (or alternatively assumed to be true / correct) by the decoder 190. In an example, the decoder 190 marks them as ASB due to the characteristics of these bits during the decoding process (for example, after a certain number of decoding iterations, the number of satisfied and unsatisfied equations for a particular bit is equal). In an example, ASB receives different processing by the decoder 190, which may be different from other bits with the same value but not yet marked.

[0061] The DBS decoding parameter is used to identify or mark variables or bits that will be skipped or otherwise not processed during one or more decoding operations / iterations. In an example, during some of the decoding iterations, bits are skipped at least partially based on the decoding state of the bit in order to speed up the decoding process. For example, if a bit is only associated with satisfied equations, then this bit will be skipped. Thus, the bit will not be processed within X iterations.

[0062] The number of decoding iterations is a decoding parameter that specifies the number of iterations of a specific decoding operation. The number of decoding operations can be any number.

[0063] If the decoding process using one or more of the decoding parameters fails, then the decoder gear determination system 180 analyzes the output of the decoding process to determine whether anything can be learned or derived from the failed decoding process. This information is then provided to the decoder 190 to enhance the error correction ability of the decoder 190. In an example, this process is initiated at least once before initiating a gear shift.

[0064] For example, the output of one or more decoding processes may indicate that a threshold amount of decoding iterations have been attempted to flip a particular bit or variable. Accordingly, the decoder staging determination system 180 determines that this particular bit is likely to be flipped. This information, along with the decoding parameters, is used to generate updated decoding parameters. The updated decoding parameters are then provided to the decoder 190 to enhance its error correction capabilities.

[0065] Additional information that can be derived from the decoding process includes, but is not limited to: an indication that one or more bits have flipped from an initial state during the decoding process of a failed codeword; an indication that one or more bits have flipped (and may have flipped back) at any time during the decoding process of a failed codeword; an indication that one or more bits have flipped more than a predetermined number of times (and may have flipped back) during the decoding process of a failed codeword; an indication that one or more bits are identified as ASB; an indication that one or more bits have an LLR value below an LLR value threshold; an indication that one or more bits have flipped during different stages (e.g., start or end) of the decoding process of a failed codeword; and an indication that one or more bits have flipped when the syndrome weight (SW) is above an SW threshold (e.g., SW is not equal to zero). In an example, the SW indicates the amount of equations that are not satisfied during LDPC code operation. Accordingly, a higher SW indicates a higher BER.

[0066] When this additional information is determined or identified, the decoder staging determination system 180 uses the information, along with the decoding parameters, to generate updated decoding parameters.

[0067] Additionally, the decoder staging determination system 180 may also change one or more decoding dynamics of subsequent decoding attempts performed by the decoder 190. In an example, the decoding dynamics are at least partially based on the additional information. For example, the decoder staging determination system 180 uses the additional / derived information to generate and / or mark one or more bits as ASB. In another example, the decoder staging determination system 180 uses the additional / derived information to change the decoding order of bits or variables (e.g., start the decoding process with variables having a high / low amount of marked bits). In yet another example, the decoder staging determination system 180 uses the additional / derived information to change the bit flip threshold for each clock to allow certain variables / bits to have more / less flips during different decoding processes / operations. In an example, the additional / derived information, including the decoding dynamics listed above, may also be combined with one or more of the previously discussed decoding parameters.

[0068] In an example, the decoder gear determination system 180 causes the decoder 190 to perform one or more decoding attempts using decoding parameters. In an example, each decoding attempt utilizes different decoding parameters. For example, the first decoding attempt uses first decoding parameters (or a first set of decoding parameters), and the second decoding attempt uses second decoding parameters (or a second set of decoding parameters). In an example, this continues until a predefined number (or threshold number) of decoding attempts have occurred.

[0069] After each failed decoding attempt, the decoder gear determination system 180 derives the additional information and generates one or more updated decoding parameters. The updated decoding parameters are then provided to the decoder 190 for subsequent decoding attempts.

[0070] This process continues until a threshold number of subsequent decoding attempts are reached, the codeword is successfully decoded, or until the decoder gear determination system 180 initiates a gear switch. When a gear switch is initiated, a second type of decoder is used to decode the codeword, and this process is repeated.

[0071] Figure 2 is a flowchart 200 showing how the error correction capability of a decoder is updated using the derived information according to a first example. In an example, the decoder is similar to the decoder 190 shown and described with respect to Figure 1 The decoder is also a first type of decoder and has a first amount of error correction capability. For example, the decoder is a ULP decoder. In another example, the decoder is an LP decoder.

[0072] In the example shown, the decoder can be used to perform several different decoding attempts using different decoding parameters. For example, the decoder performs a first decoding attempt 210 using first decoding parameters 205. If the ECC system (e.g., ECC system 185( Figure 1 )) and / or the decoder gear determination system 240 determines that the first decoding attempt 210 is unsuccessful or has failed, then additional information 235 associated with the first decoding attempt 210 is provided to the decoder gear determination system 240. In an example, the decoder gear determination system 240 is similar to the decoder gear determination system 180 shown and described with respect to Figure 1 shown and described.

[0073] Additionally, if the first decoding attempt 210 fails, then the decoder gear determination system 240 (or the ECC system) causes the decoder to perform a second decoding attempt 220. In an example, the second decoding attempt 220 uses second decoding parameters 215 that are different from the first decoding parameters 205. If the second decoding attempt 220 is unsuccessful, then additional information 235 associated with the second decoding attempt 220 is provided to the decoder gear determination system 240.

[0074] This process is repeated a predetermined number of times (e.g., N times) or until the codeword is successfully decoded. For example, if the second decoding attempt 220 is unsuccessful, the decoder performs the Nth decoding attempt 230 using the Nth decoding parameter 225. As with other attempts, in case the Nth decoding attempt 230 fails, additional information 235 associated with the Nth decoding attempt 230 is provided to the decoder stage determination system 240.

[0075] As previously discussed, the additional information 235 associated with each decoding attempt includes information about the decoding parameters used in each decoding attempt and / or information / data associated with the failed decoding attempt. For example, the decoding parameters include but are not limited to the decoding schedule, bit flip threshold, LLR associated with one or more bits or variables, the way to mark artificial soft bits ASB, DBS method, and / or the number of decoding iterations / attempts.

[0076] In an example, the additional information 235 associated with each decoding attempt includes but is not limited to: an indication that one or more bits have flipped from an initial state during the failed codeword decoding process; an indication that one or more bits have flipped (and possibly flipped back) at any time during the failed codeword decoding process; an indication that one or more bits have flipped more than a predetermined number of times (and possibly flipped back) during the failed codeword decoding process; an indication that one or more bits are identified as ASB; an indication that one or more bits have an LLR value below an LLR value threshold; an indication that one or more bits have flipped during different stages (e.g., start or end) of the failed codeword decoding process; and an indication that one or more bits have flipped when the SW is higher than the SW threshold.

[0077] When receiving the additional information 235 associated with one or more decoding attempts, the decoder stage determination system 240 uses the additional information 235 to generate one or more updated decoding parameters 245. In an example, the updated decoding parameters 245 are used to enhance the error correction ability of the decoder and to change the decoding dynamics of subsequent decoding attempts.

[0078] For example, the decoder stage determination system 240 uses the additional information 240 to generate and / or mark one or more bits as ASB. In another example, the decoder stage determination system 240 uses the additional information 235 to change the decoding order of bits or variables in the codeword. In yet another example, the decoder stage determination system 240 uses the additional information 235 to change the bit flip threshold for each clock so that certain variables / bits for subsequent decoding operations have more / fewer flips. The decoder stage determination system 240 may also use one or more of the N decoding parameters to generate the one or more updated decoding parameters 245.

[0079] In an example, after the decoder gear determination system 240 generates the one or more updated decoding parameters 245, the updated decoding parameters 245 are provided to the decoder for subsequent decoding attempts. In an example, a unique updated decoding parameter 245 is provided to the decoder for each subsequent decoding attempt. For example, a first updated decoding parameter is provided to the M decoding attempt 250. If the M decoding attempt 250 is not successful, then a second updated decoding parameter is provided to the M+1 decoding attempt 255. Similarly, if the M+1 decoding attempt 255 is not successful, then the Kth updated decoding parameter 245 is provided to the M+K decoding attempt 260.

[0080] In an example, if the M+Kth decoding attempt 260 is not successful, then the decoder gear determination system 240 initiates a gear shift and decodes the codeword using a second type of decoder. In this example, the second type of decoder has better error correction capabilities compared to the first type of decoder.

[0081] In Figure 2 the example shown, the decoding attempts are performed sequentially. For example, the time period during which one decoding attempt is in progress or being performed occurs before or after the time period during which another decoding attempt is in progress or being performed. However, these are some examples, and the decoding attempts can be performed in parallel.

[0082] Figure 3 is a flowchart 300 showing how the error correction capabilities of a decoder are updated using derived information according to a second example. As in Figure 2 the example shown, in this example, the decoder(s) is / are similar to the decoder 190 shown and described with respect to Figure 1 In addition, the decoder is a first type of decoder and has a first amount of error correction capabilities.

[0083] In an example, the decoder can be used to perform several different decoding attempts in parallel. In an example, "in parallel" means that the time period during which one decoding attempt is in progress completely overlaps with the time period during which another decoding attempt is in progress. In another example, "in parallel" means that the time period during which one decoding attempt is in progress at least partially overlaps with the time period during which another decoding attempt is in progress.

[0084] In an example, although the decoding attempts are performed in parallel, each decoding attempt uses different decoding parameters. For example, the first decoding attempt 310 is performed using the first decoding parameter 305, the second decoding attempt 320 is performed using a second decoding parameter 315 different from the first decoding parameter 305, and the Nth decoding attempt 330 is performed or carried out using the Nth decoding parameter 325.

[0085] If the ECC system (e.g., ECC system 185(Figure 1 )) and / or the decoder gear determination system 340 determines that at least one of the decoding attempts is successful, then the other decoding attempts will be aborted. However, if the ECC system and / or the decoder gear determination system 340 determines that all of the N decoding attempts have failed, then additional information 335 associated with each decoding attempt is provided to the decoder gear determination system 340. In an example, the decoder gear determination system 340 is similar to the decoder gear determination system 180 Figure 1 shown and described.

[0086] When the additional information 335 associated with the N decoding attempts is received, the decoder gear determination system 340 uses the additional information 335 to generate updated decoding parameters 345. In an example, the updated decoding parameters change the decoding dynamics of subsequent decoding attempts.

[0087] After the decoder gear determination system 340 generates one or more updated decoding parameters 345, the updated decoding parameters 345 are provided to the decoder for subsequent decoding attempts. In an example, the subsequent decoding attempts are performed in parallel, and each subsequent decoding attempt receives a unique updated decoding parameter 345. For example, the first updated decoding parameter is provided to the M decoding attempt 350, the second updated decoding parameter is provided to the M+1 decoding attempt 355, and the Kth updated decoding parameter is provided to the M+K decoding attempt 360.

[0088] If the ECC system and / or the decoder gear determination system 340 determines that at least one of the subsequent decoding attempts is successful, then the other subsequent decoding attempts are aborted. However, if none of the subsequent decoding attempts are successful, then the decoder gear determination system 340 initiates a gear shift and decodes the codeword using a second type of decoder. In an example, the second type of decoder has better error correction capabilities compared to the first type of decoder.

[0089] Figure 4 is a flowchart 400 showing how the error correction capabilities of a decoder are updated using the derived information according to a third example. In an example, the decoder is similar to the decoder 190 Figure 1 shown and described. Additionally, the decoder is a first type of decoder and has a first amount of error correction capabilities. For example, the decoder is a ULP decoder. In another example, the decoder is an LP decoder.

[0090] As Figure 2In the example shown, the decoder can be used to perform several different sequential decoding attempts using different decoding parameters. For example, the decoder performs a first decoding attempt 410 using a first decoding parameter 405. If the first decoding attempt 410 is unsuccessful, then additional information 435 associated with the first decoding attempt 410 is provided to the decoder gear determination system 440. In the example, the decoder gear determination system 440 is similar to the decoder gear determination system 180 shown and described with respect to Figure 1 the decoder gear determination system shown and described.

[0091] Additionally, the decoder gear determination system 440 causes the decoder to perform a second decoding attempt 420. In the example, the second decoding attempt 420 uses a second decoding parameter 415 that is different from the first decoding parameter 405. If the second decoding attempt 420 is unsuccessful, then additional information 435 associated with the second decoding attempt 420 is provided to the decoder gear determination system 440.

[0092] This process is repeated a predetermined number of times (e.g., N times) or until the codeword is successfully decoded. For example, if the second decoding attempt 420 is unsuccessful, then the decoder performs an Nth decoding attempt 430 using an Nth decoding parameter 425. As with other attempts, in the event that the Nth decoding attempt 430 fails, additional information 435 associated with the Nth decoding attempt 430 is provided to the decoder gear determination system 440.

[0093] The decoder gear determination system 440 uses the additional information 435 to generate an updated decoding parameter 445. In the example, the updated decoding parameter is a fusion of the additional information 435 provided for each decoding attempt. For example, the updated decoding parameter 445 includes additional information associated with the first decoding attempt 410, the second decoding attempt 420, and / or the Nth decoding attempt 430.

[0094] The updated decoding parameter 445 is provided to the decoder for subsequent decoding attempts. For example, the updated decoding parameter 445 is provided to an M+i decoding attempt 450. If the M+i decoding attempt 450 is unsuccessful, then information associated with the failed M+i decoding attempt (e.g., M+i decoding information 455) is provided to the decoder gear determination system 440. Then, the decoder gear determination system 440 can generate a new updated decoding parameter 445 and provide it to the decoder.

[0095] In the example, the fusion of the additional information 435 can occur after each decoding attempt fails. For example, if the first decoding attempt 410 fails, then the updated decoding parameter 445 includes only the additional information 435 associated with the first decoding attempt 410. If the second decoding attempt 420 fails, then the updated decoding parameter 445 includes the additional information associated with the first decoding attempt 410 and the second decoding attempt 420.

[0096] In another example, the updated decoding parameter 445 includes additional information 435 associated with all failed decoding attempts. However, if the M+i decoding attempt 450 fails, then the decoder gear determination system 440 uses the M+i decoding information 455 and one or more decoding parameters and / or one or more parameters such as those previously discussed for altering decoder dynamics to generate a new updated decoding parameter 445.

[0097] In an example, if the M+i decoding attempt 450 is not successful, then the decoder gear determination system 440 initiates a gear shift and decodes the codeword using a second type of decoder.

[0098] Figure 5 FIG. 500 is a flow chart showing how the error correction capabilities of a decoder are updated using derived information according to a fourth example. As in the examples Figure 3 shown and described, multiple decoders operate in parallel and have a first amount of error correction capabilities.

[0099] Although the decoders and decoding attempts are performed in parallel, each decoding attempt uses different decoding parameters. For example, the first decoding attempt 510 is performed using the first decoding parameter 505, the second decoding attempt 520 is performed using a second decoding parameter 515 different from the first decoding parameter 505, and the Nth decoding attempt 530 is performed or carried out using the Nth decoding parameter 525.

[0100] If the ECC system (e.g., ECC system 185( Figure 1 )) and / or the decoder gear determination system 540 determines that at least one of the decoding attempts is successful, then the other decoding attempts will be aborted. However, if the ECC system and / or the decoder gear determination system 540 determines that all of the N decoding attempts have failed, then additional information 535 associated with each decoding attempt is provided to the decoder gear determination system 540. In an example, the decoder gear determination system 540 is similar to the decoder gear determination system 180 Figure 1 shown and described.

[0101] When the additional information 535 associated with the N decoding attempts is received, the decoder gear determination system 540 uses the additional information 535 to generate an updated decoding parameter 545. In an example, the updated decoding parameter 545 is a fusion of the additional information 535 provided by each decoding attempt. For example, the updated decoding parameter 545 includes additional information associated with one or more of the first decoding attempt 510, the second decoding attempt 520, and / or the Nth decoding attempt 530.

[0102] The updated decoding parameter 545 is provided to the decoder for subsequent decoding attempts. For example, the updated decoding parameter 545 is provided to the decoder for the M+i decoding attempt 550. If the M+i decoding attempt 550 is unsuccessful, then information associated with the failed M+i decoding attempt (e.g., the M+i decoding information 555) is provided to the decoder gear determination system 540. Then, the decoder gear determination system 540 may generate a new updated decoding parameter 545 and provide it to the decoder.

[0103] In an example, this process is repeated a predetermined number of times. However, in an example, each updated decoding parameter generated using the M+i decoding information 555 has a lower confidence level. When the M+i decoding information 555 reaches a confidence level threshold, or if a subsequent M+i decoding attempt 550 is unsuccessful, the decoder gear determination system 540 initiates a gear shift and decodes the codeword using a second type of decoder.

[0104] Figure 6 A method 600 for enhancing the correction ability of a decoder of a data storage device according to an example is shown. In an example, the method 600 may be performed by the ECC system and / or the decoder gear determination system of the data storage device, such as with respect to Figure 1 the ECC system 185 and / or the decoder gear determination system 180 shown and described.

[0105] In an example, the method 600 begins with initiating a first decoding process (610). The first decoding process is initiated when a codeword is identified and provided to a first type of decoder. Additionally, the first decoding process is associated with a decoding parameter.

[0106] The decoder gear determination system and / or the ECC system of the data storage device determines (620) whether the codeword has been successfully decoded. If the decoder gear determination system and / or the ECC system determines that the codeword has been successfully decoded, then the decoding process ends (680). However, if the decoder gear determination system and / or the ECC system determines that the codeword has not been successfully decoded, then the decoder gear determination system and / or the ECC system determines (630) or derives information regarding the unsuccessful decoding process.

[0107] Next, one or more updated decoding parameters are generated (640) using the derived / determined information. In an example, the one or more updated decoding parameters include information regarding the unsuccessful decoding process and the decoding parameter.

[0108] The decoder gear determination system and / or the ECC system provides the one or more updated decoding parameters to the decoder to enhance the error correction capability of the decoder. Additionally, the decoder gear determination system and / or the ECC system determines to initiate (650) an enhanced decoding process using the one or more updated decoding parameters.

[0109] Next, the decoder gear determination system and / or the ECC system determines (660) whether the enhanced decoding process is successful. If it is determined (660) that the enhanced decoding process is successful, then the decoding process ends (680). However, if it is determined (660) that the enhanced decoding process is not successful, then the decoder gear determination system and / or the ECC system initiates a gear shift 670. In an example, when a gear shift is initiated, method 600 is repeated using a second type of decoder.

[0110] In an example, one or more operations in method 600 may be repeated before moving to other operations. For example, operation 610 and operation 620 may be repeated multiple times before operation 630 and / or 640 are executed. Similarly, operation 640, operation 650, and operation 660 may be repeated multiple times before operation 670 is executed.

[0111] Figures 7 - 8 Example storage devices that can be used with or otherwise implement the various features described herein are described. For example, regarding Figures 7 - 8 the storage devices shown and described may include various systems and components that are similar to those regarding Figure 1 shown and described. For example, regarding Figure 8 the controller 822 shown and described may be similar to Figure 1 controller 150. Similarly, memory die 808 may be similar to Figure 1 first memory die 165 and / or second memory die 170 of

[0112] Figure 7 is a perspective view of a storage device 700 that includes a three-dimensional (3D) stacked non-volatile memory according to an example. In this example, the storage device 700 includes a substrate 710. Memory cell blocks are included on or above the substrate 710. The blocks may include a first block (BLK0 720) and a second block (BLK1 730). Each block may be formed of memory cells (e.g., non-volatile memory elements). The substrate 710 may also include a peripheral region 740 that has support circuitry for the first and second blocks.

[0113] The substrate 710 may also carry circuits below the blocks, and one or more lower metal layers patterned in conductive paths to carry signals from the circuits. The blocks may be formed in the middle region 750 of the memory device 700. The memory device may also include an upper region 760. The upper region 760 may include one or more upper metal layers patterned in conductive paths to carry signals from the circuits. Each memory cell block may include a memory cell stacking region. In an example, alternating levels of stacking represent word lines. Although two blocks are depicted, additional blocks may be used, and the additional blocks may extend in the x-direction and / or the y-direction.

[0114] In the example, the length of the plane of the substrate 710 in the x direction represents the extension direction of the signal path for the word line or the control gate line (e.g., the word line or the drain terminal selection gate (SGD) line direction), and the width of the plane of the substrate 710 in the y direction represents the extension direction of the signal path for the bit line (e.g., the bit line direction). The z direction represents the height of the memory device 700.

[0115] Figure 8 is a functional block diagram of a storage device 800 according to an example. In the example, the storage device 800 is about Figure 7 A 3D stacked non-volatile memory device 700 is shown and described. Figure 8 The components depicted in the figure may be circuits. In an example, the storage device 800 includes one or more memory dies 805. Each memory die 805 includes a three-dimensional memory structure 810 (e.g., a 3D memory cell array) of memory cells, a control circuit system 815, and a read / write circuit 820. In another example, a two-dimensional memory cell array may be used. The memory structure 810 may be addressed by a first decoder 825 (e.g., a row decoder) via a word line and by a second decoder 830 (e.g., a column decoder) via a bit line. The read / write circuit 820 may also include a plurality of sense blocks 835, including SB1, SB2, ..., SBp (e.g., a sense circuit system), which allow memory cell pages to be read or programmed in parallel. The sense block 835 may include a bit line driver.

[0116] In an example, the controller 840 is included in the same memory device 800 as the one or more memory dies 805. In another example, the controller 840 is formed on a die bonded to the memory dies 805, in which case each memory die 805 may have its own controller 840. In yet another example, the controller die controls all of the memory dies 805.

[0117] Commands and data can be transferred between the host 845 and the controller 840 using the data bus 850. Commands and data can also be transferred between the controller 840 and one or more memory dies 805 via line 855. In one example, the memory die 805 includes a set of input and / or output (I / O) pins connected to line 855.

[0118] The memory structure 810 may also include one or more arrays of memory cells. The memory cells can be arranged in a three-dimensional array or a two-dimensional array. The memory structure 810 can include any type of non-volatile memory that is formed on one or more physical levels of an array of memory cells having an active region disposed above a silicon substrate. The memory structure 810 can be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

[0119] The control circuitry 815 cooperates with the read / write circuitry 820 to perform memory operations (e.g., erase, program, read, etc.) on the memory structure 810. The control circuitry 815 can include registers, ROM fuses, and other devices for storing default values such as base voltages and other parameters.

[0120] The control circuitry 815 may also include a state machine 860, an on-chip address decoder 865, and a power control module 870. The state machine 860 can provide chip-level control of various memory operations. The state machine 860 can be programmed by software. In another example, the state machine 860 does not use software but is implemented entirely in hardware (e.g., circuitry). The on-chip address decoder 865 can provide an address interface between the address used by the host 845 and / or the controller 840 and the hardware address used by the first decoder 825 and the second decoder 830.

[0121] The power control module 870 can control the power and voltage supplied to the word lines and bit lines during memory operations. The power control module 870 can include drivers for word line layers, select transistors (e.g., SGS and SGD transistors), and source lines in a 3D configuration. The power control module 870 can include one or more charge pumps for generating voltages.

[0122] The control circuitry 815, the state machine 860, the on-chip address decoder 865, the first decoder 825, the second decoder 830, the power control module 870, the sense block 835, the read / write circuitry 820, and / or the controller 840 can be considered as one or more control circuits and / or management circuits that perform some or all of the operations described herein.

[0123] In an example, the controller 840 is a circuit that can be on-chip or off-chip. Additionally, the controller 840 can include one or more processors 880, a ROM 885, a RAM 890, a memory interface 895, and a host interface 897, all of which can be interconnected. In an example, the one or more processors 880 are an example of control circuitry. Other examples can use state machines or other custom circuits designed to perform one or more functions. Devices such as the ROM 885 and the RAM 890 can contain code, such as a set of instructions. One or more of the processors 880 can be used to execute the set of instructions to provide some or all of the functions described herein.

[0124] Alternatively or additionally, one or more of the processors 880 can access code from a memory device in the memory structure 810, such as a reserved area of memory cells connected to one or more word lines. The memory interface 895, which communicates with the ROM 885, the RAM 890, and one or more of the processors 880, can be a circuit that provides an electrical interface between the controller 840 and the memory die 805. For example, the memory interface 895 can change the format or timing of signals, provide buffers, isolate from surges, latch I / O, and so on.

[0125] The one or more processors 880 can use the memory interface 895 to issue commands to the control circuitry 815 or any other component of the memory die 805. The host interface 897, which communicates with the ROM 885, the RAM 895, and the one or more processors 880, can be a circuit that provides an electrical interface between the controller 840 and the host 845. For example, the host interface 897 can change the format or timing of signals, provide buffers, isolate from surges, latch I / O, and so on. Commands and data from the host 845 are received by the controller 840 through the host interface 897. Data sent to the host 845 can be transmitted using the data bus 850.

[0126] The plurality of memory elements in the memory structure 810 can be configured such that they are connected in series or such that each element can be accessed individually. By way of non-limiting example, flash memory devices in a NAND configuration (e.g., NAND flash memory) typically contain memory elements connected in series. A NAND string is an example of a set of memory cells and select gate transistors connected in series.

[0127] The NAND flash memory array can also be configured such that the array includes multiple NAND strings. In an example, a NAND string includes multiple memory cells sharing a single bit line and is accessed as a group. Alternatively, the memory elements can be configured such that each memory element can be accessed individually (e.g., a NOR memory array). The NAND and NOR memory configurations are examples, and the memory cells can have other configurations.

[0128] Memory cells can be arranged in an ordered array (e.g., in multiple rows and / or columns) in a single memory device tier. However, the memory elements can be arranged in a non-regular or non-orthogonal configuration, or in a structure not considered an array.

[0129] In an example, a 3D memory structure can be vertically arranged as a stack of multiple 2D memory device tiers. As another non-limiting example, a 3D memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, e.g., along the y direction), where each column has multiple memory cells. The vertical columns can be arranged in a two-dimensional memory cell arrangement, where the memory cells are on multiple vertically stacked memory planes. Other configurations of memory elements in a three-dimensional form can also constitute a 3D memory array.

[0130] In another example, in a 3D NAND memory array, the memory elements can be coupled together to form vertical NAND strings traversing across multiple horizontal memory device tiers. Other 3D configurations can be envisioned, where some NAND strings contain memory elements in a single memory tier, while other strings contain memory elements across multiple memory tiers. The 3D memory array can also be designed in a NOR configuration and a ReRAM configuration.

[0131] One of ordinary skill in the art will recognize that the techniques described herein are not limited to a single specific memory structure, but cover many related memory structures within the spirit and scope of the present technology as described herein and as understood by one of ordinary skill in the art.

[0132] The term computer-readable medium as used herein can include computer storage media. Computer storage media can include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, or program modules. Computer storage media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical storage devices, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or can be used to store information and can be accessed by a computing device (e.g., host device 105( Figure 1Any other article of manufacture accessible. Any such computer storage medium can be part of a computing device. A computer storage medium does not include a carrier wave or other propagated or modulated data signal.

[0133] Additionally, examples described herein can be discussed in the general context of computer-executable instructions residing on some form of computer-readable storage medium, executable instructions such as program modules executed by one or more computers or other devices. By way of example and not limitation, computer-readable storage media can include non-transitory computer storage media and communication media. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types. The functionality of the program modules can be combined or distributed as desired in various examples.

[0134] Communication media can be implemented by computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and includes any information delivery media. The term "modulated data signal" can describe a signal that has one or more characteristics set or changed in such a manner as to encode information in the signal. By way of example and not limitation, communication media can include wired media such as a wired network or direct wired connection; and wireless media such as acoustic, radio frequency (RF), infrared (IR), and other wireless media.

[0135] Example embodiments of the present disclosure describe a method that includes: initiating a first decoding process on a codeword using a first type of decoder, the first decoding process utilizing first decoding parameters; deriving information associated with the first decoding process based at least in part on determining that the first decoding process is unsuccessful; and initiating a second decoding process using the decoder, the second decoding process utilizing updated parameters based at least in part on the information derived from the first decoding process. In an example, the method further includes initiating a third decoding process using a second decoder of a second type different from the first type based at least in part on determining that the second decoding process is unsuccessful. In an example, the first type of decoder has a first error correction capability and the second type of decoder has a second error correction capability. In an example, the method further includes initiating another decoding process on the codeword using the decoder, the another decoding process occurring before the second decoding process and utilizing another decoding parameter, wherein the first decoding process and the another decoding process are initiated sequentially. In an example, the decoder includes a pool of the first type of decoder, and the method further includes: initiating another decoding process on the codeword using the decoder, the another decoding process occurring before the second decoding process and utilizing another decoding parameter, wherein the first decoding process and the another decoding process are initiated in parallel and are performed by two separate decoders in the decoder pool. In an example, the information derived from the first decoding process further includes information derived from the another decoding process when it is determined that the another decoding process is unsuccessful. In an example, the method further includes: deriving information associated with the second decoding process based at least in part on determining that the second decoding process is unsuccessful; and initiating a third decoding process using the decoder, the third decoding process utilizing third decoding parameters based at least in part on the information derived from the second decoding process. In an example, the first decoding parameters are selected from a group of decoding parameters including one or more of the following: a decoding schedule; a bit flip threshold; a log-likelihood ratio (LLR); bits marked as suspected bit flips; bits marked as correct; bits marked as skipped; and the number of decoding iterations. In an example, the information derived from the first decoding process includes one or more of the following: an indication of one or more bits flipped from an initial state during the first decoding process; an indication of one or more bits flipped during the first decoding process; an indication of one or more bits flipped more than a predetermined number of times during the first decoding process; an indication of one or more bits marked as suspected bit flips; an indication of one or more bits identified as correct; an indication of one or more bits having an LLR value below or above an LLR value threshold; an indication of one or more bits flipped during different stages of the first decoding process; and an indication of one or more bits flipped when a syndrome weight (SW) is above or below an SW threshold.In the example, the information derived from the first decoding process includes one or more of the following: an indication that the flag bits are to be given different treatment; an indication that the decoding order is to be changed; and an indication that the toggle threshold per clock is to be changed.

[0136] Other examples describe a data storage device that includes: a controller; a first decoder of a first type and a second decoder of a second type different from the first type; and a decoder stage determination system communicatively coupled to the controller and the first and second decoders and operative to: derive decoding information from a failed codeword decoding process performed by the first decoder, the derived decoding information including information about the failed codeword decoding process; generate decoding parameters based at least in part on the derived decoding information; and cause the first decoder to initiate a codeword decoding process using the decoding parameters. In an example, the decoder stage determination system may further be operative to initiate another codeword decoding process using the second decoder based at least in part on determining that the codeword decoding process performed by the first decoder was unsuccessful. In an example, the decoder stage determination system may further be operative to: derive decoding information from a plurality of failed codeword decoding processes performed by the first decoder, where the plurality of failed codeword decoding processes are performed sequentially. In an example, the first decoder includes a decoder pool including two or more decoders of the first type, where the decoder stage determination system may further be operative to: derive decoding information from a plurality of failed codeword decoding processes performed by the two or more first decoders in the decoder pool, where the plurality of failed codeword decoding processes are performed simultaneously. In an example, the failed codeword decoding process is associated with at least one parameter selected from a group of parameters including one or more of the following: a decoding schedule; a bit flip threshold; a log likelihood ratio (LLR); bits marked as suspected bit flips; bits marked as correct; bits marked as skipped; and the number of decoding iterations. In an example, the decoding information derived from the failed codeword decoding process includes at least one of the following: an indication of one or more bits flipped from an initial state during the failed codeword decoding process; an indication of one or more bits flipped during the failed codeword decoding process; an indication of one or more bits flipped more than a predetermined number of times during the failed codeword decoding process; an indication of one or more bits marked as suspected bit flips; an indication of one or more bits identified as correct; an indication of one or more bits having an LLR value below or above an LLR value threshold; an indication of one or more bits flipped during different stages of the failed codeword decoding process; and an indication of one or more bits flipped when a syndrome weight (SW) is above or below an SW threshold. In an example, the decoding parameters include at least one of the following: an indication that marked bits are to be given different treatment; an indication that the decoding order is to be changed; and an indication that the bit flip threshold per clock is to be changed.

[0137] Yet other examples describe a data storage device that includes: a control component; and a decoder gear selection component communicatively coupled to the control component and operative to: initiate a first decoding process on a codeword using a decoding component, the first decoding process utilizing first decoding parameters; derive information associated with the first decoding process at least in part based on determining that the first decoding process is unsuccessful; generate second decoding parameters at least in part based on the information derived from the first decoding process; and initiate a second decoding process on the codeword using the decoding component, the second decoding process utilizing the second decoding parameters. In an example, the decoder gear selection component may further be operative to: initiate a third decoding process on the codeword using another decoding component at least in part based on determining that the second decoding process is unsuccessful. In an example, the decoder gear selection component may further be operative to: derive decoding information from a plurality of decoding processes performed by the decoding component, where the plurality of decoding processes are performed simultaneously.

[0138] The description and illustration of one or more aspects provided in this disclosure are not intended to limit or restrict the scope of the disclosure in any way. The aspects, examples, and details provided in this disclosure are considered sufficient to convey ownership and enable others to make and use the best mode of the claimed disclosure.

[0139] The claimed disclosure should not be construed as limited to any aspect, example, or detail provided in this disclosure. Various features (structures and methods), whether shown and described in combination or separately, are intended to be selectively rearranged, included, or omitted to produce embodiments having a particular set of features. After the description and illustration of this application have been provided, those skilled in the art may envision variations, modifications, and alternative aspects within the spirit of the broader aspects embodied in this application that do not depart from the broader scope of the claimed disclosure.

[0140] Aspects of the present disclosure have been described above with reference to schematic flowcharts and / or schematic block diagrams of methods, apparatuses, systems, and computer program products according to embodiments of the present disclosure. It should be understood that each block in the schematic flowcharts and / or schematic block diagrams, and combinations of blocks in the schematic flowcharts and / or schematic block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a computer or to another programmable data processing device to produce a machine such that the instructions executed via the processor or another programmable data processing device form means for implementing the functions and / or acts specified in one or more blocks of the schematic flowcharts and / or schematic block diagrams.

[0141] References to elements using terms such as "first", "second", etc. in this document generally do not limit the number or order of those elements. In fact, these terms can be used as a way to distinguish two or more elements or instances of elements. Thus, references to a first and second element do not mean that only two elements can be used, or that the first element comes before the second element. Additionally, unless otherwise stated, a group of elements can include one or more elements.

[0142] Terms of the form "at least one of A, B, or C" or "A, B, C, or any combination thereof" used in the specification or claims mean "A or B or C, or any combination of these elements". For example, this term can include A, or B, or C, or A and B, or A and C, or A and B and C, or 2A, or 2B, or 2C, or 2A and B, etc. As an additional example, "at least one of A, B, or C" is intended to cover A, B, C, A - B, A - C, B - C, and A - B - C, as well as multiples of the same members. Similarly, "at least one of A, B, and C" is intended to cover A, B, C, A - B, A - C, B - C, and A - B - C, as well as multiples of the same members.

[0143] Similarly, as used herein, a phrase referring to a list of items related to "and / or" refers to any combination of the items. As an example, "A and / or B" is intended to cover A alone, B alone, or A and B together. As another example, "A, B, and / or C" is intended to cover A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

Claims

1. A method comprising: Initiating a first decoding process on the codeword using a decoder of the first type, the first decoding process utilizing first decoding parameters; deriving information associated with the first decoding process based at least in part on determining that the first decoding process was unsuccessful; as well as A second decoding process is initiated using the decoder, the second decoding process utilizing updated parameters based at least in part on the information derived from the first decoding process.

2. The method according to claim 1, further comprising: Based at least in part on determining that the second decoding process was unsuccessful, a third decoding process is initiated using a second decoder of a second type different from the first type.

3. The method of claim 2, wherein the first type of decoder has a first error correction capability and the second type of decoder has a second error correction capability.

4. The method according to claim 1, further comprising: Another decoding process is initiated for the codeword using the decoder, the another decoding process being performed before the second decoding process and utilizing another decoding parameter, wherein the first decoding process and the another decoding process are initiated sequentially.

5. The method of claim 1, wherein the decoder comprises a pool of decoders of the first type, the method further comprising: Another decoding process is initiated for the codeword using the decoder, the another decoding process being performed before the second decoding process and utilizing another decoding parameter, wherein the first decoding process and the another decoding process are initiated in parallel and are performed by two separate decoders in the decoder pool.

6. The method of claim 5, wherein the information derived from the first decoding process further comprises information derived from the other decoding process when the other decoding process is determined to be unsuccessful.

7. The method according to claim 1, further comprising: deriving information associated with the second decoding process based at least in part on determining that the second decoding process was unsuccessful; as well as A third decoding process is initiated using the decoder, the third decoding process utilizing third decoding parameters based at least in part on the information derived from the second decoding process.

8. The method of claim 1, wherein the first decoding parameter is selected from a group of decoding parameters comprising one or more of: Decoding timetable; Bit flip threshold; Log-likelihood ratio (LLR); bits marked as suspected bit flips; The bits marked as correct; bits marked as skipped; and The number of decoding iterations.

9. The method of claim 1, wherein the information derived from the first decoding process comprises one or more of: an indication of one or more bits flipped from an initial state during said first decoding process; an indication of one or more bits that flipped during said first decoding process; an indication of one or more bits flipped more than a predetermined number of times during said first decoding process; an indication of one or more bits marked as suspected bit flips; an indication of the bit or bits identified as correct; an indication of one or more bits having a log likelihood ratio (LLR) value below or above a LLR value threshold; an indication of one or more bits that were flipped during different stages of said first decoding process; and An indication of one or more bits that are flipped when the syndrome weight (SW) is above or below the SW threshold.

10. The method of claim 1, wherein the information derived from the first decoding process comprises one or more of: The marker bits are given different treatment indications; an indication that the decoding order is to be changed; as well as An indication that the rollover threshold of each clock is about to change.

11. A data storage device, comprising: Controller; a first decoder of a first type and a second decoder of a second type different from the first type; as well as A decoder gear determination system is communicatively coupled to the controller and the first and second decoders and is capable of: deriving decoding information from a failed codeword decoding process performed by the first decoder, the derived decoding information comprising information about the failed codeword decoding process; generating decoding parameters based at least in part on the derived decoding information; as well as The first decoder is caused to initiate a codeword decoding process using the decoding parameters.

12. The data storage device of claim 11, wherein the decoder gear determination system is further operable to initiate another codeword decoding process using the second decoder based at least in part on determining that the codeword decoding process performed by the first decoder was unsuccessful.

13. The data storage device according to claim 11, wherein the decoder gear determination system can be further used to: Decoding information is derived from a plurality of failed codeword decoding processes performed by the first decoder, wherein the plurality of failed codeword decoding processes are performed sequentially.

14. The data storage device of claim 11, wherein the first decoder comprises a decoder pool including two or more decoders of the first type, wherein the decoder gear determination system is further operable to: Decoding information is derived from a plurality of failed codeword decoding processes performed by the two or more first decoders in the pool of decoders, wherein the plurality of failed codeword decoding processes are performed simultaneously.

15. The data storage device of claim 11, wherein the failed codeword decoding process is associated with at least one parameter selected from a group of parameters, the group of parameters comprising one or more of the following: Decoding timetable; Bit flip threshold; Log-likelihood ratio (LLR); bits marked as suspected bit flips; The bits marked as correct; bits marked as skipped; and The number of decoding iterations.

16. The data storage device of claim 11, wherein the decoding information derived from the failed codeword decoding process comprises at least one of: an indication of one or more bits flipped from an initial state during the failed codeword decoding process; an indication of one or more bits that flipped during the failed codeword decoding process; an indication of one or more bits flipped more than a predetermined number of times during the failed codeword decoding process; an indication of one or more bits marked as suspected bit flips; an indication of the bit or bits identified as correct; an indication of one or more bits having a log likelihood ratio (LLR) value below or above a LLR value threshold; an indication of one or more bits that flipped during different stages of the failed codeword decoding process; and An indication of one or more bits that are flipped when the syndrome weight (SW) is above or below the SW threshold.

17. The data storage device according to claim 11, wherein the decoding parameters include at least one of the following: Indications that the marker bits are given different treatments; an indication that the decoding order is to change; and An indication that the rollover threshold of each clock is about to change.

18. A data storage device comprising: Control components; as well as A decoder gear selection member, which is communicatively coupled to the control member and is capable of: Initiating a first decoding process on the codeword using a decoding component, the first decoding process utilizing first decoding parameters; deriving information associated with the first decoding process based at least in part on determining that the first decoding process was unsuccessful; generating second decoding parameters based at least in part on the information derived from the first decoding process; as well as A second decoding process is initiated on the codeword using the decoding means, the second decoding process utilizing the second decoding parameters.

19. The data storage device of claim 18, wherein the decoder gear selection component is further operable to initiate a third decoding process for the codeword using another decoding component based at least in part on determining that the second decoding process was unsuccessful.

20. The data storage device of claim 19, wherein the decoder gear selection component is further operable to: Decoding information is derived from a plurality of decoding processes performed by the decoding component, wherein the plurality of decoding processes are performed simultaneously.

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