Display panel and manufacturing method thereof, display device and mask

Abstract

The embodiment of the invention provides a display panel, and belongs to the technical field of display. A display backboard in the display panel is provided with a first area, a splicing area and a second area which are sequentially connected in the first direction, and the distribution density of light-emitting units in all the areas is the same. A first signal line in the display backboard is located in the splicing area, and a second signal line is located in the first area or the second area and controls the brightness of the first light-emitting unit and the second light-emitting unit respectively. The line widths of the first signal line and the second signal line are different, and / or the areas of the first electrodes of the first light-emitting unit and the second light-emitting unit are different, and the driving conditions of the first light-emitting unit and the second light-emitting unit are the same; or the first and second signal lines are spaced from each other and extend in the second direction, the signal lines are different in line width, the areas of the first electrodes of the first and second light-emitting units are different, and the voltages provided by the first and second signal lines are different. The brightness difference between the first light-emitting unit and the second light-emitting unit is within 15%. According to the embodiment of the invention, the problem of uneven display can be improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of display technologies, and in particular, to a display panel, a manufacturing method thereof, a display device, and a mask plate. Background Art

[0002] Display devices have a wide range of application scenarios in life, such as electronic devices like mobile phones and tablet computers. The display panel is an important component of the display device.

[0003] In related technologies, the display panel includes a stacked display backplane and a light-emitting functional layer. During the process of manufacturing the display panel, a mask plate is required to perform exposure and development on the display backplane. However, due to the small area of the mask plate and the great technical difficulty in developing a large-sized mask plate, the display backplane needs to be divided into a connected first region, a splicing region, and a second region, and the production of a large-sized display panel is achieved through a splicing method. For example, one mask plate is used to perform exposure on the first region and the splicing region, and another mask plate is used to perform exposure on the second region and the splicing region. That is to say, the splicing region has undergone two exposures.

[0004] Since the splicing region has undergone two exposures, in the same film layer, the patterns of some film layers in the splicing region are different from those of some film layers in the non-splicing regions (i.e., the first region and the second region), resulting in a large difference in the light-emitting brightness of multiple light-emitting units located in the splicing region and that of multiple light-emitting units located in the non-splicing regions, and causing the problem of uneven display of the display panel. Summary of the Invention

[0005] Embodiments of the present disclosure provide a display panel, a manufacturing method thereof, a display device, and a mask plate, which can improve the problem of uneven display of the display panel. The technical solutions are as follows:

[0006] In a first aspect, a display panel is provided. The display panel includes a stacked display backplane and a light-emitting functional layer. The display backplane has a first region, a splicing region, and a second region that are sequentially connected in a first direction. The light-emitting functional layer includes a plurality of light-emitting units distributed in an array, and each light-emitting unit includes a first electrode. Among them, the distribution density of the light-emitting units in the first region, the distribution density of the light-emitting units in the splicing region, and the distribution density of the light-emitting units in the second region are the same. The display backplane includes a first signal line and a second signal line on the same layer. The first signal line is located in the splicing region, and the second signal line is located in the first region or the second region. The first signal line is used to control the brightness of a first light-emitting unit, and the first light-emitting unit is one of the plurality of light-emitting units located in the splicing region. The second signal line is used to control the brightness of a second light-emitting unit, and the second light-emitting unit is one of the plurality of light-emitting units located in the first region or the second region. The line width of the first signal line is different from the line width of the second signal line, and / or the area of the first electrode of the first light-emitting unit is different from the area of the first electrode of the second light-emitting unit. The difference in the brightness between the first light-emitting unit and the second light-emitting unit under the same driving conditions is within 15%.

[0007] Optionally, the first signal line and the second signal line are connected and extend along the first direction, or the first signal line and the second signal line are spaced apart from each other and the extending direction is a second direction, and the second direction intersects the first direction. The line width of the first signal line is different from the line width of the second signal line, and the area of the first electrode located in the splicing region is the same as the area of the first electrode located in the first region or the second region.

[0008] In a second aspect, a display panel is further provided. The display panel includes a stacked display backplane and a light-emitting functional layer. The display backplane has a first region, a splicing region, and a second region that are sequentially connected in a first direction. The light-emitting functional layer includes a plurality of light-emitting units arranged in an array, and each light-emitting unit includes a first electrode. Among them, the distribution density of the light-emitting units in the first region, the distribution density of the light-emitting units in the splicing region, and the distribution density of the light-emitting units in the second region are the same. The display backplane includes a first signal line and a second signal line on the same layer. The first signal line is located in the splicing region, and the second signal line is located in the first region or the second region. The first signal line and the second signal line are spaced apart from each other and both extend in a second direction, and the second direction intersects with the first direction. The first signal line is used to control the brightness of a first light-emitting unit, where the first light-emitting unit is one of the plurality of light-emitting units located in the splicing region, and the second signal line is used to control the brightness of a second light-emitting unit, where the second light-emitting unit is one of the plurality of light-emitting units located in the first region or the second region. The line width of the first signal line is different from the line width of the second signal line, and the area of the first electrode of the first light-emitting unit is different from the area of the first electrode of the second light-emitting unit. The first signal line is configured to provide a first voltage to the first light-emitting unit, and the second signal line is configured to provide a second voltage to the second light-emitting unit. The magnitudes of the first voltage and the second voltage are different, so that the brightness difference between the first light-emitting unit and the second light-emitting unit is within 15%.

[0009] Optionally, the line width of the first signal line is smaller than the line width of the second signal line, and the area of the first electrode located in the splicing region is larger than the area of the first electrodes located in the first region and the second region, and the first voltage is smaller than the second voltage; or, the line width of the first signal line is larger than the line width of the second signal line, and the area of the first electrode located in the splicing region is smaller than the area of the first electrodes located in the first region and the second region, and the first voltage is larger than the second voltage.

[0010] Optionally, the display panel further includes a plurality of microlenses and a filling layer. The plurality of microlenses and the filling layer are sequentially located on the side of the light-emitting functional layer away from the display backplane. The refractive index of the plurality of microlenses is greater than the refractive index of the filling layer. The plurality of microlenses correspond to the plurality of light-emitting units one by one, and the orthographic projection of the plurality of microlenses on the display backplane at least partially coincides with the orthographic projection of the plurality of light-emitting units on the display backplane.

[0011] Optionally, the refractive index of the plurality of microlenses is 0.15 to 0.8 greater than the refractive index of the filling layer.

[0012] Optionally, the display backplane is a silicon-based driving backplane.

[0013] Optionally, the display backplane further includes a plurality of pixel driving circuits, and the plurality of pixel driving circuits are connected to the plurality of light-emitting units in a one-to-one correspondence; the plurality of pixel driving circuits include a first pixel driving circuit connected to the first light-emitting unit and a second pixel driving circuit connected to the second light-emitting unit, the first signal line is electrically connected to the first pixel driving circuit, and the second signal line is electrically connected to the second pixel driving circuit.

[0014] In a third aspect, a method for manufacturing a display panel is further provided, and the method includes: manufacturing a display backplane having a first region, a splicing region, and a second region connected in sequence in a first direction; manufacturing a light-emitting functional layer on one side of the display backplane, wherein the light-emitting functional layer includes a plurality of light-emitting units distributed in an array, and each of the light-emitting units includes a first electrode, and the distribution density of the light-emitting units in the first region, the distribution density of the light-emitting units in the splicing region, and the distribution density of the light-emitting units in the second region are the same; wherein the display backplane includes a first signal line and a second signal line on the same layer, the first signal line is located in the splicing region, the second signal line is located in the first region or the second region, the first signal line is used to control the brightness of a first light-emitting unit, the first light-emitting unit is one of the plurality of light-emitting units located in the splicing region, the second signal line is used to control the brightness of a second light-emitting unit, the second light-emitting unit is one of the plurality of light-emitting units located in the first region or the second region, the line width of the first signal line is different from the line width of the second signal line, and / or the area of the first electrode located in the splicing region is different from the area of the first electrode located in the first region and the second region; the difference in the brightness between the first light-emitting unit and the second light-emitting unit under the same driving conditions is within 15%.

[0015] Fourthly, a manufacturing method of a display panel is also provided. The method includes: manufacturing a display backplane, which has a first region, a splicing region, and a second region connected in sequence in a first direction; manufacturing a light-emitting functional layer on one side of the display backplane, wherein the light-emitting functional layer includes a plurality of light-emitting units distributed in an array, and each light-emitting unit includes a first electrode. The distribution density of the light-emitting units in the first region, the distribution density of the light-emitting units in the splicing region, and the distribution density of the light-emitting units in the second region are the same. Wherein, the display backplane includes a first signal line and a second signal line on the same layer. The first signal line is located in the splicing region, and the second signal line is located in the first region or the second region. The first signal line and the second signal line are spaced apart from each other and the extending direction of both is a second direction, and the second direction intersects with the first direction. The first signal line is used to control the brightness of a first light-emitting unit, and the first light-emitting unit is a light-emitting unit located in the splicing region among the plurality of light-emitting units. The second signal line is used to control the brightness of a second light-emitting unit, and the second light-emitting unit is a light-emitting unit located in the first region or the second region among the plurality of light-emitting units. The line width of the first signal line is different from the line width of the second signal line, and the area of the first electrode of the first light-emitting unit is different from the area of the first electrode of the second light-emitting unit. The first signal line is configured to provide the first voltage to the first light-emitting unit, and the second signal line is configured to provide the second voltage to the second light-emitting unit, so that the brightness difference between the first light-emitting unit and the second light-emitting unit is within 15%, and the magnitudes of the first voltage and the second voltage are different.

[0016] Optionally, the manufacturing of the display backplane includes: forming a first photoresist pattern using a first mask.

[0017] Among them, the first photomask includes a first part and a second part, and the first part and the second part are respectively used to form different parts of the first photoresist pattern in the first region and the splicing region; a second photoresist pattern is formed using a second photomask. Among them, the second photomask includes a third part and a fourth part, and the third part and the fourth part are respectively used to form different parts of the second photoresist pattern in the splicing region and the second region. At least a part of the parts of the second photoresist pattern and the first photoresist pattern in the splicing region overlap; based on the first photoresist pattern and the second photoresist pattern, a wiring layer is formed, and the wiring layer includes the first signal line and the second signal line; among them, the width of the pattern of the second part is equal to the width of the pattern of the third part, the width of the pattern of the second part is greater than the width of the pattern of the first part, the width of the pattern of the second part is greater than the width of the pattern of the fourth part, and the pattern is the region corresponding to the signal line.

[0018] Optionally, fabricating the light-emitting functional layer on one side of the display backplane includes: forming a third photoresist pattern using a third photomask. Among them, the third photomask includes a fifth part and a sixth part, and the fifth part and the sixth part are respectively used to form different parts of the third photoresist pattern in the first region and the splicing region; forming a fourth photoresist pattern using a fourth photomask. Among them, the fourth photomask includes a seventh part and an eighth part, and the seventh part and the eighth part are respectively used to form different parts of the fourth photoresist pattern in the splicing region and the second region; based on the third photoresist pattern and the fourth photoresist pattern, a plurality of first electrodes are formed; among them, the pattern of the sixth part and the pattern of the seventh part are congruent figures, the pattern of the fifth part and the pattern of the eighth part are congruent figures, the area of the pattern of the sixth part is smaller than the area of the pattern of the fifth part, and the pattern of the sixth part and the pattern of the fifth part are similar figures, and the pattern is the region corresponding to the first electrode.

[0019] In a fifth aspect, a display device is further provided. The display device includes a power supply circuit and any one of the foregoing display panels, and the power supply circuit supplies power to the display panel.

[0020] Optionally, the display device further includes a control circuit, which is configured to be electrically connected to any one of the display panels in the foregoing second aspect, and is configured to provide the first voltage to the first signal line and provide the second voltage to the second signal line.

[0021] In a sixth aspect, a photomask is further provided for fabricating a film layer of a display panel, where the display panel is any one of the foregoing display panels; the photomask includes a first part and a second part connected to each other, the first part is used to fabricate the film layer of the first region or the second region, and the second part is used to fabricate the film layer of the splicing region; the sizes of the patterns in the pattern regions of the first part and the second part are different.

[0022] The beneficial effects brought by the technical solutions provided in the present disclosure at least include: by changing the film layer pattern of the splicing region to reduce the difference between the film layer pattern in the splicing region and the film layer pattern in the first region (or the second region), thereby reducing the brightness difference between the splicing region and the first region (or the second region) of the display panel, so that the brightness difference between the first light-emitting unit and the second light-emitting unit is within 15% under the same driving conditions, improving display unevenness; or, by respectively providing different voltages to the first light-emitting unit and the second light-emitting unit through the first signal line and the second signal line, so that the brightness difference between the first light-emitting unit and the second light-emitting unit is within 15%, improving display unevenness. Description of the Drawings

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0024] Figure 1 It is a schematic diagram showing the relationship between the size of a display panel and the viewing angle provided by an embodiment of the present disclosure;

[0025] Figure 2 It is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present disclosure;

[0026] Figure 3 It is a schematic plan view of a display backplane provided by an embodiment of the present disclosure;

[0027] Figure 4 It is a schematic plan view of another display panel provided by an embodiment of the present disclosure;

[0028] Figure 5 It is a schematic plan view of another display panel provided by an embodiment of the present disclosure;

[0029] Figure 6 It is a schematic cross-sectional structure diagram of a silicon-based driving backplane provided by an embodiment of the present disclosure;

[0030] Figure 7 It is a schematic flow chart of a method for manufacturing a display panel provided by an embodiment of the present disclosure;

[0031] Figure 8 It is a schematic structural diagram of a first mask and a second mask for fabricating a plurality of signal lines on the same layer provided by an embodiment of the present disclosure;

[0032] Figure 9 It is a schematic structural diagram of a third mask and a fourth mask for fabricating a first electrode layer provided by an embodiment of the present disclosure.

[0033] Legend:

[0034] x, first direction y, second direction A, first region B, splicing region C, second region D, display region E, non-display region

[0035] 10. Display backplane 11a. First signal line 11b. Second signal line 12. Planarization layer 12a. Via 101. Substrate 102. Source-drain layer 1021. Source 1022. Drain 103. Gate insulating layer 104. Gate layer 1040. Gate 105. First insulating layer 106. First wiring layer 107. Second insulating layer 108. Second wiring layer 109. Isolation groove 110. Protective layer 111. Sidewall structure 112. Metal protective layer

[0036] 20. Light-emitting functional layer 21. First electrode 22. Light-emitting layer 23. Second electrode

[0037] 30. Color filter layer 31. First color resist block 32. Second color resist block 33. Third color resist block

[0038] 40. Microlens 41. Filling layer

[0039] 51. Encapsulation layer 52. Pixel definition layer 53. Protective layer

[0040] 601. Striped structure 602. Block structure

[0041] 61. First mask 61a. First part 61b. Second part

[0042] 62. Second mask 62a. Third part 62b. Fourth part

[0043] 63. Third mask 63a. Fifth part 63b. Sixth part

[0044] 64. Fourth mask 64a. Seventh part 64b. Eighth part Detailed implementation manners

[0045] To make the objectives, technical solutions, and advantages of the present disclosure clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

[0046] The terms used in the embodiments section of the present disclosure are only for explaining the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the ordinary meanings understood by those of ordinary skill in the relevant art to which the present disclosure belongs. The terms "first", "second", "third" and similar words used in the specification and claims of the present patent application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "a" or "an" do not indicate a quantity limitation, but indicate the presence of at least one. Words such as "include" or "comprise" mean that the elements or items appearing before "include" or "comprise" cover the elements or items listed after "include" or "comprise" and their equivalents, and do not exclude other elements or items. The orientation terms mentioned in the present disclosure, such as "top", "bottom", "upper", "lower", "left" or "right", etc., are only with reference to the directions of the accompanying drawings. Therefore, the orientation terms used are for better and clearer explanation and understanding of the embodiments of the present disclosure, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and thus cannot be construed as a limitation on the embodiments of the present disclosure.

[0047] Figure 1 is a schematic diagram showing the relationship between the size of a display panel and the field of view provided by an embodiment of the present disclosure. As Figure 1 shown, the size (length or width) of the display panel is c, the distance between the display panel and the eyeball is b, and the field of view (Field of View, FOV) is ω. From Figure 1 it can be obtained that the relationship satisfied among b, c, and ω is: c = 2 * b * tan(ω / 2), and from this, ω = 2 * tan -1 [c / (2b)]. The larger ω is, that is, the larger the FOV is, the greater the immersion feeling the user can obtain. On the premise that the distance b between the display panel and the eyeball remains unchanged, in order to make the FOV larger, the size c of the display panel needs to be as large as possible. However, currently, the mask used for manufacturing the display panel is small, and its effective exposure area is small. If this mask is used for single-exposure to manufacture a certain layer structure in the display panel, the size of the manufactured display panel is small and cannot meet the market demand.

[0048] For example, when manufacturing a silicon-based OLED (Organic Light Emitting Diode) display panel for VR (Virtual Reality) display devices, the effective exposure size of the photomask is generally about 26mm * 33mm. Even if peripheral driving is not considered (i.e., only considering the display area of the display panel and not the peripheral area), the maximum display size supported by this photomask is only about 1.65 inches, which cannot meet the market demand for display sizes greater than 1.7 inches.

[0049] One way to solve this problem is to develop a larger-sized photomask. However, this approach will increase production costs, and the technical difficulty of developing a photomask with a large effective exposure area is relatively high, and it cannot be broken through in a short time. Another way to solve this problem is to divide a larger display panel into a connected first region, a splicing region, and a second region. Use one photomask to expose the first region and the splicing region, and use another photomask to expose the second region and the splicing region. That is, the splicing region has been exposed twice, thus realizing the production of a large-sized display panel. However, since the splicing region has been exposed twice, in the same film layer, the patterns of some film layers in the splicing region are different from those of some film layers in the non-splicing regions (i.e., the first region and the second region). Therefore, there will be a relatively large brightness difference (e.g., the brightness difference is about 15% - 30%) between the splicing region of the display panel and the first region and the second region, resulting in uneven display.

[0050] The following will detail the situation where the splicing region is exposed twice, resulting in different patterns in the splicing region and the non-splicing region in the same film layer.

[0051] When using one photomask to fabricate the film layer patterns in the first region A and the splicing region B, and the graphic sizes corresponding to the first region A in this photomask are the same as those corresponding to the splicing region B; use another photomask to fabricate the film layer patterns in the splicing region B and the second region C, and the graphic sizes corresponding to the splicing region B in this photomask are the same as those corresponding to the second region C. Due to the splicing region B being exposed multiple times, affected by factors such as the alignment accuracy of repeated exposure and the diffraction phenomenon during exposure, the size differences of the film layers in the splicing region B and the first region A and the second region B in the manufactured display panel are relatively large.

[0052] Since the width of the splicing region B is relatively small compared to the width size of the display panel, for example, the width of the splicing region B is about 20μm - 50μm, and the width size of the display panel is about 10cm - 20cm; if there is a relatively large difference in the emission brightness of multiple light-emitting units in the splicing region B and multiple light-emitting units in the first region A and the second region C, there will be obvious splicing lines (bright lines or dark lines) in the splicing region.

[0053] To this end, embodiments of the present disclosure provide a display panel. By changing the film layer pattern in the splicing area, the difference between the film layer pattern in the splicing area and that in the first area (or the second area) is reduced, so as to reduce the brightness difference between the splicing area of the display panel and the first area (or the second area), making the difference within 15%, and improving display unevenness. The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0054] Figure 2 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present disclosure. As Figure 2 shown, the display panel includes a stacked display backplane 10 and a light-emitting functional layer 20.

[0055] Figure 3 is a schematic plan view of a display backplane provided by an embodiment of the present disclosure, and Figure 2 includes Figure 3 a schematic cross-sectional structure along the FF cross-section line in. As Figure 3 shown, the display backplane has a first area A, a splicing area B, and a second area C that are sequentially connected in the first direction x. The light-emitting functional layer 20 includes a plurality of light-emitting units distributed in an array, and each light-emitting unit includes a first electrode 21. Among them, the distribution density of the light-emitting units in the first area A, the distribution density of the light-emitting units in the splicing area B, and the distribution density of the light-emitting units in the second area C are the same. Here, the distribution density refers to the number of light-emitting units per unit area. The area of the first electrode 21 located in the splicing area B is the same as the area of the first electrode 21 located in the first area A and the second area B.

[0056] The display backplane 10 includes a first signal line 11a and a second signal line 11b on the same layer. The first signal line is located in the splicing area B, and the second signal line 11b is located in the first area A or the second area B. The first signal line 11a is used to control the brightness of the first light-emitting unit, where the first light-emitting unit is one of the plurality of light-emitting units located in the splicing area B, and the second signal line 11b is used to control the brightness of the second light-emitting unit, where the second light-emitting unit is one of the plurality of light-emitting units located in the first area A or the second area B. The line width of the first signal line 11a is different from the line width of the second signal line 11b. The area of the first electrode 21 located in the splicing area B is the same as the area of the first electrode 21 located in the first area A or the second area C. The difference in brightness between the first light-emitting unit and the second light-emitting unit under the same driving conditions is within 15%.

[0057] Optionally, the difference in the emission brightness between the multiple light-emitting units located in the splicing area B and the multiple light-emitting units located in the first area A and the second area C is within 5%. Optionally, the difference in the emission brightness between the multiple light-emitting units located in the splicing area B and the multiple light-emitting units located in the first area A and the second area C is within 3%.

[0058] In the embodiments of the present disclosure, the same layer means being formed by the same lithography process, or being in contact with the same surface of the same film layer, or being located on the same side of the same film layer, etc. Different layers mean being formed by different lithography processes, or being in contact with the surfaces of different film layers respectively, or being located on different sides of the same film layer, etc.

[0059] Optionally, as Figure 3 shown, the first signal line 11a and the second signal line 11b are connected and extend in the first direction x.

[0060] Optionally, as Figure 2 shown, each light-emitting unit further includes a light-emitting layer 22 and a second electrode 23, and the light-emitting layer 22 and the second electrode 23 are stacked in sequence on the side of the first electrode 21 away from the display backplane 10.

[0061] Optionally, the first electrode 21 is an anode layer and the second electrode 23 is a cathode layer.

[0062] Optionally, as Figure 2 shown, the light-emitting layer 22 is a whole-layer structure. Optionally, the light emitted by the light-emitting layer 22 is white light.

[0063] Optionally, as Figure 2 shown, the light-emitting functional layer 20 further includes a pixel definition layer 52, the pixel definition layer is located between the first electrode 21 and the light-emitting layer 22, and the pixel definition layer 52 is used to separate multiple first electrodes 21.

[0064] Exemplarily, Figure 2 in, the shape of the first electrode 21 is square. Optionally, the shape of the orthographic projection of the first electrode 21 on the first surface D can also be hexagon, triangle, circle, etc. The shape of the orthographic projection of the light-emitting unit 20 on the first surface D can be the shape of the first electrode 21 or the opening shape of the pixel definition layer 52 where the light-emitting unit 20 is located.

[0065] Optionally, as Figure 2 shown, the display panel further includes a packaging layer 51, the packaging layer 51 is located on the side of the light-emitting functional layer 20 away from the display backplane 10, and is used to protect the light-emitting functional layer 20 and the film layers located under the light-emitting functional layer 20.

[0066] Optionally, as Figure 2As shown, the display panel further includes a color filter layer 30, and the color filter layer 30 is located on the side of the encapsulation layer 40 away from the display backplane 10. The color filter layer 30 includes a plurality of color resist blocks distributed in an array and a black matrix located between any two adjacent color resist blocks, and the plurality of color resist blocks correspond to the plurality of light-emitting units one by one.

[0067] Optionally, the plurality of color resist blocks 30 include a first color resist block 31, a second color resist block 32, and a third color resist block 33. The colors corresponding to the first color resist block 31, the second color resist block 32, and the third color resist block 33 are red, green, and blue respectively, so as to convert the white light emitted by the light-emitting layer 22 into red light, green light, and blue light, realizing color display.

[0068] Optionally, the display panel may also not include the color filter layer 30. The light-emitting layer 22 includes a plurality of light-emitting blocks distributed in an array, and the colors emitted by the plurality of light-emitting blocks are different, such as red, green, and blue. In this case, the pixel definition layer 52 is also used to separate the plurality of light-emitting blocks.

[0069] Optionally, as Figure 2 shown, the display backplane further includes a planarization layer 12, and the planarization layer 12 is located between the first signal line 11a and the first electrode 21, and is used to fill the unevenness caused by structures such as the first signal line 11a, facilitating the fabrication of structures such as the first electrode 21 located above the first signal line 11a.

[0070] In the embodiment of the present disclosure, the wiring layer where the first signal line 11a is located is the wiring layer in the display backplane closest to the first electrode layer where the first electrode 21 is located, that is, there is no other conductive layer between the wiring layer where the first signal line 11a is located and the first electrode layer where the first electrode 21 is located.

[0071] Optionally, as Figure 2 shown, the orthographic projection of the first signal line 11a on the display backplane 10 at least partially coincides with the orthographic projection of the first electrode 21 of the first light-emitting unit on the display backplane 10. The orthographic projection of the second signal line 11b on the display backplane 10 at least partially coincides with the orthographic projection of the first electrode 21 of the second light-emitting unit on the display backplane 10. The planarization layer 12 has a plurality of vias 12a to facilitate the electrical connection between the first signal line 11a and the first electrode 21 through the vias 12a.

[0072] In the related art, different widths of the signal lines (the first signal line 11a and the second signal line 11b) will result in different areas of the first electrode 21 located in the splicing area B and the first electrode 21 located in the first area A and the second area C. The following will elaborate on this.

[0073] Assume that the width of the signal line located in the splicing area B is smaller than the width of the signal lines located in the first area A and the second area C, and the distance between two adjacent signal lines located in the splicing area B is greater than the distance between two adjacent signal lines located in the first area A. Therefore, when subsequently fabricating the planarization layer on the signal lines, the concave arc (as shown in Figure 2 ) on the upper surface of the planarization layer 12 between two adjacent signal lines located in the splicing area B is larger than the concave arc on the upper surface of the planarization layer 12 between two adjacent signal lines located in the first area A and the second area C.

[0074] When fabricating the first electrode 21, a whole layer of the first electrode material layer is first formed on the planarization layer 12, and then the first electrode material layer is formed into a plurality of first electrodes 21 by means such as development, exposure, and etching. Since the concave arc on the upper surface of the planarization layer 12 between two adjacent signal lines located in the splicing area B is larger than the concave arc on the upper surface of the planarization layer 12 between two adjacent signal lines located in the first area A and the second area C, the maximum thickness of the first electrode material layer located in the splicing area B is larger than the maximum thickness of the first electrode material layer located in the first area A and the second area C. When forming a plurality of first electrodes 21, the etching time required to separate the plurality of first electrodes 21 located in the splicing area B is longer than the etching time required to separate the plurality of first electrodes 21 located in the first area A and the second area C. To ensure that all the first electrodes 21 in the display panel are separated, after the etching process ends, the first electrodes 21 located in the first area A and the second area C are in an over-etched state. When the etching is performed with the same photoresist pattern in the splicing area B, the first area A, and the second area C, it will cause the area of the first electrode 21 located in the splicing area B to be larger than the area of the first electrode 21 located in the first area A and the second area C.

[0075] In some examples, the line width D1 of the first signal line 11a is 0.2 μm to 0.4 μm smaller than the line width D2 of the second signal line 11b, and it causes the size D3 of the first electrode 21 of the first light-emitting unit in the second direction y to be approximately 0.1 μm to 0.3 μm larger than the size D4 of the first electrode 21 of the second light-emitting unit in the second direction y. When the size of the first electrode 21 in the first direction x is fixed, compared with the area of the light-emitting layer 22 in the light-emitting unit located in the first area A or the second area C that is in contact with the first electrode 21, the area of the light-emitting layer 22 in the light-emitting unit located in the splicing area B that is in contact with the first electrode 21 is larger, thereby causing the brightness of the light-emitting unit in the splicing area B to be greater than the brightness of the light-emitting unit located in the first area A or the second area C, resulting in obvious display unevenness.

[0076] In the related art, a first mask is used to fabricate signal lines (a first signal line 11a and a second signal line 11b) in a first region A and a splicing region B, and a second mask is used to fabricate signal lines in the splicing region B and a second region B. If the widths of the first photoresist pattern formed by the first mask and the second photoresist pattern formed by the second mask are the same, it will result in different widths of the first signal line 11a located in the splicing region B and the second signal line 11b located in the first region A or the second region C. The following is an explanation of this:

[0077] If the photoresist used for fabricating the signal lines is a positive photoresist, the graphic size of the first signal line 11a corresponding to the first region A in the first mask is the same as the graphic size of the second signal line 11b corresponding to the second region C in the second mask, the graphic size of the first signal line 11a corresponding to the splicing region B in the first mask is the same as the graphic size of the second signal line 11b corresponding to the splicing region B in the second mask, and the graphic size of the first signal line 11a corresponding to the first region A in the first mask is larger than the graphic size of the second signal line 11b corresponding to the splicing region B in the second mask. After exposure and development, affected by repeated exposure in the splicing region B, the size of the photoresist structure retained in the splicing region B is smaller than the photoresist structures retained in the first region A and the second region B, which will result in a smaller width of the first signal line 11a located in the splicing region B than the second signal line 11b located in the first region A or the second region C. If the photoresist used for fabricating the signal lines is a negative photoresist, it will result in a larger width of the first signal line 11a located in the splicing region B than the second signal line 11b located in the first region A or the second region C. The specific process will not be elaborated here.

[0078] In the embodiment of the present disclosure, the line width D1 of the first signal line 11a is different from the line width D2 of the second signal line 11b. For example Figure 3 in the illustrated embodiment, the line width D1 of the first signal line 11a is smaller than the line width D2 of the second signal line 11b, but the area of the first electrode 21 located in the splicing region B is the same as the area of the first electrode 21 located in the first region A or the second region C.

[0079] By making the area of the first electrode 21 located in the splicing area B the same as the area of the first electrode 21 located in the first area A or the second area C, the area of the light-emitting layer 22 in the light-emitting unit located in the splicing area B that contacts the first electrode 21 is made the same as the area of the light-emitting layer 22 in the light-emitting unit located in the first area A or the second area C that contacts the first electrode 21. Therefore, under the same driving conditions, the light-emitting brightness of the light-emitting unit in the splicing area B is basically the same as that of the light-emitting unit in the first area A or the second area C. That is to say, in the embodiment of the present disclosure, by reducing the area difference between the first electrode in the splicing area B and the first electrode in the first area A or the second area C, the difference in the brightness between the light-emitting unit located in the splicing area B and the light-emitting unit located in the first area A or the second area C is reduced. Here, the same driving conditions mean that the voltage on the first signal line 11a is the same as the voltage on the second signal line 11b.

[0080] The area of the first electrode 21 located in the splicing area B can be made the same as the area of the first electrode 21 located in the first area A or the second area C in the following manner. After manufacturing a plurality of signal lines with different line widths, the signal lines include a thinner first signal line 11a and a thicker second signal line 11b, and then a planarization layer 12 and a plurality of first electrodes 21 are manufactured. When manufacturing the first electrode 21, a whole layer of first electrode material layer can be first formed on the planarization layer 12, and the maximum thickness of the first electrode material layer located in the splicing area B is greater than the maximum thickness of the first electrode material layer located in the first area A and the second area C.

[0081] If the photoresist used for manufacturing the first electrode is positive photoresist, and the third mask plate and the fourth mask plate are respectively used to manufacture a plurality of first electrodes 21, the graphic size of the first electrode 21 corresponding to the first area A in the third mask plate can be made the same as the graphic size of the first electrode 21 corresponding to the second area C in the fourth mask plate, the graphic size of the first electrode 21 corresponding to the splicing area B in the third mask plate is the same as the graphic size of the first electrode 21 corresponding to the splicing area B in the fourth mask plate, and the graphic size of the first electrode 21 corresponding to the first area A in the third mask plate is greater than the graphic size of the first electrode 21 corresponding to the splicing area B in the third mask plate, so that after exposure and development, the size of the photoresist structure retained in the splicing area B is smaller than the photoresist structures retained in the first area A and the second area B.

[0082] When etching the first electrode material layer to form a plurality of first electrodes 21, due to the thickness difference of the first electrode material layer in the splicing area B, the first area A, and the second area B, the etching time required to separate the plurality of first electrodes 21 located in the splicing area B is longer than the etching time required to separate the plurality of first electrodes 21 located in the first area A and the second area C. To ensure that all the first electrodes 21 in the display panel are separated, after the etching process is completed, the first electrodes 21 located in the first area A and the second area C are in an over-etching state, that is, the size of the first electrodes 21 actually formed in the first area A and the second area C is smaller than the size of the photoresist structure reserved in the first area A and the second area B, and the size of the first electrodes 21 actually formed in the splicing area B is equal to the size of the photoresist structure reserved in the splicing area B, so that the area of the first electrodes 21 located in the splicing area B is the same as the area of the first electrodes 21 located in the first area A or the second area C.

[0083] In another possible embodiment, the line width D1 of the first signal line 11a is larger than the line width D2 of the second signal line 11b, and the area of the first electrodes 21 located in the splicing area B is the same as the area of the first electrodes 21 located in the first area A or the second area C. Since the width of the signal lines located in the splicing area B is greater than the width of the signal lines located in the first area A and the second area C, the distance between two adjacent signal lines located in the splicing area B is less than the distance between two adjacent signal lines located in the first area A. Therefore, when subsequently fabricating the planarization layer on the signal lines, the concave arc of the upper surface of the planarization layer 12 between two adjacent signal lines located in the splicing area B is smaller than the concave arc of the upper surface of the planarization layer 12 between two adjacent signal lines located in the first area A and the second area C. When fabricating the first electrodes 21, a whole layer of the first electrode material layer can be formed on the planarization layer 12 first, and the maximum thickness of the first electrode material layer located in the splicing area B is smaller than the maximum thickness of the first electrode material layer located in the first area A and the second area C. If the photoresist used for fabricating the first electrodes is a negative photoresist, and the third mask and the fourth mask are respectively used to fabricate a plurality of first electrodes 21, the graphic size of the first electrodes 21 corresponding to the first area A in the third mask can be the same as the graphic size of the first electrodes 21 corresponding to the second area C in the fourth mask, the graphic size of the first electrodes 21 corresponding to the splicing area B in the third mask can be the same as the graphic size of the first electrodes 21 corresponding to the splicing area B in the fourth mask, and the graphic size of the first electrodes 21 corresponding to the first area A in the third mask is smaller than the graphic size of the first electrodes 21 corresponding to the splicing area B in the third mask, so that after exposure and development, the size of the photoresist structure reserved in the splicing area B is larger than the photoresist structures reserved in the first area A and the second area B.

[0084] When etching the first electrode material layer to form a plurality of first electrodes 21, due to the thickness difference of the first electrode material layer in the splicing area B, the first area A, and the second area B, the etching time required to separate the plurality of first electrodes 21 located in the splicing area B is shorter than the etching time required to separate the plurality of first electrodes 21 located in the first area A and the second area C. In order to ensure that all the first electrodes 21 in the display panel are separated, after the etching process is completed, the first electrodes 21 located in the splicing area B are in an over-etched state, that is, the size of the actually formed first electrodes 21 in the splicing area B is smaller than the size of the photoresist structure reserved in the splicing area B. Also, because the size of the photoresist structure reserved in the splicing area B is larger than the photoresist structures reserved in the first area A and the second area B, the area of the first electrodes 21 located in the splicing area B can be made the same as the area of the first electrodes 21 located in the first area A or the second area C.

[0085] By, for example, reducing the difference between the area of the first electrodes 21 located in the splicing area B and the area of the first electrodes 21 located in the first area A or the second area C, reducing the difference between the area of the first electrodes 21 located in the splicing area B and the area of the first electrodes 21 located in the first area A or the second area C, reducing the difference between the light emission brightness of the plurality of light-emitting units located in the splicing area B and the light emission brightness of the plurality of light-emitting units located in the first area A and the second area C, the display unevenness is improved.

[0086] In other possible embodiments, it is also possible to reduce the difference between the line width D1 of the first signal line 11a and the line width D2 of the second signal line 11b. For example, the difference between the line width of the second signal line 11b and the first signal line 11a in the embodiments of the present disclosure is made smaller than the difference between the line width of the second signal line 11b and the first signal line 11a in the related art. As a result, after forming the planarization layer, the concave arc of the upper surface of the planarization layer in the splicing area is smaller than the concave arc of the upper surface of the planarization layer in the related art, thereby reducing the difference between the area of the first electrodes 21 located in the splicing area B and the area of the first electrodes 21 located in the first area A or the second area B, and thus reducing the difference between the light emission brightness of the plurality of light-emitting units located in the splicing area B and the light emission brightness of the plurality of light-emitting units located in the first area A and the second area C, and improving the display unevenness.

[0087] In summary, by reducing the difference between the line width D1 of the first signal line 11a and the line width D2 of the second signal line 11b, and / or reducing the difference between the area of the first electrodes 21 located in the splicing area B and the area of the first electrodes 21 located in the first area A or the second area B, the difference between the light emission brightness of the plurality of light-emitting units located in the splicing area B and the light emission brightness of the plurality of light-emitting units located in the first area A and the second area C is reduced, and the display unevenness is improved.

[0088] Exemplarily, in combination with Figures 2 to 3 , the first signal line 11a is electrically connected to the first electrode 21 of at least one light-emitting unit arranged along the extending direction of the first signal line 11a. The second signal line 11b is electrically connected to the first electrode 21 of at least one light-emitting unit arranged along the extending direction of the second signal line 11b. A voltage can be applied to the first electrode 21 in at least one light-emitting unit through the first signal line 11a to control the brightness of the light-emitting unit; a voltage is applied to the first electrode 21 in at least one light-emitting unit through the second signal line 11b to control the brightness of the light-emitting unit and control the brightness of the light-emitting unit. In this embodiment, as Figure 2 and Figure 3 shown, the first electrode 21 of the light-emitting unit controlled by the first signal line 11a is connected to the first signal line 11a through a via hole, and the first electrode 21 of the light-emitting unit controlled by the second signal line 11b is connected to the second signal line 11b through a via hole.

[0089] In this embodiment, the display panel can be a passive OLED (Organic Light-Emitting Diode) display panel.

[0090] Optionally, the second electrodes 23 of a plurality of light-emitting units arranged in the second direction y are connected.

[0091] Optionally, the lights emitted by a plurality of light-emitting units 20 corresponding to a plurality of first electrodes 21 electrically connected to the connected first signal line 11a and second signal line 11b have the same color. That is, Figure 3 in, the lights emitted by each row of light-emitting units 20 have the same color.

[0092] Optionally, as shown in the figure, the display panel includes a display area D and a non-display area E, and the non-display area E surrounds the display area D. The display panel includes a plurality of pads (not shown in the figure), and the plurality of pads are located in the non-display area E. The first signal line 11a and the second signal line 11b extend to the non-display area E and are electrically connected to one of the pads. It is convenient for the outside to input a voltage to the connected first signal line 11a and second signal line 11b through the pads, so as to realize the control of the brightness of a plurality of light-emitting units in the display panel by the outside. Optionally, the plurality of pads are located on at least one side edge of the display backplane, for example, on one side of the display backplane in the first direction x.

[0093] In other possible embodiments, the first signal line 11a and the second signal line 11b are spaced apart from each other and both extend along the first direction x.

[0094] In other possible embodiments, the first signal line 11a and the second signal line 11b are spaced apart from each other and both extend along the second direction y. In this embodiment, the arrangement manner of the first signal line 11a and the second signal line 11b can also refer to the following Figure 4The arrangement of the first signal line 11a and the second signal line 11b shown in

[0095] Figure 4 is a schematic plan view of another display panel provided by an embodiment of the present disclosure. Compared with the foregoing embodiment, Figure 4 in the said embodiment, the film layer pattern of the splicing area is not changed to reduce the difference in the film layer patterns between the splicing area B and the first area A (or the second area C), so as to reduce the brightness difference between the splicing area B and the first area A (or the second area C) of the display panel. As Figure 4 shown, the first signal line 11a and the second signal line 11b are spaced apart from each other and the extending direction of both is the second direction y, and the second direction y intersects with the first direction x. The line width D1 of the first signal line 11a is smaller than the line width D2 of the second signal line 11b, and the area of the first electrode 21 located in the splicing area B is larger than the area of the first electrode 21 located in the first area A and the second area A. The first signal line 11a is used to control the brightness of the first light-emitting unit, and the first light-emitting unit is one of the multiple light-emitting units located in the splicing area B. The second signal line 11b is used to control the brightness of the second light-emitting unit, and the second light-emitting unit is one of the multiple light-emitting units located in the first area A or the second area C. The first signal line is configured to provide a first voltage to the first light-emitting unit, and the second signal line is configured to provide a second voltage to the second light-emitting unit. The magnitudes of the first voltage and the second voltage are different, so that the brightness difference between the first light-emitting unit controlled by the first signal line 11a and the second light-emitting unit controlled by the second signal line 11b is within 15%.

[0096] As Figure 4 shown, when the brightness difference between the first light-emitting unit and the second light-emitting unit is within 15%, the first voltage ratio is smaller than the second voltage.

[0097] When using the first mask to fabricate the film layer patterns (the film layer patterns may include the first electrode and the signal line) in the first region and the splicing region, and using the second mask to fabricate the film layer patterns (the film layer patterns may include the first electrode and the signal line) in the splicing region and the second region, if the graphic sizes corresponding to the first region in the first mask are the same as those corresponding to the splicing region, and the graphic sizes corresponding to the splicing region in the second mask are the same as those corresponding to the second region, it may cause the line widths of the aforementioned first signal line 11a and the second signal line 11b to be different. For example, the first signal line 11a is thinner and the second signal line 11b is thicker. If the same voltage is applied to the thinner first signal line 11a and the thicker second signal line 11b, since the area of the first electrode 21 located in the splicing region B is larger than the area of the first electrode 21 located in the first region A and the second region B, the contact area between the first electrode 21 located in the splicing region B and the light-emitting layer 22 is larger, and the brightness of the light emitted by the light-emitting units located in the splicing region B is greater. In the embodiments of the present disclosure, by applying a smaller voltage to the first signal line 11a with a smaller line width, the difference in the light-emitting brightness between the multiple light-emitting units located in the splicing region B and the multiple light-emitting units located in the first region A and the second region B is reduced, and the display unevenness is improved.

[0098] In other embodiments, the line width D1 of the first signal line 11a is larger than the line width D2 of the second signal line 11b, and the area of the first electrode 21 located in the splicing region B is smaller than the area of the first electrode 21 located in the first region and the second region. In this case, for the same brightness, the first signal line 11a is used to provide the first voltage, the second signal line 11b is used to provide the second voltage, and the first voltage is greater than the second voltage. If the same voltage is applied to the thicker first signal line 11a and the thinner second signal line 11b, since the area of the first electrode 21 located in the splicing region B is smaller than the area of the first electrode 21 located in the first region A and the second region A, the contact area between the first electrode 21 located in the splicing region B and the light-emitting layer 22 is smaller, and the brightness of the light emitted by the light-emitting units located in the splicing region B is smaller. In the embodiments of the present disclosure, by applying a larger voltage to the first signal line 11a with a larger line width, the difference in the light-emitting brightness between the multiple light-emitting units located in the splicing region B and the multiple light-emitting units located in the first region A and the second region B is reduced, and the display unevenness is improved.

[0099] Figure 5 is a schematic plan view of another display panel provided by the embodiments of the present disclosure. As Figure 5 shown, the line width of the first signal line 11a is the same as the line width of the second signal line 11b, and the area of the first electrode 21 located in the splicing region B is different from the area of the first electrode 21 located in the first region A and the second region B.

[0100] Exemplarily, referring again to Figure 2, the display panel further includes a plurality of microlenses 40 and a filling layer 41. The plurality of microlenses 40 and the filling layer 41 are sequentially located on the side of the light-emitting functional layer 20 away from the display backplane 10. The refractive index of the plurality of microlenses 40 is greater than that of the filling layer 41. The plurality of microlenses 40 correspond to the plurality of light-emitting units one by one. The plurality of microlenses correspond to the plurality of light-emitting units one by one, and the orthographic projection of the plurality of microlenses on the display backplane at least partially coincides with the orthographic projection of the plurality of light-emitting units on the display backplane. Here, the plurality of microlenses 40 can also be referred to as a light extraction layer. The smaller the aperture ratio of the first electrode 21, that is, the smaller the area of the first electrode 21, the less the light-emitting layer 22 in contact with the first electrode 21. The light-emitting layer 22 emits light under the voltage action of the first electrode 21 and the second electrode 23. Therefore, the brightness of the light emitted by the light-emitting layer 22 in contact with the first electrode 21 is smaller. Here, the aperture ratio of the first electrode 21 refers to the ratio of the contact area of the plurality of first electrodes 21 and the light-emitting layer 22 to the area of the display area of the display panel.

[0101] The microlenses 40 and the filling layer 41 can refract the light emitted by the light-emitting layer 22 to the human eye as much as possible, improving the brightness of the display panel.

[0102] When the aperture ratio of the first electrode 21 is smaller, the area of the first electrode 21 is smaller. When the area of the first electrode 21 is infinitely small to form a point, correspondingly, the light emitted by the partial light-emitting layer 22 above the first electrode 21 is also a point light source. When the point light source is located at the focal point of the microlens 40, the light emitted by the point light source can be all collimated by the microlens 40 to the light-emitting surface of the display panel, and all the emitted light rays are located within the eye box and finally all reach the human eye. At this time, the brightness gain of the microlens 40 to the display panel is infinite.

[0103] From the above, it can be obtained that the brightness of the light-emitting unit is related to the aperture ratio of the first electrode 21 and the gain of the microlens 40, and the brightness is proportional to the gain of the microlens 40 and inversely proportional to the aperture ratio of the first electrode 21. Through experimental verification, it is found that when the aperture ratio of the first electrode 21 is within a certain range (<40%, also called the saturation aperture ratio), even if the area sizes of the first electrodes 21 in different regions have a certain degree of fluctuation, due to the gain compensation effect of the microlens 40, the brightness difference of each region of the display panel is relatively small. When designing this scheme, only the size of the saturation aperture ratio needs to be considered, and the aperture ratio of the first electrode 21 is designed to be less than the saturation aperture ratio. By means of the adaptive compensation method of the microlens 40 for the aperture ratio of the first electrode 21, the problem of uneven display of the display panel can be improved.

[0104] In any of the embodiments shown in Figures 3 to 5 , by setting the microlenses 40 and the filling layer 41 and adopting the adaptive compensation method of the microlens 40 for the aperture ratio of the first electrode 21, the problem of uneven display of the display panel can be improved.

[0105] Exemplarily, the refractive index of the plurality of microlenses 40 is 0.15 to 0.8 greater than the refractive index of the filling layer 41, for example, the refractive index of the microlens 40 is 1.56, and the refractive index of the filling layer 41 is 1.41; or the refractive index of the microlens 40 is 2.12, and the refractive index of the filling layer 41 is 1.32. In an ideal design, the brightness of the display panel is maximum at a normal viewing angle, that is, when the line between the human eye and the center of the display panel is perpendicular to the display panel, the brightness of the display panel is maximum. When the human eye is at other positions, the angle between the line between the human eye and the center of the display panel and the line perpendicular to the display panel is recorded as α, and the larger α is, the brightness decreases parabolically. If the refractive index of the microlens 40 is too large compared with the refractive index of the filling layer 41, as α increases, the brightness will suddenly rise after decaying to a certain extent, which is manifested as the brightness of the display panel seen at a certain position other than the normal viewing angle being particularly bright, which also means that the brightness is not fully converged to the normal viewing angle.

[0106] Optionally, the shape of the microlens 40 is hemispherical, semi-elliptical, or a shape similar to a hemispherical or semi-elliptical shape with a smooth arc surface.

[0107] Optionally, the microlens 40 is made of photoresist, PDMS (polydimethylsiloxane), PMMA (polymethyl methacrylate), silicon, silicon oxide, silicon nitride, etc., and the filling layer 41 is made of UV glue (shadowless glue), AB glue (two-liquid mixed hardening glue), OCR glue (optically transparent glue), etc.

[0108] Alternatively, if Figure 2 As shown, the display panel further includes a protective layer 53, which is located on the side of the filling layer 41 away from the display back plate 10. The protective layer 53 plays a role in protecting the display panel. Optionally, the protective layer is made of glass.

[0109] Optionally, the shape of the display panel can be as follows Figures 3 to 5 The rectangle shown may also be a circle, etc. Optionally, the splicing area B passes through the middle of the rectangular display panel, or passes through the center of the circular display panel.

[0110] In some other examples, the display panel may also be an active OLED (Organic Light-Emitting Diode) display panel. In this case, the display backplane 10 further includes a plurality of pixel driving circuits, and the plurality of pixel driving circuits are connected to the plurality of light-emitting units in a one-to-one correspondence. The plurality of pixel driving circuits include a first pixel driving circuit connected to the first light-emitting unit and a second pixel driving circuit connected to the second light-emitting unit. The first signal line 11a is electrically connected to the first pixel driving circuit. The second signal line 11b is electrically connected to the second pixel driving circuit. The first signal line 11a controls the brightness of the first light-emitting unit through the first pixel driving circuit. The second signal line 11b controls the brightness of the second light-emitting unit through the second pixel driving circuit. Optionally, the pixel driving circuit includes a plurality of transistors, such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors).

[0111] Exemplarily, the display backplane further includes a plurality of third signal lines, and the extending direction of the third signal lines intersects with the extending direction of the first signal line 11a. Each third signal line is electrically connected to at least one pixel driving circuit. The first signal line 11a and the third signal lines control the first pixel driving circuit that is electrically connected to the first signal line 11a and the third signal lines at the same time, so as to control the first light-emitting unit that is electrically connected to the first pixel driving circuit; the second signal line 11b and the third signal lines control the second pixel driving circuit that is electrically connected to the second signal line 11b and the third signal lines at the same time, so as to control the second light-emitting unit that is electrically connected to the second pixel driving circuit, thereby realizing the display function.

[0112] Exemplarily, the first signal line 11a and the second signal line 11b are data lines, and the third signal lines are gate lines. That is, the first signal line 11a can be connected to the source or drain of a transistor in the first pixel driving circuit through a via, and the first electrode 21 of the light-emitting unit controlled by the first signal line 11a is connected to the source or drain of another transistor in the first pixel driving circuit through a via; the second signal line 11b can be connected to the source or drain of a transistor in the second pixel driving circuit through a via, and the first electrode 21 of the light-emitting unit controlled by the second signal line 11b is connected to the source or drain of another transistor in the second pixel driving circuit through a via.

[0113] Exemplarily, when the display panel is an active OLED display panel, the display backplane 10 may be a silicon-based driving backplane. Since a silicon mask is used to fabricate signal lines during the process of manufacturing the silicon-based driving backplane, and the silicon mask is relatively small and requires secondary exposure of some areas, the embodiments of the present disclosure are particularly suitable for display panels including silicon-based driving backplanes. In addition, since the display panel fabricated with a silicon-based driving backplane has a relatively small overall size, small pixels, and high resolution, the display panel fabricated with a silicon-based driving backplane is particularly suitable for VR display devices.

[0114] An exemplary description of the structure of the silicon-based driving backplane will be given below. Figure 6 It is a schematic cross-sectional structure diagram of a silicon-based driving backplane provided by an embodiment of the present disclosure. As Figure 6 shown, the silicon-based driving backplane includes a plurality of transistors, and the transistors may be metal oxide semiconductor field effect transistors (MOS).

[0115] Exemplarily, the silicon-based driving backplane includes a substrate 101, a source-drain layer 102, a gate insulating layer 103, a gate layer 104, a first insulating layer 105, a first wiring layer 106, a second insulating layer 107, a second wiring layer 108, and a planarization layer 12 stacked in sequence. Among them, the first signal line 11a and the second signal line 11b may be located in the second wiring layer 108.

[0116] Exemplarily, the display backplane includes a stacked first wiring layer 106 and a second wiring layer 108, and the second wiring layer 108 is located on the side of the first wiring layer 106 close to the light-emitting functional layer 20. Since the resistance of the source-drain layer 102 and the gate layer 104 is relatively large, the first wiring layer 106 is separately provided as a single layer, for example, disposed above the source-drain layer 102; the second wiring layer is separately provided as a single layer, for example, disposed above the gate layer 104. It is convenient to use a material with a relatively small resistance, such as a metal material, to fabricate the first signal line 11a and the second signal line 11b. The second wiring layer 108 is disposed on the side of the first wiring layer 106 close to the light-emitting functional layer 200. The interference of the electrical signals in the first signal line 11a and the second signal line 11b to the transistors can be reduced.

[0117] Exemplarily, the gate layer 104 includes a gate 1040, the source-drain layer 102 includes a source 1021 and a drain 1022, and the gate 1040, the source 1021, and the drain 1022 form a transistor.

[0118] Optionally, the transistor can be an N-type MOS transistor or a P-type MOS transistor. For an N-type MOS transistor, the substrate 101 located below the N-type MOS transistor can be a P-type semiconductor, and the source electrode 1021 and the drain electrode 1022 can be N-type semiconductors; for a P-type MOS transistor, the substrate 101 located below the P-type MOS transistor can be an N-type semiconductor, and the source electrode 1021 and the drain electrode 1022 can be P-type semiconductors.

[0119] Optionally, the sidewalls of the gate 1040 have a spacer structure 111 for protecting the sidewalls of the gate 1040. Exemplarily, the spacer structure 111 is fabricated using a spacer process. Optionally, the material for fabricating the spacer structure 111 is silicon oxide.

[0120] Optionally, a metal protection layer 112 is further provided on the surface of the gate 1040 away from the substrate 101. It is used to protect the top surface of the gate 1040 and does not affect the electrical connection between the gate 1040 and other structures. Optionally, the material for fabricating the metal protection layer 112 is a refractory metal.

[0121] Optionally, the silicon-based driving backplane 10 further includes a plurality of isolation trenches 109 located between two adjacent transistors. Optionally, the isolation trenches 109 are formed using a shallow trench isolation (STI) process. Optionally, the isolation trenches 109 are filled with deposited oxide.

[0122] Optionally, there are a plurality of vias in the gate insulating layer 103 to facilitate the connection between the traces in the first trace layer 106 and the transistors.

[0123] Optionally, the material for fabricating the gate layer 104 is one or more of metal materials such as aluminum, molybdenum, copper, and titanium.

[0124] Exemplarily, the materials for fabricating the gate insulating layer 103, the first insulating layer 105, the first trace layer 106, and the second insulating layer 107 can be silicon oxide, silicon nitride, silicon oxynitride, etc.

[0125] Optionally, a protection layer 110 is provided on the surface of the trace (such as the first signal line 11a) to prevent the metal in the trace from migrating and diffusing with the silicon in the silicon-based driving backplane. The material for fabricating the protection layer can be silicon oxide or silicon nitride.

[0126] Exemplarily, the planarization layer 12 is made of an organic insulating material such as resin.

[0127] Alternatively, in other embodiments, the display backplane 10 may be a driving backplane including a plurality of TFTs (Thin Film Transistors), rather than the aforementioned silicon-based driving backplane 10. For example, the display backplane 10 may be an LTPO (Low-temperature Polycrystalline oxide) backplane or an LTPS (Low-Temperature Poly-Silicon) backplane. Optionally, the display backplane includes a gate layer, an active layer, and a source-drain layer. Among them, the active layer is made of a low-temperature polycrystalline silicon material and a metal oxide semiconductor material such as IGZO (Indium Gallium Zinc Oxide), or the active layer is made of a low-temperature polycrystalline silicon material.

[0128] Figure 7 It is a schematic flowchart of a method for manufacturing a display panel provided by an embodiment of the present disclosure. As Figure 7 shown, the method includes:

[0129] In step S1, a display backplane is manufactured. The display backplane has a first region, a splicing region, and a second region that are sequentially connected in a first direction.

[0130] In step S2, a light-emitting functional layer is manufactured on one side of the display backplane. Among them, the light-emitting functional layer includes a plurality of light-emitting units distributed in an array, and each light-emitting unit includes a first electrode. The distribution density of the light-emitting units in the first region, the distribution density of the light-emitting units in the splicing region, and the distribution density of the light-emitting units in the second region are the same. Among them, the display backplane includes a first signal line and a second signal line on the same layer. The first signal line is located in the splicing region, and the second signal line is located in the first region or the second region. The first signal line is used to control the brightness of the first light-emitting unit, and the first light-emitting unit is one of the plurality of light-emitting units located in the splicing region. The second signal line is used to control the brightness of the second light-emitting unit, and the second light-emitting unit is one of the plurality of light-emitting units located in the first region or the second region. The line width of the first signal line is different from the line width of the second signal line, and / or the area of the first electrode located in the splicing region is different from the area of the first electrode located in the first region and the second region. The difference in the brightness between the first light-emitting unit and the second light-emitting unit under the same driving conditions is within 15%. This method can be used to manufacture Figure 3 the display panel shown.

[0131] An embodiment of the present disclosure also provides another method for manufacturing a display panel. The method includes: replacing step S2 in the above method with: fabricating a light-emitting functional layer on one side of a display backplane. The light-emitting functional layer includes a plurality of light-emitting units distributed in an array, and each light-emitting unit includes a first electrode. The distribution density of the light-emitting units in the first region, the distribution density of the light-emitting units in the splicing region, and the distribution density of the light-emitting units in the second region are the same. The display backplane includes a first signal line and a second signal line on the same layer. The first signal line is located in the splicing region, and the second signal line is located in the first region or the second region. The first signal line and the second signal line are spaced apart from each other and both extend in the second direction, and the second direction intersects the first direction. The first signal line is configured to control the brightness of a first light-emitting unit, and the first light-emitting unit is one of the plurality of light-emitting units located in the splicing region. The second signal line is configured to control the brightness of a second light-emitting unit, and the second light-emitting unit is one of the plurality of light-emitting units located in the first region or the second region. The line width of the first signal line is different from the line width of the second signal line, and the area of the first electrode of the first light-emitting unit is different from the area of the first electrode of the second light-emitting unit. The first signal line is configured to provide a first voltage to the first light-emitting unit, and the second signal line is configured to provide a second voltage to the second light-emitting unit, so that the brightness difference between the first light-emitting unit and the second light-emitting unit is within 15%. This method can be used to manufacture Figure 4 the display panel shown.

[0132] Figure 8 FIG. 6 is a schematic structural diagram of a first mask and a second mask for manufacturing a plurality of signal lines on the same layer provided by an embodiment of the present disclosure. Manufacturing the display backplane includes:

[0133] In the first step, use the first mask 61 as shown in part a of Figure 8 to form a first photoresist pattern. The first mask 61 includes a first part 61a and a second part 61b. The first part 61a and the second part 61b are respectively used to form different parts of the first photoresist pattern in the first region and the splicing region.

[0134] In the second step, use the second mask 62 as shown in part b of Figure 8 to form a second photoresist pattern. The second mask 62 includes a third part 62a and a fourth part 62b. The third part 62a and the fourth part 62b are respectively used to form different parts of the second photoresist pattern in the splicing region and the second region. At least a part of the second photoresist pattern and the first photoresist pattern in the splicing region overlap.

[0135] In the third step, based on the first photoresist pattern and the second photoresist pattern, form a wiring layer, and the wiring layer includes a first signal line and a second signal line.

[0136] Among them, the width of the pattern of the second part 61b is equal to the width of the pattern of the third part 62a, the width of the pattern area of the second part 61b is greater than the width of the pattern area of the first part 61a, the width of the pattern area of the second part 61b is greater than the width of the pattern area of the fourth part 62b, and the pattern area is the area corresponding to the signal line.

[0137] Exemplarily, when manufacturing the signal line, a whole layer of conductive material layer is obtained by means such as deposition, and a whole layer of photoresist is formed on the conductive material layer by means such as coating. The photoresist is exposed and developed using a mask plate, and part of the photoresist is removed by means such as solvent dissolution, and the remaining part of the photoresist forms a photoresist structure. By means such as etching, the part of the conductive material layer not covered by the photoresist structure is removed, so as to retain the part of the conductive material layer located under the photoresist structure, forming a signal line. Finally, the photoresist structure is removed by means such as etching.

[0138] In a possible embodiment, the photoresist used for manufacturing the signal line is a positive photoresist. Correspondingly, as Figure 8 shown, the first mask plate 61 and the second mask plate 62 include a plurality of strip structures 601, the plurality of strip structures 601 correspond to a plurality of signal lines, and the width of the strip structure 601 of the second part 61b is greater than the width of the strip structure 601 of the first part 61a. For the positive photoresist, the exposed part of the photoresist is dissolved in subsequent processing; the unexposed part of the photoresist is not dissolved in subsequent processing, and this part of the photoresist is used to protect the position where the corresponding signal line is located, facilitating the formation of the signal line by means such as etching. If the width of the strip structure 601 of the first part 61a is the same as the width of the strip structure 601 of the second part 61b, due to the fact that the photoresist in the splicing area has experienced repeated exposure, affected by the alignment accuracy of the repeated exposure, the actually exposed area of the photoresist in the splicing area will be larger than the theoretically designed exposed area of the photoresist in the splicing area, so that too much photoresist is dissolved in subsequent processing, leaving less photoresist, and the manufactured signal line is thinner. By making the width of the strip structure 601 of the second part 61b greater than the width of the strip structure 601 of the first part 61a in the embodiments of the present disclosure, the difference between the width of the signal line in the splicing area and the width of the signal line in the first area or the second area is made smaller. Optionally, the first mask plate 61 and the second mask plate 62 are used to expose the photoresist in different areas respectively, and then the developing and etching processes are carried out.

[0139] Optionally, the width of the strip structure 601 of the second part 61b is 5% - 10% greater than the width of the strip structure 601 of the first part 61a. If this percentage is too small, the width of the signal line in the splicing area will be too small relative to the width of the signal line in the non-splicing area; if this percentage is too large, the width of the signal line in the splicing area will be too large relative to the width of the signal line in the non-splicing area.

[0140] In another possible embodiment, the photoresist used to fabricate the signal lines is a negative photoresist. Correspondingly, the first mask 61 and the second mask 62 include a plurality of strip-shaped openings, the plurality of strip-shaped openings corresponding to the plurality of signal lines, and the width of the strip-shaped openings in the second portion 61b being smaller than the width of the strip-shaped openings in the first portion 61a. For a negative photoresist, the unexposed portion of the photoresist is dissolved in subsequent processing; the exposed portion of the photoresist is not dissolved in subsequent processing, and this portion of the photoresist is used to protect the position where the corresponding signal line is located, facilitating the formation of the signal line by means such as etching. If the width of the strip-shaped openings in the first portion 61a is the same as the width of the strip-shaped openings in the second portion 61b, due to the photoresist in the splicing area undergoing repeated exposure, affected by the alignment accuracy of the repeated exposure, the actually exposed area of the photoresist in the splicing area will be larger than the theoretically designed exposed area of the photoresist in the splicing area, resulting in too much photoresist not being dissolved in subsequent processing, leaving more photoresist, and the fabricated signal line being thicker. By making the width of the strip-shaped openings in the second portion 61b smaller than the width of the strip-shaped openings in the first portion 61a in the embodiments of the present disclosure, the difference between the width of the signal line in the splicing area and the width of the signal line in the first area or the second area is relatively small.

[0141] Optionally, the width of the strip-shaped openings in the first portion 61a is 5% to 10% greater than the width of the strip-shaped openings in the second portion 61b. If this percentage is too small, the width of the signal line in the splicing area will be too large relative to the width of the signal line in the non-splicing area; if this percentage is too large, the width of the signal line in the splicing area will be too small relative to the width of the signal line in the non-splicing area.

[0142] In other embodiments, the signal line can also be fabricated in the following manner: First, a whole layer of photoresist is formed by means such as coating, the photoresist is exposed and developed using a mask, and through means such as solvent dissolution, part of the photoresist is removed, and the remaining part of the photoresist forms a photoresist structure; then a whole layer of conductive material layer covering the photoresist structure is obtained by means such as deposition, and through means such as metal lift-off process, the photoresist structure and the conductive material layer located above the photoresist structure are removed, and the remaining part of the conductive material layer forms the signal line.

[0143] In this manufacturing method, if the photoresist is a positive photoresist, the first mask 61 and the second mask 62 include a plurality of strip-shaped openings, and the width of the strip-shaped openings in the second part 61b is smaller than the width of the strip-shaped openings in the first part 61a. The explanation is as follows: If the width of the strip-shaped openings in the second part 61b is equal to the width of the strip-shaped openings in the first part 61a, that is, the pattern size of the first signal line 11a corresponding to the first region A in the first mask is the same as the pattern size of the second signal line 11b corresponding to the second region C in the second mask, the pattern size of the first signal line 11a corresponding to the splicing region B in the first mask is the same as the pattern size of the second signal line 11b corresponding to the splicing region B in the second mask, and the pattern size of the first signal line 11a corresponding to the first region A in the first mask is the same as the pattern size of the second signal line 11b corresponding to the splicing region B in the second mask. After exposure and development, due to the influence of repeated exposure in the splicing region B, the size of the photoresist structure removed in the splicing region B is larger than the photoresist structures removed in the first region A and the second region B. The position of the removed photoresist structure corresponds to the position of the signal line. Therefore, the width of the first signal line 11a located in the splicing region B will be larger than the width of the second signal line 11b located in the first region A or the second region C. In the present disclosure, by making the width of the strip-shaped openings in the second part 61b smaller than the width of the strip-shaped openings in the first part 61a, the gap between the line widths of the formed first signal line 11a and the second signal line 11b is reduced.

[0144] If the photoresist is a negative photoresist, the first mask 61 and the second mask 62 include a plurality of strip structures 601, and the width of the strip structures 601 in the second part 61b is greater than the width of the strip structures 601 in the first part 61a. The explanation is as follows: If the width of the strip structures in the second part 61b is equal to the width of the strip structures in the first part 61a, that is, the pattern size of the first signal line 11a corresponding to the first region A in the first mask is the same as the pattern size of the second signal line 11b corresponding to the second region C in the second mask, the pattern size of the first signal line 11a corresponding to the splicing region B in the first mask is the same as the pattern size of the second signal line 11b corresponding to the splicing region B in the second mask, and the pattern size of the first signal line 11a corresponding to the first region A in the first mask is the same as the pattern size of the second signal line 11b corresponding to the splicing region B in the second mask. After exposure and development, affected by repeated exposure in the splicing region B, the size of the photoresist structure removed in the splicing region B is smaller than the photoresist structures removed in the first region A and the second region B. The position of the removed photoresist structure corresponds to the position of the signal line. Therefore, the width of the first signal line 11a located in the splicing region B is smaller than the width of the second signal line 11b located in the first region A or the second region C. In the present disclosure, by making the width of the strip structures in the second part 61b greater than the width of the strip structures in the first part 61a, the gap between the line widths of the formed first signal line 11a and the second signal line 11b is reduced.

[0145] Figure 9 It is a schematic structural diagram of a third mask and a fourth mask for manufacturing a first electrode layer provided by an embodiment of the present disclosure. The following steps are included in manufacturing a plurality of first electrodes of a light-emitting functional layer on one side of a display backplane. Among them, the first electrode layer includes a plurality of first electrodes.

[0146] The first step is to use the third mask 63 as shown in part (a) of Figure 9 to form a second photoresist pattern. Among them, the third mask 63 includes a fifth part 63a and a sixth part 63b, and the fifth part 63a and the sixth part 63b are respectively used to form different parts of the third photoresist pattern in the first region and the splicing region.

[0147] The second step is to use the fourth mask 64 as shown in part (b) of Figure 9 to form a fourth photoresist pattern. Among them, the fourth mask 64 includes a seventh part 64a and an eighth part 64b, and the seventh part 64a and the eighth part 64b are respectively used to form different parts of the fourth photoresist pattern in the splicing region and the second region.

[0148] The third step is to form a plurality of first electrodes based on the third photoresist pattern and the fourth photoresist pattern.

[0149] Among them, the pattern of the sixth part 63b and the pattern of the seventh part 64a are congruent patterns, the pattern of the fifth part 63a and the pattern of the eighth part 64b are congruent patterns, the area of the pattern of the sixth part 63b is smaller than the area of the pattern of the fifth part 63a, and the pattern of the sixth part 63b and the pattern of the fifth part 63a are similar patterns, and the pattern is the area corresponding to the first electrode 21.

[0150] When the photoresist used for manufacturing the signal line is a positive photoresist, and in the first mask and the second mask, the widths of the strip structures of the first part and the second part are the same, the width of the signal line located in the splicing area B is smaller than the width of the signal line located in the first area A and the second area C. When subsequently manufacturing the planarization layer located on the signal line, the concave arc of the planarization layer between two adjacent signal lines located in the splicing area B is larger than the concave arc of the planarization layer between two adjacent signal lines located in the first area A and the second area C. Therefore, when manufacturing the first electrode 21, the thickness of the first electrode material layer located in the splicing area B is larger than the thickness of the first electrode material layer located in the first area A and the second area C. When forming a plurality of first electrodes 21 from the first electrode material layer by means of, for example, etching, if the area of the pattern region of the fifth part 63a is approximately equal to or equal to the area of the pattern region of the sixth part 63b, the etching time required to separate a plurality of first electrodes 21 located in the splicing area B is longer than the etching time required to separate a plurality of first electrodes 21 located in the first area A and the second area C. To ensure that all the first electrodes 21 in the display panel are separated, after the etching process ends, the first electrodes 21 located in the first area A and the second area C are in an over-etched state, which in turn causes the area of the first electrodes 21 located in the splicing area B to be larger than the area of the first electrodes 21 located in the first area A and the second area C. In the embodiments of the present disclosure, by making the area of the pattern region of the sixth part 63b smaller than the area of the pattern region of the fifth part 63a, the difference between the area of the first electrode 21 in the splicing area B and the area of the first electrode 21 in the first area A or the second area C is made smaller.

[0151] Exemplarily, when manufacturing the first electrode 21, a whole layer of the first electrode 21 material layer is obtained by means of, for example, deposition, and a whole layer of photoresist is formed on the first electrode 21 material layer by means of, for example, coating. The photoresist is exposed and developed using a mask, and part of the photoresist is removed by means of, for example, solvent dissolution. The part of the photoresist that is not removed forms a photoresist structure. By means of, for example, etching, the part of the conductive material layer that is not covered by the photoresist structure is removed, so as to retain the part of the first electrode 21 material layer located under the photoresist structure, and a plurality of first electrodes 21 are formed. By means of, for example, etching, the photoresist structure is removed.

[0152] In a possible embodiment, the photoresist used to fabricate the first electrode 21 is a positive photoresist. Correspondingly, as Figure 9 shown, the third mask 63 and the fourth mask 64 include a plurality of block structures 602. The plurality of block structures 602 correspond to the plurality of first electrodes 21. The area of the block structures 602 in the sixth portion 63b is smaller than the area of the block structures 602 in the fifth portion 63a. For positive photoresist, the exposed portion of the photoresist dissolves in subsequent processing; the unexposed portion of the photoresist does not dissolve in subsequent processing, and this portion of the photoresist is used to protect the position where the corresponding first electrode 21 is located, facilitating the formation of the first electrode 21 by means such as etching. If the area of the block structures 602 in the fifth portion 63a is the same as the area of the block structures 602 in the sixth portion 63b, due to the photoresist in the splicing area B experiencing repeated exposure, affected by the alignment accuracy of the repeated exposure, the actually exposed area of the photoresist in the splicing area B will be larger than the theoretically designed exposed area of the photoresist in the splicing area B, resulting in excessive dissolution of the photoresist in subsequent processing, leaving less photoresist, and the area of the fabricated first electrode 21 is smaller. By making the area of the block structures 602 in the sixth portion 63b smaller than the area of the block structures 602 in the fifth portion 63a in the embodiments of the present disclosure, the first electrode 21 located in the splicing area B is smaller, thus improving the problem that the area of the first electrode 21 in the splicing area B is too large.

[0153] Optionally, the area of the block structures 602 in the sixth portion 63b is 5% - 20% smaller than the area of the block structures 602 in the fifth portion 63a. This design can solve the problem that the area of the first electrode 21 located in the splicing area B is relatively large. If this percentage is too small, the area of the first electrode 21 in the splicing area B will be too large relative to the area of the first electrode 21 in the non-splicing area B; if this percentage is too large, the area of the first electrode 21 in the splicing area B will be too small relative to the area of the first electrode 21 in the non-splicing area B.

[0154] When the photoresist used to fabricate the signal line is a negative photoresist, and in the first mask and the second mask, the widths of the strip structures in the first part and the second part are the same, the width of the signal line located in the splicing area B fabricated is greater than the width of the signal lines located in the first area A and the second area C. When subsequently fabricating the planarization layer on the signal line, the concave arc of the planarization layer between two adjacent signal lines located in the splicing area B is smaller than the concave arc of the planarization layer between two adjacent signal lines located in the first area A and the second area C. Therefore, when fabricating the first electrode 21, the thickness of the material layer of the first electrode 21 located in the splicing area B is smaller than the thickness of the material layer of the first electrode 21 located in the first area A and the second area C. When forming a plurality of first electrodes 21 by etching the material layer of the first electrode 21, if the area of the graphic region of the fifth part 63a is approximately the same as or equal to the area of the graphic region of the sixth part 63b, the etching time required to separate the plurality of first electrodes 21 located in the splicing area B is shorter than the etching time required to separate the plurality of first electrodes 21 located in the first area A and the second area C. To ensure that all the first electrodes 21 in the display panel are separated, after the etching process ends, the first electrodes 21 located in the splicing area B are in an over-etched state, which in turn results in the area of the first electrodes 21 located in the splicing area B being smaller than the area of the first electrodes 21 located in the first area A and the second area C. In the embodiments of the present disclosure, by making the area of the graphic region of the sixth part 63b greater than the area of the graphic region of the fifth part 63a, the difference between the area of the first electrodes 21 in the splicing area B and the area of the first electrodes 21 in the first area A or the second area C is made smaller.

[0155] In a possible embodiment, the photoresist used to fabricate the first electrode 21 is a negative photoresist. Correspondingly, the third mask 63 and the fourth mask 64 include a plurality of block-shaped openings, the plurality of block-shaped openings corresponding to the plurality of first electrodes 21, and the area of the block-shaped openings in the sixth portion 63b being larger than the area of the block-shaped openings in the fifth portion 63a. For a negative photoresist, the unexposed portion of the photoresist is dissolved in subsequent processing; the exposed portion of the photoresist is not dissolved in subsequent processing, and this portion of the photoresist is used to protect the position where the corresponding first electrode 21 is located, facilitating the formation of the first electrode 21 by means such as etching. If the area of the block-shaped openings in the fifth portion 63a is the same as the area of the block-shaped openings in the sixth portion 63b, due to the photoresist in the splicing area B experiencing repeated exposure, affected by the alignment accuracy of the repeated exposure, the actually exposed area of the photoresist in the splicing area B will be larger than the theoretically designed exposed area of the photoresist in the splicing area B, resulting in too much photoresist being dissolved in subsequent processing, leaving less photoresist, and the area of the fabricated first electrode 21 being larger. In the embodiment of the present disclosure, by making the area of the block-shaped structure 602 in the sixth portion 63b larger than the area of the block-shaped structure 602 in the fifth portion 63a, the first electrode 21 located in the splicing area B is made smaller, thereby improving the problem that the area of the first electrode 21 in the splicing area B is too small.

[0156] Optionally, the area of the block-shaped openings in the fifth portion is less than 5% to 20% of the area of the block-shaped openings in the sixth portion. If this percentage is too small, the area of the first electrode 21 in the splicing area will be too small relative to the area of the first electrode 21 in the non-splicing area; if this percentage is too large, the area of the first electrode 21 in the splicing area will be too large relative to the area of the first electrode 21 in the non-splicing area.

[0157] Exemplarily, when fabricating the first electrode 21, a whole layer of photoresist can also be formed first by means such as coating, the photoresist is exposed and developed using a mask, and part of the photoresist is removed by means such as solvent dissolution, and the remaining part of the photoresist forms a photoresist structure. Then, a whole layer of the first electrode 21 material layer covering the photoresist structure is obtained by means such as deposition, and the photoresist structure and the first electrode 21 material layer located above the photoresist structure are removed by means such as laser lift-off (LLO), and the remaining part of the first electrode 21 material layer forms the first electrode 21. In this fabrication method, if the photoresist is a positive photoresist, the third mask 63 and the fourth mask 64 include a plurality of block-shaped openings, and the area of the block-shaped openings in the sixth portion 63b is smaller than the area of the block-shaped openings in the fifth portion 63a. If the photoresist is a negative photoresist, the third mask 63 and the fourth mask 64 include a plurality of block-shaped structures 602, and the area of the block-shaped structures 602 in the sixth portion 63b is larger than the area of the block-shaped structures 602 in the fifth portion 63a.

[0158] Exemplarily, the first mask 61, the second mask 62, the third mask 61 or the fourth mask 64 further includes a transparent substrate, such as a quartz substrate, which can support the graphic area of the mask and does not affect the manufacturing process of exposure and development at the same time.

[0159] The embodiments of the present disclosure also provide a display device, which includes any one of the foregoing display panels and a power supply circuit for supplying power to the display panel.

[0160] Exemplarily, the display device provided by the embodiments of the present disclosure can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0161] The display device has the same effects as the foregoing display panel and will not be elaborated herein.

[0162] Exemplarily, the display device further includes a control circuit, and the control circuit is Figure 4 electrically connected to the display panel in the illustrated embodiment, and is configured to provide a first voltage to the first signal line and a second voltage to the second signal line, and the magnitudes of the first voltage and the second voltage are different.

[0163] For the first light-emitting unit controlled by the first signal line and the second light-emitting unit controlled by the second signal line, in the related art, when the brightness of the first light-emitting unit and the second light-emitting unit is the same, the magnitudes of the first voltage and the second voltage are the same; while in the embodiments of the present disclosure, when the brightness of the first light-emitting unit and the second light-emitting unit is the same, the first voltage and the second voltage are different.

[0164] Optionally, when the display panel is the Figure 4 display panel shown, the first voltage is greater than the second voltage so that the brightness of the light-emitting unit controlled by the first signal line is the same as the brightness of the light-emitting unit controlled by the second signal line.

[0165] The embodiments of the present disclosure also provide a mask for manufacturing a film layer of a display panel. The display backplane includes a first region A, a splicing region B, and a second region C that are sequentially connected in the first direction x. The mask includes a connected first part and a second part. The first part is used to manufacture the film layer of the first region or the second region, and the second part is used to manufacture the film layer of the splicing region. The sizes of the graphics in the graphic area of the first part and the graphic area of the second part are different. Here, the graphics in the graphic area of the first part and the graphics in the graphic area of the second part can be strip structures, strip openings, block structures, or block openings.

[0166] Exemplarily, for a photomask for fabricating signal lines (including a first signal line 11a and a second signal line 11b), the difference in the dimensions of the patterns in the first part of the pattern region and the second part of the pattern region means that the dimensions of the patterns in the first part of the pattern region and the second part of the pattern region are different in the second direction y. For a photomask for fabricating a first electrode, the difference in the dimensions of the patterns in the first part of the pattern region and the second part of the pattern region means that the dimensions of the patterns in the first part of the pattern region and the second part of the pattern region are different in both the first direction x and the second direction y.

[0167] Exemplarily, the photomask includes a first photomask and a second photomask. The first photomask includes a first part and a second part, and the first part and the second part are respectively used to form signal lines in a first region A and a splicing region B. The second photomask includes a third part and a fourth part, and the third part and the fourth part are respectively used to form signal lines in the splicing region B and a second region C. The pattern of the second part and the pattern of the third part are congruent patterns, the width of the pattern of the second part is greater than the width of the pattern of the first part, and the width of the pattern of the second part is greater than the width of the pattern of the fourth part.

[0168] Optionally, the first photomask and the second photomask include a plurality of strip structures, and the width of the strip structure of the second part is 5% - 10% greater than the width of the strip structure of the first part.

[0169] Optionally, the first photomask and the second photomask include a plurality of strip openings, and the width of the strip opening of the first part is 5% - 10% greater than the width of the strip opening of the second part.

[0170] Exemplarily, the photomask includes a third photomask and a fourth photomask. The third photomask includes a fifth part and a sixth part, and the fifth part and the sixth part are respectively used to form a plurality of first electrodes in a first region A and a splicing region B. The fourth photomask includes a seventh part and an eighth part, and the seventh part and the eighth part are respectively used to form a plurality of first electrodes in the splicing region B and a second region C. The pattern of the sixth part and the pattern of the seventh part are congruent patterns, the pattern of the fifth part and the pattern of the eighth part are congruent patterns, the area of the pattern of the sixth part is smaller than the area of the pattern of the fifth part, and the pattern of the sixth part and the pattern of the fifth part are similar patterns, and the pattern is the region corresponding to the first electrode.

[0171] Optionally, the third photomask and the fourth photomask include a plurality of block structures, and the area of the block structure of the sixth part is 5% - 20% smaller than the area of the block structure of the fifth part.

[0172] Optionally, the third photomask and the fourth photomask include a plurality of block openings, and the area of the block opening of the fifth part is 5% - 20% smaller than the area of the block opening of the sixth part.

[0173] For other content of the mask plate, please refer to the foregoing embodiments, which will not be elaborated herein.

[0174] The above are only optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A display panel, characterized in that, The display panel includes a stacked display backplane (10) and a light-emitting functional layer (20). The display backplane (10) has a first region, a splicing region, and a second region that are sequentially connected in a first direction; The light-emitting functional layer (20) includes a plurality of light-emitting units distributed in an array. Each light-emitting unit includes a first electrode (21). Among them, the distribution density of the light-emitting units in the first region, the distribution density of the light-emitting units in the splicing region, and the distribution density of the light-emitting units in the second region are the same; The display backplane (10) includes a first signal line (11a) and a second signal line (11b) on the same layer. The first signal line (11a) is located in the splicing region, and the second signal line (11b) is located in the first region or the second region. The first signal line (11a) is used to control the brightness of a first light-emitting unit, and the first light-emitting unit is one of the plurality of light-emitting units located in the splicing region. The second signal line (11b) is used to control the brightness of a second light-emitting unit, and the second light-emitting unit is one of the plurality of light-emitting units located in the first region or the second region; The line width of the first signal line (11a) is different from the line width of the second signal line (11b), and / or the area of the first electrode (21) of the first light-emitting unit is different from the area of the first electrode (21) of the second light-emitting unit; The difference in the brightness of the first light-emitting unit and the brightness of the second light-emitting unit under the same driving conditions is within 15%; 2. The display panel according to claim 1, wherein The first signal line (11a) and the second signal line (11b) are connected and extend along the first direction, or the first signal line (11a) and the second signal line (11b) are spaced apart from each other and the extending direction is the second direction, and the second direction intersects with the first direction; The line width of the first signal line (11a) is different from the line width of the second signal line (11b), and the area of the first electrode (21) located in the splicing region is the same as the area of the first electrode (21) located in the first region or the second region; 3. A display panel, characterized in that, The display panel includes a stacked display backplane (10) and a light-emitting functional layer (20). The display backplane (10) has a first region, a splicing region, and a second region that are sequentially connected in a first direction; The light-emitting functional layer (20) includes a plurality of light-emitting units distributed in an array. Each light-emitting unit includes a first electrode (21). Among them, the distribution density of the light-emitting units in the first region, the distribution density of the light-emitting units in the splicing region, and the distribution density of the light-emitting units in the second region are the same; The display backplane (10) includes a first signal line and a second signal line on the same layer. The first signal line is located in the splicing region, and the second signal line is located in the first region or the second region. The first signal line (11a) and the second signal line (11b) are spaced apart from each other and the extending directions are both the second direction, and the second direction intersects with the first direction; The first signal line (11a) is used to control the brightness of a first light-emitting unit, which is one of the multiple light-emitting units located in the splicing area. The second signal line is used to control the brightness of a second light-emitting unit, which is one of the multiple light-emitting units located in the first area or the second area; The line width of the first signal line (11a) is different from the line width of the second signal line (11b), and the area of the first electrode (21) of the first light-emitting unit is different from the area of the first electrode (21) of the second light-emitting unit; The first signal line is configured to provide a first voltage to the first light-emitting unit, and the second signal line is configured to provide a second voltage to the second light-emitting unit. The magnitudes of the first voltage and the second voltage are different, so that the brightness difference between the first light-emitting unit and the second light-emitting unit is within 15%.

4. The display panel according to claim 3, wherein The line width of the first signal line (11a) is smaller than the line width of the second signal line (11b), and the area of the first electrode (21) located in the splicing area is larger than the area of the first electrode (21) located in the first area and the second area, and the first voltage is smaller than the second voltage; or, The line width of the first signal line (11a) is larger than the line width of the second signal line (11b), and the area of the first electrode (21) located in the splicing area is smaller than the area of the first electrode (21) located in the first area and the second area, and the first voltage is larger than the second voltage.

5. The display panel according to any one of claims 1 to 4, characterized in that, The display panel further includes a plurality of microlenses (40) and a filling layer (41). The plurality of microlenses (40) and the filling layer (41) are sequentially located on a side of the light-emitting functional layer (20) away from the display backplane (10). The refractive index of the plurality of microlenses (40) is greater than the refractive index of the filling layer (41). The plurality of microlenses (40) correspond to the plurality of light-emitting units one by one, and the orthographic projection of the plurality of microlenses (40) on the display backplane (10) at least partially coincides with the orthographic projection of the plurality of light-emitting units on the display backplane (10).

6. The display panel according to claim 5, wherein The refractive index of the plurality of microlenses (40) is 0.15 to 0.8 greater than the refractive index of the filling layer (41).

7. The display panel according to any one of claims 1 to 4 and claim 6, characterized in that, The display backplane (10) is a silicon-based driving backplane.

8. The display panel according to any one of claims 1 to 4 and claim 6, characterized in that, The display backplane (10) further includes a plurality of pixel driving circuits, and the plurality of pixel driving circuits are connected to the plurality of light-emitting units one by one; The plurality of pixel driving circuits include a first pixel driving circuit connected to the first light-emitting unit and a second pixel driving circuit connected to the second light-emitting unit. The first signal line (11a) is electrically connected to the first pixel driving circuit, and the second signal line (11b) is electrically connected to the second pixel driving circuit.

9. A manufacturing method of a display panel, characterized in that The method includes: Fabricating a display backplane having a first area, a splicing area, and a second area connected in sequence in a first direction; A light-emitting functional layer is fabricated on one side of the display backplane. Among them, the light-emitting functional layer includes a plurality of light-emitting units distributed in an array, and each light-emitting unit includes a first electrode. The distribution density of the light-emitting units in the first region, the distribution density of the light-emitting units in the splicing region, and the distribution density of the light-emitting units in the second region are the same; Among them, the display backplane includes a first signal line and a second signal line on the same layer. The first signal line is located in the splicing region, and the second signal line is located in the first region or the second region. The first signal line is used to control the brightness of a first light-emitting unit, and the first light-emitting unit is a light-emitting unit located in the splicing region among the plurality of light-emitting units. The second signal line is used to control the brightness of a second light-emitting unit, and the second light-emitting unit is a light-emitting unit located in the first region or the second region among the plurality of light-emitting units. The line width of the first signal line is different from the line width of the second signal line, and / or the area of the first electrode located in the splicing region is different from the area of the first electrodes located in the first region and the second region; The difference in brightness between the first light-emitting unit and the second light-emitting unit under the same driving conditions is within 15%.

10. A method for manufacturing a display panel, characterized in that, The method includes: Fabricating a display backplane, where the display backplane has a first region, a splicing region, and a second region connected in sequence in a first direction; A light-emitting functional layer is fabricated on one side of the display backplane. Among them, the light-emitting functional layer includes a plurality of light-emitting units distributed in an array, and each light-emitting unit includes a first electrode. The distribution density of the light-emitting units in the first region, the distribution density of the light-emitting units in the splicing region, and the distribution density of the light-emitting units in the second region are the same; Among them, the display backplane includes a first signal line and a second signal line on the same layer. The first signal line is located in the splicing region, and the second signal line is located in the first region or the second region. The first signal line and the second signal line are spaced apart from each other and the extending direction of both is the second direction, and the second direction intersects with the first direction. The first signal line is used to control the brightness of a first light-emitting unit, and the first light-emitting unit is a light-emitting unit located in the splicing region among the plurality of light-emitting units. The second signal line is used to control the brightness of a second light-emitting unit, and the second light-emitting unit is a light-emitting unit located in the first region or the second region among the plurality of light-emitting units. The line width of the first signal line is different from the line width of the second signal line, and the area of the first electrode of the first light-emitting unit is different from the area of the first electrode of the second light-emitting unit; The first signal line is configured to provide a first voltage to the first light-emitting unit, and the second signal line is configured to provide a second voltage to the second light-emitting unit, so that the difference in brightness between the first light-emitting unit and the second light-emitting unit is within 15%, and the magnitudes of the first voltage and the second voltage are different.

11. The manufacturing method according to claim 9 or 10, characterized in that, The fabricating of the display backplane includes: A first photoresist pattern is formed using a first mask (61), wherein the first mask (61) includes a first part (61a) and a second part (61b), and the first part (61a) and the second part (61b) are respectively used to form different parts of the first photoresist pattern in the first region and the splicing region; A second photoresist pattern is formed using a second mask (62), wherein the second mask (62) includes a third part (62a) and a fourth part (62b), and the third part (62a) and the fourth part (62b) are respectively used to form different parts of the second photoresist pattern in the splicing region and the second region, and at least a part of the second photoresist pattern and the first photoresist pattern in the splicing region overlap; Based on the first photoresist pattern and the second photoresist pattern, a wiring layer is formed, and the wiring layer includes the first signal line and the second signal line; Wherein, the width of the pattern of the second part (61b) is equal to the width of the pattern of the third part (62a), the width of the pattern of the second part (61b) is greater than the width of the pattern of the first part (61a), the width of the pattern of the second part (61b) is greater than the width of the pattern of the fourth part (62b), and the pattern is the region corresponding to the signal line.

12. The manufacturing method according to claim 9 or 10, characterized in that, Fabricating a light-emitting functional layer (20) on one side of the display backplane (10) includes: A third photoresist pattern is formed using a third mask (63), wherein the third mask (63) includes a fifth part (63a) and a sixth part (63b), and the fifth part (63a) and the sixth part (63b) are respectively used to form different parts of the third photoresist pattern in the first region and the splicing region; A fourth photoresist pattern is formed using a fourth mask (64), wherein the fourth mask (64) includes a seventh part (64a) and an eighth part (64b), and the seventh part (64a) and the eighth part (64b) are respectively used to form different parts of the fourth photoresist pattern in the splicing region and the second region; Based on the third photoresist pattern and the fourth photoresist pattern, a plurality of first electrodes are formed; Wherein, the pattern of the sixth part (63b) and the pattern of the seventh part (64a) are congruent figures, the pattern of the fifth part (63a) and the pattern of the eighth part (64b) are congruent figures, the area of the pattern of the sixth part (63b) is smaller than the area of the pattern of the fifth part (63a), and the pattern of the sixth part (63b) and the pattern of the fifth part (63a) are similar figures, and the pattern is the region corresponding to the first electrode (21).

13. A display device, characterized in that, The display device includes a power supply circuit and a display panel as described in any one of claims 1 to 8, and the power supply circuit supplies power to the display panel.

14. The display device according to claim 13, wherein The display device further includes a control circuit, which is electrically connected to the display panel as described in claim 3 or 4, and is configured to supply the first voltage to the first signal line and supply the second voltage to the second signal line.

15. A photomask, characterized in that, A film layer for manufacturing the display panel, where the display panel is the display panel according to any one of claims 1 to 8; The mask includes a connected first part (61a) and a second part (61b). The first part (61a) is used to manufacture the film layer of the first region or the second region, and the second part (61b) is used to manufacture the film layer of the splicing region; The sizes of the patterns in the pattern regions of the first part (61a) and the second part (61b) are different.

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