Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device. The array substrate comprises a plurality of pixel driving circuits. Each pixel driving circuit comprises a first transistor and a driving transistor. The array substrate comprises: a substrate; the semiconductor layer is located on one side of the substrate, and the semiconductor layer comprises a first active layer pattern; the first metal layer is located on the side, away from the substrate, of the semiconductor layer, the first metal layer comprises a first gate layer pattern, and the first gate layer pattern and the first active layer pattern are overlapped; the overlapped part is a first channel on the first active layer pattern, and the first transistor and the driving transistor share the first channel and the first gate layer pattern. According to the pixel driving circuit layout of the array substrate, space is saved, and the array substrate is suitable for being used in a display panel with high-density pixel arrangement.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to an array substrate, a display panel, and a display device. Background Art

[0002] Organic Light Emitting Display (OLED) has many advantages such as all-solid state, self-luminous, wide viewing angle, wide color gamut, fast response speed, high luminous efficiency, high brightness, high contrast ratio, ultra-thin, ultra-light, low power consumption, wide operating temperature range, large-size and flexible panel fabrication, and simple manufacturing process. It can achieve true flexible display and has broad development prospects. In recent years, it has attracted more and more attention in the market.

[0003] The organic light emitting display device lights up the light-emitting pixels through a pixel driving circuit to realize corresponding picture display. Figure 1 An equivalent schematic diagram of a pixel driving circuit is shown. In the prior art, according to Figure 1 The pixel driving circuit arranged on the display panel has a complex layout structure and requires a large layout space, making it impossible to further improve the pixel density of the display panel. Summary of the Invention

[0004] Aiming at the problems in the prior art, the purpose of the present invention is to provide an array substrate, a display panel, and a display device, which can save the layout space of the pixel driving circuit and are applicable to display panels with high pixel density.

[0005] An embodiment of the present invention provides an array substrate, including a plurality of pixel driving circuits. The pixel driving circuit includes a first transistor and a driving transistor. The array substrate includes:

[0006] A substrate;

[0007] A semiconductor layer, located on one side of the substrate. The semiconductor layer includes a first active layer pattern;

[0008] A first metal layer, located on the side of the semiconductor layer away from the substrate. The first metal layer includes a first gate layer pattern, and the first gate layer pattern overlaps with the first active layer pattern; the overlapping part is a first channel on the first active layer pattern;

[0009] The first transistor and the driving transistor share the first channel and the first gate layer pattern.

[0010] In some embodiments, the pattern of the first channel is in a shape of a "J".

[0011] In some embodiments, the first gate layer pattern includes a first pattern and a second pattern connected along a first direction, and an area of the first pattern is smaller than an area of the second pattern;

[0012] Wherein, the second pattern overlaps with a middle portion of the first active layer pattern, and the first pattern overlaps with a first end or a second end of the first active layer pattern.

[0013] In some embodiments, the pixel driving circuit further includes an initialization transistor, a data writing transistor, and a compensation transistor;

[0014] The semiconductor layer further includes a third active layer pattern of the initialization transistor, a fourth active layer pattern of the data writing transistor, and a fifth active layer pattern of the compensation transistor;

[0015] The first metal layer further includes a third gate layer pattern of the initialization transistor, a fourth gate layer pattern of the data writing transistor, and a fifth gate layer pattern of the compensation transistor;

[0016] Wherein, the third gate layer pattern overlaps with the third active layer pattern, the fourth gate layer pattern overlaps with the fourth active layer pattern; the fifth gate layer pattern overlaps with the fifth active layer pattern.

[0017] In some embodiments, the pixel driving circuit further includes a reset transistor, a first light-emitting control transistor, and a second light-emitting control transistor;

[0018] The semiconductor layer further includes a sixth active layer pattern of the reset transistor, a seventh active layer pattern of the first light-emitting control transistor, and an eighth active layer pattern of the second light-emitting control transistor;

[0019] The first metal layer further includes a sixth gate layer pattern of the reset transistor, a seventh gate layer pattern of the first light-emitting control transistor, and an eighth gate layer pattern of the second light-emitting control transistor;

[0020] Wherein, the sixth active layer pattern overlaps with the sixth gate layer pattern, the seventh active layer pattern overlaps with the seventh gate layer pattern, and the eighth active layer pattern overlaps with the eighth gate layer pattern.

[0021] In some embodiments, the pixel driving circuit further includes a storage capacitor;

[0022] The array substrate further includes a second metal layer on a side of the first metal layer away from the substrate; the second metal layer overlaps with the first gate layer pattern, and an overlapping portion of the first gate layer pattern and a vertical projection of the second metal layer on the substrate forms the storage capacitor.

[0023] In some embodiments, an overlapping area between the second metal layer and the first gate layer pattern is 120 μm 2 ~200 μm 2 。

[0024] In some embodiments, it further includes a third metal layer disposed along a first direction on a side of the second metal layer away from the substrate; the third metal layer includes a first scan signal line, a second scan signal line, and a third scan signal line;

[0025] The first scan signal line overlaps with a third gate layer pattern of the initialization transistor;

[0026] The second scan signal line overlaps with a fourth gate layer pattern of the write transistor and a fifth gate layer pattern of the compensation transistor;

[0027] The third scan signal line overlaps with a sixth gate layer pattern of the reset transistor.

[0028] In some embodiments, the third metal layer further includes an initialization voltage signal, a reset voltage signal line, and a first power supply voltage signal line; a third active layer pattern of the initialization transistor overlaps with the initialization voltage signal line;

[0029] The second metal layer overlaps with the first power supply voltage signal line;

[0030] A sixth active layer pattern of the reset transistor overlaps with the reset voltage signal line.

[0031] In some embodiments, it further includes a fourth metal layer disposed along a second direction on a side of the third metal layer away from the substrate.

[0032] In some embodiments, the fourth metal layer includes a data line and the first power supply voltage signal line; the data line overlaps with a fourth active layer pattern for data writing; the first power supply voltage signal line overlaps with the third metal layer.

[0033] An embodiment of the present invention further provides a display panel, including the array substrate as described above.

[0034] An embodiment of the present invention further provides a display device, including the display substrate as described above.

[0035] The array substrate, display panel, and display device provided by the present invention have the following advantages:

[0036] On the array substrate provided by the present invention, the layout space of the pixel driving circuit is small, and it can be applied to high pixel density panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Other features, objects, and advantages of the present invention will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0038] Figure 1 is an equivalent schematic diagram of a pixel driving circuit;

[0039] Figure 2 is a layout schematic diagram of a semiconductor layer and a first metal layer provided on the array substrate according to an embodiment of the present invention;

[0040] Figure 3 is a layout schematic diagram of a semiconductor layer and a first metal layer provided on the array substrate according to another embodiment of the present invention;

[0041] Figure 4 is a layout schematic diagram of the array substrate provided with a second metal layer according to an embodiment of the present invention;

[0042] Figure 5 is a layout diagram of the array substrate provided with a second metal layer according to another embodiment of the present invention;

[0043] Figure 6 is a partial enlarged view of the array substrate provided with a second metal layer according to another embodiment of the present invention;

[0044] Figure 7 is a layout schematic diagram of the array substrate provided with contact holes according to an embodiment of the present invention;

[0045] Figure 8 is a layout schematic diagram of the array substrate provided with a third metal layer according to an embodiment of the present invention;

[0046] Figure 9 is Figure 8 a cross-sectional schematic diagram taken along the cutting line AA' in

[0047] Figure 10 is Figure 8 a cross-sectional schematic diagram taken along the cutting line BB' in

[0048] Figure 11 is a layout schematic diagram of the array substrate provided with a fourth metal layer according to an embodiment of the present invention;

[0049] Figure 12 is Figure 11 a cross-sectional schematic diagram in the direction of the cutting line CC' in

[0050] Figure 13 is Figure 11 Schematic diagram of a cross-sectional view in the direction of the middle cutting line DD';

[0051] Figure 14 is Figure 11 Schematic diagram of a cross-sectional view in the direction of the middle cutting line EE';

[0052] Figure 15 It is a layout schematic diagram of an array substrate after setting a fourth metal layer provided by another embodiment of the present invention;

[0053] Figure 16 It is a layout schematic diagram of an array substrate after setting a fourth metal layer provided by another embodiment of the present invention.

[0054] Reference numerals:

[0055] 10 Substrate 73 Third insulating layer

[0056] 20 Buffer layer 74 Fourth insulating layer

[0057] 30 Semiconductor layer 75 Fifth insulating layer

[0058] 31 First active layer pattern 80 Fourth metal layer

[0059] 40 First metal layer T1 First transistor

[0060] 41 First gate layer pattern T2 Driving transistor

[0061] 41a First pattern T3 Initialization transistor

[0062] 41b Second pattern T4 Data writing transistor

[0063] 43 Third gate layer pattern T5 Compensation transistor

[0064] 44 Fourth gate layer pattern T6 Reset transistor

[0065] 45 Fifth gate layer pattern T7 First light-emitting control transistor

[0066] 46 Sixth gate layer pattern T8 Second light-emitting control transistor

[0067] 47 Seventh gate layer pattern Sn-1 First scan signal line

[0068] 48 Eighth gate layer pattern Sn Second scan signal line

[0069] 50 Second metal layer Sn+1 Third scan signal line

[0070] 51 Via for Vres reference voltage signal line

[0071] 60 Third metal layer for Data data line

[0072] 71 First insulating layer for ELVDD first power supply voltage signal line

[0073] 72 Second insulating layer for Vint initialization voltage signal line

[0074] En Emission control signal line Detailed implementation manners

[0075] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their repetitive description will be omitted. "Or" or "either...or" in the specification may mean "and" or "or".

[0076] The following specific examples illustrate the embodiments of the present application, and those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in the present application. The present application can also be implemented or applied through other different specific embodiments, and various details in the present application can also be modified or changed according to different viewpoints and application systems without departing from the spirit of the present application. It should be noted that, without conflict, the embodiments and features in the embodiments of the present application can be combined with each other.

[0077] To solve the problems in the prior art, an embodiment of the present invention provides an array substrate. Figure 1 An equivalent schematic diagram of a pixel driving circuit in the array substrate provided by the embodiment of the present invention is shown. The present application is based on Figure 1 the equivalent schematic diagram of the pixel driving circuit shown for layout design. As Figure 1 shown, the pixel driving circuit includes a first transistor T1, a driving transistor T2, an initialization transistor T3, a data writing transistor T4, a compensation transistor T5, a reset transistor T6, a first emission control transistor T7, and a second emission control transistor T8.

[0078] The first transistor T1 and the driving transistor T2 are turned on and off in response to the potential of the second node n2; the control terminals of the first transistor T1 and the driving transistor T2 are electrically connected to the second node n2.

[0079] The initialization transistor T3 responds to the first scan signal to transfer an initialization voltage to the second node n2. The first end of the initialization transistor T3 is electrically connected to the initialization voltage signal line Vint, the second end of the initialization transistor T3 is electrically connected to the second node n2, and the control end of the initialization transistor T3 is electrically connected to the first scan signal line Sn-1.

[0080] The data write transistor T4 and the compensation transistor T5 respond to the second scan signal to transfer a data voltage and the threshold voltage Vth of the first transistor T1 to the second node n2 and store them in the storage capacitor Cs. The control end of the data write transistor T4 is electrically connected to the second scan signal line Sn, the first end of the data write transistor T4 is electrically connected to the data line Data, and the second end of the data write transistor T4 is electrically connected to the first end of the first transistor T1. The control end of the compensation transistor T5 is electrically connected to the second scan signal line Sn, the first end of the compensation transistor T5 is electrically connected to the second end of the first transistor T1, and the second end of the compensation transistor T5 is electrically connected to the second node n2. Since the sizes of the first transistor T1 and the driving transistor T2 are exactly the same, the threshold voltage of the driving transistor T2 is the same as the threshold voltage of the first transistor T1. The first plate of the storage capacitor Cs is electrically connected to the second node n2, and the second plate of the storage capacitor Cs is electrically connected to the first power supply voltage signal line ELVDD.

[0081] The reset transistor T6 responds to the third scan signal to write a reference voltage to the first end of the light-emitting element OLED to reset the potential of the first end of the light-emitting element OLED. The control end of the reset transistor T6 is electrically connected to the third scan signal line Sn+1, the first end of the reset transistor T6 is electrically connected to the reset voltage signal line Vres, and the second end of the reset transistor T6 is electrically connected to the anode of the light-emitting element. Here, the anode of the light-emitting element OLED is the anode of the light-emitting element.

[0082] The first light-emitting control transistor T7 and the second light-emitting control transistor T8 respond to the light-emitting control signal to drive the light-emitting element OLED to emit light. The control end of the first light-emitting control transistor T7 is electrically connected to the light-emitting control signal line En, the first end of the first light-emitting control transistor T7 is electrically connected to the first power supply voltage signal line ELVDD, and the second end of the first light-emitting control transistor T7 is electrically connected to the first end of the driving transistor T2. The control end of the second light-emitting control transistor T8 is electrically connected to the light-emitting control signal line En, the first end of the second light-emitting control transistor T8 is electrically connected to the second end of the driving transistor T2, and the second end of the second light-emitting control transistor T8 is electrically connected to the anode of the light-emitting element OLED.

[0083] It should be noted that in the circuit provided by the embodiments of the present application, the nodes do not represent actual existing components, but represent the convergence points of relevant electrical connections in the circuit diagram. That is to say, these nodes are nodes equivalent to the convergence points of relevant electrical connections in the circuit diagram. The control end of the transistor refers to the gate of the transistor, the first end of the transistor refers to one of the source or drain of the transistor, and the second end of the transistor refers to the other of the source or drain. The transistor includes a P-type transistor and an N-type transistor. In this embodiment, the P-type transistor is taken as an example for illustration.

[0084] The array substrate provided by the embodiments of the present invention includes a plurality of pixel driving circuits. However, only the layout of one pixel driving circuit is taken as an example here to introduce the present invention in detail. The layouts of the remaining pixel driving circuits can be any of those introduced in the following embodiments.

[0085] Figures 2 to 16 Shows Figure 1 The layout design of each layer of the pixel driving circuit in and the schematic cross-sectional structure of some positions thereof. Combining Figures 2 to 16 It can be obtained that the array substrate provided by the embodiments of the present invention includes a substrate 10, and the pixel driving circuit is located on one side of the substrate 10; the pixel driving circuit includes a first transistor T1 and a driving transistor T2. The array substrate includes a semiconductor layer 30, which is located on one side of the substrate 10. The semiconductor layer 30 includes a first active layer pattern 31; a first metal layer 40, which is located on the side of the semiconductor layer 30 away from the substrate 10. The first metal layer 40 includes a first gate layer pattern 41. The first gate layer pattern 41 and the first active layer pattern 31 overlap in the vertical projection on the substrate 10, and the overlapping part in the first active layer pattern 31 is the first channel; the first transistor T1 and the driving transistor T2 share the first channel and the first gate layer pattern 41.

[0086] By making the first transistor T1 and the driving transistor T2 share the channel and the gate, the layout space of the pixel driving circuit is saved, which is beneficial to the use in a display panel with a high pixel density.

[0087] It should be noted that here the first metal layer 40 is the gate of the transistor formed in the pixel driving circuit, and the semiconductor layers on both sides of the channel are the source or drain of the transistor formed in the pixel driving circuit.

[0088] Exemplarily, the material of the semiconductor layer 30 is low-temperature polysilicon, but it is not limited thereto. As Figure 9 、 Figure 10 、 Figure 12 And Figure 14 Shown, a buffer layer 20 is further provided between the substrate 10 and the semiconductor layer 30 to enable good contact between the substrate 10 and the semiconductor layer 30.

[0089] In this embodiment, the first channels of the first transistor T1 and the driving transistor T2 are in a zigzag pattern, that is, the channels of the first transistor T1 and the driving transistor T2 are bent. Since the emission brightness of the light-emitting element in the pixel is related to the driving current generated by the driving transistor, and the driving current is controlled by the data signal transmitted by the data line, increasing the channel length of the driving transistor T2 can increase the data voltage range of the data signal and improve the control ability of the driving transistor T2 over the light emission of the light-emitting element, thereby improving the display effect of the display panel. When in some high-PPI products, the pixel layout space is narrow and not sufficient to achieve a sufficiently long channel, the above-mentioned bent channel can be adopted to increase the channel length to meet the channel length requirement. Please refer to Figure 1 and Figure 2 As shown in the white line part, the first channel is designed to be bent, further lengthening the charging path and the light-emitting path. Among them, according to Figure 1 and Figure 2 it can be obtained that the path from the data writing transistor T4, the first transistor T1, the compensation transistor T5 to the second node n2 is the charging path. The path from the first light-emitting control transistor T7, the driving transistor T2 to the second light-emitting control transistor T8 is the light-emitting path.

[0090] Please continue to refer to Figure 2 , the first gate layer pattern 41 includes a first pattern 41a and a second pattern 42b connected along the first direction, and the area of the first pattern 41a is smaller than the area of the second pattern 41b; the orthographic projection shape of the first gate layer pattern 41 on the substrate 10 is a flag shape. In some embodiments, the first gate layer pattern 41 only includes the second pattern 41b, while in this embodiment, adding the first pattern 41a to extend the area of the first gate layer pattern 41 can increase the area of the storage capacitor Cs set subsequently, reduce the change amount of the gate potential of the driving transistor T2 caused by leakage, and improve the voltage stabilization effect.

[0091] As Figure 2 and Figure 3 shown, wherein, the second pattern 41b overlaps with the middle part of the first active layer pattern 31, and the first pattern 41a overlaps with the first end or the second end of the first active layer pattern 31, that is, the first gate layer pattern 41 is disposed to be biased to the left or right of the first active layer pattern 31. At this time, the first transistor T1 and the driving transistor T2 can also be regarded as a four-terminal device. Exemplarily, as Figure 2As shown, the four-terminal device includes a first terminal n1, a second terminal n2 (i.e., the second node), a third terminal n3, and a fourth terminal n4. The first terminal n1 and the fourth terminal n4 can be regarded as the source electrodes of the four-terminal device, the second terminal n2 can be regarded as the gate electrode of the four-terminal device, and the third terminal n3 can be regarded as the drain electrode of the four-terminal device. During use, it can be considered that the gate electrode, the source electrode, and one of the drain electrodes of the four-terminal device are used, and the other drain electrode is floating to achieve the conduction function of the thin-film transistor.

[0092] As Figure 3 shown, in another embodiment, the first pattern 41a overlaps with the second end of the first active layer pattern 31. At this time, the first transistor T1 and the driving transistor T2 can also be regarded as a four-terminal device. The four-terminal device includes a first terminal n1, a second terminal n2, a third terminal n3, and a fourth terminal n4. The first terminal n1 and the fourth terminal n4 can be regarded as the drain electrodes, the second terminal n2 can be regarded as the gate electrode, and the third terminal n3 can be regarded as the source electrode.

[0093] Please continue to refer to Figure 2 and Figure 3 , the pixel driving circuit further includes an initialization transistor T3, a data writing transistor T4, and a compensation transistor T5; the semiconductor layer 30 further includes a third active layer pattern of the initialization transistor T3, a fourth active layer pattern of the data writing transistor T4, and a fifth active layer pattern of the compensation transistor T5;

[0094] The first metal layer 40 further includes a third gate layer pattern 43 of the initialization transistor T3, a fourth gate layer pattern 44 of the data writing transistor T4, and a fifth gate layer pattern 45 of the compensation transistor T5. The third gate layer pattern 43 overlaps with the vertical projection of the third active layer pattern on the substrate 10, and the overlapping part is the channel of the initialization transistor T3; the fourth gate layer pattern 44 overlaps with the vertical projection of the fourth active layer pattern on the substrate 10, and the overlapping part is the channel of the data writing transistor T4; the fifth active layer pattern overlaps with the vertical projection of the fifth gate layer pattern 45 on the substrate 10, and the overlapping part is the channel of the compensation transistor T5.

[0095] The third gate layer pattern 43 of the initialization transistor T3 has two non-connected overlapping parts with the third active layer pattern. The design of the third gate layer pattern 43 and the third active layer pattern of the initialization transistor T3 is equivalent to designing the initialization transistor T3 as a double-gate transistor, that is, the initialization transistor T3 includes a first sub-transistor T3a and a second sub-transistor T3b.

[0096] The fifth gate layer pattern 45 of the compensation transistor T5 has two non - connected overlapping portions with the fifth active layer pattern. The design of the fifth gate layer pattern 45 and the fifth active layer pattern of the compensation transistor T5 is equivalent to designing the compensation transistor T5 as a double - gate transistor, that is, the compensation transistor T5 includes a third sub - transistor T5a and a fourth sub - transistor T5b.

[0097] Furthermore, the pixel driving circuit further includes a reset transistor T6, a first light - emitting control transistor T7, and a second light - emitting control transistor T8; then the semiconductor layer 30 further includes a sixth active layer pattern of the reset transistor T6, a seventh active layer pattern of the first light - emitting control transistor T7, and an eighth active layer pattern of the second light - emitting control transistor T8;

[0098] The first metal layer 40 further includes a sixth gate layer pattern 46 of the reset transistor T6, a seventh gate layer pattern 47 of the first light - emitting control transistor T7, and an eighth gate layer pattern 48 of the second light - emitting control transistor T8;

[0099] Among them, the vertical projection of the sixth active layer pattern and the sixth gate layer pattern 46 on the substrate 10 has an overlap, and the overlapping portion is the channel of the reset transistor T6; the vertical projection of the seventh active layer pattern and the seventh gate layer pattern 47 on the substrate 10 has an overlap, and the overlapping portion is the channel of the first light - emitting control transistor T7; the vertical projection of the eighth active layer pattern and the eighth gate layer pattern 48 on the substrate 10 has an overlap, and the overlapping portion is the channel of the second light - emitting control transistor T8.

[0100] In this embodiment, the seventh gate layer pattern 47 is connected to the eighth gate layer pattern 48, which is equivalent to the light - emitting control signal line En and can realize the transmission of the light - emitting control signal.

[0101] Please continue to refer to Figure 2 , on the semiconductor layer 30 where the fifth active layer pattern of the compensation transistor T5, the first active layer pattern of the first transistor T1 and the driving transistor T2, and the eighth active layer pattern of the second light - emitting control transistor T8 are connected, it is designed as a stepped structure (shown by the oval dotted line frame), which can reduce the parasitic capacitance of this section of the semiconductor, reduce the charging difficulty; reduce the light - irradiated area of the semiconductor layer, reduce the influence of the photo - generated carrier effect on the drain node of the compensation / or driving transistor, and weaken the current change caused by the potential fluctuation.

[0102] As Figure 9 and Figure 10 shown, a first insulating layer 71 is provided between the semiconductor layer 30 and the first metal layer 40. The first insulating layer 71 can be made of silicon oxide (SiO2). The first insulating layer 71 is not shown in the layout design.

[0103] As Figure 4 and Figure 10As shown, in one embodiment, the array substrate further includes a second metal layer 50 on a side of the first metal layer 40 away from the substrate 10; the second metal layer 50 overlaps a vertical projection of the first gate layer pattern 41 on the substrate 10, and an overlapping portion of the second metal layer 50 and the vertical projection of the first gate layer pattern 41 on the substrate 10 forms a storage capacitor Cs, that is, the first gate layer pattern 41 is the first electrode plate of the storage capacitor Cs, and the second metal layer 50 is the second electrode plate of the storage capacitor Cs. In some embodiments, an overlapping area of the second metal layer 50 and the first gate layer pattern 41 is 120μm 2 ~200μm 2 .

[0104] Please continue to refer to Figure 4 , the area of the second metal layer 50 is not limited to only overlapping with the first gate layer pattern 41. See Figure 4 the dashed box in, the second metal layer 50 also overlaps a vertical projection of the third active layer pattern of the initialization transistor T3, the fifth active layer pattern of the compensation transistor T5, the fourth active layer pattern of the data writing transistor T4, the seventh active layer pattern of the first light-emitting control transistor T7, and the eighth active layer pattern of the second light-emitting control transistor T8 on the substrate 10. The second metal layer 50 shields the semiconductor layer, can shield the influence of other node voltage changes and pulse signal voltage transitions on the potential of the shielded semiconductor layer through the capacitive coupling effect. On the other hand, it can block light and avoid the change of the carrier concentration of the semiconductor layer caused by light incidence, thereby affecting the potential of this section of the semiconductor layer.

[0105] As Figure 5 shown, in another embodiment, the second metal layer 50 also shields a part of the semiconductor layer of other transistors, as shown in Figure 5 the dashed square box in Figure 5 Compared with Figure 4 the second metal layer 50 in, the difference is that the area of the second metal layer 50 increases and covers a larger area of the semiconductor layer. Compared with Figure 4 the second metal layer 50 shown Figure 5 the area of the second metal layer 50 in further increases, that is, the shielding area increases, which can better weaken the influence of pulse signal voltage transitions and other node potential couplings on the lower electrode plate (i.e., the first gate layer pattern 41) of the capacitor, and reduce the gate voltage fluctuation and current fluctuation of the pixel driving circuit in the compensation stage and the light-emitting stage.

[0106] A portion of the second metal layer 50 shields the semiconductor layer of the driving transistor T2, where the source electrode of the driving transistor T2 can be shielded to weaken the influence of voltage changes at other nodes and pulse signal transitions on the source electrode potentials of the driving transistor T2 and the compensation transistor T5. According to the MOSFET current formula, the current I of a transistor is proportional to (Vgs - Vth). 2 , according to the formula, shielding the source electrode of the transistor is beneficial to the stability of the compensation current of the compensation transistor T5 and the emission current of the driving transistor T2.

[0107] As Figure 6 shown, in another embodiment, the overlapping area of the second metal layer 50 and the semiconductor layer 30 in the second metal layer 50 compared to the design in Figure 5 is relatively reduced, and the reduction in the area of the second metal layer 50 reduces the parasitic capacitance generated by the second metal layer 50 to other signals, especially reduces the parasitic capacitance of the scan line and the data line, thereby reducing the delay of Tr (rise time) and Tf (fall time) during signal transmission and improving the display uniformity of the panel.

[0108] As Figure 4 , Figure 5 , Figure 6 and Figure 10 shown, a via hole 51 is provided on the first electrode plate of the storage capacitor Cs. The via hole 51 is opposite to the first gate layer pattern 41. The length of the via hole 51 is denoted as m, and the width is denoted as n, satisfying: m ≥ 1.5 μm, n ≥ 1.5 μm, so as to weaken the potential fluctuation generated by the capacitive coupling effect received by the second electrode plate of the storage capacitor Cs, that is, the gate of the driving transistor T2.

[0109] As Figure 10 shown, a second insulating layer 72 is provided between the first metal layer 40 and the second metal layer 50. Among them, the overlapping portion (shown by the dotted line box in the figure) of the projections of the first metal layer 40 and the second metal layer 50 on the substrate 10 forms the storage capacitor Cs; the dielectric constant of the second insulating layer 72 is greater than that of the first insulating layer 71. Further, please refer to Figure 10 , a third insulating layer 73 is further provided on the side of the second metal layer 50 away from the substrate 10. The second insulating layer 72 and the third insulating layer 73 are not shown in the layout design either.

[0110] As Figure 7As shown, the pixel driving circuit further includes a plurality of contact holes (shown in the dotted box in the figure), which are disposed on each insulating layer. By providing contact holes on each insulating layer, the semiconductor layer or each metal layer is exposed, and subsequently, the semiconductor layer and each metal layer are electrically connected to the signal line to provide an electrical signal to the semiconductor layer and the metal layer. It should be noted that the planar layout diagram only shows the functional layers included in the array substrate. The functional layers include a semiconductor layer, a first metal layer, a second metal layer, etc. In practice, adjacent two functional layers need to be separated by an insulating layer. Therefore, an insulating film is provided between adjacent functional layers in practice.

[0111] As Figures 8 to 10 shown, the pixel driving circuit further includes a third metal layer 60 disposed along a first direction, and the third metal layer 60 is located on a side of the second metal layer 50 away from the substrate 10. In this embodiment, the first direction is the left-right direction as seen from the paper surface, that is, the horizontal direction. The resistivity of the third metal layer 60 is less than that of the first metal layer 40 and the second metal layer 50. By using the third metal layer 60 to transmit the horizontal scanning signal, the impedance of the scanning signal can be reduced, and the delay of the voltage rise and fall caused by RC Loading (capacitive resistance load) during the circuit transmission process of the signal can be reduced.

[0112] As Figure 8As shown, the third metal layer 60 includes a first scan signal line Sn-1, a second scan signal line Sn, a third scan signal line Sn+1, source / drain electrodes of a data writing transistor T4, source / drain electrodes of a compensation transistor T5, source / drain electrodes of a first light-emitting control transistor T7, source / drain electrodes of a second light-emitting control transistor T8, a first power supply voltage signal line ELVDD, an initialization voltage signal line Vint, and a reset voltage signal line Vres. Among them, the first scan signal line Sn-1 overlaps with a third gate layer pattern 43 of an initialization transistor T3, and the first scan signal line Sn-1 is electrically connected to the third gate layer pattern 43 through a contact hole; the second scan signal line Sn overlaps with a fourth gate layer pattern 44 of a writing transistor T4 and a fifth gate layer pattern 45 of a compensation transistor T5, and the second scan signal line Sn is electrically connected to the fourth gate layer pattern 44 and the fifth gate layer pattern 45 through contact holes; the third scan signal line Sn+1 overlaps with a sixth gate layer pattern 46 of a reset transistor T6, and the third scan signal line Sn+1 is electrically connected to the sixth gate layer pattern 46 through a contact hole; a third active layer pattern of the initialization transistor T3 overlaps with the initialization voltage signal line Vint, and the initialization voltage signal line Vint is electrically connected to the third active layer pattern through a contact hole; the second metal layer 50 overlaps with the first power supply voltage signal line ELVDD, and the first power supply voltage signal is electrically connected to the second metal layer 50 and one end of a seventh active layer pattern of the first light-emitting control transistor T7 through a contact hole; the source / drain electrodes of the data writing transistor T4 overlap with a fourth active layer pattern of the data writing transistor T4; the source / drain electrodes of the compensation transistor T5 overlap with a fifth active layer pattern of the compensation transistor T5, and the source / drain electrodes of the compensation transistor T5 are electrically connected to the first gate layer pattern 41; the source / drain electrodes of the first light-emitting control transistor T7 overlap with an active layer pattern of the first light-emitting control transistor T7, and the source / drain electrodes of the first light-emitting control transistor T7 are electrically connected to one end of the active layer of the first light-emitting control transistor T7.

[0113] In some other embodiments, the initialization voltage signal line Vint and the reset voltage signal line Vres can be semiconductor layers. When the initialization voltage signal line Vint and the reset voltage signal line Vres are semiconductor layers, as Figure 2 and Figure 3 shown, they can be arranged on the same layer as the semiconductor layer 30. When the initialization voltage signal line Vint and the reset voltage signal line Vres are semiconductor layers, the resistance of the semiconductor layer is large, and the ESD resistance effect is good. During the process preparation, static electricity is easily transmitted along the metal or semiconductor layer. The larger the resistance, the easier it is to eliminate the influence of static electricity. The longer the propagation path, the easier it is for the static charge to be dispersed, preventing charge accumulation and breakdown.

[0114] The first power supply voltage signal line ELVDD is horizontally and parallelly connected to the second metal layer 50 to transmit the first power supply voltage signal, which helps to reduce the voltage drop (IR Drop) during signal transmission and improve the panel current uniformity.

[0115] Preferably, the thickness of the third insulating layer 73 is greater than the sum of the thicknesses of the first insulating layer 71 and the second insulating layer 72. The increase in the thickness of the third insulating layer 73 can reduce the parasitic capacitance on the signal line and the risk of electrostatic shock. Because the signal line connects multiple transistors in series to form a complete circuit except for the light-emitting element, and there are many stacked layers below, it can avoid serious electrostatic damage during the process due to the insufficient thickness of the third insulating layer 73.

[0116] In another embodiment, the third insulating layer 73 can be a double-layer insulating layer. The third insulating layer 73 includes a first sub-insulating layer and a second sub-insulating layer. The first sub-insulating layer has the same material as the second insulating layer 72, which can avoid the second insulating layer 72 being affected by lattice matching stress and thermal matching stress and thus affecting the stability of the storage capacitor Cs. The dielectric constant of the material of the first sub-insulating layer is relatively small, which can relatively reduce the parasitic capacitance between the third metal layer 60, the second metal layer 50, and the semiconductor layer 30.

[0117] As Figures 11 to 16 shown, the pixel driving circuit further includes a fourth metal layer 80 and a fourth insulating layer 74. The fourth metal layer 80 is arranged on the side of the substrate 10 away from the third insulating layer 73 along the second direction, and the fourth insulating layer 74 is arranged on the side of the fourth metal layer 80 away from the substrate 1. Here, the second direction is the up-and-down direction as seen in the paper surface, that is, the longitudinal direction. As Figure 11 shown, the fourth metal layer 80 includes a data line Data and a first power supply voltage signal line ELVDD (longitudinal). Figure 12 Shows Figure 11 the cross-sectional schematic diagram taken along the section line CC'. As Figure 12 shown, in some embodiments, the size of the contact hole formed on the fourth insulating layer 74 is larger than the size of the contact hole formed on the third insulating layer 73. The fourth insulating layer 74 can be an organic layer, and the setting of the contact hole on the organic layer can be obtained through exposure and development. The large size of the contact hole on the organic layer can ensure complete opening. The contact hole on the third insulating layer 73 is an inorganic layer, so the third insulating layer 73 can be obtained through a process. The small size of the contact hole on the inorganic insulating layer can save space.

[0118] Please continue to refer to Figure 11, the second metal layer 50 overlaps with the fourth active layer pattern on the data writing transistor T4 (see the dashed box). Here, the second metal layer 50 can block the semiconductor layer on the data writing transistor T4, and can attract more power on the data line Data and the second scan signal line Sn to the signal line of the fourth metal layer 80 for transmitting the first power supply voltage signal (vertically), enhancing the shielding effect on the data line Data and the second scan signal line Sn, and weakening the influence of the two pulse signals on the potential of other nodes in the circuit.

[0119] Figure 13 shows Figure 11 a cross-sectional schematic view taken along the section line DD’ in Figure 13 As shown, a fifth insulating layer 75 is provided on the side away from the fourth metal layer 80. In some embodiments, the fifth insulating layer 75 can be an organic layer and can play a planarizing role. A contact hole is opened in the fourth insulating layer 74 to expose the first power supply voltage signal line ELVDD (vertically) below the contact hole, so that the first power supply voltage signal line ELVDD (horizontally) provided on the fourth insulating layer 74 forms a contact with the source-drain electrodes of the first light-emitting control transistor T7 through the contact hole, that is, the source-drain electrodes of the first light-emitting control transistor T7 are electrically connected to the first power supply voltage signal line ELVDD.

[0120] The setting of the longitudinal signal transmission line can transmit the first power supply voltage signal in both horizontal and vertical directions, improving the uniformity of the panel during the initialization process; the longitudinal signal line covers part or all of the left semiconductor, which can reduce the influence of light incidence on the carrier concentration of the semiconductor layer in its area and reduce the drain potential fluctuation caused by the photo-generated carrier effect.

[0121] As Figure 11 and Figure 14 shown, the fourth metal layer 80 further includes an anode (Anode) signal transmission layer, which is electrically connected to the source-drain electrodes of the second light-emitting control transistor T8 through a contact hole. It should be noted that the contact hole provided on the anode signal transmission layer and the contact hole of the source-drain electrodes of the second light-emitting control transistor T8 are staggered in the thickness direction of the substrate 10.

[0122] As Figure 15 shown, in another embodiment, the fourth metal layer 80 further includes an initialization voltage signal line Vint. The initialization voltage signal line Vint in the fourth metal layer 80 is arranged longitudinally and is connected to the horizontally-wired initialization voltage signal line Vint by forming a contact hole in the fourth insulating layer 74. The initialization voltage signal line Vint is designed as a horizontal and vertical mesh-like interleaved structure to improve the uniformity of the panel during the anode reset process. In some other embodiments, the reset voltage signal line Vres can also be designed as a horizontal and vertical mesh-like interleaved structure.

[0123] As shown Figure 16 in FIG. 4, the fourth metal layer 80 further includes a second power supply voltage signal line ELVSS that transmits a second power supply voltage signal. The second power supply voltage signal line ELVSS is not connected to any signal line below it, and is used to reduce the IR Drop (voltage drop) of the ELVSS signal and improve the current uniformity of the panel. In some other embodiments, the fourth metal layer 80 may also be other signal lines and is not electrically connected to the signal lines below it, and those skilled in the art can make specific settings according to actual needs.

[0124] In a complete pixel, it includes Figure 11 , Figure 15 and Figure 16 any one of the pixel circuits shown or a combination thereof.

[0125] An embodiment of the present invention further provides a display panel, including the above-described array substrate, and all technical effects of the above-described array substrate can be achieved, which will not be elaborated here.

[0126] An embodiment of the present invention further provides a display device, including the above-described array substrate, and all technical effects of the above-described array substrate can be achieved, which will not be elaborated here. The display device can be a mobile phone, a computer, a camera, a watch, a video camera, a projector, a billboard, an automotive display, etc.

[0127] The display panel and the display device provided by the present invention have the following advantages:

[0128] The array substrate includes a plurality of pixel driving circuits, and the pixel driving circuit includes a first transistor and a driving transistor; the array substrate includes a substrate, a semiconductor layer, and a first metal layer; wherein, the semiconductor layer is located on one side of the substrate, and the semiconductor layer includes a first active layer pattern; the first metal layer is located on the side of the semiconductor layer away from the substrate, and the first metal layer includes a first gate layer pattern, and the first gate layer pattern overlaps with the first active layer pattern; the overlapping part is a first channel in the first active layer pattern; the first transistor and the driving transistor share the first channel and the first gate layer pattern. The layout of the pixel driving circuit of the array substrate provided by the present invention saves space and is applicable to display panels with high-density pixel arrangements.

[0129] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. An array substrate, characterized in that, It includes multiple pixel driving circuits, and each pixel driving circuit includes a first transistor and a driving transistor; The array substrate includes: A substrate; A semiconductor layer located on one side of the substrate, and the semiconductor layer includes a first active layer pattern; A first metal layer located on the side of the semiconductor layer away from the substrate. The first metal layer includes a first gate layer pattern, and the first gate layer pattern overlaps with the first active layer pattern. The overlapping part on the first active layer pattern is a first channel; The first transistor and the driving transistor share the first channel and the first gate layer pattern.

2. The array substrate according to claim 1, wherein The pattern of the first channel is in a shape like the Chinese character 'ji'.

3. The array substrate according to claim 2, wherein The first gate layer pattern includes a first pattern and a second pattern connected in a first direction, and the area of the first pattern is smaller than that of the second pattern; Wherein, the second pattern overlaps with the middle part of the first active layer pattern, and the first pattern overlaps with the first end or the second end of the first active layer pattern.

4. The array substrate according to claim 3, wherein, The pixel driving circuit further includes an initialization transistor, a data writing transistor, and a compensation transistor; The semiconductor layer further includes a third active layer pattern of the initialization transistor, a fourth active layer pattern of the data writing transistor, and a fifth active layer pattern of the compensation transistor; The first metal layer further includes a third gate layer pattern of the initialization transistor, a fourth gate layer pattern of the data writing transistor, and a fifth gate layer pattern of the compensation transistor; Wherein, the third gate layer pattern overlaps with the third active layer pattern, the fourth gate layer pattern overlaps with the fourth active layer pattern; and the fifth gate layer pattern overlaps with the fifth active layer pattern.

5. The array substrate according to claim 4, wherein The pixel driving circuit further includes a reset transistor, a first light-emitting control transistor, and a second light-emitting control transistor; The semiconductor layer further includes a sixth active layer pattern of the reset transistor, a seventh active layer pattern of the first light-emitting control transistor, and an eighth active layer pattern of the second light-emitting control transistor; The first metal layer further includes a sixth gate layer pattern of the reset transistor, a seventh gate layer pattern of the first light-emitting control transistor, and an eighth gate layer pattern of the second light-emitting control transistor; Wherein, the sixth active layer pattern overlaps with the sixth gate layer pattern, the seventh active layer pattern overlaps with the seventh gate layer pattern, and the eighth active layer pattern overlaps with the eighth gate layer pattern.

6. The array substrate according to claim 5, wherein The pixel driving circuit further includes a storage capacitor; The array substrate further includes a second metal layer located on the side of the first metal layer away from the substrate; the second metal layer overlaps with the first gate layer pattern, and the overlapping part of the first gate layer pattern and the vertical projection of the second metal layer on the substrate forms the storage capacitor.

7. The array substrate according to claim 6, wherein The overlapping area of the second metal layer and the first gate layer pattern is 120 μm 2 to 200 μm 2 .

8. The array substrate according to claim 7, wherein It further includes a third metal layer arranged in the first direction and located on the side of the second metal layer away from the substrate; the third metal layer includes a first scan signal line, a second scan signal line, and a third scan signal line; The first scan signal line overlaps with the third gate layer pattern of the initialization transistor; The second scanning signal line overlaps with the fourth gate layer pattern of the writing transistor and the fifth gate layer pattern of the compensation transistor; The third scanning signal line overlaps with the sixth gate layer pattern of the reset transistor.

9. The array substrate according to claim 8, wherein The third metal layer further includes an initialization voltage signal line, a reset voltage signal line, and a first power supply voltage signal line; The third active layer pattern of the initialization transistor overlaps with the initialization voltage signal line; The second metal layer overlaps with the first power supply voltage signal line; The sixth active layer pattern of the reset transistor overlaps with the reset voltage signal line.

10. The array substrate according to claim 9, wherein It further includes a fourth metal layer arranged along the second direction, located on a side of the third metal layer away from the substrate.

11. The array substrate according to claim 10, characterized in that, The fourth metal layer includes a data line and the first power supply voltage signal line; the data line overlaps with the fourth active layer pattern of the data writing transistor; the first power supply voltage signal line overlaps with the third metal layer.

12. A display panel, characterized in that, It includes the array substrate according to any one of claims 1 to 11.

13. A display device, characterized in that, It includes the array substrate according to any one of claims 1 to 11.

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