Display panel and display equipment

Abstract

The embodiment of the invention discloses a display panel and display equipment, the display panel comprises a common electrode arranged in a display area, and a first common signal line and a second common signal line which are arranged in a non-display area, and the first common signal line and the second common signal line are both connected with the common electrode. A feedback line is arranged in each of the middle-end region and the far-end region of the second common signal line to form a multi-region feedback mechanism to improve the detection accuracy of the common electrode, and then the compensation lines of the middle-end region and the far-end region of the second common signal line are utilized to perform accurate compensation, namely, according to the feedback mechanism of the far-end region, the detection accuracy of the common electrode is improved. The far end of the common electrode is subjected to potential compensation through the compensation line of the far-end area, and the middle end of the common electrode can be subjected to potential compensation through the compensation line of the middle-end area according to the feedback mechanism of the middle-end area, so that the potential stability of the common electrode is improved.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] In a liquid crystal display panel with a conventional VA structure, a pixel electrode includes a main pixel electrode and a sub-pixel electrode, and the sub-pixel requires a common electrode trace for voltage division. However, the potential of the common electrode trace is easily coupled and crosstalk occurs, making the potential of the common electrode trace unstable. Summary of the Invention

[0003] Embodiments of this application provide a display panel and a display device, which can improve the stability of the potential of the common electrode structure.

[0004] An embodiment of this application provides a display panel, including a display area and a non-display area. The non-display area is located on the periphery of the display area. The non-display area includes a first area and a second area arranged along a second direction and oppositely disposed across the display area. The first area has a bonding area configured to bond a circuit board. The display panel includes an array substrate, and the array substrate includes:

[0005] A common electrode, disposed in the display area;

[0006] A first common signal line, disposed in the first area, and the first common signal line is connected to one side of the common electrode close to the first area;

[0007] A second common signal line, disposed in the non-display area and extending along the outer peripheral direction of the display area. The second common signal line includes a proximal area close to the first area, a distal area close to the second area, and a middle area between the proximal area and the distal area;

[0008] Two first functional lines, in a first direction intersecting with the second direction, the two first functional lines are spaced apart from each other by the display area. One first functional line is connected to one side of the second common signal line in the middle area, and the other first functional line is connected to the other side of the second common signal line in the middle area; and

[0009] Two second functional lines, in the first direction, the two second functional lines are spaced apart from each other by the display area. One second functional line is connected to one side of the second common signal line in the distal area, and the other second functional line is connected to the other side of the second common signal line in the distal area;

[0010] Among them, one of the two first function lines is a first compensation line, and the other is a first feedback line; one of the two second function lines is a second compensation line, and the other is a second feedback line.

[0011] Optionally, in some embodiments of the present application, the non-display area further includes a third area and a fourth area arranged along the first direction and relatively arranged apart from the display area, the second common signal line includes a first sub-line, a second sub-line and a third sub-line, the first sub-line is arranged in the third area, the second sub-line is arranged in the second area, the third sub-line is arranged in the fourth area, one end of the second sub-line is connected to the first sub-line, and the other end of the second sub-line is connected to the third sub-line;

[0012] One of the two first functional lines is arranged in the third area and connected to the first sub-line, and the other is arranged in the fourth area and connected to the third sub-line; one of the two second functional lines is arranged in the third area and connected to the first sub-line or the second sub-line, and the other is arranged in the fourth area and connected to the third sub-line or the second sub-line.

[0013] Optionally, in some embodiments of the present application, the array substrate further includes a first connecting line extending along the first direction and located in the first area, and a pixel electrode located in the display area, the pixel electrode includes a main pixel electrode and a sub-pixel electrode, the common electrode includes a plurality of voltage-dividing electrode lines, the sub-pixel electrode is connected to the voltage-dividing electrode line through a first transistor, the plurality of voltage-dividing electrode lines are arranged along the first direction, and the plurality of voltage-dividing electrode lines are connected to one of the first connecting lines;

[0014] The first connecting line is connected to the first common signal line through a first switching portion.

[0015] Optionally, in some embodiments of the present application, the first common signal line includes a first portion and a second portion, an end of the first portion and an end of the second portion are cross-connected, the first portion is configured as a first input end of the common signal, the second portion is configured as a second input end of the common signal, and a connection between the first portion and the second portion is connected to the first common signal line through the first transfer portion;

[0016] The length of the first portion is equal to the length of the second portion.

[0017] Optionally, in some embodiments of the present application, a plurality of the first common signal lines are arranged at intervals along the first direction, and each of the first common signal lines is connected to the same first connecting line via a first transfer portion.

[0018] Optionally, in some embodiments of the present application, the array substrate further includes data lines and fan-out traces. The data lines are disposed in the display area along the second direction, and the fan-out traces are disposed in the first area. Each data line is correspondingly connected to one of the fan-out traces;

[0019] In the same film layer, a shielding line is disposed between the fan-out trace closest to the first common signal line and the first common signal line.

[0020] Optionally, in some embodiments of the present application, the distance from the fan-out trace closest to the first common signal line to the shielding line is less than the distance from the shielding line to the first common signal line.

[0021] Optionally, in some embodiments of the present application, in the third area, the first sub-line is disposed along the second direction, the extending direction of the first functional line is parallel to the extending direction of the first sub-line, and one of the first functional lines is connected to the first sub-line;

[0022] The first sub-line includes a third portion and a fourth portion. In the second direction, the fourth portion is connected to the side of the third portion close to the second area; on the side of the first sub-line away from the display area, in the first direction, a part of the fourth portion protrudes from the third portion to form a protruding portion, and the first functional line is connected to the side of the protruding portion away from the second area;

[0023] Wherein, the side edge of the first functional line away from the display area is flush with the side edge of the fourth portion away from the display area.

[0024] Optionally, in some embodiments of the present application, the common electrode further includes a plurality of body electrodes. The main pixel electrode and the sub-pixel electrode of a pixel electrode respectively overlap with the same body electrode partially to form a storage capacitor;

[0025] In the first direction, the plurality of body electrodes are connected in sequence. In the second direction, the plurality of body electrodes are arranged at intervals; the array substrate further includes a first lead and a second lead. In the second direction, the first lead and the second lead are arranged at intervals. One end of the first lead is connected to the first sub-line, one end of the first lead is connected to the side of the body electrode corresponding to the main pixel electrode, one end of the second lead is connected to the first sub-line, and one end of the second lead is connected to the side of the body electrode corresponding to the sub-pixel electrode.

[0026] Optionally, in some embodiments of the present application, the second sub-line includes a fifth portion and a sixth portion, and the fifth portion and the sixth portion are both extended along the first direction. In the second direction, the fifth portion and the sixth portion are spaced apart, and the fifth portion and the sixth portion are connected in parallel between the first sub-line and the third sub-line.

[0027] Optionally, in some embodiments of the present application, the fifth portion is located on a side of the sixth portion close to the display area, the fifth portion is connected to the fourth portion, and the second functional line is connected to an end of the fifth portion close to the fourth portion.

[0028] Optionally, in some embodiments of the present application, in the second direction, the width of the sixth portion is greater than the width of the fifth portion.

[0029] Optionally, in some embodiments of the present application, the fifth portion and the fourth portion are arranged in the same layer and cross-connected; the sixth portion is connected to the end of the fourth portion close to the second area through a second transition portion, and the second transition portion and the second functional line are arranged in different layers;

[0030] A plurality of the voltage-dividing electrode lines extend into the second area, a plurality of the voltage-dividing electrode lines are connected to the fifth portion, and a plurality of the voltage-dividing electrode lines are connected to the sixth portion.

[0031] Optionally, in some embodiments of the present application, each of the voltage-dividing electrode lines is connected to the fifth portion via a fourth transition portion, and a plurality of the fourth transition portions are arranged at intervals along the first direction;

[0032] The array substrate also includes a second connecting line arranged in the second area and extending along the first direction, a plurality of the voltage-dividing electrode lines are connected to a second connecting line, the second connecting line is connected to the sixth part through a plurality of fifth adapters, and the plurality of fifth adapters are arranged at intervals along the first direction.

[0033] Optionally, in some embodiments of the present application, the array substrate further includes an electrostatic protection circuit disposed in the second area, the electrostatic protection circuit is connected to the data line, and the electrostatic protection circuit is disposed between the second connecting line and the fifth portion.

[0034] Optionally, in some embodiments of the present application, the fifth part and the data line are arranged in different layers, the fifth part is provided with a plurality of opening groups, the plurality of opening groups are arranged at intervals along the first direction, each of the opening groups includes at least one opening, and each of the data lines passes through all the openings in one of the opening groups.

[0035] An embodiment of the present application further provides a display device, which includes a source driver structure and a display panel as described in any one of the above embodiments. The source driver structure is bonded to the bonding area of the display panel, and is configured to provide a common signal to the first common signal line and the second common signal line, provide a compensation voltage to the first compensation line and the second compensation line, and collect feedback signals of the first feedback line and the second feedback line.

[0036] In the display panel of the embodiment of the present application, a feedback line is provided in each of the middle region and the distal region of the second common signal line to form a multi-region feedback mechanism to improve the accuracy of detecting the common electrode. Then, precise compensation is performed using the compensation lines in the middle region and the distal region of the second common signal line. That is, according to the feedback mechanism in the distal region, the distal end of the common electrode is compensated for potential through the compensation line in the distal region, and according to the feedback mechanism in the middle region, the middle region of the common electrode is compensated for potential through the compensation line in the middle region to improve the potential stability of the common electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a top view structural schematic diagram of an array substrate in the display panel provided by an embodiment of the present application;

[0038] Figure 2 is a circuit schematic diagram of a display area of the display panel provided by an embodiment of the present application;

[0039] Figure 3 is Figure 1 an enlarged schematic diagram of part R1 in

[0040] Figure 4 is Figure 1 an enlarged schematic diagram of part R2 in

[0041] Figure 5 is Figure 1 an enlarged schematic diagram of part R3 in

[0042] Figure 6 is Figure 1 an enlarged schematic diagram of part R4 in

[0043] Figure 7 is a structural schematic diagram of the display device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0044] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation manners described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the embodiments can be combined with each other without further elaboration, and in the case of no contrary description, the orientation terms such as "upper" and "lower" usually refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the drawings; and "inner" and "outer" are relative to the outline of the device; the terms "first", "second", "third", etc. are only used as labels, and do not impose numerical requirements or establish an order.

[0045] An embodiment of the present application provides a display panel and a display device, which will be described in detail below. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments.

[0046] In Figure 1 , the first direction F1 may be a direction parallel to one side of the display panel 100 in a plan view, and may be, for example, the horizontal direction of the display panel 100. The second direction F2 may be a direction parallel to the other side of the display panel 100 in a plan view, and may be the longitudinal direction of the display panel 100.

[0047] Optionally, the first direction F1 and the second direction F2 are perpendicularly arranged or non-perpendicularly arranged. The display panel 100 of the embodiment of the present application is described by taking the first direction F1 and the second direction F2 being perpendicular as an example, but is not limited thereto.

[0048] The display panel 100 may have a rectangular shape or a square shape in a plan view, but the implementation manner is not limited thereto. In some implementation manners, the display panel 100 may have a rectangular shape with vertical corners or rounded corners in a plan view. The display panel 100 may include two short sides arranged in the first direction F1 and two long sides arranged in the second direction F2 in a plan view.

[0049] The display panel 100 may include a display area AA and a non-display area NA. In a plan view, the shape of the display area AA may correspond to the shape of the display panel 100. For example, when the display panel 100 has a rectangular shape in a plan view, the display area AA may also have a rectangular shape.

[0050] The display area AA can be an area including pixels for displaying an image. The pixels can be arranged in a matrix form. The pixels can have a rectangular shape, a rhombic shape, or a square shape in a plan view, but the embodiments are not limited thereto. For example, in a plan view, the pixels can have another quadrilateral shape other than a rectangular shape, a rhombic shape, or a square shape, another polygon shape other than a quadrilateral shape, a circular shape, or an elliptical shape.

[0051] The non-display area NA can be an area that does not include pixels and thus does not display an image. The non-display area NA can be arranged on the outer peripheral side of the display area AA. As Figure 1 shown, the non-display area NA can surround the display area AA, but the embodiments are not limited thereto.

[0052] The non-display area NA includes a first area N1 and a second area N2 that are arranged along the second direction F2 and are disposed opposite to each other with respect to the display area AA. The first area N1 has a bonding area N11 configured to bond a circuit board.

[0053] The non-display area NA further includes a third area N3 and a fourth area N4 that are arranged along the first direction F1 and are disposed opposite to each other with respect to the display area AA.

[0054] The display panel 100 is a liquid crystal display panel, which includes an array substrate 10 and a counter substrate, and the array substrate 10 and the counter substrate are disposed opposite to each other. A liquid crystal layer is provided between the array substrate 10 and the counter substrate.

[0055] Optionally, the display panel 100 can be a panel with a Fringe Field Switching (FFS) technology driving architecture, can also be a panel with an In-Plane Switching (IPS) technology driving architecture, or can also be a panel with a Vertical Alignment (VA) technology driving architecture, and so on.

[0056] It should be noted that hereinafter, the display panel 100 being a panel with a VA architecture will be taken as an example for elaboration, but it is not limited thereto.

[0057] The array substrate 10 includes a common electrode 11, a first common signal line 12, a second common signal line 13, two first functional lines 14, and two second functional lines 15.

[0058] The common electrode 11 is disposed in the display area AA. The first common signal line 12 is disposed in the first area N1. The first common signal line 12 is connected to one side of the common electrode 11 close to the first area N1. The second common signal line 13 is disposed in the non-display area NA and extends along the outer peripheral direction of the display area AA. The portions of the common electrode 11 close to the second area N2, the third area N3, and the fourth area N4 are correspondingly connected to the adjacent second common signal line 13.

[0059] The second common signal line 13 includes a proximal region h1 close to the first area N1, a distal region h3 close to the second area N2, and a middle region h2 located between the proximal region h1 and the distal region h3.

[0060] In the first direction F1, there is a gap of the display area AA between two first functional lines 14. One first functional line 14 is connected to one side of the second common signal line 13 in the middle region h2, and the other first functional line 14 is connected to the other side of the second common signal line 13 in the middle region h2.

[0061] In the first direction F1, there is a gap of the display area AA between two second functional lines 15. One second functional line 15 is connected to one side of the second common signal line 13 in the distal region h3, and the other second functional line 15 is connected to the other side of the second common signal line 13 in the distal region h3.

[0062] Among them, one of the two first functional lines 14 is a first compensation line 141, and the other is a first feedback line 142. One of the two second functional lines 15 is a second compensation line 151, and the other is a second feedback line 152.

[0063] In the display panel 100 according to the embodiment of the present application, a feedback line is provided in each of the middle region h2 and the distal region h3 of the second common signal line 13 to form a multi-region feedback mechanism to improve the detection accuracy of the common electrode 11, and then precise compensation is performed by using the compensation lines in the middle region h2 and the distal region h3 of the second common signal line 13. That is, according to the feedback mechanism of the distal region h3, the potential of the distal end of the common electrode 11 is compensated by the compensation line in the distal region h3; according to the feedback mechanism of the middle region h2, the potential of the middle end of the common electrode 11 is compensated by the compensation line in the middle region h2 to improve the potential stability of the common electrode 11.

[0064] Secondly, it should be understood that the first common signal line 12 is configured to provide a common signal to the proximal end of the common electrode 11. The second common signal line 13 is configured to provide a common signal to the middle end and the distal end of the common electrode 11.

[0065] Optionally, in some embodiments, both the first compensation line 141 and the second compensation line 151 are located within one of the third region N3 and the fourth region N4, and the first feedback line 142 and the second feedback line 152 are located within the other of the third region N3 and the fourth region N4. For example, both the first compensation line 141 and the second compensation line 151 are located within the third region N3, and the first feedback line 142 and the second feedback line 152 are located within the fourth region N4.

[0066] Alternatively, in some embodiments, as Figure 1 shown, both the first compensation line 141 and the second feedback line 152 are located within one of the third region N3 and the fourth region N4, and the first feedback line 142 and the second compensation line 151 are located within the other of the third region N3 and the fourth region N4. For example, both the first compensation line 141 and the second feedback line 152 are located within the third region N3, and the first feedback line 142 and the second compensation line 151 are located within the fourth region N4. It should be noted that the embodiments of the present application are described by taking Figure 1 as an example, but are not limited thereto.

[0067] In addition, in some embodiments, both of the two second functional lines 15 may be set as compensation lines, one of the two first functional lines 14 is a compensation line, and the other is a feedback line. Alternatively, both of the two first functional lines 14 may be set as compensation lines, and one of the two second functional lines 15 is a compensation line, and the other is a feedback line.

[0068] Optionally, in some embodiments, at least one of the first feedback line 142 and the second feedback line 152 is multiplexed as a compensation line. Through time-division multiplexing, the first feedback line 142 and the second feedback line 152 have a detection function and a compensation function. For example, when it is detected that the first compensation line 141 and the second compensation line 151 still cannot reach the set threshold after compensating the potential of the common electrode 11, the feedback function of at least one of the first feedback line 142 and the second feedback line 152 can be suspended, and the compensation function can be activated to assist in compensating the common electrode 11, so that the common electrode 11 reaches the set threshold potential, thereby improving the potential stability of the common electrode 11.

[0069] Optionally, please refer to Figure 2 , in some embodiments, the array substrate 10 includes a first transistor T1, a second transistor T2, a third transistor T3, and a pixel electrode 16. The pixel electrode 16 includes a main pixel electrode 161 and a sub-pixel electrode 162. The common electrode 11 includes a plurality of voltage-dividing electrode lines 111, and the sub-pixel electrode 162 is connected to the voltage-dividing electrode line 111 through the first transistor T1.

[0070] Among them, the gates of the first transistor T1, the second transistor T2, and the third transistor T3 are connected to the same scanning line G1, and the sources of the second transistor T2 and the third transistor T3 are connected to the same data line D1. The drain of the second transistor T2 is connected to the main pixel electrode 161, the drain of the third transistor T3 is connected to the sub-pixel electrode 162, the source of the first transistor T1 is connected to the drain of the third transistor T3, and the drain of the first transistor T1 is connected to the voltage dividing electrode line 111. A main storage capacitor is formed between the main pixel electrode 161 and the common electrode 11. A sub-storage capacitor is formed between the sub-pixel electrode 162 and the common electrode 11.

[0071] During the display process, when the scanning line G1 is turned on, the first transistor T1, the second transistor T2, and the third transistor T3 are turned on simultaneously, and the data line D1 charges the main pixel electrode 161 and the sub-pixel electrode 162 with a data voltage. At the same time, the first transistor T1 leaks a part of the charge on the sub-pixel electrode 162 to the voltage dividing electrode line 111, making the brightness of the area of the sub-pixel electrode 162 lower than that of the area of the main pixel electrode 161.

[0072] Please continue to refer to Figure 1 , in some embodiments of the present application, the second common signal line 13 includes a first sub-line 13a, a second sub-line 13b, and a third sub-line 13c. The first sub-line 13a is disposed in the third region N3, the second sub-line 13b is disposed in the second region N2, and the third sub-line 13c is disposed in the fourth region N4. One end of the second sub-line 13b is connected to the first sub-line 13a, and the other end of the second sub-line 13b is connected to the third sub-line 13c.

[0073] One of the two first functional lines 14 is disposed in the third region N3 and connected to the first sub-line 13a, and the other is disposed in the fourth region N4 and connected to the third sub-line 13c. One of the two second functional lines 15 is disposed in the third region N3 and connected to the first sub-line 13a or the second sub-line 13b, and the other is disposed in the fourth region N4 and connected to the third sub-line 13c or the second sub-line 13b.

[0074] Optionally, one of the two first functional lines 14 is connected to the middle end of the first sub-line 13a, and the other is connected to the middle end of the third sub-line 13c. One of the two second functional lines 15 is connected to the end of the first sub-line 13a or the end of the second sub-line 13b close to the first sub-line 13a, and the other is connected to the end of the third sub-line 13c or the end of the second sub-line 13b close to the third sub-line 13c.

[0075] Among them, the first compensation line 141 is connected to the middle end of the first sub-line 13a or the third sub-line 13c, and the second compensation line 151 is connected to the end of the common electrode 11. Based on the fact that the voltage drop at the proximal end of the common electrode 11 is the smallest and the voltage drop at the distal end is the largest, the first compensation voltage is transmitted from the middle of the common electrode 11 to the proximal end and the distal end, and the second compensation voltage is transmitted from the distal end to the proximal end of the common electrode 11, thereby improving the uniformity and stability of the overall potential of the common electrode 11.

[0076] Please refer to Figure 3 In some embodiments of the present application, the array substrate 10 further includes a first connection line 171 extending along the first direction F1 and located in the first area N1. A plurality of voltage dividing electrode lines 111 are arranged along the first direction F1, and the plurality of voltage dividing electrode lines 111 are connected to a first connection line 171.

[0077] The first connection line 171 is connected to the first common signal line 12 through the first transfer portion 181 .

[0078] It can be understood that connecting a plurality of voltage-dividing electrode lines 111 to a first connecting line 171 simultaneously can reduce the number of ports of the first common signal line 12 connected to the plurality of voltage-dividing electrode lines, thereby narrowing the frame.

[0079] Optionally, the first connection line 171 and the first common signal line 12 are arranged in different layers, that is, an insulating layer is arranged between the two. The first adapter 181 is arranged in different layers from the first connection line 171 and the first common signal line 12, respectively, and the first adapter 181 is arranged above the first connection line 171 and the first common signal line 12. One end of the first adapter 181 is connected to the first common signal line 12 through the first via group k1, and the other end of the first adapter 181 is connected to the first connection line 171 through the second via group k2.

[0080] Optionally, the first via group k1 has multiple vias, and the second via group k2 also has multiple vias. The first adapter 181 is connected to the first connection line 171 and the first common signal line 12 respectively by a via group, which increases the connection area to reduce impedance, thereby improving the potential stability of the common electrode 11.

[0081] Optionally, a plurality of wirings 18 a are connected between the first end portion of the first transition portion 181 connected to the first common signal line 12 and the second end portion of the first connection line 171 , and the plurality of wirings 18 a are arranged at intervals.

[0082] The plurality of lines 18a are spaced apart to form a transmission area, so that light from the back of the array substrate 10 can pass through the transmission area to irradiate the light-curing sealant, thereby improving the curing efficiency of the light-curing sealant. It should be understood that the light-curing sealant is arranged between the array substrate 10 and the opposing substrate.

[0083] Optionally, the material of the first connection portion 181 may be a transparent conductive metal oxide such as indium tin oxide or indium zinc oxide to improve the light transmittance.

[0084] Optionally, in some embodiments of the present application, a first common signal line 12 includes a first portion 12a and a second portion 12b, and the ends of the first portion 12a and the second portion 12b are cross-connected. The first portion 12a is configured as the first input end of the common signal, and the second portion 12b is configured as the second input end of the common signal. The connection portion between the first portion 12a and the second portion 12b is connected to the first common signal line 12 through the first connection portion 181. The lengths of the first portion 12a and the second portion 12b are equal.

[0085] It can be understood that the first common signal line 12 has two signal input ends, which improves the efficiency of the common signal input into the first common signal line 12. Subsequently, based on the fact that the length of the first portion 12a is equal to the length of the second portion 12b, the connection portion between the first portion 12a and the second portion 12b is located at the middle position of the first common signal line 12, so that the first common signal line 12 can transmit the common signal to the first connection line 171 more stably, more evenly and more efficiently.

[0086] Optionally, in some embodiments of the present application, multiple first common signal lines 12 are arranged at intervals along the first direction F1, and each first common signal line 12 is correspondingly connected to the same first connection line 171 through a first connection portion 181.

[0087] It can be understood that using multiple first common signal lines 12 to transmit the common signal to the first connection line 171 simultaneously improves the uniformity and stability of the common signal entering the common electrode 11.

[0088] Optionally, both the first portion 12a and the second portion 12b are grid traces to improve the light transmittance. And the middle area of the connection portion between the first portion 12a and the second portion 12b is a sheet structure to improve the connection stability between the first common signal line 12 and the first connection portion 181.

[0089] Optionally, in some embodiments of the present application, the array substrate 10 further includes a data line D1 and a fan-out trace S1. The data line D1 extends along the second direction F2 in the display area AA, and the fan-out trace S1 is arranged in the first area N1, and each data line D1 is correspondingly connected to a fan-out trace S1.

[0090] In the same film layer, a shielding line p1 is provided between the fan-out trace S1 closest to the first common signal line 12 and the first common signal line 12.

[0091] It can be understood that in the same film layer, a shielding line p1 is inserted between the fan-out trace S1 and the first common signal line 12 to reduce the coupling risk of the data signal to the first common signal line 12, thereby improving the stability of the common signal.

[0092] Optionally, in some embodiments, the shielding line p1 is set to be grounded.

[0093] Optionally, the width of the first common signal line 12 is greater than the widths of the data line D1 and the fan-out trace S1, reducing the impedance of the first common signal line 12 and improving the stability of the common signal transmission.

[0094] Optionally, in some embodiments of the present application, the distance from the fan-out trace S1 closest to the first common signal line 12 to the shielding line p1 is less than the distance from the shielding line p1 to the first common signal line 12. Such a setting is to reduce the interference of the data signal to the first common signal line 12.

[0095] Optionally, the distance from the shielding line p1 to the first common signal line 12 is greater than four times the distance from the shielding line p1 to the closest fan-out trace S1.

[0096] Please refer to Figure 4 , in some embodiments of the present application, in the third region N3, the first sub-line 13a extends along the second direction F2, and the extending direction of the first functional line 14 is parallel to the extending direction of the first sub-line 13a. A first functional line 14 is connected to the first sub-line 13a.

[0097] It should be noted that in the third region N3, the first functional line 14 can be the first feedback line 142, or can be the first compensation line 141.

[0098] The first sub-line 13a includes a third part 133 and a fourth part 134. In the second direction F2, the fourth part 134 is connected to the side of the third part 133 close to the second region N2. On the side of the first sub-line 13a away from the display area AA, in the first direction F1, a part of the fourth part 134 protrudes from the third part 133 to form a protruding part 34a. The first functional line 14 is connected to the side of the protruding part 34a away from the second region N2.

[0099] Among them, the edge of the first functional line 14 away from the display area AA is flush with the edge of the fourth part 134 away from the display area AA.

[0100] It can be understood that connecting the first functional line 14 to the protruding part 34a and being flush with the side of the fourth part 134, that is, using the recessed space formed by the protruding part 34a to set the first functional line 14, without additionally setting the wiring space for the first functional line 14, achieving the effect of narrowing the border.

[0101] Optionally, in some embodiments, a hollow opening p2 is provided on one side of the first sub-line 13a close to the display area AA, the scan line G1 extends to the hollow opening p2 and is connected to the gate signal lead line G2 through the third adapter 183, and the gate signal lead line G2 is connected to the gate driving circuit. The third adapter 183 is provided in the hollow opening p2.

[0102] The gate signal lead line G2 and the voltage dividing electrode line 111 are arranged on the same layer, the scanning line G1 and the first sub-line 13 a are arranged on the same layer, and the third transfer portion 183 and the first transfer portion 181 are arranged on the same layer.

[0103] It is understandable that the hollow opening p2 is used to avoid the scanning line G1 and the third adapter 183 for transmitting the gate signal, thereby reducing the interference of the gate signal on the second common signal line 13 and improving the potential stability of the common signal in the second common signal line 13 .

[0104] In some embodiments, a redundant pixel electrode p3 is overlapped above the first sub-line 13a, and the redundant pixel electrode p3 and the first sub-line 13a are arranged in different layers. A plurality of redundant pixel electrodes p3 are arranged at intervals along the extension direction of the first sub-line 13a. The redundant pixel electrode p3 is a floating electrode, which is electrically isolated from other devices.

[0105] It is understandable that providing a floating redundant pixel electrode p3 on the first sub-line 13 a can reduce the interference of the upper signal of the first sub-line 13 a on the first sub-line 13 a, thereby improving the stability of the common signal in the second common signal line 13 .

[0106] Optionally, the redundant pixel electrode p3 and the pixel electrode 16 are provided in the same layer and are made of the same material.

[0107] Optionally, in some embodiments of the present application, the common electrode 11 further includes a plurality of body electrodes 112 , and a primary pixel electrode 161 and a secondary pixel electrode 162 of a pixel electrode 16 are respectively overlapped with a portion of the same body electrode 112 to form a storage capacitor.

[0108] In the first direction F1, the plurality of body electrodes 112 are connected in sequence. In the second direction F2, the plurality of body electrodes 112 are arranged at intervals. The array substrate 10 further includes a first lead 191 and a second lead 192. In the second direction F2, the first lead 191 and the second lead 192 are arranged at intervals, one end of the first lead 191 is connected to the first sub-line 13a, one end of the first lead 191 is connected to a side of the body electrode 112 corresponding to the main pixel electrode 161, one end of the second lead 192 is connected to the first sub-line 13a, and one end of the second lead 192 is connected to a side of the body electrode 112 corresponding to the sub-pixel electrode 162.

[0109] It can be understood that in the region of the row pixel electrode 16, two common signal input terminals are respectively corresponding to the region of the main pixel electrode 161 and the region of the sub-pixel electrode 162, improving the uniformity and transmission efficiency of the common signal input, thereby improving the stability of the signal in the common electrode 11.

[0110] Please refer to Figure 5 and Figure 6 In some embodiments of the present application, the second sub-line 13b includes a fifth portion 135 and a sixth portion 136. Both the fifth portion 135 and the sixth portion 136 are arranged to extend along the first direction F1. In the second direction F2, the fifth portion 135 and the sixth portion 136 are arranged at intervals. The fifth portion 135 and the sixth portion 136 are connected in parallel between the first sub-line 13a and the third sub-line 13c.

[0111] It can be understood that the fifth portion 135 and the sixth portion 136 are connected in parallel to reduce the voltage drop of the second sub-line 13b, thereby improving the stability of the common signal.

[0112] Optionally, in some embodiments of the present application, the fifth portion 135 is located on the side of the sixth portion 136 closer to the display area AA. The fifth portion 135 is connected to the fourth portion 134, and a second functional line 15 is connected to one end of the fifth portion 135 close to the fourth portion 134.

[0113] It should be noted that the second functional line 15 can be a second compensation line 151, or can be a second feedback line 152.

[0114] It can be understood that based on the fact that the fifth portion 135 is closer to the display area AA, if the second functional line 15 is the second compensation line 151, then connecting the second functional line 15 to the fifth portion 135 can compensate the common electrode 11 faster, improving the stability of the common signal. If the second functional line 15 is the second feedback line 152, then connecting the second functional line 15 to the fifth portion 135 can more accurately feedback the potential situation of the common electrode 11, so as to accurately compensate the common electrode 11 from the far end to improve the stability of the common signal potential.

[0115] Optionally, in some embodiments of the present application, in the second direction F2, the width of the sixth portion 136 is greater than the width of the fifth portion 135.

[0116] It can be understood that based on the fact that the sixth portion 136 is located outside the fifth portion 135, the width of the sixth portion 136 is relatively wide. On the one hand, it can increase the area of the sixth portion 136 to reduce the voltage drop of the second common signal line 13, thereby improving the stability of the common signal; on the other hand, by using the relatively wide sixth portion 136 arranged outside the fifth portion 135, it can better isolate the interference of external signals to the common signal in the display area AA, improving the signal stability of the common electrode 11.

[0117] Optionally, in some embodiments of the present application, the fifth portion 135 is disposed in the same layer and cross-connected with the fourth portion 134. The sixth portion 136 is connected to the end of the fourth portion 134 near the second region N2 through a second transition portion 182, and the second transition portion 182 and the second functional line 15 are disposed in different layers.

[0118] The plurality of voltage-dividing electrode lines 111 extend into the second region N2 , the plurality of voltage-dividing electrode lines 111 are connected to the fifth portion 135 , and the plurality of voltage-dividing electrode lines 111 are connected to the sixth portion 136 .

[0119] It is understandable that the sixth portion 136 is connected to the fourth portion 134 via the second adapter portion 182, which can prevent the second common signal line 13 from being short-circuited with other signal lines. Secondly, the voltage-dividing electrode line 111 is simultaneously connected to the fifth portion 135 and the sixth portion 136, so that the far end of the voltage-dividing electrode line 111 has two signal output terminals, thereby improving the stability of the input signal of the common electrode 11.

[0120] Optionally, a side of the sixth portion 136 close to the fourth area N4 is connected to an end of the third sub-line 13c away from the first area N1 through another second transition portion 182. The fifth portion 135 and the third sub-line 13c are disposed in the same layer and connected.

[0121] Optionally, in some embodiments of the present application, each voltage-dividing electrode line 111 is connected to the fifth portion 135 via a fourth transition portion 184 , and a plurality of fourth transition portions 184 are arranged at intervals along the first direction F1 .

[0122] The array substrate 10 further includes a second connection line 172 disposed in the second area N2 and extending along the first direction F1. A plurality of voltage-dividing electrode lines 111 are connected to a second connection line 172. The second connection line 172 is connected to the sixth portion 136 via a plurality of fifth adapter portions 185. The plurality of fifth adapter portions 185 are arranged at intervals along the first direction F1.

[0123] It is understandable that by using a second connecting line 172 to simultaneously connect multiple voltage-dividing electrode lines 111, multiple voltage-dividing electrode lines 111 can be connected in parallel, which can reduce the impedance of the common electrode. Secondly, the fourth adapter 184 and the fifth adapter 185 are each spaced apart along the first direction F1, which improves the uniformity of the common signal input to the common electrode 11.

[0124] Optionally, the second connection line 172 and the voltage-dividing electrode line 111 are arranged in the same layer, and the fifth portion 135 and the sixth portion 136 are arranged in different layers from the voltage-dividing electrode line 111. The fourth transition portion 184, the fifth transition portion 185 and the first transition portion 181 are arranged in the same layer and made of the same material.

[0125] Optionally, in some embodiments of the present application, the array substrate 10 further includes an electrostatic protection circuit 101 disposed in the second region N2. The electrostatic protection circuit 101 is connected to the data line D1 and is disposed between the second connection line 172 and the fifth part 135.

[0126] It can be understood that the electrostatic protection circuit 101 is configured to prevent external static electricity from entering the data line D1 in the display area AA. Secondly, since both the second connection line 172 and the fifth part 135 are connected to the same common signal, an equipotential region is formed between the second connection line 172 and the fifth part 135 to reduce the risk of electrostatic field interference caused by local charge accumulation, thereby suppressing electrostatic accumulation.

[0127] Optionally, in some embodiments of the present application, the fifth part 135 and the data line D1 are disposed on different layers. The fifth part 135 is provided with a plurality of opening groups p4, and the plurality of opening groups p4 are arranged at intervals along the first direction F1. Each opening group p4 includes at least one opening p01, and each data line D1 correspondingly passes through all the openings p01 in one opening group p4.

[0128] It can be understood that the data line D1 correspondingly passes through the openings p01 of the opening group p4 to reduce the overlapping area between the data line D1 and the fifth part 135, thereby reducing the interference of the data signal on the common signal and improving the potential stability of the common electrode 11.

[0129] Optionally, in some embodiments, the overall structures of a first functional line 14, a second functional line 15, and a third sub-line 13c in the fourth region N4 are symmetrically arranged about the central axis of the display area AA with respect to the overall structures of another first functional line 14, another second functional line 15, and a first sub-line 13a in the third region N3. That is, the first sub-line 13a and the third sub-line 13c are axially symmetrically arranged, the first functional line 14 in the fourth region N4 and the first functional line 14 in the third region N3 are axially symmetrically arranged, the second functional line 15 in the fourth region N4 and the second functional line 15 in the third region N3 are axially symmetrically arranged, and the structures on the side of the second sub-line 13b close to the third region N3 and the structures on the side of the second sub-line 13b close to the fourth region N4 are axially symmetrically arranged.

[0130] Please refer to Figure 7 , the embodiment of the present application further provides a display device 1000, which includes a source driving structure 200 and a display panel 100 as described in any one of the above embodiments. The source driving structure 200 is bonded to the bonding area of the display panel 100. The source driving structure 200 is configured to provide a common signal to the first common signal line 12 and the second common signal line 13, provide a compensation voltage to the first compensation line 141 and the second compensation line 151, and collect the feedback signals of the first feedback line 142 and the second feedback line 152.

[0131] In the display device 1000 according to the embodiment of the present application, a feedback line is provided in each of the middle region h2 and the distal region h3 of the second common signal line 13 to form a multi-region feedback mechanism to improve the accuracy of detecting the common electrode 11. Then, precise compensation is performed using the compensation lines in the middle region h2 and the distal region h3 of the second common signal line 13. That is, according to the feedback mechanism in the distal region h3, the potential of the distal end of the common electrode 11 is compensated through the compensation line in the distal region h3. According to the feedback mechanism in the middle region h2, the potential of the middle end of the common electrode 11 is compensated through the compensation line in the middle region h2 to improve the potential stability of the common electrode 11.

[0132] Optionally, the source driver structure 200 includes a plurality of flexible circuit boards 201 and a printed driver board 202. The plurality of flexible circuit boards 201 are respectively bonded to the first region N1 of the display panel 100. A first common signal line 12 connects two flexible circuit boards 201. At least one flexible circuit board 201 is connected to a printed driver board 202. The printed driver board 202 is configured to provide a common signal and a compensation voltage to the common electrode 11, and collect the feedback signal of the common electrode 11 and provide the compensation voltage to the common electrode 11 according to the feedback signal.

[0133] It should be noted that the structure of the display panel 100 of the display device 1000 according to the embodiment of the present application is similar to or the same as the structure of the display panel 100 in any of the above embodiments. Therefore, the structure of the display panel 100 of the display device 1000 can be specifically referred to Figures 1 to 6 for the description, so it will not be elaborated here.

[0134] Optionally, the display device 1000 can be applied to various products and can be used within the various products. The various products include, for example, televisions, notebook computers, monitors, billboards, Internet of Things devices, and portable electronic devices including mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players, navigation devices, and ultra-mobile personal computers.

[0135] In addition, the display device 1000 according to some embodiments can be applied to wearable devices and can be used within the wearable devices. The wearable devices include smart watches, watch phones, glasses-type displays, and head-mounted displays. In addition, according to some embodiments, the display device 1000 can be applied to the display screen in the instrument panel for automobiles, the central instrument panel for automobiles, or the central information display arranged on the dashboard, the in-vehicle mirror display replacing the side mirror of the automobile, and the display of the entertainment system arranged on the back of the front seat for the rear seat passengers in the automobile.

[0136] The above has introduced in detail a display panel and a display device provided by an embodiment of the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A display panel, comprising a display area and a non-display area, wherein the non-display area is located at a peripheral side of the display area, the non-display area comprises a first area and a second area arranged along a second direction and oppositely disposed apart from the display area, the first area having a binding area configured to bind a circuit board, characterized in that: The display panel includes an array substrate, and the array substrate includes: A common electrode, arranged in the display area; A first common signal line is disposed in the first area, and the first common signal line is connected to a side of the common electrode close to the first area; A second common signal line is arranged in the non-display area and extends around the outer circumference of the display area, the second common signal line is connected to the common electrode, and the second common signal line includes a proximal region close to the first area, a distal region close to the second area, and a middle region between the proximal region and the distal region; Two first function lines, in a first direction intersecting the second direction, the display area is spaced between the two first function lines, one first function line is connected to the second common signal line and is located on one side of the middle end area, and the other first function line is connected to the second common signal line and is located on the other side of the middle end area; and Two second functional lines, in the first direction, the display area is spaced between the two second functional lines, one second functional line is connected to the second common signal line and is located at one side of the remote area, and the other second functional line is connected to the second common signal line and is located at the other side of the remote area; Among them, one of the two first function lines is a first compensation line, and the other is a first feedback line; one of the two second function lines is a second compensation line, and the other is a second feedback line.

2. The display panel according to claim 1, characterized in that: The non-display area further includes a third area and a fourth area arranged along the first direction and oppositely disposed apart from the display area, the second common signal line includes a first sub-line, a second sub-line and a third sub-line, the first sub-line is disposed in the third area, the second sub-line is disposed in the second area, the third sub-line is disposed in the fourth area, one end of the second sub-line is connected to the first sub-line, and the other end of the second sub-line is connected to the third sub-line; One of the two first functional lines is arranged in the third area and connected to the first sub-line, and the other is arranged in the fourth area and connected to the third sub-line; one of the two second functional lines is arranged in the third area and connected to the first sub-line or the second sub-line, and the other is arranged in the fourth area and connected to the third sub-line or the second sub-line.

3. The display panel according to claim 2, characterized in that: The array substrate further comprises a first connection line extending along the first direction and located in the first area, and a pixel electrode located in the display area, the pixel electrode comprises a main pixel electrode and a sub-pixel electrode, the common electrode comprises a plurality of voltage-dividing electrode lines, the sub-pixel electrode is connected to the voltage-dividing electrode line via a first transistor, the plurality of voltage-dividing electrode lines are arranged along the first direction, and the plurality of voltage-dividing electrode lines are connected to one of the first connection lines; The first connecting line is connected to the first common signal line through a first switching portion.

4. The display panel according to claim 3, characterized in that: The first common signal line includes a first portion and a second portion, an end of the first portion and an end of the second portion are cross-connected, the first portion is configured as a first input end of the common signal, the second portion is configured as a second input end of the common signal, and a connection between the first portion and the second portion is connected to the first common signal line through the first transfer portion; The length of the first portion is equal to the length of the second portion.

5. The display panel according to claim 4, characterized in that: A plurality of the first common signal lines are arranged at intervals along the first direction, and each of the first common signal lines is connected to the same first connecting line via a corresponding first transfer portion.

6. The display panel according to any one of claims 3 to 5, characterized in that: In the third area, the first sub-lines are extended along the second direction, the extension direction of the first functional lines is parallel to the extension direction of the first sub-lines, and a first functional line is connected to the first sub-lines; The first sub-line includes a third portion and a fourth portion, and in the second direction, the fourth portion is connected to a side of the third portion close to the second area; on a side of the first sub-line away from the display area, in the first direction, a portion of the fourth portion protrudes from the third portion to form a protruding portion, and the first functional line is connected to a side of the protruding portion away from the second area; Wherein, an edge of a side of the first functional line away from the display area is flush with an edge of a side of the fourth portion away from the display area.

7. The display panel according to claim 6, characterized in that: The common electrode further comprises a plurality of body electrodes, and a main pixel electrode and a sub-pixel electrode of the pixel electrode are respectively overlapped with a portion of the same body electrode to form a storage capacitor; In the first direction, the plurality of body electrodes are connected in sequence, and in the second direction, the plurality of body electrodes are arranged at intervals; the array substrate also includes a first lead and a second lead, and in the second direction, the first lead and the second lead are arranged at intervals, one end of the first lead is connected to the first sub-line, one end of the first lead is connected to a side of the body electrode corresponding to the main pixel electrode, one end of the second lead is connected to the first sub-line, and one end of the second lead is connected to a side of the body electrode corresponding to the sub-pixel electrode.

8. The display panel according to claim 7, characterized in that: A redundant pixel electrode is overlapped above the first sub-line, the redundant pixel electrode and the first sub-line are arranged in different layers, a plurality of the redundant pixel electrodes are arranged at intervals along the extension direction of the first sub-line, and the redundant pixel electrode is a floating electrode.

9. The display panel according to claim 6, characterized in that: The second sub-line includes a fifth portion and a sixth portion, both of which are extended along the first direction. In the second direction, the fifth portion and the sixth portion are spaced apart, and the fifth portion and the sixth portion are connected in parallel between the first sub-line and the third sub-line.

10. The display panel according to claim 9, characterized in that: The fifth portion is located at a side of the sixth portion close to the display area, the fifth portion is connected to the fourth portion, and a second functional line is connected to an end of the fifth portion close to the fourth portion.

11. The display panel according to claim 10, characterized in that: In the second direction, the width of the sixth portion is greater than the width of the fifth portion.

12. The display panel according to claim 10, characterized in that: The fifth portion is arranged in the same layer as the fourth portion and is cross-connected; the sixth portion is connected to the end of the fourth portion close to the second area through a second transition portion, and the second transition portion and the second functional line are arranged in different layers; A plurality of the voltage-dividing electrode lines extend into the second area, a plurality of the voltage-dividing electrode lines are connected to the fifth portion, and a plurality of the voltage-dividing electrode lines are connected to the sixth portion.

13. The display panel according to claim 12, characterized in that: Each of the voltage-dividing electrode lines is connected to the fifth portion via a fourth transition portion, and a plurality of the fourth transition portions are arranged at intervals along the first direction; The array substrate also includes a second connecting line arranged in the second area and extending along the first direction, a plurality of the voltage-dividing electrode lines are connected to a second connecting line, the second connecting line is connected to the sixth part through a plurality of fifth adapters, and the plurality of fifth adapters are arranged at intervals along the first direction.

14. The display panel according to claim 13, characterized in that: The array substrate further includes an electrostatic protection circuit disposed in the second area, the electrostatic protection circuit is connected to the data line, and the electrostatic protection circuit is disposed between the second connection line and the fifth portion.

15. The display panel according to claim 14, characterized in that: The fifth part and the data line are arranged in different layers. The fifth part is provided with a plurality of opening groups. The plurality of opening groups are arranged at intervals along the first direction. Each of the opening groups includes at least one opening. Each of the data lines passes through all the openings in one of the opening groups.

16. A display device, characterized in that: It includes a source driving structure and a display panel as described in any one of claims 1 to 15, wherein the source driving structure is bound to a binding area of ​​the display panel, and the source driving structure is configured to provide a common signal to the first common signal line and the second common signal line, provide a compensation voltage to the first compensation line and the second compensation line, and collect feedback signals from the first feedback line and the second feedback line.

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