Hardware acceleration module and data reading method and device

Abstract

The present application provides a hardware acceleration module and a data reading method and device. The hardware acceleration module is connected to a storage module and a processing module respectively. The hardware acceleration module includes a read-write controller, a data register, an address register, and a comparison register. The data register is used to store valid data read from multiple structures in the storage module. The address register is used to store the address offset corresponding to each valid data in the multiple structures in the storage module. The comparison register is used to perform an equality comparison on the read valid data. The read-write controller is used to read from the first structure in the storage module to the end of the last structure. When the comparison register determines that the valid data meets a preset condition, the read valid data is sent to the processing module. The solution of the present application can improve the efficiency of data reading.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and in particular to a hardware acceleration module and a data reading method and device. Background Art

[0002] Currently, in the field of non-volatile data storage technology, when managing Nand Flash particles with firmware, it is necessary to perform pattern matching on data (such as indexes, addresses, and other data) stored in the continuous address space of the chip's internal cache to find the required data addresses or other information. Frequent operations on the internal storage buffer can lead to a large amount of address space fragmentation, such as one or more unused 32-bit address spaces, thus forming discrete address space fragments. In existing technologies, reading data stored in discrete address space fragments takes a significant amount of time, resulting in inefficient reading of data in discrete storage spaces. Therefore, improving data reading efficiency has become a pressing issue. Summary of the Invention

[0003] The main technical problem solved by the present invention is the low efficiency of reading data in discrete space.

[0004] According to a first aspect, a hardware acceleration module is provided, which is connected to a storage module and a processing module respectively. The storage module stores a plurality of structures, each structure containing a data segment of valid data and a data segment of an address offset. The hardware acceleration module includes a read-write controller, a data register, an address register, and a comparison register; the data register is used to store valid data read from a plurality of structures in the storage module; the address register is used to store the address offset corresponding to the respective valid data in the plurality of structures in the storage module; the comparison register is used to compare the valid data read; the read-write controller is used to: read from the first structure in the storage module until the end of the last structure, wherein, after any one of the structures is read and any one of the structures is equal When it is not the end structure, the valid data and address offset of any one of the structures are written into the data register and the address register respectively, and the next structure corresponding to any one of the structures is read from the storage module according to the address indicated by the address offset of the any one of the structures; if it is determined that the end structure is read, the data reading of the multiple structures is terminated, and after each structure is read, all the read valid data are compared according to the comparison register to determine whether the read valid data meets the preset conditions; if it is determined according to the comparison register that the valid data meets the preset conditions, the read valid data is sent to the processing module, wherein the valid data can be traced by the processing module based on the address offset stored in the address register of the valid data.

[0005] According to a second aspect, a data reading method is provided, which is applied to a hardware acceleration module, and the hardware acceleration module is connected to a storage module and a processing module respectively, comprising: reading from the first structure in the storage module to the end of the last structure, wherein, when any one of the structures is read and the any one of the structures is not the last structure, the valid data and address offset of the any one of the structures are written to the hardware acceleration module data register and the address register of the hardware acceleration module respectively, and the next structure corresponding to the any one of the structures is read from the storage module according to the address indicated by the address offset of the any one of the structures; if it is determined that the last structure is read, the data reading of the multiple structures is terminated, and after each structure is read, all the read valid data are compared according to the hardware acceleration module comparison register to determine whether the read valid data meets a preset condition; if it is determined according to the comparison register that the valid data meets the preset condition, the read valid data is sent to the processing module, wherein the valid data can be traced by the processing module based on the address offset stored in the address register of the valid data.

[0006] According to a third aspect of an embodiment of the present application, a data reading device is provided, the device being applied to a hardware acceleration module, the hardware acceleration module being connected to a storage module and a processing module respectively, comprising: a reading unit configured to read from the first structure in the storage module until the end of the last structure, wherein, when any one of the structures is read and the any one of the structures is not the last structure, the valid data and address offset of the any one of the structures are written to the data register of the hardware acceleration module and the address register of the hardware acceleration module respectively, and the address indicated by the address offset of the any one of the structures is read from the storage module; The block reads the next structure corresponding to any one of the structures; a judging unit is used to end the data reading of the multiple structures if it is determined that the end structure is read, and compare all the read valid data according to the comparison register of the hardware acceleration module after reading each structure to determine whether the read valid data meets the preset condition; a sending unit is used to send the read valid data to the processing module if it is determined according to the comparison register that the valid data meets the preset condition, wherein the valid data can be traced by the processing module based on the address offset stored by the valid data in the address register.

[0007] According to the hardware acceleration module of the above embodiment, the hardware acceleration module is provided with a read-write controller, a data register, an address register, and a comparison register. The read-write controller reads from the first structure in the storage module connected to the hardware acceleration module until the end of the last structure. After reading the last structure and completing the data reading of multiple structures, all the valid data read are compared according to the comparison register. When it is determined that the valid data meets the preset conditions according to the comparison register, the valid data read is stored in the data register and sent to the processing module connected to the hardware acceleration module. At the same time, the address offset corresponding to the valid data read is stored in the address register. The solution of the present application enables the read-write controller of the hardware acceleration module to continuously read data from multiple structures in the storage module based on the address offset of the starting address of the valid data and the next structure in the structure, thereby avoiding the increase in reading time caused by operations such as addressing in the storage module and improving data reading efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0009] Figure 1 2 is a schematic diagram of a data reading system according to an embodiment of the present application.

[0010] Figure 2 FIG. 4 is a schematic diagram of a hardware acceleration module according to an embodiment of the present application.

[0011] Figure 3 1 is a timing diagram of data reading by a hardware acceleration module according to an embodiment of the present application.

[0012] Figure 4 It is a flowchart of a method for reading data according to an embodiment of the present application.

[0013] Figure 5 4 is a block diagram of a data reading device according to an embodiment of the present application.

[0014] Figure 6 It is a hardware structure diagram of an electronic device according to an embodiment of the present application.

[0015] The above-mentioned drawings have shown clear embodiments of the present invention, which will be described in more detail later. These drawings and textual descriptions are not intended to limit the scope of the present invention in any way, but to illustrate the concept of the present invention to computer technicians in this field through specific embodiments. DETAILED DESCRIPTION

[0016] The present invention will be further described in detail below by means of specific embodiments in conjunction with the accompanying drawings. Similar elements in different embodiments are numbered with associated similar elements. In the following embodiments, many detailed descriptions are provided to enable the present application to be better understood. However, those skilled in the art will readily appreciate that some of the features may be omitted in different circumstances, or may be replaced by other elements, materials, or methods. In some cases, some operations related to the present application are not shown or described in the specification. This is to avoid the core portion of the present application being overwhelmed by excessive descriptions, and for those skilled in the art, it is not necessary to describe these related operations in detail. They will fully understand the related operations based on the description in the specification and the general technical knowledge in the art.

[0017] In addition, the features, operations, or characteristics described in the specification may be combined in any appropriate manner to form various embodiments. Furthermore, the steps or actions in the method description may be reordered or adjusted in a manner readily apparent to those skilled in the art. Therefore, the various sequences in the specification and drawings are provided solely for the purpose of clearly describing a particular embodiment and are not intended to be mandatory, unless otherwise specified.

[0018] Component numbers used herein, such as "first" and "second," are used solely to distinguish the components being described and do not convey any sequential or technical meaning. References to "connection" and "coupling" herein, unless otherwise specified, include both direct and indirect connections (couplings).

[0019] Currently, in the field of non-volatile data storage technology, the traditional approach to managing address space fragmentation caused by firmware managing Nand Flash particles is to fragment the internal storage buff to improve internal storage buff utilization. During this operation, the internal storage buff used for data transmission between the host and Nand Flash particles will be suspended, affecting the performance of the entire chip. Alternatively, these fragmented spaces can be left alone and cleared in a centralized manner after a large amount of space storage data becomes invalid. However, the existing method leads to low data reading efficiency and insufficient storage space utilization.

[0020] In an embodiment of the present invention, a hardware acceleration module is provided with a read-write controller, a data register, an address register, and a comparison register. The read-write controller reads data from the first structure in the storage module connected to the hardware acceleration module until the end of the last structure. When the last structure is read and the data reading of multiple structures is completed, all the valid data read are compared according to the comparison register after each structure is read. When it is determined that the valid data meets the preset conditions according to the comparison register, the valid data read is stored in the data register and sent to the processing module connected to the hardware acceleration module. At the same time, the address offset corresponding to the valid data read is stored in the address register. The solution of the present application enables the read-write controller of the hardware acceleration module to continuously read data from multiple structures in the storage module based on the address offset of the starting address of the valid data and the next structure in the structure, thereby avoiding the increase in reading time caused by operations such as addressing in the storage module and improving data reading efficiency.

[0021] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically separate entities. That is, these functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices. The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily need to be executed in the order described. For example, some operations / steps may be further decomposed, while others may be combined or partially combined, so the actual execution order may vary depending on the actual situation.

[0022] See also Figure 1 , Figure 1 FIG. 1 shows a hardware acceleration module provided by an embodiment of the present application. In a specific embodiment, the hardware acceleration module 120 is connected to the storage module 110 and the processing module 130, respectively. Figure 1 As shown, the storage module stores multiple structures, each structure contains a data segment of valid data and a data segment of address offset, and the hardware acceleration module 120 includes a read-write controller 121, a data register 124, an address register 122, and a comparison register 123. Figure 2As shown, the data register is used to store the valid data read from the multiple structures in the storage module; the address register is used to store the address offset corresponding to the valid data of each of the multiple structures in the storage module; the comparison register is used to compare the valid data read; the read-write controller is used to: read from the first structure in the storage module to the end of the last structure, wherein, when any one of the structures is read and the any one of the structures is not the last structure, the valid data and address offset of the any one of the structures are written to the data register and the address register respectively, and according to The next structure corresponding to any one of the structures is read from the storage module at the address indicated by the address offset of any one of the structures; if it is determined that the end structure is read, the data reading of the multiple structures is terminated, and after each structure is read, all the read valid data are compared according to the comparison register to determine whether the read valid data meets the preset condition; if it is determined according to the comparison register that the valid data meets the preset condition, the read valid data is sent to the processing module, wherein the valid data can be traced by the processing module based on the address offset stored in the address register by the valid data.

[0023] In the current field of non-volatile data storage technology, such as EMMC, UFS, and SSD storage hardware, firmware management of Nand Flash chips requires pattern matching of data (such as indexes and addresses) stored in the continuous address space of the chip's internal cache to find the required data address or other information. Frequent operations on the internal storage buffer can lead to a high degree of address space fragmentation. As this address space fragmentation accumulates, the corresponding data in the storage space becomes distributed in a non-contiguous and scattered manner on the physical or logical storage media. This storage mode may lead to reduced access efficiency and increased management complexity, or in order to adapt to scenarios (such as distributed systems) and to improve scalability or fault tolerance, the storage space is actively set to discrete storage space, which in turn makes the data reading process complicated and the reading efficiency low. Therefore, in order to solve this problem, the solution of the present application sets up a hardware acceleration module, which is provided with a read-write controller, a data register, an address register and a comparison register, so as to read data stored in a structure of a storage module connected to the hardware acceleration module through the read-write controller, data register, address register and comparison register, and send the read valid data to the processing module connected to the hardware acceleration module, so as to realize the rapid reading of the data stored in the storage module and improve the data processing efficiency.

[0024] As a way, in order to ensure that the hardware acceleration module can read data from multiple structures stored in the storage module, a read-write controller can be set in the hardware acceleration module, so that the read-write controller can read data from multiple structures stored in the storage module based on the connection relationship between the hardware acceleration module and the storage module.

[0025] As a method to ensure that the storage space within the discrete space of the storage module can be fully utilized and to avoid the problem of inefficient data access due to the complexity of allocation and addressing of fragmented storage, multiple structures consisting of valid data and address offsets can be set to fill the corresponding discrete space. Optionally, each structure includes a data segment of valid data and a data segment of the address offset corresponding to the valid data, so that the valid data is stored in a dispersed manner in discontinuous areas, and the location of the valid data is tracked by the address offset.

[0026] Optionally, the discrete space may be first divided into blocks according to a fixed size to obtain data blocks, and then the valid data and address offsets may be stored in each of the divided data blocks. For example, the discrete space may be divided into blocks according to a size of 64 bits, so that each structure is 64 bits in size, wherein the upper 32 bits are used to store valid data and the lower 32 bits are used to store address offsets. Optionally, the storage module may be a module using SRAM, which has a certain number of address fragments inside and is filled with structures including data segments of valid data and data segments of address offsets, thereby improving the storage space utilization of the storage module.

[0027] Optionally, in order to be able to perform continuous data reading operations on multiple structures in the discrete storage space in the storage module, the read-write controller of the hardware acceleration module can read data on multiple structures in sequence, and the order in which the read-write controller reads multiple structures is to start reading from the first structure until the last structure is read, thereby completing the data reading operation on multiple structures in the storage module.

[0028] Optionally, in order to ensure that the data read by the hardware acceleration module is complete data, when the end structure is read, the read-write controller is controlled to stop the reading operation in the storage module, and the data read by the read-write controller is determined based on the comparison register to determine whether the preset conditions are met. Only when the conditions are met will the valid data read be stored in the data register in the hardware acceleration module, and the address offset of the valid address will be stored in the address register in the hardware acceleration module. At the same time, the valid data read is sent to the processing module, so that the processing module can perform processing based on the received valid data.

[0029] Optionally, in order to ensure that the data received by the processing module is complete and valid, when the read-write controller reads the last structure, all the read data from the first structure to the last structure are compared and matched to determine whether all the data read by the read-write controller meets the preset conditions, and then all the read data are sent to the processing module when it is determined that all the data meets the preset conditions.

[0030] Optionally, to accurately determine whether the data read by the read / write controller meets preset conditions, a comparison register can be set in the hardware acceleration module. After the read / write controller completes the data reading operation on multiple structures in the storage module, the preset conditions and corresponding comparison data stored in the comparison register are obtained, and then a determination is made as to whether all read data meets the preset conditions. Optionally, a pattern to be matched, such as a string, regular expression, or binary feature template, can be pre-stored in the comparison register to set the preset conditions.

[0031] Optionally, after determining that all valid data read by the read-write controller meets preset conditions, it is determined that the read-write controller has completed the reading operation of the data of multiple structures in the storage module. In order to ensure that the subsequent processing module can process the valid data, a data register and an address register can be set in the hardware acceleration module, so that the valid data is stored in the data register and the address offset corresponding to the valid data is stored in the address register, so that the valid data stored in the data register can be sent to the processing module, so that the processing module can process the valid data received from the data register.

[0032] Optionally, when the processing module is processing valid data, in order to ensure the accuracy of the processing results, the processing module can trace the valid data based on the address offset stored in the address register of the valid data, so as to know the source of the valid data and ensure that the valid data is valid. Optionally, the processing module can receive a traceability instruction sent by other processors or verify the source of the valid data during the process of processing the valid data, and can trace the valid data based on the address register in the hardware acceleration module.

[0033] Optionally, in order to ensure that the processing module can trace the address offset based on the valid data stored in the address register, the corresponding relationship between the valid data and the address offset in the structure of the storage module can be stored, or the valid data can carry the identifier of its corresponding address offset, so that the corresponding address offset can be determined based on the identifier of the valid data, and whether there is an address offset with the same identifier in the address register, so as to achieve traceability, or the address offset can also be sent to the processing module at the same time, so that the processing module can trace the valid data through the address offset.

[0034] In an embodiment of the present application, a hardware acceleration module is provided with a read-write controller, a data register, an address register, and a comparison register. The read-write controller reads data from the first structure in the storage module connected to the hardware acceleration module until the end of the last structure. When the data reading of the last structure is read and the reading of the data of multiple structures is completed, all the valid data read are compared according to the comparison register. When it is determined that the valid data meets the preset conditions according to the comparison register, the valid data read is stored in the data register and sent to the processing module connected to the hardware acceleration module. At the same time, the address offset corresponding to the valid data read is stored in the address register. The solution of the present application enables the read-write controller of the hardware acceleration module to continuously read data from multiple structures in the storage module based on the address offset of the starting address of the valid data and the next structure in the structure, thereby avoiding the increase in reading time caused by operations such as addressing in the storage module and improving data reading efficiency.

[0035] In some embodiments, the read-write controller compares all the valid data sizes read according to the comparison register to determine whether the valid data read meets the preset conditions, including: if the read-write controller determines that the last structure has been read among the multiple structures, then obtains the comparison data size configured in the comparison register; the read-write controller compares the actual data size of the valid data read with the comparison data size to obtain a comparison result; if the read-write controller determines that the comparison result indicates that the actual data size is equal to the comparison data size, then determines that the valid data read meets the preset conditions.

[0036] As a way to ensure the accuracy of the valid data received by the processing module, when the read-write controller reads the last structure and determines that the data reading operation of multiple structures of the storage module is completed, all the valid data read from the first structure to the last structure will be compared based on the comparison register. When it is determined that all the valid data read meet the preset conditions, the read-write controller will send the valid data to the processing module.

[0037] Optionally, since the pattern to be matched is stored in advance in the comparison register, such as a string, a regular expression or a binary feature template, the comparison data size corresponding to the required data indicated in the pattern to be matched in the comparison register can be directly obtained, thereby facilitating the determination of whether the valid data meets the preset conditions based on the comparison data size.

[0038] Optionally, in order to ensure the integrity of the valid data received by the processing module, the read-write controller can first determine the actual data size corresponding to all the valid data read, and then compare the actual data size with the comparison data size to determine whether the valid data actually read by the read-write controller is complete.

[0039] Optionally, when it is determined that the actual data size is equal to the comparison data size, it can be determined that all valid data read by the read-write controller is complete, thereby determining that the valid data read meets the preset conditions, and then all valid data can be stored in the data register and the address offset that meets the preset conditions can be stored in the address register, and all valid data can be sent to the processing module at the same time, so that the processing module can process the valid data according to actual needs.

[0040] Optionally, if it is determined that the actual data size is not equal to the comparison data size, it is determined that the read-write controller may have a read-write error, so the read-write controller can be controlled to re-perform the data reading operation from the first structure in the storage module, and until the end structure is read, thereby ending the data reading operation on the structure, and again determining whether the valid data read meets the preset conditions based on the comparison register.

[0041] Optionally, when it is determined that the valid data corresponding to any read structure does not meet the preset conditions, the structure can be re-read and the read valid data can be re-determined to determine whether the preset conditions are met. Alternatively, when it is determined that the valid data corresponding to any read structure does not meet the preset conditions, an error message is generated to prompt the user that the data reading failed.

[0042] In some embodiments, the read / write controller is further configured to obtain a reference data size corresponding to any one of the multiple structures in the storage module, and configure a comparison data size of the comparison register according to the reference data size.

[0043] As a method to further ensure the accuracy of valid data, when configuring the comparison register, the reference data size corresponding to any structure in the storage module can be first determined, and then the reference data size corresponding to any structure can be configured as the comparison data size in the comparison register. Alternatively, the total reference data size can be determined based on the reference data size corresponding to any structure and the number of all structures, and then the total reference data size can be configured as the comparison data size in the comparison register. This ensures that the valid data read by the read-write controller in the hardware acceleration module can be determined to be complete based on the total parameter data size actually corresponding to all structures in the storage module, avoiding the situation where the incomplete data read by the acceleration module is sent to the processing module, affecting the subsequent work of the processing module.

[0044] In some embodiments, for the multiple structures stored in the storage module, the address offset of the previous structure is the starting address of the next structure; the address offset of the last structure is an invalid address; the read-write controller is also used to determine whether the read structure is the last structure; wherein, when the read-write controller determines whether the address offset of the read structure is an invalid address, if so, it is determined that the read structure is the last structure, otherwise, it is determined that the read structure is not the last structure.

[0045] As a way, in order to improve the storage space utilization of the storage module and improve the reading efficiency of valid data, the data segment of valid data and the data segment of address offset can be included in any structure of multiple structures of the storage module, and the address indicated in the data segment of the address offset is the starting address of the next structure, that is, the valid data of the current structure and the address offset of the next structure are included in one structure, so that the next structure can be read continuously after reading the current structure without re-addressing the structure.

[0046] Optionally, in order to prevent the read-write controller of the hardware acceleration module from continuously performing data reading operations in the storage module, the corresponding address offset of the last structure among the multiple structures of the storage module is set to an invalid address, and the read-write controller is configured to end the data reading operation on the storage module when an invalid address is read.

[0047] In some embodiments, the hardware acceleration module is connected to the storage module via a direct port connection.

[0048] To improve the efficiency of the hardware acceleration module's data reads from the storage module, the hardware acceleration module and the storage module can be connected directly via a port connection. Both the hardware acceleration module and the storage module have end-to-end data transmission interfaces, allowing data to be transferred between the end-to-end hardware acceleration module and the storage module via a REQ / ACK mode, reducing the time overhead associated with the data transmission protocol.

[0049] In some embodiments, the read / write controller is further configured to read valid data corresponding to the Nth structure and an address offset of the N+1th structure from a plurality of structures within N clock signals.

[0050] As a way to ensure that the hardware acceleration module can continuously read data in the discrete space of the storage module, the valid data stored in the current structure is read within the corresponding current clock signal, so as to read the address offset of the next structure, thereby determining the location of the valid data corresponding to the next structure based on the address offset, and realizing continuous reading of multiple structures. Figure 3 As shown, the starting address of the first structure is read within the first clock signal and the first valid period of the request signal. Due to the use of an end-to-end transmission interface, the hardware acceleration module can read the valid data of the first structure and the address offset of the starting address of the next structure within the first valid period of the confirmation signal (which is also the second valid period of the request signal), and read the corresponding valid data and the address offset of the starting address of the next structure according to the read starting address of the second structure within the second clock signal and the first valid period of the confirmation signal, and so on, until the invalid address in the last structure is read.

[0051] In some embodiments, the hardware acceleration module further includes a target address register, which is used to store the address of the valid data of the first structure among the multiple structures; the read-write controller obtains the address of the valid data of the first structure from the target address register, and reads the first structure from the storage module according to the address of the valid data of the first structure.

[0052] As a way, in order to avoid the read-write controller spending a lot of time to address the first structure of multiple structures when reading data from multiple structures in the storage module, the first structure of the multiple structures can be first stored at a fixed address in the storage module, and then pre-written into the target address register in the hardware acceleration module based on the fixed address, so that the hardware acceleration module can read the valid data corresponding to the first structure and the address offset as the starting address of the next structure from the storage module based on the address of the valid data of the first structure in the target address register, thereby realizing continuous data reading of multiple structures.

[0053] In some embodiments, the read data bit width of the read / write controller is greater than the processing data bit width of the processing module.

[0054] As a way, in order to further improve the reading efficiency of the hardware acceleration module in reading data from the storage module, the processing data bit width corresponding to the processing module can be determined first, and then the read data bit width of the read-write controller can be configured based on the processing data bit width, so that the read data bit width of the read-write controller is greater than the processing data bit width of the processing module, thereby achieving higher data throughput.

[0055] As another method, the data bit width occupied by any structure in the storage module can be determined, and the read-write data bit width of the read-write controller can be set to the data bit width occupied by any structure in the storage module, so as to ensure that the read-write controller can read the data segment corresponding to the complete structure within one clock signal.

[0056] See also Figure 4 , Figure 4 The data reading method provided by an embodiment of the present application is shown. In a specific embodiment, the data reading method can be applied to Figure 5 The data reading device 300 and the electronic device 400 equipped with the data reading device 300 are shown. Figure 6 ). The specific process of this embodiment will be described below. Of course, it is understandable that the method can be executed by a computer terminal with computing and processing capabilities, or other processors, or memory chips. Figure 4 The process shown is described in detail, and the data reading method may specifically include the following steps:

[0057] Step 210: Read from the first structure in the storage module to the last structure. When any one of the structures is read and the structure is not the last structure, the valid data and address offset of the structure are written to the hardware acceleration module data register and the address register of the hardware acceleration module, respectively. The next structure corresponding to the structure is read from the storage module according to the address indicated by the address offset of the structure.

[0058] In step 220, if it is determined that the last structure has been read, the data reading of the multiple structures is terminated, and after each structure is read, all the valid data read are compared according to the comparison register of the hardware acceleration module to determine whether the valid data read meets the preset conditions.

[0059] Step 230: If it is determined according to the comparison register that the valid data meets the preset condition, the read valid data is sent to the processing module, wherein the valid data can be traced by the processing module based on the address offset stored in the address register by the valid data.

[0060] In some embodiments, the multiple structures are stored in the storage module. Among the multiple structures, each structure includes valid data and address offset, the address offset of the previous structure is the starting address of the next structure, and the address offset of the last structure is an invalid address. The method also includes: determining whether the read structure is the last structure; judging whether the address offset of the read structure is an invalid address, if so, determining that the read structure is the last structure, otherwise, determining that the read structure is not the last structure.

[0061] In an embodiment of the present application, data of multiple structures are read through a hardware acceleration module, so that continuous reading of multiple structures can be achieved based on the data segment including valid data in any structure and the address offset as the starting address of the next structure, so that valid data can be read quickly and accurately, while improving the utilization rate of storage space and the reading efficiency of valid data. When it is determined that the end structure has been read and the data reading of multiple structures is ended, it is determined whether the read valid data meets the preset conditions based on the comparison register, and the valid data is sent to the processing module only when it is determined that the preset conditions are met, thereby ensuring the accuracy of the valid data received by the processing module.

[0062] Figure 5 FIG. 1 is a block diagram of a data reading device according to an embodiment of the present application. Figure 5As shown, the data reading device 300 is applied to a hardware acceleration module, and the hardware acceleration module is connected to the storage module and the processing module respectively. The data reading device 300 includes: a reading unit 310, a judgment unit 320 and a sending unit 330.

[0063] A reading unit 310 is used to read from the first structure in the storage module to the end of the last structure, wherein, when any one of the structures is read and the any one of the structures is not the last structure, the valid data and address offset of the any one of the structures are written to the hardware acceleration module data register and the address register of the hardware acceleration module respectively, and the next structure corresponding to the any one of the structures is read from the storage module according to the address indicated by the address offset of the any one of the structures; a judgment unit 320 is used to end the data reading of the multiple structures if it is determined that the last structure is read, and after reading each structure, all the read valid data are compared according to the hardware acceleration module comparison register to determine whether the read valid data meets the preset condition; a sending unit 330 is used to send the read valid data to the processing module if it is determined according to the comparison register that the valid data meets the preset condition, wherein the valid data can be traced by the processing module based on the address offset stored in the address register of the valid data.

[0064] In some embodiments, the multiple structures are stored in the storage module. Among the multiple structures, each structure includes valid data and address offset, the address offset of the previous structure is the starting address of the next structure, and the address offset of the last structure is an invalid address. The data reading device 300 also includes: a first determination unit, used to determine whether the read structure is the last structure; a second determination unit, used to determine whether the address offset of the read structure is an invalid address. If so, it is determined that the read structure is the last structure; otherwise, it is determined that the read structure is not the last structure.

[0065] According to one aspect of the embodiments of the present application, an electronic device is also provided, such as Figure 6 As shown, the electronic device 400 includes a processor 410 and one or more memories 420. The one or more memories 420 are used to store program instructions executed by the processor 410. When the processor 410 executes the program instructions, the above-mentioned data reading method is implemented.

[0066] Furthermore, the processor 410 may include one or more processing cores. The processor 410 runs or executes instructions, programs, code sets or instruction sets stored in the memory 420, and calls data stored in the memory 420. Optionally, the processor 410 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 410 can integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. Among them, the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing display content; and the modem is used to handle wireless communications. It is understandable that the above-mentioned modem may not be integrated into the processor, but may be implemented separately through a communication chip.

[0067] According to one aspect of the present application, a computer-readable storage medium is provided. The computer-readable storage medium may be included in the electronic device described in the above embodiments, or may exist independently without being incorporated into the electronic device. The computer-readable storage medium carries computer-readable instructions. When the computer-readable storage instructions are executed by a processor, the method of any of the above embodiments is implemented.

[0068] It should be noted that the computer-readable medium described in the embodiments of this application may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more conductors, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium may include a data signal transmitted in baseband or as part of a carrier wave, which carries computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, or any suitable combination thereof.

[0069] The units involved in the embodiments described in this application may be implemented by software or hardware, and the units described may also be set in a processor. In some cases, the names of these units do not constitute limitations on the units themselves.

[0070] The above examples are used to illustrate the present invention, which are only used to help understand the present invention and are not intended to limit the present invention. Those skilled in the art can make several simple deductions, modifications or substitutions based on the concept of the present invention.

Claims

1. A hardware acceleration module, characterized in that: The hardware acceleration module is connected to the storage module and the processing module respectively. The storage module stores a plurality of structures, each of which contains a data segment of valid data and a data segment of address offset. The hardware acceleration module includes a read-write controller, a data register, an address register, and a comparison register. The data register is used to store valid data read from multiple structures in the storage module; The address register is used to store the address offset corresponding to the valid data of each of the multiple structures in the storage module; The comparison register is used to compare the valid data read; The read-write controller is used to: Reading from the first structure in the storage module to the last structure, wherein, when any one of the structures is read and the any one of the structures is not the last structure, writing the valid data and the address offset of the any one of the structures into the data register and the address register respectively, and reading the next structure corresponding to the any one of the structures from the storage module according to the address indicated by the address offset of the any one of the structures; If it is determined that the last structure is read, then the data reading of the multiple structures is terminated, and after each structure is read, all the read valid data are compared according to the comparison register to determine whether the read valid data meets the preset condition; If it is determined according to the comparison register that the valid data meets the preset condition, the read valid data is sent to the processing module, wherein the valid data can be traced by the processing module based on the address offset stored by the valid data in the address register.

2. The hardware acceleration module according to claim 1, wherein: The comparing all the valid data read according to the comparison register to determine whether the valid data read meets a preset condition includes: If the read / write controller determines that the last structure has been read from the plurality of structures, then the read / write controller obtains the size of the comparison data configured in the comparison register; The read / write controller compares the actual data size of the read valid data with the comparison data size to obtain a comparison result; If the read / write controller determines that the comparison result indicates that the actual data size is equal to the comparison data size, it determines that the read valid data meets the preset condition.

3. The hardware acceleration module according to claim 2, wherein: The read / write controller is further configured to obtain a reference data size corresponding to any one of the multiple structures in the storage module, and configure a comparison data size of the comparison register according to the reference data size.

4. The hardware acceleration module according to claim 1, wherein: For the multiple structures stored in the storage module, the address offset of the previous structure is the starting address of the next structure; the address offset of the last structure is an invalid address; The read-write controller is also used to determine whether the structure read is the end structure; wherein, when the read-write controller determines whether the address offset of the structure read is an invalid address, if so, it is determined that the structure read is the end structure, otherwise, it is determined that the structure read is not the end structure.

5. The hardware acceleration module according to claim 1, wherein: The hardware acceleration module is connected to the storage module via a direct port connection.

6. The hardware acceleration module according to claim 1, wherein: The hardware acceleration module also includes a target address register, which is used to store the address of the valid data of the first structure among the multiple structures; the read-write controller obtains the address of the valid data of the first structure from the target address register, and reads the first structure from the storage module according to the address of the valid data of the first structure.

7. The hardware acceleration module according to claim 1, wherein: The read data bit width of the read / write controller is greater than the processing data bit width of the processing module.

8. A method for reading data, characterized in that: The method is applied to a hardware acceleration module, which is connected to a storage module and a processing module respectively, and includes: Reading from the first structure in the storage module to the last structure, wherein, when any one of the structures is read and the any one of the structures is not the last structure, writing the valid data and the address offset of the any one of the structures into the data register of the hardware acceleration module and the address register of the hardware acceleration module respectively, and reading the next structure corresponding to the any one of the structures from the storage module according to the address indicated by the address offset of the any one of the structures; If it is determined that the last structure is read, the data reading of the multiple structures is terminated, and after each structure is read, all the valid data read are compared according to the comparison register of the hardware acceleration module to determine whether the valid data read meets the preset conditions; If it is determined according to the comparison register that the valid data meets the preset condition, the read valid data is sent to the processing module, wherein the valid data can be traced by the processing module based on the address offset stored by the valid data in the address register.

9. The method according to claim 8, characterized in that The multiple structures are stored in the storage module. In the multiple structures, each structure includes valid data and an address offset. The address offset of the previous structure is the starting address of the next structure, and the address offset of the last structure is an invalid address. The method further includes: Determine whether the read structure is the end structure; It is determined whether the address offset of the read structure is an invalid address. If so, it is determined that the read structure is the end structure. Otherwise, it is determined that the read structure is not the end structure.

10. A data reading device, characterized in that: The device is applied to a hardware acceleration module, which is connected to a storage module and a processing module respectively, and includes: a reading unit, configured to read from the first structure in the storage module to the last structure, wherein when any one of the structures is read and the any one of the structures is not the last structure, writing the valid data and address offset of the any one of the structures into the hardware acceleration module data register and the address register of the hardware acceleration module respectively, and reading the next structure corresponding to the any one of the structures from the storage module according to the address indicated by the address offset of the any one of the structures; a judgment unit, configured to terminate the reading of data from the multiple structures if it is determined that the last structure has been read, and compare all the valid data read according to the comparison register of the hardware acceleration module to determine whether the valid data read meets a preset condition; A sending unit is used to send the read valid data to the processing module if it is determined according to the comparison register that the valid data meets the preset condition, wherein the valid data can be traced by the processing module based on the address offset stored in the address register by the valid data.

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