Apparatus and method for notifying predictor with data object range information in pointer

Abstract

The invention relates to an apparatus and method for notifying a predictor with data object range information in a pointer. A processor of an aspect includes a cache hierarchy and a memory access unit coupled with the cache hierarchy. The memory access unit performs a demand load based on the Y-bit pointer such that the first one or more cache lines are loaded from the memory into the cache hierarchy. The Y-bit pointer has an X-bit virtual address field and a data object range field in one or more of the bits [Y-1: X]. A data object range field stores values. The processor also includes a prefetch unit coupled with the cache hierarchy. The prefetch unit determines whether to prefetch a second one or more cache lines adjacent to the first one or more cache lines from the memory into the cache hierarchy based at least in part on the value.

Description

Technical Field

[0001] Embodiments described herein generally relate to processors. Specifically, embodiments described herein generally relate to processors having a prefetch unit, an address translation unit, and other predictors. Background Art

[0002] Many processors include a prefetch unit to prefetch data (e.g., cache lines) from memory before the data is needed. The prefetcher may make predictions based on history, statistical algorithms, and so on. Correctly prefetching the data that will be needed may often help improve performance, as this may help ensure that the data is already in the cache when it is needed. Incorrectly prefetching data that is not actually needed may often degrade performance and / or increase power consumption, as prefetching data that is not needed may evict data that will actually be needed from the cache, and / or spend power loading data into the cache when the data is not actually needed. Summary of the Invention

[0003] According to one aspect of the present application, there is provided an apparatus, comprising: a cache hierarchy; a memory access unit coupled to the cache hierarchy, the memory access unit being configured to perform demand loading based on a Y-bit pointer such that a first one or more cache lines are loaded from memory into the cache hierarchy, the Y-bit pointer having an X-bit virtual address field and a data object range field in one or more bits of bits [Y-1:X], the data object range field being configured to store a value; and a prefetch unit coupled to the cache hierarchy, the prefetch unit being configured to determine whether to prefetch a second one or more cache lines adjacent to the first one or more cache lines from the memory into the cache hierarchy at least in part based on the value.

[0004] According to another aspect of the present application, there is provided a method, comprising: performing demand loading based on a Y-bit pointer, including loading a first one or more cache lines from memory into a cache hierarchy, the Y-bit pointer having an X-bit virtual address and a data object range value in one or more bits of bits [Y-1:X]; and determining whether to prefetch a second one or more cache lines adjacent to the first one or more cache lines from the memory into the cache hierarchy at least in part based on the data object range value. Brief Description of the Drawings

[0005] Various examples in accordance with the present disclosure will be described with reference to the accompanying drawings, in which:

[0006] Figure 1A block diagram of an embodiment of a processor having a prefetch unit operable to determine whether to prefetch additional cache lines from memory into a cache hierarchy based at least in part on the value of a data object range field.

[0007] Figure 2 The block diagram shows how the range of a data object maps to different slot sizes. The range of the data object is indicated by an arrow.

[0008] Figure 3 A block diagram of a first exemplary embodiment of a suitable 64-bit pointer and data object range field.

[0009] Figure 4 A block diagram of a second exemplary embodiment of a suitable 64-bit pointer and data object range field.

[0010] Figure 5 A block diagram of a third exemplary embodiment of a suitable 64-bit pointer and data object range field.

[0011] Figure 6 A block diagram of a fourth exemplary embodiment of a suitable 64-bit pointer and data object range field.

[0012] Figure 7 A block diagram of a fifth exemplary embodiment of a suitable 64-bit pointer and data object range field.

[0013] Figure 8 A block diagram of a sixth exemplary embodiment of a suitable 64-bit pointer and data object range field.

[0014] Figure 9 A block diagram of an embodiment of a processor having an exemplary cache hierarchy and a plurality of predictors at different levels of the cache hierarchy, the predictors using either the data object range field in a 64-bit virtual address pointer or the data object range field in a corresponding 64-bit physical address pointer.

[0015] Figure 10 A block diagram of a prefetch unit operable to detect a list node pointer of a linked list in code by detecting a pointer identification value in the code.

[0016] Figure 11 A block diagram of an embodiment of a processor operable to execute a prefetch instruction.

[0017] Figure 12 Illustrates an example computing system.

[0018] Figure 13The block diagram illustrates an example processor and / or system-on-chip (SoC) that may have one or more cores and have an integrated memory controller.

[0019] The block diagram of FIG. 14(A) illustrates an example in-order pipeline and an example register renaming, out-of-order issue / execution pipeline according to some examples.

[0020] The block diagram of FIG. 14(B) illustrates an example in-order architecture core and an example register renaming, out-of-order issue / execution architecture core to be included in a processor according to an example.

[0021] Figure 15 An example of the (one or more) execution unit circuits is illustrated.

[0022] Figure 16 It is a block diagram of a register architecture according to some examples.

[0023] Figure 17 An example of an instruction format is illustrated.

[0024] Figure 18 An example of an addressing information field is illustrated.

[0025] Figure 19 An example of a first prefix is illustrated.

[0026] FIGS. 20(A)-(D) illustrate how to use Figure 19 examples of the R, X, and B fields of the first prefix in

[0027] FIGS. 21(A)-(B) illustrate an example of a second prefix.

[0028] Figure 22 An example of a third prefix is illustrated.

[0029] Figure 23 The block diagram of illustrates the use of a software instruction converter according to an example, which is used to convert binary instructions in a source instruction set architecture into binary instructions in a target instruction set architecture. Detailed Description

[0030] Disclosed herein are methods, apparatuses, systems, instructions, and non-transitory machine-readable storage media that use data object range information in a pointer to notify a predictor. In the following description, numerous specific details are set forth (e.g., specific bit fields, pointer layouts, processor configurations, microarchitecture details, sequences of operations, etc.). However, embodiments can be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the understanding of the specification.

[0031] Figure 1 is a block diagram of an embodiment of a processor 100 that has a prefetch unit 112 for determining whether to prefetch additional cache lines 130 from a memory 126 into a cache hierarchy 110 based at least in part on the value of a data object range field 108 of a 64-bit pointer 104 (broadly representing a Y-bit pointer, where Y is 64 in this example but could be other numbers such as 72, 80, 128, or some other number). The data object range field can represent one or more bits in the 64-bit pointer indicating whether a data object is contained within the current cache line, or within various possible numbers of adjacent cache lines, within the same page, etc. Such an indication can be useful to a predictor so that it can better predict whether adjacent cache lines should be prefetched, or whether a TLB should be speculatively populated with additional page mappings, etc. The data object range field can also simply be referred to as a field, a set of bits, etc. Additionally, the content stored in the data object range field can also be referred to as an indicator, a value, data, etc. In some embodiments, the processor can be a general-purpose processor (e.g., the type of general-purpose microprocessor or central processing unit (CPU) used in desktop computers, laptop computers, servers, and other computer systems). Alternatively, the processor can be a specialized processor. Examples of suitable specialized processors include, but are not limited to, coprocessors, graphics processors, network processors, machine learning processors, artificial intelligence processors, cryptographic processors, embedded processors, digital signal processors (DSPs), and controllers (e.g., microcontrollers). In some embodiments, the processor can include (e.g., be disposed on) at least one integrated circuit or semiconductor die. In some embodiments, the processor can include at least some hardware (e.g., transistors, capacitors, circuits, non-volatile memory storing circuit-level instructions / control signals).

[0032] The processor includes a memory access unit 102. In various embodiments, the memory access unit can be a load unit, a load / store unit, Figure 14BThe memory access circuit 1464, gather / scatter unit, and so on. The memory access unit is operable to access data in the memory (e.g., load data from the memory). In some embodiments, the memory access unit is operable to perform a demand load 122 based on the 64-bit pointer 104. For example, the demand load may be performed in response to the processor executing a scalar load instruction, a vector load instruction, a gather instruction, a move instruction, or other instructions for loading data from the memory into the processor. The instruction may indicate the 64-bit pointer (e.g., explicitly specify or implicitly indicate a general-purpose register or other register storing the 64-bit pointer). The 64-bit pointer includes 64 bits or bit positions. Bit 0 is the least significant or lowest-order bit or bit position, and bit 63 is the most significant or highest-order bit or bit position.

[0033] The 64-bit pointer has an X-bit virtual address field 106 in bits [X-1:0] for storing the X-bit virtual address. Virtual memory is a commonly adopted memory management technique that provides an abstraction of the actual physical storage locations available on a computer and is typically used to create the illusion that there are more actual physical storage locations available than there really are. When using virtual memory, software uses virtual addresses to access data in the memory. These virtual addresses contain addresses or values that point to or indicate the virtualized locations of the data. Virtual addresses are sometimes referred to as linear addresses and broadly represent logical addresses rather than the actual physical addresses of the actual physical storage locations where the data is stored. Address translation is used to translate or convert virtual addresses to physical addresses.

[0034] The processor also includes an address translation unit 116. The address translation unit is operable to translate virtual addresses into physical addresses. The address translation unit may include one or more translation lookaside buffers (TLBs) 118. In one aspect, there may be a single TLB. In another aspect, there may be multiple TLBs at multiple different levels (e.g., relative distance from the memory access unit). The TLBs may represent caches that may cache or otherwise store previously obtained virtual-to-physical address translations. For example, after performing a page table walk to translate a virtual address into a physical address, the address translation may be cached in the TLB. If an address translation is needed again within a sufficiently short period, the address translation can be quickly retrieved from the TLB without having to repeat the slower page table walk. When loading data using a virtual address, the TLB may be checked. A TLB "hit" occurs when the appropriate address translation is stored in one or more of the TLBs. Conversely, a TLB "miss" occurs when the appropriate address translation is not stored in one or more of the TLBs. In the case of a TLB miss, the address translation unit may perform a page table walk. For example, the address translation unit may include a memory management unit (MMU), page fault handler unit or logic, page table walk unit or logic, and so on. The page table walk may walk or proceed through a set of hierarchical page tables or structures to obtain the virtual-to-physical address translation. The determined address translation may be stored in the TLB for possible future use.

[0035] The 64-bit pointer also has the most significant bits [63:X]. These bits are higher and beyond the X bits used to address a location in memory. The 64 bits of the 64-bit pointer can address a huge address space, which most applications did not need previously. More precisely, as shown here, only the least significant X-bit virtual address field is used to store the X-bit virtual address to allow addressing a smaller but sufficient address space. As an example, in certain processors available from Intel Corporation, Santa Clara, California, USA, only 48 bits or 57 bits are used for the X-bit virtual address field. As will be further discussed below, in some embodiments, the most significant bits [63:X] may be used for the data object range field 108 to store values useful for prediction.

[0036] Demand loading 122 can cause data (e.g., scalar data elements, vectors of data elements, etc.) to be loaded into one or more registers of the processor (e.g., one or more scalar general-purpose registers, one or more vector registers, etc.). Typically, demand loading can also cause a first set of one or more cache lines 128 containing the data to be loaded from memory into the cache hierarchy 110. In the illustrated example embodiment, the data is fully contained within the fifth cache line (CL5), so the first set of one or more cache lines in this example is the single cache line CL5. More generally, the number of cache lines loaded by demand loading may depend on the amount of data being loaded and / or the position of the data relative to the cache line boundaries. For example, if a data element or vector of data elements is contained within a single cache line, then a single cache line can be loaded; or if the data elements or vector of data elements being loaded span and are contained within two cache lines, then two cache lines can be loaded, and so on.

[0037] The cache hierarchy can broadly represent two or more caches at two or more different cache levels (e.g., relative distance from the memory access unit 102). In other embodiments, instead of a cache hierarchy, a single cache level may optionally be used. Including a cache hierarchy helps to improve performance. Loading data from memory tends to have a relatively high latency. Each cache can represent a relatively small, fast-access local storage that is closer to the memory access unit than memory. During operation, the cache hierarchy can be used to cache or store a subset of the data from memory that has been loaded into the processor. Subsequently, when the processor wants to read data from memory or write data to memory, the processor can first check whether a copy of the data is stored in the cache. If the data is stored in the cache, then the processor can access the data from the cache without performing a relatively slow access to the data in memory. Additionally, for the cache hierarchy to be most effective, relevant data that is likely to be needed in the near future should be stored therein. If the data needed for processing is already in the cache hierarchy, then it can be processed more quickly without having to wait for a slower access to the data from memory.

[0038] Refer again to Figure 1, embodiments in which the processor includes a prefetch unit 112. In various embodiments, the prefetch unit may be a prefetch engine, a hardware prefetcher, a prefetch circuit, and so on. The prefetch unit is operable to prefetch data (e.g., cache lines) from memory before the data is needed (e.g., anticipating a subsequent demand load such as demand load 122 as already described). Generally, the prefetcher may monitor demand loads and use past behavior / history, algorithms, heuristics, etc. to assist it in deciding whether to prefetch additional data. Correctly prefetching data that will be needed may tend to improve performance, as this may help ensure that the data is already present in the cache hierarchy when it is needed. Incorrectly prefetching data that will not actually be needed may tend to degrade performance and / or increase power consumption, as loading data that is not needed may evict data that will actually be needed from the cache, and / or spend power loading data into the cache when it will not actually be needed. Thus, improving the ability of the prefetch unit to correctly prefetch data may be useful and can provide the advantage of improving performance and / or reducing unnecessary power consumption.

[0039] As described above, the data to be loaded by demand load 122 (e.g., scalar data elements, vectors of data elements, etc.) is contained in a first set of one or more cache lines 128 that contain the data. In the illustrated example embodiment, the data is fully contained within the fifth cache line (CL5), and thus the first set of one or more cache lines in this example is the single cache line CL5. The data is part of a data object, specifically data object 2 in the illustrated example. In addition to CL5, data object 2 also includes the sixth cache line CL6, the seventh cache line CL7, and the eighth cache line CL8. Data object 2 is located between data object 1 and data object 3. Data object 1 includes the first cache line CL1, the second cache line CL2, the third cache line CL3, and the fourth cache line CL4. Data object 3 includes the ninth cache line CL9 and the tenth cache line CL10. This is just an illustrative example. Other data objects may have other amounts of data (e.g., other numbers of cache lines).

[0040] A data object can broadly represent a cohesive set of a particular type of data or a data set that is used together and is distinguishable or different in some way from surrounding data objects. Several illustrative examples of suitable types of data objects include, but are not limited to, strings, tables, arrays, linked lists, nodes of linked lists, and other types of data structures, matrices, vector arrays, and other mathematical arrangements of data, and so on. From another perspective, an object can also be a linearly contiguous region of a heap allocated by a memory allocator (e.g., via malloc / new) in a given allocation. Generally, a data object may be such that when you use a part of it (e.g., a data element, a vector, etc.), you are relatively likely to use other parts of it. For example, when you load a data element of a matrix for processing, other data elements of that matrix are also relatively likely to be processed (e.g., because the processing of the data element may be part of a larger operation on the entire matrix (e.g., multiplication, transpose, etc.)). Thus, for example, if CL5 includes a data element of a matrix loaded by demand loading, it may be appropriate to also load or prefetch CL6 through CL8 into the cache hierarchy because they contain all other data elements of that matrix and are also relatively likely to be processed in the near future. In cache terms, when using a part of a data object (e.g., CL5), the likelihood of using other parts of the data object (e.g., CL6 through CL8) is referred to as "spatial locality". In some embodiments, information about data objects (e.g., their extent, bounds, size, etc.) can be used to inform predictors (e.g., prefetch unit 112, address translation unit 116) to affect and help improve their predictions.

[0041] Referring again to Figure 1 , a 64-bit pointer also has the most significant bits [63:X]. These bits are more significant compared to the X bits used for addressing a location in memory. In some embodiments, a data object extent field can be included in one or more of the bits [63:X]. The number of one or more bits used, as well as the location of the one or more bits used, can vary widely between implementations. This may depend in part on the value of X (e.g., the value of X may vary considerably between implementations), whether the bits [63:X] are already being used or are intended to be used for another purpose, whether that purpose can be enabled and disabled, the number of one or more bits required by a particular implementation, and so on.

[0042] One or more bits of the data object range field can be used to store a value. As an example, the value can be stored in the data object range field by software (e.g., the dynamic memory allocation function malloc() in the C language or other memory allocator software). For example, software can allocate memory for data object 2 (e.g., CL5 to CL8), and then store the corresponding value based on data object 2 in the data object range field.

[0043] In some embodiments, the value in the data object range field 108 can include information useful for notifying predictors (e.g., the prefetch unit 112, the address translation unit 116, etc.) and / or improving the performance of the predictors. For example, the value can include information useful for helping the prefetch unit 112 perform the following operations: determining (e.g., predicting) whether to prefetch a second set of one or more additional adjacent cache lines 130 (e.g., CL6 to CL8) when a first set of one or more cache lines 128 (e.g., CL5) are demand-loaded 122. As another example, the value can include information useful for helping the address translation unit 116 perform the following operations: determining (e.g., predicting) whether to obtain and store in the (one or more) TLBs 118 the address translation for adjacent memory locations (e.g., those corresponding to the second set of one or more additional adjacent cache lines (e.g., CL6 to CL8)) when a first set of one or more cache lines 128 (e.g., CL5) are demand-loaded 122. In different embodiments, only one or both of the address translation unit and the prefetch unit can utilize the data object range field. As shown, the prefetch unit can optionally include a value interpretation unit 113 (e.g., circuitry or other logic) for interpreting the value from the data object range field, and the value interpretation unit 113 is coupled to a unit 114 (e.g., circuitry or other logic) for making predictions and / or decisions based on the value.

[0044] In some embodiments, the value in the data object range field 108 may include information regarding the bounds and / or boundaries and / or range and / or size and / or data volume and / or number of cache lines of data object 2 (e.g., a data object including data loaded by demand load 122 based on the 64-bit pointer 104). For example, in some embodiments, the value may include information regarding whether data object 2 is fully contained within the first set of one or more cache lines 128 (e.g., CL5) loaded by the demand load, or whether data object 2 includes an additional amount of data (e.g., a second set of one or more cache lines 130). One possible scenario is that the value is at least a first value to indicate that data object 2 including the first set of one or more cache lines 128 is contained within the first set of one or more cache lines 128, or a different second value to indicate that data object 2 is not contained within the first set of one or more cache lines 128. As another example, in some embodiments, the value may include information regarding the location of the boundary of data object 2 and / or the additional amount of data containing data object 2. One possible scenario is that the value indicates that the boundary of data object 2 is outside a certain specified or otherwise indicated number of additional adjacent cache lines or data volume (e.g., 1, 2, 3, 4, 5, 6, 7, 8, 10, 16, 32, or 64 cache lines) and / or a certain specified or otherwise indicated number of additional adjacent cache lines or data volume (e.g., 1, 2, 3, 4, 5, 6, 7, 8, 10, 16, 32, or 64 cache lines) contains data object 2. The value can be any one of two, three, four, five, six, seven, eight, or more than eight different values to provide these different types of indications.

[0045] In some embodiments, the prefetch unit 112 may be operable to determine whether to prefetch one or more additional adjacent cache lines 130 adjacent to one or more cache lines 128 loaded by the demand load 122 into the cache hierarchy 110, at least in part based on the value in the data object range field 108. For example, in the illustrated example, the value may indicate to the prefetch unit that the load includes a second set of one or more cache lines 130 including CL6 through CL8. Prefetchers typically prefetch at the cache line granularity, and thus most of the discussion herein is in terms of cache lines, although the scope of the present invention is not so limited and other implementations may of course prefetch at other granularities (e.g., half cache lines, bytes, portions of pages, etc.). This may help inform the prefetch unit as to when it should continue prefetching data or when it should stop prefetching data, based on the specified information regarding the range of data object 2 (e.g., the prefetch unit does not need to rely on historical or statistical algorithms to try to guess the range, but rather the range can be explicitly provided by software), which may help improve prefetching, help improve performance, help reduce unnecessary power consumption, etc. This may also in some cases help improve security or safety, since speculative memory accesses can be avoided or prevented before a data leak may occur when the data object range field indicates an out-of-bounds memory access.

[0046] In some embodiments, the address translation unit 116 may be operable to determine whether to obtain and store address translations in the TLB 118 for one or more additional adjacent memory locations adjacent to one or more cache lines loaded by the demand load 122, at least in part based on the value in the data object range field 108. For example, in the illustrated example, the value may indicate to the address translation unit to populate the (one or more) TLB with additional translations corresponding to the second set of one or more cache lines 130. For example, if the value indicates that the range straddles the next page and the TLB does not contain a translation for the next page, the address translation unit may decide to start a page walk. Optionally, a page table entry may be extended by one bit to indicate the termination page of a large data object, to indicate to the address translation unit not to predictively populate TLB entries for subsequent pages.

[0047] That is, in some embodiments, the data object range field and / or the values stored therein may be useful for helping predictors (e.g., prefetch unit 112, address translation unit 116) make predictions (e.g., whether to prefetch one or more adjacent cache lines, whether to obtain and store in the TLB the translation of adjacent memory locations), etc. This may help inform the address translation unit, based on the specified information about the range of data object 2, when it should obtain and store the translation in the (one or more) TLBs, or when it should not do so (e.g., the address translation unit does not need to rely on historical or statistical algorithms to try to guess the range, but the range can be explicitly provided by software), which may help improve the efficiency of obtaining address translations, help improve performance, help reduce unnecessary power consumption, etc.

[0048] Additionally, the data object range field 108 and the values therein are also included in the 64-bit pointer 104. Thus, when the pointer is available, the value is effectively immediately available. Another possible scenario might be to look up and load the value from memory (e.g., a table of tags in memory). However, such a lookup takes additional time. Providing the information in the pointer itself is generally faster.

[0049] Table 1 lists examples of the possible values and meanings of the 1-bit data object range field.

[0050] Value Meaning 0 The data object is contained within a single cache line 1 The data object is contained within multiple cache lines

[0051] Table 2 lists a first example of the possible values and meanings of the 2-bit data object range field.

[0052] Value Meaning 00 The data object is contained within a single cache line 01 The data object is contained within two cache lines 10 The data object is contained within four cache lines 11 The data object exceeds four cache lines

[0053] Table 3 lists a second example of the possible values and meanings of the 2-bit data object range field.

[0054] Value Meaning 00 The data object is contained within a single cache line 01 The data object is contained within two cache lines 10 The data object is contained within a page 11 The data object exceeds the page

[0055] Table 4 lists examples of the possible values and meanings of the 3-bit data object range field.

[0056]

[0057]

[0058] Those skilled in the art and benefiting from the present disclosure will understand that these are just a few illustrative examples of possible values and their meanings. In other examples, different meanings can be assigned to the values and / or values can be assigned to the meanings in different ways. Additionally, the meanings can be expressed at other granularities different from those shown, for example, in terms of bytes, words, parts of a page, and so on. Further, if more detailed information is desired, the values can optionally have four or more bits.

[0059] Figure 2 The block diagram of shows how the range of a data object maps to different slot sizes. The range of the data object is marked with an arrow. For the 64 - byte slot size in the bottom row, each box is a 512 - bit cache line. In this case, the range fits within one cache line, so there is no need to fetch an adjacent cache line. For the 128 - byte slot size, each box represents two 512 - bit cache lines. For the 256 - byte row, the boxes represent four cache lines, and the range fits within four cache lines. For the 512 - byte row, the boxes represent eight cache lines, and the range fits within eight cache lines. In some cases, when the number of bits in the data object range field is small, and thus the number of different granularities (e.g., number of cache lines) that can be defined is small, some unnecessary cache lines may be prefetched. For example, for the 512 - byte row, the range fits within eight cache lines, so eight cache lines can be fetched, although as the range shows, some of them are not needed. The data object range value is actually describing a slot, and due to the limited number of bits in the pointer expressing the range, this is a limitation of the resolution. There may not be enough encoding space in the range field to precisely specify the actual bounds of the data object. In this case, the prefetch unit knows the slot in which the data object fits. However, the prefetch unit can fetch a cache line adjacent to the currently accessed cache line, as long as such a cache line is still within the slot described by the data object range value and located by the address being accessed by the processor.

[0060] Figure 3FIG. 0 is a block diagram of a first exemplary embodiment of a suitable 64-bit pointer 304 and a data object range field 308. The 64-bit pointer has a 57-bit virtual address field 306 in the least significant bits [56:0] for storing a 57-bit virtual address. The most significant bit, i.e., bit 63, is a user / supervisor (U / S) bit for indicating whether the 64-bit pointer refers to data at the user-level privilege (e.g., accessible by application software) or data at the supervisor-level privilege (e.g., accessible by an operating system, hypervisor, or other supervisory system software). The 64-bit pointer also has bits [62:57]. In some embodiments, any one or more of the bits [62:57] can optionally be the data object range field 308 as described elsewhere herein. The cloud is used to indicate that the data object range field can be in any one or more of these bits, including in non-consecutive bit positions.

[0061] Figure 4 FIG. 4 is a block diagram of a second exemplary embodiment of a suitable 64-bit pointer 404 and a data object range field 405. The 64-bit pointer has a 57-bit virtual address field 406 in bits [56:0] for storing a 57-bit virtual address. Bit 63 is the user / supervisor (U / S) bit. In this embodiment, bits [60:57] are reserved for other purposes. As an example, these bits [60:57] can optionally be reserved for a memory tag field 450 to store memory tags to be used in a key-based security protection mechanism, where the memory tags in bits [60:57] should or must match those stored in a table in memory to allow memory access using the 64-bit pointer. When bits [60:57] are reserved, in some embodiments, either or both of the bits [62:61] can optionally be the data object range field 408 as described elsewhere herein. The cloud is used to indicate that the data object range field can be in any one or more of the bits [62:61]. As another option, the memory tag feature can optionally be turned off or disabled to free up some of those bits for the data object range field.

[0062] Figure 5FIG. is a block diagram of a third exemplary embodiment of a suitable 64-bit pointer 504 and a data object range field 508. The 64-bit pointer has a 48-bit virtual address field 506 in bits [47:0] for storing a 48-bit virtual address. Bit 63 is the user / supervisor (U / S) bit. The 64-bit pointer also has bits [62:48]. In some embodiments, any one or more of bits [62:48] may optionally be the data object range field 508 as described elsewhere herein. The cloud is used to indicate that the data object range field may be in any one or more of these bits, including in non-consecutive bit positions.

[0063] Figure 6 FIG. is a block diagram of a fourth exemplary embodiment of a suitable 64-bit pointer 604 and a data object range field 608. The 64-bit pointer has a 48-bit virtual address field 606 in bits [47:0] for storing a 48-bit virtual address. Bit 63 is the user / supervisor (U / S) bit. In this embodiment, bits [60:57] are reserved for another purpose (e.g., a memory tag field 650 for storing a memory tag as described previously). In some embodiments, any one or more of bits [62:61] and bits [56:48] may optionally be the data object range field 608 as described elsewhere herein. The cloud is used to indicate that the data object range field may be in any one or more of bits [62:61] and bits [56:48], including in non-consecutive bit positions. As another option, the memory tag feature may optionally be turned off or disabled to free up some of these bits for the data object range field.

[0064] Figure 7 FIG. is a block diagram of a fifth exemplary embodiment of a suitable 64-bit pointer 704 and a data object range field 708. The 64-bit pointer has a 57-bit virtual address field 706 in bits [56:0] for storing a 57-bit virtual address. In this embodiment, bit 63 is not used as the user / supervisor (U / S) bit. Rather, bit 63 is an available bit that may optionally be used for the data object range field. In some embodiments, any one or more of bits [63:57] may optionally be the data object range field 708 as described elsewhere herein. The cloud is used to indicate that the data object range field may be in any one or more of bits [63:57], including in non-consecutive bit positions.

[0065] Figure 8It is a block diagram of a sixth exemplary embodiment of a suitable 64-bit pointer 804 and a data object range field 808. The 64-bit pointer has a 48-bit virtual address field 806 in bits [47:0] for storing a 48-bit virtual address. In this embodiment, bit 63 is not used as a user / supervisor (U / S) bit. More precisely, bit 63 is an available bit that can optionally be used for the data object range field. In some embodiments, any one or more of bits [63:48] can optionally be the data object range field 808 as described elsewhere herein. The cloud is used to indicate that the data object range field can be located in any one or more of bits [63:48], including in non-consecutive bit positions.

[0066] Figure 9 It is a block diagram of an embodiment of a processor 900 that has an exemplary cache hierarchy 910 and multiple predictors at different levels of the cache hierarchy, where the predictors either use the data object range field 908 in a 64-bit virtual address pointer 904 or use the data object range field 968 in a corresponding 64-bit physical address pointer 966. The processor includes a memory access unit 902. The memory access unit can be similar or identical to Figure 1 the memory access unit 102. The memory access unit is operable to perform a demand load 922 of data from memory using the 64-bit virtual address pointer 904. The 64-bit virtual address pointer has an X-bit virtual address field 906 in bits [X-1:0] for storing an X-bit virtual address as previously described. The 64-bit virtual address pointer also has a data object range field 908 in any one or more of bits [63:X] for storing a value as previously described. The loading of the data can cause a first set of one or more cache lines to be loaded from memory into the cache hierarchy as previously described.

[0067] The illustrated exemplary cache hierarchy includes a first-level (L1) cache 961, a second-level (L2) cache 962, and a third-level (L3) cache 963. The L1 cache is closer to the memory access unit than the L2 cache, and the L2 cache is closer to the memory access unit than the L3 cache. Generally, the L1 cache is smaller than the L2 cache, and the L2 cache is smaller than the L3 cache, although this is not required. In the illustrated exemplary embodiment, the L1 and L2 caches can be located inside the core 964, while the L3 cache can be located outside the core or in a non-core 965. In some cases, the L3 cache can be shared by this core and other cores (e.g., caching data for this core and other cores) rather than being dedicated to this core. This is just one example of a suitable cache hierarchy. Other cache hierarchies can broadly include two or more caches at two or more different cache levels.

[0068] In the illustrated example embodiment, the in-core prefetch unit 912 and the in-core address translation unit 916 are at the same level as the L1 cache and / or otherwise correspond to the L1 cache 961. Additionally, the out-of-core prefetch unit 972 and the out-of-core address translation unit 974 are at the same level as the L3 cache and / or otherwise correspond to the L3 cache 963. Although not shown, there may optionally be additional in-core prefetch units and in-core address translation units at the same level as the L2 cache. The out-of-core predictors are closer to the memory than the in-core predictors or are “downstream” of the in-core predictors. These predictors may optionally be similar or identical to those described elsewhere herein (e.g., having any one or more of the same or similar characteristics), except in aspects related to the location of these predictors (e.g., in-core or out-of-core) and / or whether they use the 64-bit virtual address pointer 904 or the 64-bit physical address pointer 966. To avoid obscuring the description, the different and / or additional characteristics of the Figure 9 predictors will be described primarily without repeating all the characteristics that may optionally be the same or similar to those already described.

[0069] The in-core prefetch unit and the in-core address translation unit may use the data object range field 908 in the 64-bit virtual address pointer 904. For example, the in-core prefetch unit may determine whether to prefetch from memory into the cache hierarchy a second one or more cache lines adjacent to the first one or more cache lines loaded due to a demand load, at least in part based on the value or content of the data object range field 908 in the 64-bit virtual address pointer 904.

[0070] In contrast, the non-core prefetch unit and the non-core address translation unit may use the data object range field 968 in the 64-bit physical address pointer 966. For example, the non-core prefetch unit may determine whether to prefetch from memory into the cache hierarchy a second one or more cache lines adjacent to the first one or more cache lines loaded due to a demand load, at least in part based on the value or content of the data object range field 968 in the 64-bit physical address pointer 966. As part of address translation, the value of the data object range field 908 in the 64-bit virtual address pointer may be copied to or otherwise included in the data object range field 968 of the 64-bit physical address pointer. For the data object range fields of the 64-bit virtual address and the 64-bit physical address pointer, the same one or more bit positions or fields may optionally be used, but this is not required. Additionally, the Y-bit physical address corresponding to the X-bit virtual address and translated from the X-bit virtual address may be stored in the Y-bit physical address field 970 of the 64-bit physical address pointer. It should be understood that this is just an example. In other embodiments, the virtual address and the physical address may be provided to other levels of the memory hierarchy. As an example, the virtual address may be used only by the L1 cache, after which the physical address may be used. As another example, the physical address may be used at the L1 cache and all subsequent levels of the cache hierarchy. As yet another example, even if a virtual address is provided to a given cache level (e.g., L1, or L2, or L3), in the case where multiple virtual addresses alias to the same physical address, the physical address may be provided to that cache level (e.g., L1, or L2, or L3).

[0071] In various embodiments, the in-core and non-core prefetch units, as well as the address translation unit, may operate or coordinate together in different ways, and the scope of the present invention is not limited to any known ways in which they may operate or coordinate. How they operate together may depend on various factors, e.g., the cache hierarchy, whether the cache includes or does not include data in other caches, which level in the cache hierarchy the data is desired to be prefetched to, and so on. In one example embodiment, the in-core prefetch unit may prefetch data unless there is a reason for the non-core prefetch unit to prefetch data. One such possible reason is if the data is to be shared by multiple cores and thus it may be better to include it in the L3 cache. Another such possible reason is if the data is too large to fit in the L1 cache but may be stored in the L3 cache or the overflow may be stored in the L3 cache. In some embodiments, whether to use the in-core prefetcher or the non-core prefetcher to prefetch may depend on the amount of data to be prefetched as indicated by the data object range field. Generally, either or both of the in-core prefetcher and the non-core prefetcher may appropriately use their respective data object range fields to prefetch data according to the specific implementation. In some embodiments, the prefetcher for different cache levels may operate independently of each other.

[0072] In some embodiments, the pointer identification value may optionally be stored in a 64-bit pointer. The pointer identification value may broadly represent a value that software may use, according to convention or understanding, to identify a pointer. As a specific illustrative example, the pointer identification value may be the 8-bit value "10110100". Alternatively, any one of the other 256 possible values that can be encoded with 8 bits may instead be used. Software (e.g., A new or alternative memory allocator) can select pointer identification values (e.g., the 8-bit value "10110100") and store these pointer identification values (e.g., the 8-bit value "10110100") in all or at least some of the pointers in the code or data to help allow the pointers to be detected by a prefetch unit or other predictor. The prefetch unit or other predictor can also understand that, by convention, this 8-bit value is a pointer identification value and can scan the code (e.g., the data stream of the code into the processor) or the data and detect the pointer identification values (e.g., instances of the 8-bit value "10110100") in 64-consecutive-bit portions of the code and infer that they are 64-bit pointers. In some cases, the prefetch unit or other predictor can scan data locations that are naturally aligned to an 8-byte boundary based on the convention that 64-bit pointers are aligned to an 8-byte boundary to avoid the inefficiency of scanning for pointers at all possible data alignments. Including a pointer identification value in a pointer may help allow a prefetch unit or other predictor to be able to determine the location of a pointer in many different kinds of code or data structures, including complex data structures or arrangements (e.g., linked list data structures). It is not required that all pointers have a pointer identification value to allow them to be detected and prefetched. Rather, software (e.g., a memory allocator) can intelligently select a subset of the pointers that have a pointer identification value. For example, the software can select the subset to include those pointers that are considered relatively likely to be utilized to achieve better performance by identifying which data is most likely to be used in a particular program flow and thus which data is relatively more suitable for processor prefetching.

[0073] There is a statistical likelihood that the 8-bit value "10110100" may occur naturally or coincidentally in the code other than being placed in a pointer by software. That is, false positives may occur, i.e., detecting the 8-bit value "10110100" does not truly detect a pointer. However, the more bits the pointer identification value has, the more unique or rare its coincidental occurrence is, and thus the less likely a false positive is. Generally, to keep the number of false positives relatively low, it may be better if the pointer identification value includes at least six bits, at least seven bits, or more than seven bits (e.g., 8 bits, 9 bits, or more bits). Representatively, for a 7-bit pointer identification value, such a false positive may occur approximately once every 128 detections of an 8-bit pointer identification value (e.g., 2 to the 7th power), for an 8-bit pointer identification value, such a false positive may occur approximately once every 256 detections of an 8-bit pointer identification value (e.g., 2 to the 8th power), and so on. Any bits described elsewhere in this document can be used to store the pointer identification value (e.g., Figure 5 the bits [62:48] in Figure 7Bits [63:57], etc.). Additionally, even with 5-level paging, it may include the S-bit and the most significant linear address bit (hereinafter referred to as the "S'-bit") defined by Intel's Linear Address Space Separation (LASS) to produce an 8-bit value, since the S and S' values are complementary to each other and, when combined with the remaining 6 higher-order bits, can be used by hardware to identify pointers in code or data streams. Other bit patterns may be implied for identifying addresses, for example, for a string of zeros for the higher-order address bits when the program does not map these linear addresses (since it only uses a small amount of memory).

[0074] Figure 10 is a block diagram of a prefetch unit 1012 that is operable to detect a list node pointer 1106 of a linked list 1077 in code 1076 by detecting a pointer identification value 1080 in the code. The linked list includes a first list node 1078-1 and a first list node pointer 1006-1. The first list node pointer points to a second list node 1078-2 having a second list node pointer 1006-2. The second list node pointer points to a third list node 1078-3 having a third list node pointer 1006-3. The third list node pointer may point to further list nodes (not shown). The first list node pointer has a pointer identification value 1080-1 (e.g., an 8-bit value 01010101). Similarly, the second list node pointer has the same identification value 1080-2, and the third list node pointer has the same identification value 1080-3. For example, when allocating the next node in the list, the pointer identification value may be included in the pointer returned by malloc / new. In the illustrated example, the first list node pointer further includes an optional data object range field 1008-1, the second list node pointer further includes an optional data object range field 1008-2, and the third list node pointer further includes an optional data object range field 1008-3. If there are sufficient bits available after including the pointer identification value in the pointer, it may generally be advantageous to also include a data object range field in the pointer to provide the prefetcher with information about the range of its associated data object, as described elsewhere herein. However, the pointer identification value may alternatively be used without using the data object range field.

[0075] The prefetch unit 1012 can examine the code 1076, detect the pointer identification value 1080, and thereby locate the first, second, and third list node pointers 1006. For example, when the prefetcher sees a pointer identification value (e.g., in a cache line), it can infer that it is included in a pointer. Once the pointer is located, the prefetcher can then use the pointer to prefetch data. For example, the prefetcher can traverse or follow the list node pointers of a linked list and prefetch the cache lines and / or data objects indicated by the list node pointers in advance. Although linked lists are often non - contiguous in memory. Without a pointer identification code, it is often difficult for the prefetch unit to detect and traverse or follow the pointers of such linked lists. As shown, the prefetch unit can optionally include a pointer identification value detection unit 1082 (e.g., circuitry or other logic) to detect the pointer identification value.

[0076] In some embodiments, when a data object range field 1008 is included, the prefetch unit can use the value in the data object range field to obtain an amount of data (e.g., cache lines) based on information about the range of the data object pointed to by the list node pointer. As an example, in the illustrated example, the first data object range field 1008 - 1 can notify the prefetch unit to prefetch a single cache line of the second list node 1078 - 2 at the location pointed to by the first list node pointer, the second data object range field 1008 - 2 can notify the prefetch unit to prefetch four cache lines of the third list node 1078 - 3 at the location pointed to by the second list node pointer, the third data object range field 1008 - 3 can notify the prefetch unit to prefetch two cache lines at the location pointed to by the third list node pointer, and so on. As shown, the prefetch unit can optionally include circuitry or other logic 1014 to determine whether to prefetch one or more additional cache lines based on the data object range field / value.

[0077] Figure 11 is a block diagram of an embodiment of a processor 1100 that is operable to execute prefetch instructions 1182. The processor is coupled to a memory 1126. The processor can receive prefetch instructions. The prefetch instructions can represent macro instructions, machine code instructions, or other instructions of the processor's instruction set. The prefetch instructions can have various formats or encodings, e.g., those further described below (e.g., for Figures 17 - 22 ). The instruction has one or more fields for an opcode that at least partially or fully specifies the operation to be performed. In some embodiments, the prefetch instructions can have a new prefix to modify the behavior of existing prefetch instructions to have the new features described below in connection with data object range value and memory tag comparison.

[0078] In some embodiments, a prefetch instruction may explicitly specify (e.g., via one or more fields or a set of bits) or otherwise indicate (e.g., implicitly indicate) the 64-bit pointer 1104. As an example, an instruction may have one or more fields or one or more sets of bits to specify a general-purpose register 1183 in which to store the 64-bit pointer. As another example, a prefetch instruction (e.g., its opcode) may implicitly indicate the general-purpose register in which to store the 64-bit pointer, without the prefetch instruction having any non-opcode fields or bits to specify the general-purpose register. In some embodiments, a prefetch instruction may optionally specify the cache level in which to store data, but this is not required. In some embodiments, a prefetch instruction may not specify or otherwise indicate a destination register. That is, a prefetch instruction may be an instruction that prefetches data into the cache hierarchy 1110 in advance without loading a data demand into a register of the processor. A prefetch instruction may be placed in the code (e.g., by a compiler) well before such a subsequent demand-load instruction, such that by the time the demand-load instruction is executed, the data needed and the data needed based on the data object range field are already in the cache hierarchy 1110.

[0079] General-purpose register 1183 may represent an architecturally visible register or architectural register visible to software and / or the programmer, and / or may be a register identified by an instruction of the processor's instruction set to identify an operand. Such architectural registers contrast with other non-architectural registers in the microarchitecture (e.g., temporary registers, reorder buffers, retirement registers, etc.). General-purpose registers may be implemented in different ways in different microarchitectures and are not limited to any particular design. Examples of suitable types of registers include, but are not limited to, dedicated physical registers, dynamically allocated physical registers using register renaming, and combinations thereof.

[0080] The 64-bit pointer 1104 includes an X-bit virtual address 1106 and a data object range field value 1108. These may be similar or identical to those discussed elsewhere herein. For example, the data object range field value 1108 may be similar or identical to any one or more of the data object range fields 108, 308, 408, 508, 608, 708, 808, and 908. In some embodiments, the 64-bit pointer may optionally have a memory tag 1150, although this is not required. In one embodiment, the memory tag 1150 is similar or identical to the memory tag stored in the memory tag field 450, although other memory tags are also suitable.

[0081] The processor includes a decoding unit 1184 (e.g., decoding circuitry). The decoding unit can be coupled to receive prefetched instructions. The decoding unit is operable to decode the prefetched instructions into one or more lower-level control signals, operations, or decoded instructions (e.g., one or more microinstructions, micro-operations, microcode entry points, etc.). The decoding unit and / or its instruction recognition and decoding logic can be implemented using various instruction decoding mechanisms, including but not limited to microcode read only memory (ROM), look-up tables, hardware implementations, programmable logic arrays (PLAs), other mechanisms suitable for implementing the instruction decoding unit, and combinations thereof. In some embodiments, the decoding unit can include at least some hardware (e.g., transistors, integrated circuits, on-die read only memory or other non-volatile memory storing microcode or other hardware-level instructions, or any combination thereof). In some embodiments, the decoding unit can be included on a die, integrated circuit, or semiconductor substrate.

[0082] The execution unit 1185 (e.g., execution circuitry) is coupled to the decoding unit 1184 (e.g., to receive one or more lower-level control signals, operations, or decoded instructions). The execution unit is also coupled to access a 64-bit pointer (e.g., coupled to a general register). In some embodiments, the execution unit can be located on the die or integrated circuit together with the decoding unit. The execution unit is operable to perform operations corresponding to the prefetched instructions 1182. For example, one or more lower-level control signals, operations, or decoded instructions can be executed by the execution unit to control the execution unit to perform operations corresponding to the prefetched instructions (e.g., operations at least partially specified by the opcode of the prefetched instructions). In some embodiments, the execution unit can be implemented as part of and / or together with a cache controller. In other embodiments, the execution unit can be implemented as part of and / or together with a prefetch unit. For memory access instructions (e.g., load instructions, gather instructions, etc.), operations similar or analogous to those described for the prefetched instructions can be performed. Some embodiments can use alternative or enhanced encodings for memory access instructions, e.g., by adding or modifying certain prefixes, to select to enter or exit such operations.

[0083] The execution unit can receive the 64-bit pointer 1104. The X-bit virtual address 1106 can indicate a first memory location 1186-1. For example, the X-bit virtual address can be translated into a corresponding physical address pointing to the first memory location. As shown, the first through fourth memory locations 1186-1 to 1186-4 are in the memory.

[0084] In some embodiments, when an optional memory tag 1150 is included, each memory location has associated memory tags 1187-1 through 1187-4. For example, a first memory tag 1187-1 may correspond to a first memory location 1186-1, a second memory tag 1187-2 may correspond to a second memory location 1186-2, and so on. In some cases, the memory tags may optionally be stored in these memory locations. In other cases, the memory tags may be stored in a table (e.g., a memory tag table) and may be looked up based on the address used to access the memory location. In different embodiments, the memory tags may be mapped to the memory locations with different granularities. In some embodiments, each memory tag may be mapped to a different respective 128-bit memory location, although larger or smaller granularities may alternatively be used (e.g., the memory tags may be mapped to 64-bit memory locations, half cache lines, cache lines, etc.).

[0085] In some embodiments, when an optional memory tag 1150 is included, before the execution unit can load data from a first memory location 1186-1, the execution unit and / or the processor may compare the memory tag 1150 with the first memory tag 1187-1. These two memory tags may be used for a lock-and-key type of security or protection mechanism, where the ability to load data from the first memory location 1186-1 is conditioned on the two memory tags being compatible (e.g., matching). Similarly, each other memory location may use this lock-and-key type of security or protection mechanism with its respective tag. If the two tags are compatible (e.g., match), then the data in the first memory location may be accessed (e.g., loaded into the cache hierarchy 1110 and / or the processor). If the two tags are not compatible (e.g., do not match), then the data in the first memory location may not be accessed (e.g., may not be loaded into the cache hierarchy and / or the processor). In some cases, when the tags do not match, an exception condition (e.g., an exception, a fault, a memory access privilege violation, etc.) may also be triggered. Some embodiments may optionally allow access to the data in the first memory location (e.g., load it into the cache hierarchy and / or the processor), and then generate an exception and / or record in a register that a mismatch has occurred.

[0086] In some embodiments, the execution unit may also operate to load an amount of data 1130 (e.g., one or more cache lines) based on the data object range value 1108 into the cache hierarchy 1110. The amount of data may include data loaded from a first memory location 1186-1 indicated by a 64-bit pointer and data from adjacent memory locations based on the data object range value. In some embodiments, the amount of data may be loaded into a specific level of the cache hierarchy specified by a prefetch instruction, although this is not required. In some embodiments, when an optional memory tag 1150 is included, the memory tag 1150 may be compared with the corresponding tags of each additional memory location loaded (e.g., memory locations 1186-2, 1186-3, 1186-4, etc.) before loading the data at that memory location. In some embodiments, even if the loaded memory tags are not compared with the optional memory tag 1150, memory tags 1187-1, 1187-2, etc. may be loaded for the purpose of predicting what prefetch operations will be effective for optimizing performance. For example, if software first accesses memory location 1186-1 and the processor is deciding whether to prefetch memory location 1186-2, the processor may load memory tags 1187-1 and 1187-2, and if the two loaded memory tags are the same, predict that the pending prefetch is useful, or if the two loaded memory tags are different, predict that the pending prefetch may not be needed (e.g., if tag 1187-1 is different from tag 1187-2, infer that an object boundary may have been crossed). It is not required that the memory tags be stored in a separate table in memory. As another option, it may also be possible to store the tags at least in some bits that are typically used for error correction codes or other such metadata for data at associated memory locations. Memory tags may be accessed in parallel with accessing data (e.g., prefetching data may also prefetch memory tags). Memory tags may optionally be stored in the cache hierarchy as metadata. The prefetch unit may determine whether the memory tag of a previous cache line (e.g., a cache line loaded by a demand load) matches the memory tag of an adjacent prefetch cache line. If the processor provides the correct memory tag value for accessing a cache line (e.g., as part of a physical address or associated metadata), the prefetch unit may check whether the subsequent memory tag associated with the cache line has changed, and if it has changed, select not to prefetch the previous or subsequent cache line adjacent to the different memory tag value because it will likely have a tag value different from the access tag value. For example, if the prefetch unit discovers a different tag value at the beginning of the current cache line, it knows not to prefetch the cache line adjacent on that side. If the prefetch unit discovers a different tag value at the end of the current cache line, it knows not to prefetch the cache line adjacent on that side.If both ends of the current cache line have tags different from the current tag used to access the cache line, the prefetcher knows not to prefetch adjacent lines on either side. In some embodiments, one or more of the memory addressing levels such as linear, physical, guest physical, and / or host physical may be used to index and map the memory tags 1187-1, 1187-2, and so on.

[0087] Performing prefetching in response to a prefetch instruction (e.g., rather than performing prefetching with a prefetch unit without a prefetch instruction) may provide certain advantages for some implementations. For example, the instruction can directly access the data object range value, and in some cases, passing the range information to the hardware by the instruction may be more efficient in the hardware compared to the prefetcher needing to observe other accesses using such a pointer (e.g., the interference with the performance and area-critical memory access stream in the microarchitecture may be smaller).

[0088] In some embodiments, pointer arithmetic may be restricted based on the data object range value as described elsewhere herein. In some embodiments, a pointer arithmetic instruction is operable to cause the processor and / or execution unit to use the data object range value to determine whether a pointer arithmetic operation should be allowed or blocked due to exceeding the range indicated by the data object range value. When the range will be exceeded, the instruction may generate an exception condition (e.g., an exception, a fault, an error). Thus, the data object range value serves not only as a hint for performance improvement purposes but also as a protection. There may also be some incompatible programs because pointing just past the end of an allocation at the end of a for loop is a valid and common software idiom even if the pointer value will not be dereferenced. To enhance compatibility, some embodiments may allow such pointer arithmetic. Some embodiments may further encode into the pointer when it has exceeded its authorized bounds so that dereferencing will not be allowed in that state. Other embodiments may allow the pointer value to further stray beyond the object bounds while still preventing it from being dereferenced.

[0089] In other embodiments, pointer arithmetic may be restricted based on a violation check failure. Intel's Linear Address Space Separation (LASS) describes S bits that, as part of a violation check, are compared with one or more address bits, where the most significant of these bits is hereinafter referred to as the S' bit. The S bits and the S' bit, and perhaps some additional address bits, should all be zero or all be one, depending on whether the pointer refers to user-level memory or supervisor-level memory. In some embodiments, pointer arithmetic instructions are operable to cause the processor and / or execution unit to use the violation check and / or violation check bits to determine whether a pointer arithmetic operation should be allowed or blocked due to being outside the allowed range indicated by the position of the violation check bits. The violation check bits (e.g., the S' bit) may be physically or logically shifted to a position that just captures the allowed range of the least significant address bits representing the range of addresses within which a data object is contained (e.g., the address of a cache line). As long as pointer arithmetic on the least significant bits of the pointer keeps the pointer still within the range of the data object, the position of the violation check bits (e.g., the S' bit) can be such that its value is not changed (e.g., remains zero or one). However, when pointer arithmetic on the least significant bits of the pointer causes the pointer to point outside the range of the data object, the position of the violation check bits (e.g., the S' bit) can be such that its value is changed (e.g., from zero to one, or from one to zero). This flipping or change of the violation check bits (e.g., the S' bit) may cause it to become inconsistent with other violation check bits (e.g., the S bits), potentially causing the violation check to fail and resulting in an exception condition (e.g., an exception, an error, etc.). Intel's Linear Address Masking (LAM) may cause the processor to ignore the content of certain pointer bits during a violation check, with the effect of shifting the S' bit to a lower significant bit position below the slice of the pointer that is ignored. Changing the position of the S' bit to detect pointer arithmetic outside a specified data range will further shift the S' bit to an even lower significant bit position.

[0090] This change in the value of the normalization check bit (e.g., the S' bit) and / or the failure of the normalization check can act as a tripwire to detect when pointer arithmetic operations have caused the range of a data object to be exceeded and can be used to prevent pointer arithmetic operations (e.g., by causing an exceptional condition). If the normalization check does not fail, the S' bit can be effectively removed or stripped, thus concatenating the regular address bits and using the regular address bits to perform data access. As another option, instead of moving the normalization check bit (e.g., the S' bit), an alternative would be to XOR the normalization check bit (e.g., the S' bit) in its regular bit position (e.g., bit 56 or bit 47) with the bit value of the address bit at the bit position at the end of the marked allowed range. In other words, the value of the S' bit (e.g., bit position 56) and the value of the address bit (e.g., the sixth least significant bit position) can be XORed. This may help provide results similar to moving the S' bit without actually moving the S' bit. This can allow the S' bit to remain in its regular position while all the least significant bits remain as true address bits without having to move the S' bit into the least significant address bits as an intermediate normalization check bit.

[0091] Example computer architecture.

[0092] The example computer architecture is described in detail below. Other system designs and configurations known in the art for laptop computers, desktop computers, handheld personal computers (PCs), personal digital assistants, engineering workstations, servers, blade servers, network devices, network hubs, switches, routers, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular telephones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, various systems or electronic devices capable of incorporating the processors and / or other execution logic disclosed herein are suitable.

[0093] Figure 12An example computing system is illustrated. The multi-processor system 1200 is an interface system and includes multiple processors or cores, including a first processor 1270 and a second processor 1280 coupled via an interface 1250 (e.g., a point-to-point (P-P) interconnect, a fabric, and / or a bus). In some examples, the first processor 1270 and the second processor 1280 are homogeneous. In some examples, the first processor 1270 and the second processor 1280 are heterogeneous. Although the example system 1200 is shown as having two processors, the system can have three or more processors, or can be a single-processor system. In some examples, the computing system is a system on a chip (SoC).

[0094] Processors 1270 and 1280 are shown as including integrated memory controller (IMC) circuits 1272 and 1282, respectively. Processor 1270 also includes interface circuits 1276 and 1278; similarly, the second processor 1280 includes interface circuits 1286 and 1288. Processors 1270, 1280 can exchange information via interface circuits 1278, 1288 through interface 1250. IMCs 1272 and 1282 couple processors 1270, 1280 to their respective memories, namely memory 1232 and memory 1234, which can be part of the main memories locally attached to the respective processors.

[0095] Processors 1270, 1280 can each use interface circuits 1276, 1294, 1286, 1298 to exchange information with a network interface (NW I / F) 1290 via respective interfaces 1252, 1254. The network interface 1290 (e.g., one or more of an interconnect, a bus, and / or a fabric, which is a chipset in some examples) can optionally exchange information with a coprocessor 1238 via an interface circuit 1292. In some examples, the coprocessor 1238 is a dedicated processor, such as a high-throughput processor, a network or communication processor, a compression engine, a graphics processor, a general purpose graphics processing unit (GPGPU), a neural-network processing unit (NPU), an embedded processor, and so on.

[0096] A shared cache (not shown) may be included in either processor 1270, 1280, or outside both processors but connected to these processors via an interface (such as a P-P interconnect), such that: if a processor is placed in a low power mode, the local cache information of either or both processors can also be stored in the shared cache.

[0097] Network interface 1290 may be coupled to first interface 1216 via interface circuit 1296. In some examples, first interface 1216 may be an interface such as a Peripheral Component Interconnect (PCI) interconnect, a PCI Express interconnect, or another I / O interconnect. In some examples, first interface 1216 is coupled to a power control unit (PCU) 1217, which may include circuitry, software, and / or firmware to perform power management operations regarding processors 1270, 1280, and / or coprocessor 1238. PCU 1217 provides control information to a voltage regulator (not shown) such that the voltage regulator generates an appropriate regulated voltage. PCU 1217 also provides control information to control the generated operating voltage. In various examples, PCU 1217 may include various power management logic units (circuits) to perform hardware-based power management. Such power management may be fully controlled by the processor (e.g., controlled by various processor hardware and may be triggered by workload and / or power constraints, thermal constraints, or other processor constraints), and / or power management may be performed in response to an external source (e.g., a platform or power management source or system software).

[0098] PCU 1217 is illustrated as existing as a logic separate from processors 1270 and / or processor 1280. In other cases, PCU 1217 may execute on one or more given cores in the core (not shown) of processor 1270 or 1280. In some cases, PCU 1217 may be implemented as a microcontroller (dedicated or general-purpose) or other control logic that is configured to execute its own dedicated power management code (sometimes referred to as P-code). In still other examples, the power management operations to be performed by PCU 1217 may be implemented outside the processor, such as by a separate power management integrated circuit (PMIC) or another component outside the processor. In still other examples, the power management operations to be performed by PCU 1217 may be implemented within the BIOS or other system software.

[0099] Various I / O devices 1214 and a bus bridge 1218 can be coupled to a first interface 1216, and the bus bridge couples the first interface 1216 to a second interface 1220. In some examples, one or more additional processors 1215 are coupled to the first interface 1216, such as a coprocessor, a high throughput many integrated core (MIC) processor, a GPGPU, an accelerator (such as a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array (FPGA), or any other processor. In some examples, the second interface 1220 can be a low pin count (LPC) interface. Various devices can be coupled to the second interface 1220, and these devices include, for example, a keyboard and / or a mouse 1222, a communication device 1227, and a storage circuit 1228. The storage circuit 1228 can be one or more non-transitory machine-readable storage media as described below, such as a disk drive or other mass storage device, which can include instructions / code and data 1230 in some examples and can implement the storage device `ISAB03. Additionally, audio I / O 1224 can be coupled to the second interface 1220. Note that architectures other than the above-described point-to-point architecture are also possible. For example, a system such as the multi-processor system 1200 can implement a multi-drop interface or other such architectures instead of the point-to-point architecture.

[0100] Example core architectures, processors, and computer architectures.

[0101] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, the implementations of these cores can include: 1) general-purpose in-order cores, for general computing purposes; 2) high-performance general-purpose out-of-order cores, for general computing purposes; 3) specialized cores, mainly for graphics and / or scientific (throughput) computing purposes. The implementations of different processors can include: 1) CPUs, including one or more general-purpose in-order cores for general computing purposes and / or one or more general-purpose out-of-order cores for general computing purposes; and 2) coprocessors, including one or more specialized cores mainly for graphics and / or scientific (throughput) computing purposes. These different processors result in different computer system architectures, which can include: 1) the coprocessor and the CPU on separate chips; 2) the coprocessor and the CPU on separate dies within the same package; 3) the coprocessor and the CPU on the same die (in this case, such a coprocessor is sometimes referred to as specialized logic, such as integrated graphics and / or scientific (throughput) logic, or as a specialized core); and 4) a system on a chip (SoC), which can be included on the same die as the described CPU (sometimes referred to as the (one or more) application cores or the (one or more) application processors), the above-mentioned coprocessor, and additional functions. Example core architectures are described next, followed by a description of example processors and computer architectures.

[0102] Figure 13 FIG. illustrates a block diagram of an example processor and / or SoC 1300, which can have one or more cores and have an integrated memory controller. The processor 1300 illustrated by the solid-line block diagram has a single core 1302(A), a system agent unit circuit 1310, and a set of one or more interface controller unit circuits 1316, while the optionally added dashed-line block diagram illustrates an alternative processor 1300 as having multiple cores 1302(A)-(N), a set of one or more integrated memory control unit circuits 1314 in the system agent unit circuit 1310, specialized logic 1308, and a set of one or more interface controller unit circuits 1316. Note that the processor 1300 can be Figure 12 one of the processors 1270 or 1280 or the coprocessors 1238 or 1215.

[0103] Thus, different implementations of the processor 1300 can include: 1) a CPU, where the dedicated logic 1308 is integrated graphics and / or scientific (throughput) logic (which can include one or more cores, not shown), and the cores 1302(A)-(N) are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, or a combination of both); 2) a coprocessor, where the cores 1302(A)-(N) are a large number of dedicated cores mainly for graphics and / or scientific (throughput) purposes; and 3) a coprocessor, where the cores 1302(A)-(N) are a large number of general-purpose in-order cores. Thus, the processor 1300 can be a general-purpose processor, a coprocessor, or a special-purpose processor, such as a network or communication processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput integrated many-core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor can be implemented on one or more chips. The processor 1300 can be part of one or more substrates and / or can be implemented on one or more substrates using any of a variety of process technologies, such as complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

[0104] The memory hierarchy includes one or more levels of cache unit circuits 1304(A)-(N) within cores 1302(A)-(N), a group of one or more shared cache unit circuits 1306, and an external memory (not shown) coupled to the group of integrated memory controller unit circuits 1314. The group of one or more shared cache unit circuits 1306 may include one or more intermediate-level caches, such as a second-level (L2), third-level (L3), fourth-level (L4) or other level of cache, such as a last level cache (LLC), and / or combinations thereof. Although in some examples interface network circuit 1312 (e.g., a ring interconnect) provides an interface to dedicated logic 1308 (e.g., integrated graphics logic), the group of shared cache unit circuits 1306, and system agent unit circuit 1310, alternative examples use any number of well-known techniques to provide an interface to these units. In some examples, coherence is maintained between one or more circuits in the shared cache unit circuits 1306 and the cores 1302(A)-(N). In some examples, interface controller unit circuit 1316 couples these cores 1302 to one or more other devices 1318, such as one or more I / O devices, storage devices, one or more communication devices (e.g., wireless networks, wired networks, etc.), and so on.

[0105] In some examples, one or more of the cores 1302(A)-(N) have multithreading capabilities. System agent unit circuit 1310 includes those components that coordinate and operate the cores 1302(A)-(N). System agent unit circuit 1310 may include, for example, a power control unit (PCU) circuit and / or a display unit circuit (not shown). The PCU may be or may include the logic and components needed to regulate the power states of the cores 1302(A)-(N) and / or the dedicated logic 1308 (e.g., integrated graphics logic). The display unit circuit is used to drive one or more externally connected displays.

[0106] The cores 1302(A)-(N) may be homogeneous with respect to an instruction set architecture (ISA). Alternatively, the cores 1302(A)-(N) may be heterogeneous with respect to the ISA; that is, a subset of the cores 1302(A)-(N) may be capable of executing one ISA, while other cores may be capable of executing only a subset of that ISA or may be capable of executing another ISA.

[0107] Example core architectures - in-order and out-of-order core block diagrams.

[0108] The block diagram of FIG. 14(A) illustrates an example in-order pipeline and an example register renaming, out-of-order issue / execution pipeline, both according to some examples. The block diagram of FIG. 14(B) illustrates an example in-order architecture core and an example register renaming, out-of-order issue / execution architecture core, both to be included in a processor, according to an example. Figures 14(A) - 14(B) The solid boxes in Figures 14(A) - 14(B) illustrate the in-order pipeline and in-order core, while the optional addition of the dashed boxes illustrates the register renaming, out-of-order issue / execution pipeline and core. Given that the in-order aspects are a subset of the out-of-order aspects, the out-of-order aspects will be described.

[0109] In FIG. 14(A), the processor pipeline 1400 includes a fetch stage 1402, an optional length decoding stage 1404, a decode stage 1406, an optional allocation (Alloc) stage 1408, an optional rename stage 1410, a schedule (also known as dispatch or issue) stage 1412, an optional register read / memory read stage 1414, an execution stage 1416, a write-back / memory write stage 1418, an optional exception handling stage 1422, and an optional commit stage 1424. One or more operations may be performed in each of these processor pipeline stages. For example, during the fetch stage 1402, one or more instructions are fetched from an instruction memory, and during the decode stage 1406, the fetched one or more instructions may be decoded, an address using a forwarding register port (e.g., a load store unit (LSU) address) may be generated, and branch forwarding (e.g., immediate offset or link register (LR)) may be performed. In one example, the decode stage 1406 and the register read / memory read stage 1414 may be combined into one pipeline stage. In one example, during the execution stage 1416, the decoded instructions may be executed, LSU address / data pipelining to an Advanced Microcontroller Bus (AMB) interface may be performed, multiplication and addition operations may be performed, arithmetic operations with branch results may be performed, and so on.

[0110] As an example, the exemplary register renaming, out-of-order issue / execution architecture core of FIG. 14(B) may implement pipeline 1400 in the following manner: 1) Instruction fetch circuitry 1438 performs fetch and length decoding stages 1402 and 1404; 2) Decoding circuitry 1440 performs decoding stage 1406; 3) Rename / allocator unit circuitry 1452 performs allocation stage 1408 and rename stage 1410; 4) (One or more) scheduler circuitry 1456 performs scheduling stage 1412; 5) (One or more) physical register file circuitry 1458 and memory unit circuitry 1470 perform register read / memory read stage 1414; (One or more) execution clusters 1460 perform execution stage 1416; 6) Memory unit circuitry 1470 and (one or more) physical register file circuitry 1458 perform writeback / memory write stage 1418; 7) Various circuitry may be involved in exception handling stage 1422; and 8) Retirement unit circuitry 1454 and (one or more) physical register file circuitry 1458 perform commit stage 1424.

[0111] FIG. 14(B) shows that processor core 1490 includes a front-end unit circuitry 1430 coupled to an execution engine unit circuitry 1450, and both are coupled to a memory unit circuitry 1470. Core 1490 may be a reduced instruction set architecture computing (RISC) core, a complex instruction set architecture computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As another option, core 1490 may be a specialized core, such as a network or communication core, a compression engine, a coprocessor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, and so on.

[0112] The front-end unit circuit 1430 may include a branch prediction circuit 1432, which is coupled to an instruction cache circuit 1434, which is coupled to an instruction translation lookaside buffer (TLB) 1436, which is coupled to an instruction fetch circuit 1438, which is coupled to a decoding circuit 1440. In one example, the instruction cache circuit 1434 is included in the memory unit circuit 1470 rather than in the front-end circuit 1430. The decoding circuit 1440 (or decoder) may decode the instruction and generate one or more micro-operations, microcode entry points, micro-instructions, other instructions, or other control signals as output, which are decoded from the original instruction, or otherwise reflect the original instruction, or are derived from the original instruction. The decoding circuit 1440 may also include an address generation unit (AGU, not shown) circuit. In one example, the AGU uses the forwarded register ports to generate LSU addresses and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decoding circuit 1440 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), and the like. In one example, the core 1490 includes a microcode ROM (not shown) or other medium that stores microcode for certain macro-instructions (e.g., in the decoding circuit 1440 or otherwise within the front-end circuit 1430). In one example, the decoding circuit 1440 includes a micro-operation (micro-op) or operation cache (not shown) to save / cache the decoded operations, micro-tags, or micro-operations generated during the decoding or other stages of the processor pipeline 1400. The decoding circuit 1440 may be coupled to a rename / allocator unit circuit 1452 in the execution engine circuit 1450.

[0113] The execution engine circuit 1450 includes a rename / allocator unit circuit 1452, which is coupled to a retirement unit circuit 1454 and a set of one or more scheduler circuits 1456. The scheduler circuits 1456 represent any number of different schedulers, including reservation stations, a central instruction window, and so on. In some examples, the (one or more) scheduler circuits 1456 may include an arithmetic logic unit (ALU) scheduler / scheduling circuit, an ALU queue, an address generation unit (AGU) scheduler / scheduling circuit, an AGU queue, and so on. The (one or more) scheduler circuits 1456 are coupled to the (one or more) physical register file circuits 1458. Each of the physical register file circuits 1458 represents one or more physical register files, and different physical register files among these physical register files store one or more different data types, such as scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points, status (e.g., an instruction pointer that is the address of the next instruction to be executed), and so on. In one example, the (one or more) physical register file circuits 1458 include a vector register unit circuit, a write mask register unit circuit, and a scalar register unit circuit. These register units may provide architected vector registers, vector mask registers, general-purpose registers, and so on. The (one or more) physical register file circuits 1458 are coupled to the retirement unit circuit 1454 (also referred to as a retirement queue) to illustrate various ways that can be used to implement register renaming and out-of-order execution (e.g., using the (one or more) reorder buffer(s) (ROB) and the (one or more) retirement register files; using the (one or more) future heaps, the (one or more) history buffers, and the (one or more) retirement register files; using a register map and a pool of registers; and so on). The retirement unit circuit 1454 and the (one or more) physical register file circuits 1458 are coupled to the (one or more) execution clusters 1460. The (one or more) execution clusters 1460 include a set of one or more execution unit circuits 1462 and a set of one or more memory access circuits 1464. The (one or more) execution unit circuits 1462 may perform various arithmetic, logical, floating-point, or other types of operations (e.g., shifts, additions, subtractions, multiplications) on various types of data (e.g., scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points). Although some examples may include several execution units or execution unit circuits dedicated to a specific function or set of functions, other examples may include only one execution unit circuit or multiple execution units / execution unit circuits that perform all functions.(One or more) scheduler circuits 1456, (one or more) physical register file circuits 1458, and (one or more) execution clusters 1460 are shown as potentially being multiple because some examples create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating point / tight integer / tight floating point / vector integer / vector floating point pipelines, and / or memory access pipelines, each of which has its own scheduler circuit, (one or more) physical register file circuits, and / or execution cluster—and in the case of a separate memory access pipeline, in some examples only the execution cluster of that pipeline has (one or more) memory access unit circuits 1464). It should also be understood that in cases where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution while the rest are in-order.

[0114] In some examples, the execution engine unit circuit 1450 may perform load / store unit (LSU) address / data pipelining to an advanced microcontroller bus (AMB) interface (not shown), as well as address phase and write-back, data phase load, store, and branch.

[0115] A set of memory access circuits 1464 are coupled to a memory unit circuit 1470, which includes a data TLB circuit 1472, which is coupled to a data cache circuit 1474, which is coupled to a level 2 (L2) cache circuit 1476. In one example, the memory access circuits 1464 may include a load unit circuit, a store address unit circuit, and a store data unit circuit, each of which is coupled to the data TLB circuit 1472 in the memory unit circuit 1470. An instruction cache circuit 1434 is further coupled to the level 2 (L2) cache circuit 1476 in the memory unit circuit 1470. In one example, the instruction cache 1434 and the data cache 1474 are combined into a single instruction and data cache (not shown) in the L2 cache circuit 1476, a level 3 (L3) cache circuit (not shown), and / or main memory. The L2 cache circuit 1476 is coupled to one or more other levels of cache and ultimately to main memory.

[0116] The core 1490 may support one or more instruction sets (e.g., x86 instruction set architecture (optionally with some extensions added with more recent versions); MIPS instruction set architecture; ARM instruction set architecture (optionally with optional additional extensions such as NEON)), which includes the (one or more) instructions described herein. In one example, the core 1490 includes logic to support a packed data instruction set architecture extension (e.g., AVX1, AVX2), thereby allowing operations used by many multimedia applications to be performed using packed data.

[0117] Example execution unit circuit.

[0118] Figure 15 An example of (one or more) execution unit circuits is illustrated, such as the (one or more) execution unit circuits 1462 of FIG. 14(B). As shown, the (one or more) execution unit circuits 1462 may include one or more ALU circuits 1501, an optional vector / single instruction multiple data (SIMD) circuit 1503, a load / store circuit 1505, a branch / jump circuit 1507, and / or a floating-point unit (FPU) circuit 1509. The ALU circuit 1501 performs integer arithmetic and / or Boolean operations. The vector / SIMD circuit 1503 performs vector / SIMD operations on packed data (e.g., SIMD / vector registers). The load / store circuit 1505 executes load and store instructions to load data from memory into registers or store data from registers to memory. The load / store circuit 1505 may also generate addresses. The branch / jump circuit 1507 causes a branch or jump to a certain memory address depending on the instruction. The FPU circuit 1509 performs floating-point arithmetic. The width of the (one or more) execution unit circuits 1462 varies depending on the example and may be in the range of, for example, from 16 bits to 1024 bits. In some examples, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two 128-bit execution units are logically combined to form a 256-bit execution unit).

[0119] Example register architecture.

[0120] Figure 16is a block diagram of a register architecture 1600 according to some examples. As shown, the register architecture 1600 includes vector / SIMD registers 1610, whose widths vary from 128 bits to 1024 bits. In some examples, the vector / SIMD registers 1610 are physically 512 bits, and depending on the mapping, only some of the lower bits are used. For example, in some examples, the vector / SIMD registers 1610 are 512-bit ZMM registers: the lower 256 bits are used for YMM registers, and the lower 128 bits are used for XMM registers. Thus, there is register overlay. In some examples, the vector length field selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the previous length. A scalar operation is an operation performed on the lowest-order data element position in a ZMM / YMM / XMM register; the higher-order data element positions are either kept the same as they were before the instruction or are zeroed, depending on the example.

[0121] In some examples, the register architecture 1600 includes write mask / predicate registers 1615. For example, in some examples, there are 8 write mask / predicate registers (sometimes referred to as k0 through k7), each of which is 16 bits, 32 bits, 64 bits, or 128 bits in size. The write mask / predicate registers 1615 can allow merging (e.g., allowing any set of elements in the destination to be protected from update during the execution of any operation) and / or zeroing (e.g., zeroing the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation). In some examples, each data element position in a given write mask / predicate register 1615 corresponds to a data element position in the destination. In other examples, the write mask / predicate registers 1615 are scalable and consist of a set number of enable bits for a given vector element (e.g., 8 enable bits for each 64-bit vector element).

[0122] The register architecture 1600 includes multiple general-purpose registers 1625. These registers can be 16 bits, 32 bits, 64 bits, etc., and can be used for scalar operations. In some examples, these registers are named RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0123] In some examples, the register architecture 1600 includes a scalar floating-point (FP) register file 1645, which is used to perform scalar floating-point operations on 32 / 64 / 80-bit floating-point data using the x87 instruction set architecture extensions, or as MMX registers to perform operations on 64-bit packed integer data, and to save operands for some operations performed between MMX and XMM registers.

[0124] One or more flag registers 1640 (e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, comparison, and system operations. For example, one or more flag registers 1640 can store condition code information such as carry, parity, auxiliary carry, zero, sign, and overflow. In some examples, one or more flag registers 1640 are referred to as program status and control registers.

[0125] Segment registers 1620 contain segment pointers for accessing memory. In some examples, these registers are named CS, DS, SS, ES, FS, and GS.

[0126] Machine-specific registers (MSRs) 1635 control and report on processor performance. Most MSRs 1635 handle system-related functions and are not accessible to applications. Machine check registers 1660 consist of control, status, and error-reporting MSRs for detecting and reporting hardware errors.

[0127] One or more instruction pointer registers 1630 store instruction pointer values. One or more control registers 1655 (e.g., CR0-CR4) determine the operating mode of the processor (e.g., processors 1270, 1280, 1238, 1215, and / or 1300) and the characteristics of the currently executing task. Debug registers 1650 control and allow monitoring of the debug operations of the processor or core.

[0128] Memory (mem) management registers 1665 specify the locations for data structures in protected mode memory management. These registers can include a global descriptor table register (GDTR), an interrupt descriptor table register (IDTR), a task register, and a local descriptor table register (LDTR).

[0129] Alternative examples may use wider or narrower registers. Additionally, alternative examples may use more, fewer, or different register files and registers. The register architecture 1600 may be used, for example, in the register file / memory ISAB08, or in the physical register file circuit 1458.

[0130] Instruction Set Architecture.

[0131] An instruction set architecture (ISA) may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, position of bits) to specify the operation to be performed (e.g., opcode) and the operand(s) on which the operation is to be performed and / or other data field(s) (e.g., mask), etc. Some instruction formats are further decomposed by the definition of instruction templates (or sub-formats). For example, an instruction template of a given instruction format may be defined as having different subsets of the fields of that instruction format (the included fields are generally in the same order, but at least some have different bit positions since fewer fields are included) and / or may be defined as having a given field interpreted in a different way. Thus, each instruction of the ISA is expressed using a given instruction format (and if defined, using a given instruction template within that instruction format), and includes fields for specifying the operation and operands. For example, an example ADD instruction has a specific opcode and an instruction format that includes an opcode field to specify the opcode and an operand field to select the operands (source 1 / destination and source 2); and the occurrence of this ADD instruction in the instruction stream will have specific contents in the operand fields that select the specific operands. Additionally, while the following description is in the context of the x86 ISA, applying the teachings of the present disclosure to other ISAs is within the knowledge of those skilled in the art.

[0132] Example instruction formats.

[0133] Examples of the (one or more) instructions described herein may be implemented in different formats. Additionally, example systems, architectures, and pipelines are detailed below. Examples of the (one or more) instructions may be executed on these systems, architectures, and pipelines, but are not limited to those detailed.

[0134] Figure 17Illustrates an example of an instruction format. As shown, an instruction can include multiple components, which include but are not limited to one or more fields for the following: one or more prefixes 1701, an opcode 1703, addressing information 1705 (e.g., register identifiers, memory addressing information, etc.), a displacement value 1707, and / or an immediate numeric value 1709. Note that some instructions utilize some or all of the fields of this format, while other instructions may only use the fields of the opcode 1703. In some examples, the illustrated order is the order in which these fields are to be encoded, however it should be understood that in other examples, these fields can be encoded in a different order, combined, etc.

[0135] (One or more) prefix fields 1701 modify the instruction when used. In some examples, one or more prefixes are used for repeat string instructions (e.g., 0xF0, 0xF2, 0xF3, etc.), provide section override (e.g., 0x2E, 0x36, 0x3E, 0x26, 0x64, 0x65, 0x2E, 0x3E, etc.), perform bus lock operations, and / or change operand (e.g., 0x66) and address size (e.g., 0x67). Certain instructions require mandatory prefixes (e.g., 0x66, 0xF2, 0xF3, etc.). Some of these prefixes can be considered "traditional" prefixes. Other prefixes (one or more examples of which are detailed herein) indicate and / or provide further capabilities, such as specifying particular registers, etc. These other prefixes typically follow the "traditional" prefixes.

[0136] The opcode field 1703 is used to at least partially define the operation to be performed upon decoding of the instruction. In some examples, the length of the main opcode encoded in the opcode field 1703 is one, two, or three bytes. In other examples, the main opcode can be of other lengths. An additional 3-bit opcode field is sometimes encoded in another field.

[0137] The addressing information field 1705 is used to address one or more operands of the instruction, such as a location in memory or one or more registers. Figure 18Illustrates an example of the addressing information field 1705. In this illustration, an optional MOD R / M byte 1802 and an optional Scale, Index, Base (SIB) byte 1804 are shown. The MOD R / M byte 1802 and the SIB byte 1804 are used to encode up to two operands of an instruction, and each operand is either a direct register or an effective memory address. Note that these fields are all optional, that is, not all instructions include one or more of these fields. The MOD R / M byte 1802 includes a MOD field 1842, a register (reg) field 1844, and an R / M field 1846.

[0138] The content of the MOD field 1842 differentiates between memory access and non-memory access modes. In some examples, when the MOD field 1842 has a binary value of 11 (11b), register direct addressing mode is used, otherwise register indirect addressing mode is used.

[0139] The register field 1844 can encode a destination register operand or a source register operand, or can also encode an opcode extension and is not used to encode any instruction operand. The content of the register field 1844 directly specifies or specifies the location of the source or destination operand (in a register or in memory) through address generation. In some examples, the register field 1844 is supplemented with additional bits from a prefix (e.g., prefix 1701) to allow for greater addressing.

[0140] The R / M field 1846 can be used to encode an instruction operand that references a memory address, or can be used to encode a destination register operand or a source register operand. Note that in some examples, the R / M field 1846 can be combined with the MOD field 1842 to specify an addressing mode.

[0141] The SIB byte 1804 includes a scale factor field 1852, an index field 1854, and a base address field 1856 for address generation. The scale field 1852 indicates a scale factor. The index field 1854 specifies the index register to be used. In some examples, the index field 1854 is supplemented with additional bits from a prefix (e.g., prefix 1701) to allow for greater addressing. The base address field 1856 specifies the base register to be used. In some examples, the base address field 1856 is supplemented with additional bits from a prefix (e.g., prefix 1701) to allow for greater addressing. In practice, the content of the scale field 1852 allows the content of the index field 1854 to be scaled for memory address generation (e.g., for address generation using 2 缩放 * index + base address).

[0142] Some addressing forms utilize displacement values to generate memory addresses. For example, memory addresses can be generated according to 2 缩放 *index + base + displacement, index * scale + displacement, r / m + displacement, instruction pointer (RIP / EIP) + displacement, register + displacement, etc. The displacement can be a value such as 1 byte, 2 bytes, 4 bytes, etc. In some examples, the displacement field 1707 provides this value. Additionally, in some examples, the use of the displacement factor is encoded in the MOD field of the addressing information field 1705, which indicates a compressed displacement scheme for which the displacement value is calculated and stored in the displacement field 1707.

[0143] In some examples, the immediate value field 1709 specifies an immediate value for the instruction. The immediate value can be encoded as a 1-byte value, 2-byte value, 4-byte value, etc.

[0144] Figure 19 An example of the first prefix 1701(A) is illustrated. In some examples, the first prefix 1701(A) is an example of a REX prefix. Instructions using this prefix can specify general-purpose registers, 64-bit packed data registers (e.g., single instruction, multiple data (SIMD) registers or vector registers), and / or control and debug registers (e.g., CR8 - CR15 and DR8 - DR15).

[0145] Instructions using the first prefix 1701(A) can specify up to three registers using a 3-bit field, depending on the format: 1) using the reg field 1844 and R / M field 1846 of the MOD R / M byte 1802; 2) using the MOD R / M byte 1802 and the SIB byte 1804, including using the reg field 1844 and the base field 1856 and index field 1854; or 3) using the register field of the opcode.

[0146] In the first prefix 1701(A), bit positions 7:4 are set to 0100. Bit position 3 (W) can be used to determine the operand size but cannot determine the operand width alone. Thus, when W = 0, the operand size is determined by the code segment descriptor (CS.D), and when W = 1, the operand size is 64 bits.

[0147] Note that adding another bit allows addressing 16 (2 4 ) registers, while the separate MOD R / M reg field 1844 and MOD R / M R / M field 1846 can each address only 8 registers.

[0148] In the first prefix 1701(A), bit position 2 (R) can be an extension of the reg field 1844 of MOD R / M, and can be used to modify the reg field 1844 of MOD R / M when this field encodes a general-purpose register, a 64-bit packed data register (e.g., an SSE register), or a control or debug register. When the MOD R / M byte 1802 specifies other registers or defines an extended opcode, R is ignored.

[0149] Bit position 1 (X) can modify the SIB byte index field 1854.

[0150] Bit position 0 (B) can modify the base address in the R / M field 1846 of MOD R / M or the base address field 1856 of the SIB byte; or it can modify the opcode register field for accessing a general-purpose register (e.g., general-purpose register 1625).

[0151] Figures 20(A)-(D) illustrate examples of how the R, X, and B fields of the first prefix 1701(A) are used. Figure 20(A) illustrates that when the SIB byte 1804 is not used for memory addressing, R and B from the first prefix 1701(A) are used to extend the reg field 1844 and the R / M field 1846 of the MODR / M byte 1802. Figure 20(B) illustrates that when the SIB byte 1804 is not used, R and B from the first prefix 1701(A) are used to extend the reg field 1844 and the R / M field 1846 of the MOD R / M byte 1802 (register-register addressing). Figure 20(C) illustrates that when the SIB byte 1804 is used for memory addressing, R, X, and B from the first prefix 1701(A) are used to extend the reg field 1844 of the MOD R / M byte 1802 and the index field 1854 and the base address field 1856. Figure 20(D) illustrates that when a register is encoded in the opcode 1703, B from the first prefix 1701(A) is used to extend the reg field 1844 of the MOD R / M byte 1802.

[0152] Figures 21(A)-(B) illustrate an example of a second prefix 1701(B). In some examples, the second prefix 1701(B) is an example of a VEX prefix. The second prefix 1701(B) encoding allows an instruction to have more than two operands and allows SIMD vector registers (e.g., vector / SIMD register 1610) to be longer than 64 bits (e.g., 128 bits and 256 bits). The use of the second prefix 1701(B) provides a syntax for three-operand (or more) operations. For example, a previous two-operand instruction performed an operation such as A = A + B, which overwrote the source operand. The use of the second prefix 1701(B) enables the operands to perform non-destructive operations, such as A = B + C.

[0153] In some examples, the second prefix 1701(B) has two forms - a two-byte form and a three-byte form. The two-byte second prefix 1701(B) is mainly used for 128-bit, scalar, and some 256-bit instructions; while the three-byte second prefix 1701(B) provides a compact replacement for 3-byte opcode instructions and the first prefix 1701(A).

[0154] Figure 21(A) illustrates an example of the two-byte form of the second prefix 1701(B). In one example, the format field 2101 (byte 0 2103) contains the value C5H. In one example, byte 1 2105 includes an "R" value in bit [7]. This value is the complement of the "R" value of the first prefix 1701(A). Bit [2] is used to specify the length (L) of the vector (where a value of 0 is a scalar or 128-bit vector, and a value of 1 is a 256-bit vector). Bits [1:0] provide opcode extensibility equivalent to some traditional prefixes (e.g., 00 = no prefix, 01 = 66H, 10 = F3H, and 11 = F2H). Bits [6:3], shown as vvvv, can be used for: 1) encoding the first source register operand, which is specified in inverted (one's complement) form and is valid for instructions with two or more source operands; 2) encoding the destination register operand, which is specified in one's complement form, for certain vector shifts; or 3) not encoding any operand, and this field is reserved and should contain a value, such as 1111b.

[0155] Instructions using this prefix can use the MOD R / M R / M field 1846 to encode instruction operands that reference memory addresses, or to encode destination register operands or source register operands.

[0156] Instructions using this prefix can use the MOD R / M reg field 1844 to encode a destination register operand or a source register operand, or be treated as an opcode extension and not be used to encode any instruction operand.

[0157] For instruction syntax that supports four operands, the vvvv, MOD R / M R / M field 1846, and MOD R / M reg field 1844 encode three of the four operands. Then bits [7:4] of the immediate value field 1709 are used to encode the third source register operand.

[0158] Figure 21(B) illustrates an example of the three-byte form of the second prefix 1701(B). In one example, the format field 2111 (byte 0 2113) contains the value C4H. Byte 1 2115 includes "R", "X", and "B" in bits [7:5], which are the complements of these values of the first prefix 1701(A). Bits [4:0] of byte 1 2115 (shown as mmmmm) include content for encoding one or more implicit leading opcode bytes as needed. For example, 00001 means a 0FH leading opcode, 00010 means a 0F38H leading opcode, 00011 means a 0F3AH leading opcode, and so on.

[0159] The use of bit [7] of byte 2 2117 is similar to W of the first prefix 1701(A), including helping to determine the operand size that can be promoted. Bit [2] is used to specify the length (L) of the vector (where a value of 0 is a scalar or 128-bit vector, and a value of 1 is a 256-bit vector). Bits [1:0] provide opcode extensibility equivalent to some traditional prefixes (e.g., 00 = no prefix, 01 = 66H, 10 = F3H, and 11 = F2H). Bits [6:3], shown as vvvv, can be used for: 1) encoding the first source register operand, which is specified in inverted (one's complement) form and is valid for instructions with two or more source operands; 2) encoding the destination register operand, which is specified in one's complement form and is used for certain vector shifts; or 3) not encoding any operand, and this field is reserved and should contain a certain value, such as 1111b.

[0160] Instructions using this prefix can use the MOD R / M R / M field 1846 to encode an instruction operand that references a memory address, or encode a destination register operand or a source register operand.

[0161] Instructions using this prefix can use the MOD R / M reg field 1844 to encode a destination register operand or a source register operand, or be treated as an opcode extension and not be used to encode any instruction operand.

[0162] For instruction syntaxes that support four operands, the vvvv, MOD R / M R / M field 1846, and MOD R / M reg field 1844 encode three of the four operands. Then bits [7:4] of the immediate value field 1709 are used to encode the third source register operand.

[0163] Figure 22 Illustrates an example of the third prefix 1701(C). In some examples, the third prefix 1701(C) is an example of an EVEX prefix. The third prefix 1701(C) is a four-byte prefix.

[0164] The third prefix 1701(C) can encode 32 vector registers in 64-bit mode (e.g., 128-bit, 256-bit, and 512-bit registers). In some examples, instructions that utilize a write mask / operation mask (see the discussion of registers in the previous figures, e.g., Figure 16 ) or predicates use this prefix. The operation mask register allows conditional processing or selection control. Operation mask instructions — whose source / destination operand is an operation mask register and treat the content of the operation mask register as a single value — are encoded using the second prefix 1701(B).

[0165] The third prefix 1701(C) can encode functionality specific to instruction classes (e.g., packed instructions with “load + operation” semantics can support an embedded broadcast function, floating-point instructions with rounding semantics can support a static rounding function, floating-point instructions with non-rounding arithmetic semantics can support a “suppress all exceptions” function, etc.).

[0166] The first byte of the third prefix 1701(C) is the format field 2211, which has a value of 62H in one example. The subsequent bytes are called the payload bytes 2215 - 2219 and together form a 24-bit value of P[23:0], providing specific capabilities in the form of one or more fields (detailed herein).

[0167] In some examples, P[1:0] of payload byte 2219 is the same as the two least significant mm bits. In some examples, P[3:2] is reserved. Bit P[4] (R') allows access to the upper 16 vector register set when combined with P[7] and the reg field 1844 of MOD R / M. When SIB type addressing is not required, P[6] can also provide access to the upper 16 vector registers. P[7:5] consists of R, X, and B, which are operand specifier modifier bits for vector registers, general-purpose registers, and memory addressing, and when combined with the MOD R / M register field 1844 and the MOD R / M R / M field 1846, allow access to the next set of 8 registers beyond the lower 8 registers. P[9:8] provides opcode extensibility equivalent to some traditional prefixes (e.g., 00 = no prefix, 01 = 66H, 10 = F3H, and 11 = F2H). P

[10] is a fixed value 1 in some examples. P[14:11], shown as vvvv, can be used for: 1) encoding the first source register operand, which is specified in inverted (ones' complement) form and is valid for instructions with two or more source operands; 2) encoding the destination register operand, which is specified in ones' complement form for certain vector shifts; or 3) not encoding any operand, and this field is reserved and should contain a certain value, e.g., 1111b.

[0168] P

[15] is similar to the W of the first prefix 1701(A) and the second prefix 1711(B), and can be used as an opcode extension bit or an operand size promotion.

[0169] P[18:16] specifies the index of a register in an operation mask (write mask) register (e.g., write mask / predicate register 1615). In one example, a particular value aaa = 000 has special behavior, implying that no operation mask is used for that particular instruction (this can be achieved in various ways, including using a hardwired all-ones operation mask or hardware that bypasses the masking hardware). When combined, the vector mask allows any set of elements in the destination to be protected from update during the execution of any operation (specified by the base and enhanced operations); in another example, the old value of each element of the destination is retained (if the corresponding mask bit has a value of 0). In contrast, when zeroing, the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the base and enhanced operations); in one example, the elements of the destination are set to 0 when the corresponding mask bit has a value of 0. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the span of elements being modified, from the first to the last); however, the elements being modified do not have to be contiguous. Thus, the operation mask field allows for partial vector operations, including loads, stores, arithmetic, logic, etc. While in the described example, the content of the operation mask field selects which one of several operation mask registers contains the operation mask to be used (so the content of the operation mask field indirectly identifies the masking to be performed), alternatively or additionally, alternative examples allow the content of the mask write field to directly specify the masking to be performed.

[0170] P

[19] can be combined with P[14:11] to encode a second source vector register in a non-destructive source syntax that can utilize P

[19] to access the upper 16 vector registers. P

[20] encodes a variety of functions that vary across different classes of instructions and can affect the meaning of the vector length / rounding control specifier field (P[22:21]). P

[23] indicates support for merge-write masking (e.g., when set to 0) or support for zeroing and merge-write masking (e.g., when set to 1).

[0171] Examples of the encoding of registers in instructions using the third prefix 1701(C) are detailed in the following table.

[0172]

[0173] Table 1: 32-register support in 64-bit mode

[0174]

[0175]

[0176] Table 2: Encoding Register Specifiers in 32-bit Mode

[0177] [2:0] REG. Type General Purpose REG MOD R / M Reg k0 - k7 Source VVVV vvvv k0 - k7 Second Source RM MOD R / M R / M k0 - k7 First Source {k1} aaa k0 - k7 Operation Mask

[0178] Table 3: Encoding of Operation Mask Register Specifiers

[0179] Program code can be applied to the input information to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor, such as a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a microprocessor, or any combination thereof.

[0180] The program code can be implemented in a high-level procedural or object-oriented programming language to communicate with the processing system. If desired, the program code can also be implemented in assembly or machine language. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language can be a compiled language or an interpreted language.

[0181] Examples of the mechanisms disclosed herein can be implemented in hardware, software, firmware, or a combination of these implementation approaches. An example can be implemented as a computer program or program code, executed on a programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0182] One or more aspects of at least one example can be implemented by representative instructions stored on a machine-readable medium, which represent various logics within a processor. When these instructions are read by the machine, they cause the machine to fabricate the logic for performing the techniques described herein. These representations are referred to as “Intellectual Property (IP) cores” and can be stored on a tangible machine-readable medium and provided to various customers or manufacturing facilities to be loaded into the manufacturing machines that make the logic or processor.

[0183] These machine-readable storage media can include—but are not limited to—non-transitory tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as: hard disks, any other type of disk (including floppy disks, optical disks, compact disk read-only memory (CD-ROM), compact disk rewritable (CD-RW), and magneto-optical disks), semiconductor devices (e.g., read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM)), magnetic or optical cards, or any other type of medium suitable for storing electronic instructions.

[0184] Accordingly, examples also include non-transitory tangible machine-readable media that contain instructions or contain design data that defines the structural, circuit, device, processor, and / or system characteristics described herein, such as a Hardware Description Language (HDL). Such examples may also be referred to as program products.

[0185] Emulation (including binary translation, code morphing, etc.).

[0186] In some cases, an instruction converter can be used to convert instructions from a source instruction set architecture to a target instruction set architecture. For example, the instruction converter can translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert the instructions to one or more other instructions to be processed by the core. The instruction converter can be implemented in software, hardware, firmware, or a combination thereof. The instruction converter can be on the processor, off the processor, or part on the processor and part off the processor.

[0187] Figure 23The block diagram illustrates the use of a software instruction converter according to an example for converting binary instructions in a source ISA into binary instructions in a target ISA. In the illustrated example, the instruction converter is a software instruction converter, but alternatively, the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 23 Shows that a program in a high-level language 2302 can be compiled using a first ISA compiler 2304 to generate a first ISA binary code 2306, which can be natively executed by a processor 2316 having at least one first ISA core. The processor 2316 having at least one first ISA core represents any such processor that is capable of performing substantially the same functions as an Intel processor having at least one first ISA core by compatibly executing or otherwise processing (1) a substantial portion of the first ISA or (2) a target code version of an application or other software targeted to run on a processor having at least one first ISA core, so as to achieve substantially the same results as a processor having at least one first ISA core. The first ISA compiler 2304 represents a compiler operable to generate the first ISA binary code 2306 (e.g., target code), which can be executed on the processor 2316 having at least one first ISA core with or without additional linking processing. Similarly, Shows that a program in a high-level language 2302 can be compiled using an alternative ISA compiler 2308 to generate an alternative ISA binary code 2310, which can be natively executed by a processor 2314 that does not have a first ISA core. An instruction converter 2312 is used to convert the first ISA binary code 2306 into a code that can be natively executed by the processor 2314 that does not have a first ISA core. This converted code need not be the same as the alternative ISA binary code 2310; however, the converted code will implement the overall operation and be composed of instructions from that alternative ISA. Thus, the instruction converter 2312 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device that does not have a first ISA processor or core to execute the first ISA binary code 2306 through emulation, simulation, or any other process. Figure 23 For any of the components, features, and details described in

[0188] For Figures 2 - 10 any one of them, the components, features, and details described can also optionally apply to Figure 1。Any components, features, and details described for any processor or device disclosed herein (e.g., 100, 900, 1100) can optionally be applicable to any method disclosed herein, and in embodiments, such methods can optionally be performed by such a processor or device and / or utilize such a processor or device to perform. Any processor or device described herein in embodiments (e.g., 100, 900, 1100) can optionally be included in any system disclosed herein (e.g., Figures 12 - 13 any system). Any instructions disclosed herein can optionally have the features or details of the instruction formats shown herein in some embodiments (e.g., for Figures 17 - 22 those described).

[0189] Referring to "an example", "one example", etc. indicates that the described example may include a specific feature, structure, or characteristic, but not necessarily every example includes that specific feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same example. Additionally, when a specific feature, structure, or characteristic is described in connection with one example, it should be considered within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in connection with other examples (whether explicitly described or not).

[0190] The processor components disclosed herein can be said to and / or claimed to be operable, operative, capable, able, configured, adapted, or otherwise to perform operations. For example, a decoder can be said to and / or claimed to decode instructions, an execution unit can be said to and / or claimed to store results, and so on. As used herein, these expressions refer to the characteristics, attributes, or properties of a component when in a powered-off state, and do not mean that the component or the device or apparatus including the component is currently powered on or in an operating state. For clarity, it is to be understood that the processors and devices claimed herein are not claimed to be powered on or operating.

[0191] In the specification and / or claims, the terms "coupled" and / or "connected" and their derivatives may be used. These terms are not intended to be synonyms of each other. Rather, in embodiments, "connected" can be used to indicate that two or more elements make direct physical and / or electrical contact with each other. "Coupled" can mean that two or more elements make direct physical and / or electrical contact with each other. However, "coupled" can also mean that two or more elements do not make direct contact with each other, but still cooperate or interact with each other. For example, a predictor can be coupled to a cache hierarchy through one or more intermediate components. In the drawings, arrows are used to show connections and couplings.

[0192] Some embodiments include a manufacture (e.g., a computer program product) that includes a machine-readable medium. The medium can include a mechanism that provides information in a machine-readable form, such as storing information. The machine-readable medium can provide or store thereon instructions or sequences of instructions that, if executed by a machine and / or when executed by a machine, can operate to cause the machine to perform and / or result in the machine performing one or more of the operations, methods, or techniques disclosed herein.

[0193] In some embodiments, the machine-readable medium can include a tangible and / or non-transitory machine-readable storage medium. For example, the non-transitory machine-readable storage medium can include floppy disks, optical storage media, optical discs, optical data storage devices, CD-ROMs, magnetic disks, magneto-optical discs, read only memory (ROM), programmable ROM (PROM), erasable-and-programmable ROM (EPROM), electrically-erasable-and-programmable ROM (EEPROM), random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), flash memory, phase change memory, phase change data storage materials, non-volatile memory, non-volatile data storage devices, non-transitory memory, non-transitory data storage devices, and so on. The non-transitory machine-readable storage medium does not include transitory propagated signals. In some embodiments, the storage medium can include a tangible medium that includes solid-state substances or materials, such as semiconductor materials, phase change materials, magnetic solid-state materials, solid-state data storage materials, and so on. Alternatively, a non-tangible transitory computer-readable transmission medium can optionally be used, such as, for example, electrical, optical, acoustic, or other forms of propagated signals - such as carrier waves, infrared signals, and digital signals.

[0194] Examples of suitable machines include, but are not limited to, general-purpose processors, special-purpose processors, digital logic circuits, integrated circuits, and so on. Other examples of suitable machines include computer systems or other electronic devices that include a processor, digital logic circuit, or integrated circuit. Examples of such computer systems or electronic devices include, but are not limited to, desktop computers, laptop computers, notebook computers, tablet computers, netbooks, smart phones, cellular phones, servers, network devices (e.g., routers and switches), mobile Internet devices (MID), smart TVs, set-top boxes.

[0195] In addition, in the various examples described above, unless otherwise specifically noted, alternative language such as the phrase “at least one of A, B, or C” or “A, B, and / or C” shall be understood to mean A, B, or C, or any combination thereof (i.e., A and B, A and C, B and C, and A, B, and C).

[0196] In the foregoing description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments. However, other embodiments may be practiced without some of these specific details. Various modifications and variations can be made without departing from the broader spirit and scope of the disclosure as set forth in the claims. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive. The scope of the invention is not determined by the specific examples provided above, but only by the appended claims. In other instances, well-known circuits, structures, devices, and operations are shown in block diagram form and / or without detail to avoid obscuring the description.

[0197] Example embodiments

[0198] The following examples relate to further embodiments. The specific details in the examples can be used anywhere in one or more embodiments.

[0199] Example 1 is a processor or other device that includes a cache hierarchy and a memory access unit coupled to the cache hierarchy. The memory access unit performs demand loading based on a 64-bit pointer such that a first one or more cache lines are loaded from memory into the cache hierarchy. The 64-bit pointer has an X-bit virtual address field and a data object range field in one or more bits in bits [63:X], and the data object range field stores a value. The device also includes a prefetch unit coupled to the cache hierarchy. The prefetch unit determines whether to prefetch a second one or more cache lines adjacent to the first one or more cache lines from the memory into the cache hierarchy at least in part based on the value.

[0200] Example 2 includes the device as described in Example 1, wherein the value indicates a range of a data object that includes the first one or more cache lines.

[0201] Example 3 includes the device as described in any one of Examples 1 to 2, wherein the prefetch unit: (1) does not prefetch the second one or more cache lines when the value is a first value used to indicate that the data object is included in the first one or more cache lines; and / or (2) prefetches the second one or more cache lines when the value is a second value used to indicate that the data object is not included in the first one or more cache lines.

[0202] Example 4 includes the apparatus according to any one of Examples 1 to 3, wherein the prefetch unit determines to prefetch the memory amount that is adjacent to the first one or more cache lines and includes the second one or more cache lines when the value is a third value for indicating the memory amount containing the data object.

[0203] Example 5 includes the apparatus according to any one of Examples 1 to 4, wherein the prefetch unit: (1) does not prefetch the second one or more cache lines when the value is a first value for indicating that the data object is included in the first one or more cache lines; and / or (2) prefetches the first memory amount that is adjacent to the first one or more cache lines and includes the second one or more cache lines when the value is a second value for indicating the first memory amount containing the data object; and / or (3) prefetches the second memory amount that is adjacent to the first one or more cache lines and includes the second one or more cache lines when the value is a third value for indicating the second memory amount containing the data object, wherein the second memory amount is greater than the first memory amount; and / or (4) prefetches the third memory amount that is adjacent to the first one or more cache lines and includes the second one or more cache lines when the value is a fourth value for indicating the third memory amount containing the data object, wherein the third memory amount is greater than the second memory amount.

[0204] Example 6 includes the apparatus according to any one of Examples 1 to 5, wherein the 64-bit pointer has a field in one or more bits in bits [63:X] that are not used for the data object range field to store a pointer identification value, and optionally, wherein the prefetch unit detects the pointer identification value in the code or data to locate the 64-bit pointer in the code or data.

[0205] Example 7 includes the apparatus according to any one of Examples 1 to 6, further including an address translation unit coupled to the memory access unit, the address translation unit determining at least in part based on the value whether to obtain and store in a translation lookaside buffer (TLB) the address translation of a memory location adjacent to the first one or more cache lines.

[0206] Example 8 includes the apparatus according to any one of Examples 1 to 7, wherein the prefetch unit determines whether to prefetch the second one or more cache lines at least in part based on the value to be obtained from the 64-bit pointer having the X-bit virtual address field.

[0207] Example 9 includes the apparatus as described in any one of Examples 1 to 7, wherein the prefetch unit determines whether to prefetch the second one or more cache lines at least in part based on the value to be obtained from the physical address, the physical address being translated from the 64-bit pointer having the X-bit virtual address field, and optionally, wherein the physical address has a data object range field for storing the value.

[0208] Example 10 is a method that includes performing a demand load based on a 64-bit pointer, including loading a first one or more cache lines from a memory into a cache hierarchy. The pointer has an X-bit virtual address and a data object range value in one or more bits in bits [63:X]. The method further includes determining whether to prefetch a second one or more cache lines adjacent to the first one or more cache lines from the memory into the cache hierarchy at least in part based on the data object range value.

[0209] Example 11 includes the method as described in Example 10, wherein determining whether to prefetch the second one or more cache lines includes: (1) determining not to prefetch the second one or more cache lines when the data object range value indicates that the data object is included within the first one or more cache lines; and / or (2) determining to prefetch the second one or more cache lines when the data object range value indicates that the data object is not included within the first one or more cache lines.

[0210] Example 12 includes the method as described in any one of Examples 10 to 11, wherein determining whether to prefetch the second one or more cache lines includes determining to prefetch the second one or more cache lines, and optionally further includes determining a number of cache lines adjacent to the first one or more cache lines to prefetch based on the data object range value.

[0211] Example 13 includes the method as described in any one of Examples 10 to 12, and further includes detecting a pointer identification value in one or more bits in bits [63:X] not used for the data object range value.

[0212] Example 14 includes the method as described in any one of Examples 10 to 13, and further includes determining whether to obtain and store in a translation lookaside buffer (TLB) an address translation of a memory location adjacent to the first one or more cache lines at least in part based on the data object range value.

[0213] Example 15 is a computer system or other system that includes a dynamic random access memory (DRAM) and a processor coupled to the DRAM. The processor includes a cache hierarchy and a memory access unit coupled to the cache hierarchy. The memory access unit performs a demand load based on a 64-bit pointer such that a first one or more cache lines are loaded from memory into the cache hierarchy. The 64-bit pointer has an X-bit virtual address field and a data object range field in one or more bits in bits [63:X]. The data object range field stores a value. The processor further includes a prefetch unit coupled to the cache hierarchy. The prefetch unit determines whether to prefetch a second one or more cache lines adjacent to the first one or more cache lines from memory into the cache hierarchy at least in part based on the value.

[0214] Example 16 includes the system as described in Example 15, wherein the value indicates a range of a data object including the first one or more cache lines.

[0215] Example 17 includes the system as described in any one of Examples 15 to 16, wherein the prefetch unit: (1) does not prefetch the second one or more cache lines when the value is a first value for indicating that the data object is included in the first one or more cache lines; and / or (2) prefetches the second one or more cache lines when the value is a second value for indicating that the data object is not included in the first one or more cache lines.

[0216] Example 18 includes the system as described in any one of Examples 15 to 17, wherein the 64-bit pointer has a field in one or more bits in bits [63:X] not used for the data object range field to store a pointer identification value, and optionally, wherein the prefetch unit detects the pointer identification value in code to locate the 64-bit pointer in the code.

[0217] Example 19 includes the system as described in any one of Examples 15 to 18, further including an address translation unit coupled to the memory access unit, the address translation unit determining whether to obtain and store in a translation lookaside buffer (TLB) an address translation of a memory location adjacent to the first one or more cache lines at least in part based on the value.

[0218] Example 20 includes the system as described in any one of Examples 15 to 19, wherein the value indicates a range of a data object including the first one or more cache lines, and wherein the 64-bit pointer has a field in one or more bits of bits [63:X] not used for the data object range field to store a pointer identification value, and optionally, wherein the prefetch unit detects the pointer identification value in the code to locate the 64-bit pointer in the code.

[0219] Example 21 is an apparatus that includes means for performing each operation of the method as described in any one of Examples 10 to 14.

[0220] Example 22 is an apparatus that includes circuitry for performing each operation of the method as described in any one of Examples 10 to 14.

[0221] Example 23 is a manufacture that includes a machine-readable medium including instructions that, if executed by a machine, cause the machine to perform the method as described in any one of Examples 10 to 14.

Claims

1. A device comprising: Cache hierarchy; a memory access unit coupled to the cache hierarchy, the memory access unit configured to perform a demand load based on a Y-bit pointer such that a first one or more cache lines are loaded from a memory into the cache hierarchy, the Y-bit pointer having an X-bit virtual address field and a data object range field in one or more of bits [Y-1:X], the data object range field configured to store a value; as well as A prefetch unit coupled to the cache hierarchy is configured to determine whether to prefetch a second one or more cache lines adjacent to the first one or more cache lines from the memory into the cache hierarchy based at least in part on the value.

2. The device according to claim 1, wherein: The value indicates a range of data objects that includes the first one or more cache lines.

3. The device according to claim 1, wherein: The pre-fetch unit is used for: when the value is a first value indicating that the data object is contained within the first one or more cache lines, not prefetching the second one or more cache lines; and When the value is a second value indicating that the data object is not contained within the first one or more cache lines, the second one or more cache lines are pre-fetched.

4. The device as claimed in claim 3, wherein: The prefetch unit is configured to, when the value is a third value indicating an amount of memory containing the data object, determine to prefetch the amount of memory adjacent to the first one or more cache lines and including the second one or more cache lines.

5. The device according to claim 1, wherein: The pre-fetch unit is used for: when the value is a first value indicating that the data object is contained within the first one or more cache lines, not prefetching the second one or more cache lines; when the value is a second value indicating a first amount of memory containing the data object, pre-fetching the first amount of memory adjacent to the first one or more cache lines and including the second one or more cache lines; when the value is a third value indicating a second amount of memory containing the data object, prefetching the second amount of memory adjacent to the first one or more cache lines and including the second one or more cache lines, wherein the second amount of memory is greater than the first amount of memory; and When the value is a fourth value indicating a third amount of memory containing the data object, prefetching the third amount of memory adjacent to the first one or more cache lines and including the second one or more cache lines, wherein the third amount of memory is greater than the second amount of memory.

6. The device according to any one of claims 1 to 5, wherein: The Y-bit pointer has a field for storing a pointer identification value in one or more bits in bits [Y-1:X] that are not used for the data object range field, and wherein the prefetch unit is used to detect the pointer identification value in the code or data to locate the Y-bit pointer in the code or data.

7. The apparatus of any one of claims 1 to 5, further comprising an address translation unit coupled to the memory access unit, the address translation unit configured to determine whether to obtain and store in a translation lookaside buffer (TLB) an address translation of a memory location adjacent to the first one or more cache lines based at least in part on the value.

8. The device according to any one of claims 1 to 5, wherein: The prefetch unit is configured to determine whether to prefetch the second one or more cache lines based at least in part on the value to be obtained from the Y-bit pointer having the X-bit virtual address field.

9. The device according to any one of claims 1 to 5, wherein: The prefetch unit is configured to determine whether to prefetch the second one or more cache lines based at least in part on the value to be obtained from a physical address translated from the Y-bit pointer having the X-bit virtual address field, the physical address having a data object range field for storing the value.

10. A method comprising: performing a demand load including loading a first one or more cache lines from a memory into a cache hierarchy based on a Y-bit pointer having an X-bit virtual address and a data object range value in one or more of bits [Y-1:X]; and A determination is made based at least in part on the data object range value whether to prefetch a second one or more cache lines adjacent to the first one or more cache lines from the memory into the cache hierarchy.

11. The method of claim 10, wherein: Determining whether to prefetch the second one or more cache lines includes: When the data object range value indicates that the data object is contained within the first one or more cache lines, determining not to prefetch the second one or more cache lines; and When the data object range value indicates that the data object is not contained within the first one or more cache lines, it is determined to prefetch the second one or more cache lines.

12. The method of claim 10, wherein: Determining whether to prefetch the second one or more cache lines includes determining that the second one or more cache lines are to be prefetched, and further includes determining a number of cache lines adjacent to the first one or more cache lines to prefetch based on the data object range value.

13. The method according to any one of claims 10 to 12, further comprising: A pointer identification value is detected in one or more bits in bits [Y-1:X] that are not used for the data object range value.

14. The method according to any one of claims 10 to 12, further comprising: A determination is made based at least in part on the data object range value whether to obtain and store in a translation lookaside buffer (TLB) address translations for memory locations adjacent to the first one or more cache lines.

15. A system comprising: Dynamic random access memory (DRAM); as well as A processor coupled to the DRAM, the processor comprising: Cache hierarchy; a memory access unit coupled to the cache hierarchy, the memory access unit configured to perform a demand load based on a Y-bit pointer so that a first one or more cache lines are loaded from the DRAM into the cache hierarchy, the Y-bit pointer having an X-bit virtual address field and a data object range field in one or more bits of bits [Y-1:X], the data object range field storing a value; and A prefetch unit coupled to the cache hierarchy is configured to determine whether to prefetch a second one or more cache lines adjacent to the first one or more cache lines from the DRAM into the cache hierarchy based at least in part on the value.

16. The system of claim 15, wherein: The value indicates a range of data objects that includes the first one or more cache lines.

17. The system of claim 15, wherein: The pre-fetch unit is used for: when the value is a first value indicating that the data object is contained within the first one or more cache lines, not prefetching the second one or more cache lines; and When the value is a second value indicating that the data object is not contained within the first one or more cache lines, the second one or more cache lines are pre-fetched.

18. A system as claimed in any one of claims 15 to 17, wherein: The Y-bit pointer has a field for storing a pointer identification value in one or more bits in bits [Y-1:X] not used for the data object range field, and wherein the prefetch unit is used to detect the pointer identification value in the code to locate the Y-bit pointer in the code.

19. The system of any one of claims 15 to 17, further comprising an address translation unit coupled to the memory access unit, the address translation unit configured to determine whether to obtain and store in a translation lookaside buffer (TLB) an address translation of a memory location adjacent to the first one or more cache lines based at least in part on the value.

20. The system of any one of claims 15 to 17, wherein: The value indicates a range of a data object including the first one or more cache lines, and wherein the Y-bit pointer has a field for storing a pointer identification value in one or more bits in bits [Y-1:X] not used for the data object range field, and wherein the prefetch unit is used to detect the pointer identification value in the code to locate the Y-bit pointer in the code.

21. A computer program product comprising instructions which, when executed by a processor, cause the processor to perform operations comprising: performing a demand load including loading a first one or more cache lines from a memory into a cache hierarchy based on a Y-bit pointer having an X-bit virtual address and a data object range value in one or more of bits [Y-1:X]; and A determination is made based at least in part on the data object range value whether to prefetch a second one or more cache lines adjacent to the first one or more cache lines from the memory into the cache hierarchy.

22. The computer program product of claim 21, wherein: The instructions for causing the processor to determine whether to prefetch the second one or more cache lines include instructions that, when executed by the processor, cause the processor to: When the data object range value indicates that the data object is contained within the first one or more cache lines, determining not to prefetch the second one or more cache lines; and When the data object range value indicates that the data object is not contained within the first one or more cache lines, it is determined to prefetch the second one or more cache lines.

23. The computer program product of claim 21, wherein: The instructions for causing the processor to determine whether to prefetch the second one or more cache lines include instructions that, when executed by the processor, cause the processor to: determining to prefetch the second one or more cache lines; and A number of cache lines adjacent to the first one or more cache lines are determined to be pre-fetched based on the data object range value.

24. A computer program product as claimed in any one of claims 21 to 23, wherein: The instructions include instructions that, when executed by the processor, cause the processor to perform the following operations: detecting a pointer identification value in one or more bits of bits [Y-1:X] that are not used for the data object range value.

25. An apparatus comprising: Cache hierarchy; a first means coupled to the cache hierarchy, the first means for performing a demand load based on a Y-bit pointer so that a first one or more cache lines are loaded from a memory into the cache hierarchy, the Y-bit pointer having an X-bit virtual address field and a data object range field in one or more bits of bits [Y-1:X], the data object range field for storing a value; as well as A second means, coupled to the cache hierarchy, is configured to determine whether to prefetch a second one or more cache lines adjacent to the first one or more cache lines from the memory into the cache hierarchy based at least in part on the value.

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