Artificial intelligence chip and operation method thereof

Abstract

The invention provides an artificial intelligence chip and an operation method thereof. The artificial intelligence chip comprises a shared memory, a plurality of arbitration circuits, a first execution unit, a second execution unit, a first splitting circuit and a second splitting circuit. The arbitration circuits are coupled to a plurality of memory banks of a shared memory in a one-to-one manner. The first splitting circuit distributes access information to a corresponding arbitration circuit based on a first access target of the first execution unit issuing the first access request. The second splitting circuit distributes the access information to a corresponding arbitration circuit based on a second access target of the second execution unit issuing the second access request. Each arbitration circuit selectively executes one of the access information distributed by the first splitting circuit and the access information distributed by the second splitting circuit to access the corresponding repository.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to an artificial intelligence chip and an operation method thereof. Background Art

[0002] An arithmetic device such as an artificial intelligence (AI) chip can provide huge computing power. The huge computing power of the AI chip stems from a large number of internal hardware cores. An AI chip usually includes multiple programmable processors, such as a Stream Processor Cluster (SPC). Each programmable processor usually includes multiple Compute Units (CUs, or computing cores), and each Compute Unit usually includes multiple Execution Units (EUs, or execution cores), such as at least one of an Integer (INT) core, a FloatingPoint (FP) core, a Tensor core (Tcore), and / or a Vector core (Vcore). By programming to organize various types of Compute Units, the programmable multi-processor can support general computing, scientific computing, and neural network computing.

[0003] Each Compute Unit also includes a shared memory. In the same Compute Unit, different Execution Units exchange data through the shared memory. When an Execution Unit accesses the shared memory, other Execution Units cannot access the shared memory. However, in actual operation scenarios, the addresses at which different Execution Units access the shared memory may not conflict with each other. Therefore, the situation of "when an Execution Unit accesses the shared memory, other Execution Units cannot access the shared memory" will cause waste of the bandwidth of the shared memory. Due to the slow memory operation, the AI calculation latency is relatively high. How to enable different Execution Units in the same Compute Unit to access the shared memory in a more efficient manner is one of many technical issues in this field. Summary of the Invention

[0004] The present invention provides an artificial intelligence chip and an operation method thereof to efficiently access the shared memory in a Compute Unit.

[0005] In an embodiment according to the present invention, an artificial intelligence chip includes a shared memory, a plurality of arbitration circuits, a first execution unit, a second execution unit, a first splitting circuit, and a second splitting circuit. The shared memory includes a plurality of repositories. The plurality of arbitration circuits are coupled to the plurality of repositories in a one-to-one manner. The first splitting circuit is coupled to the first execution unit and the plurality of arbitration circuits. In response to a first access request issued by the first execution unit, the first splitting circuit distributes the access information corresponding to the first access request to a corresponding one of the plurality of arbitration circuits based on the first access target of the first access request. The second splitting circuit is coupled to the second execution unit and the plurality of arbitration circuits. In response to a second access request issued by the second execution unit, the second splitting circuit distributes the access information corresponding to the second access request to a corresponding one of the plurality of arbitration circuits based on the second access target of the second access request. Each of the plurality of arbitration circuits selectively executes one of the access information distributed by the first splitting circuit and the access information distributed by the second splitting circuit to access a corresponding one of the plurality of repositories.

[0006] In an embodiment according to the present invention, an operation method includes: providing a plurality of repositories by a shared memory of an artificial intelligence chip; in response to a first access request issued by a first execution unit, distributing, by a first splitting circuit, the access information corresponding to the first access request to a corresponding one of a plurality of arbitration circuits based on a first access target of the first access request; in response to a second access request issued by a second execution unit, distributing, by a second splitting circuit, the access information corresponding to the second access request to a corresponding one of the plurality of arbitration circuits based on a second access target of the second access request; and selectively executing, by each of the plurality of arbitration circuits, one of the access information distributed by the first splitting circuit and the access information distributed by the second splitting circuit to access a corresponding one of the plurality of repositories.

[0007] Based on the above, the splitting circuit distributes the access information corresponding to the access request to the corresponding arbitration circuit based on the access target of the access request of the corresponding execution unit to access the corresponding repository in the shared memory. Each repository is configured with an arbitration circuit to arbitrate access requests from different execution units. When one execution unit accesses the corresponding repository in the shared memory, other execution units can access other repositories in the shared memory without waiting. In other words, different execution units can access the same shared memory simultaneously. Therefore, the artificial intelligence chip can efficiently access the shared memory in the computing unit. Description of the Drawings

[0008] Figure 1 is a schematic diagram of a circuit block of an electronic system illustrated according to an embodiment; Figure 2It is a schematic block diagram of a programmable processor shown according to an embodiment; Figure 3 It is a schematic block diagram of an artificial intelligence chip according to an embodiment of the present invention; Figure 4 It is a schematic flowchart of an operation method of an artificial intelligence chip according to an embodiment of the present invention; Figure 5 And Figure 6 It is a schematic block diagram of a split circuit and an arbitration circuit shown according to an embodiment of the present invention.

[0009] Explanation of reference numerals in the drawings 100: Electronic system; 110: First artificial intelligence chip; 111_1: First programmable processor; 111_a: a-th programmable processor; 112: Secondary cache; 120: Main memory; 200: Programmable processor; 210_1: First computing unit; 210_b: b-th computing unit; 211_1_1: First_1 execution unit; 211_1_c: First_c execution unit; 211_b_1: b_1 execution unit; 211_b_d: b_d execution unit; 212_1: First shared memory; 212_b: b-th shared memory; 220: Interface circuit; 300: Second artificial intelligence chip; 310_1: First execution unit; 310_e: e-th execution unit; 320_1: First split circuit; 320_e: e-th split circuit; 321_1: First write split circuit; 321_e: e-th write split circuit; 322_1: Second_1 sideband memory; 322_e: Second_e sideband memory; 323_1: First read split circuit; 323_e: e-th read split circuit; 324_1: First data collection circuit; 324_e: The e-th data collection circuit; 325_1: The 5_1-th sideband memory; 325_e: The 5_e-th sideband memory; 330_1: The 1st arbitration circuit; 330_2: The 2nd arbitration circuit; 330_n: The n-th arbitration circuit; 331: The 1st arbiter; 332: The 2nd arbiter; 333: Selector; 340: Shared memory; B1: The 1st repository; B2: The 2nd repository; Bn: The n-th repository; C11: The C_1_1-th first-in-first-out buffer; C12: The C_1_2-th first-in-first-out buffer; C1n: The C_1_n-th first-in-first-out buffer; Ce1: The C_e_1-th first-in-first-out buffer; Ce2: The C_e_2-th first-in-first-out buffer; Cen: The C_e_n-th first-in-first-out buffer; D11: The D_1_1-th first-in-first-out buffer; D12: The D_1_2-th first-in-first-out buffer; D1n: The D_1_n-th first-in-first-out buffer; De1: The D_e_1-th first-in-first-out buffer; De2: The D_e_2-th first-in-first-out buffer; Den: The D_e_n-th first-in-first-out buffer; F11: The 11-th first-in-first-out buffer; F12: The 12-th first-in-first-out buffer; F1n: The 1n-th first-in-first-out buffer; Fe1: The e1-th first-in-first-out buffer; Fe2: The e2-th first-in-first-out buffer; Fen: The en-th first-in-first-out buffer. Detailed implementation mode

[0010] Reference will now be made in detail to the exemplary embodiments of the present invention. Examples of the exemplary embodiments are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts. Components / elements / steps with the same reference numerals or the same terms used in different embodiments may be referred to each other's relevant descriptions.

[0011] As used throughout the specification of this case (including the claims), the term "coupled (or connected)" can refer to any direct or indirect connection means. For example, if it is described in the text that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connection means. The terms "first", "second", etc. mentioned throughout the specification of this case (including the claims) are used to name components or to distinguish different embodiments or scopes, rather than to limit the upper or lower limit of the number of components, nor to limit the order of the components.

[0012] Figure 1 FIG. 6 is a block circuit diagram of an electronic system 100 shown according to an embodiment. Figure 1 The shown electronic system 100 includes a first artificial intelligence chip 110 and a main memory 120. The electronic system 100 can access the main memory 120. In different application cases, the first artificial intelligence chip 110 can be used as a Graphics Processing Unit (GPU), a General-Purpose computing on GPU (GPGPU), or other processing circuits. The first artificial intelligence chip 110 can provide huge computing power. The huge computing power of the first artificial intelligence chip 110 comes from a large number of internal hardware cores. In Figure 1 the shown embodiment, the first artificial intelligence chip 110 includes a level 2 cache (L2 Cache) 112 and multiple programmable processors, such as Figure 1 the shown first programmable processor 111_1,..., the a-th programmable processor 111_a. The number a of the first programmable processor 111_1 to the a-th programmable processor 111_a is an integer determined according to the actual design. In different application cases, the first programmable processor 111_1 to the a-th programmable processor 111_a can be a stream processor cluster or other processors. The first programmable processor 111_1 to the a-th programmable processor 111_a can access the main memory 120 through the level 2 cache 112. In different application cases, the main memory 120 can include High Bandwidth Memory (HBM) or other memories.

[0013] Figure 2 FIG. 16 is a block circuit diagram of a programmable processor 200 shown according to an embodiment. Figure 2 The shown programmable processor 200 can refer to Figure 1Related description of any one of the first programmable processors 111_1 to the a-th programmable processor 111_a shown. Figure 2 The programmable processor 200 shown can be used as Figure 1 One of many implementation examples of any one of the first programmable processors 111_1 to the a-th programmable processor 111_a shown. In Figure 2 The embodiment shown, the programmable processor 200 includes an interface circuit 220 and a plurality of computing units, such as Figure 2 The first computing unit 210_1 shown, …, the b-th computing unit 210_b. The number b of the first computing unit 210_1 to the b-th computing unit 210_b is an integer determined according to the actual design. The first computing unit 210_1 to the b-th computing unit 210_b can access the secondary cache 112 through the interface circuit 220. By programming to organize various types of computing units, the programmable processor 200 can support general computing, scientific computing, and neural network computing.

[0014] Each of the first computing unit 210_1 to the b-th computing unit 210_b includes a shared memory and a plurality of execution units, such as at least one of an integer core, a floating-point core, a tensor core, and / or a vector core. In the same computing unit, different execution units exchange data through the shared memory and access the secondary cache 112 through the shared memory. In Figure 2 The embodiment shown, the first computing unit 210_1 includes the first shared memory 212_1 and the first_1 execution unit 211_1_1, …, the first_c execution unit 211_1_c, and the b-th computing unit 210_b includes the b-th shared memory 212_b and the b_1 execution unit 211_b_1, …, the b_d execution unit 211_b_d. The number c of the first_1 execution unit 211_1_1 to the first_c execution unit 211_1_c and the number d of the b_1 execution unit 211_b_1 to the b_d execution unit 211_b_d are integers determined according to the actual design. The following embodiments will illustrate how to enable different execution units among the first_1 execution unit 211_1_1 to the first_c execution unit 211_1_c to simultaneously access different banks of the first shared memory 212_1, or enable different execution units among the b_1 execution unit 211_b_1 to the b_d execution unit 211_b_d to simultaneously access different banks of the b-th shared memory 212_b.

[0015] Figure 3 It is a circuit block diagram of a second artificial intelligence chip 300 according to an embodiment of the present invention. Figure 3The second artificial intelligence chip 300 shown includes a shared memory 340 and a plurality of arbitration circuits, such as Figure 3 the first arbitration circuit 330_1, the second arbitration circuit 330_2,..., the nth arbitration circuit 330_n shown. The number n of the first arbitration circuit 330_1 to the nth arbitration circuit 330_n is an integer determined according to the actual design. The shared memory 340 includes a plurality of memory banks, such as Figure 3 the first memory bank B1, the second memory bank B2,..., the nth memory bank Bn shown. The first arbitration circuit 330_1 to the nth arbitration circuit 330_n are coupled to the first memory bank B1 to the nth memory bank Bn in a one-to-one manner. Figure 3 The second artificial intelligence chip 300 shown can refer to Figure 1 the relevant description of the first artificial intelligence chip 110 shown and make an analogy, and Figure 3 the shared memory 340 shown can refer to Figure 2 the relevant description of the first shared memory 212_1 or the bth shared memory 212_b shown and make an analogy.

[0016] The second artificial intelligence chip 300 further includes a plurality of execution units and a plurality of split circuits, such as Figure 3 the first execution unit 310_1,..., the e-th execution unit 310_e and the first split circuit 320_1,..., the e-th split circuit 320_e shown. The number e of the first execution unit 310_1 to the e-th execution unit 310_e is an integer determined according to the actual design. Figure 3 The first execution unit 310_1 to the e-th execution unit 310_e shown can refer to Figure 2 the relevant description of the first_1 execution unit 211_1_1 to the first_c execution unit 211_1_c shown and make an analogy, or refer to Figure 2The related descriptions of the b_1th execution unit 211_b_1 to the b_dth execution unit 211_b_d shown are given and extended by analogy. For example (but not limited to this), one of the 1st execution unit 310_1 and the e-th execution unit 310_e is a tensor core, and the other of the 1st execution unit 310_1 and the e-th execution unit 310_e is a vector core. The 1st splitting circuit 320_1 is coupled to the 1st execution unit 310_1 and the 1st arbitration circuit 330_1 to the n-th arbitration circuit 330_n. The e-th splitting circuit 320_e is coupled to the e-th execution unit 310_e and the 1st arbitration circuit 330_1 to the n-th arbitration circuit 330_n. The shared memory 340, the 1st arbitration circuit 330_1 to the n-th arbitration circuit 330_n, the 1st execution unit 310_1 to the e-th execution unit 310_e, and the 1st splitting circuit 320_1 to the e-th splitting circuit 320_e are arranged in the same computing unit of the 2nd artificial intelligence chip 300.

[0017] Figure 4 It is a schematic flowchart of an operation method of an artificial intelligence chip according to an embodiment of the present invention. Each step in the schematic flowchart or a combination of steps in the flowchart can be implemented by various means, such as hardware, one or more computer-readable media storing computer programs, or computer program products. In some embodiments, Figure 4 The operation method shown can be implemented in firmware or software (i.e., a program). For example, Figure 4 The related operations of the operation method shown can be implemented as non-transitory machine-readable instructions (codes or programs), and the non-transitory machine-readable instructions can be stored in a "non-temporary machine-readable storage medium". When the non-transitory machine-readable instructions are executed by a computer, the operation method shown can be implemented Figure 4 In other embodiments, Figure 4 The operation method shown can be implemented in hardware, for example, implemented in Figure 3At least one of the first execution units 310_1 to the e-th execution unit 310_e, the first splitting circuits 320_1 to the e-th splitting circuits 320_e, and the first arbitration circuits 330_1 to the n-th arbitration circuits 330_n shown. In some other embodiments, one or more steps in the process schematic diagram can be embodied by a computer program of a computer program product. The computer program product can be stored by one or more memory devices in a computing device and executed by a processor in the computing device. The computer program product can be implemented on a computer or other programmable device to generate a machine such that the computer program product generates functions for implementing those specified in the steps of the process schematic diagram. The computer program product can include one or more computer-readable memories (on which computer program instructions can be stored), or the computer program instructions of one or more computer program products can also be loaded onto a computer or other programmable device.

[0018] Please refer to Figure 3 and Figure 4 , all of the first execution units 310_1 to the e-th execution unit 310_e need to access the shared memory 340. In step S410, the shared memory 340 provides multiple repositories of the first repository B1 to the n-th repository Bn. In an actual operating scenario, any one or more of the first execution units 310_1 to the e-th execution unit 310_e will issue an access request. In response to the first execution unit 310_1 (the first execution unit) issuing a first access request, the first splitting circuit 320_1 (the first splitting circuit) distributes the access information corresponding to the first access request to a corresponding one (the corresponding arbitration circuit) among the first arbitration circuits 330_1 to the n-th arbitration circuits 330_n based on the first access target of the first access request (step S420). In response to the e-th execution unit 310_e (the second execution unit) issuing a second access request, the e-th splitting circuit 320_e (the second splitting circuit) distributes the access information corresponding to the second access request to a corresponding one (the corresponding arbitration circuit) among the first arbitration circuits 330_1 to the n-th arbitration circuits 330_n based on the second access target of the second access request (step S430). Each of the first arbitration circuits 330_1 to the n-th arbitration circuits 330_n selectively executes one of the access information distributed by the first splitting circuits 320_1 to the e-th splitting circuits 320_e (that is, one of the access information distributed by the first execution unit and the access information distributed by the second execution unit) to access a corresponding one (the corresponding repository) among the multiple repositories (the first repository B1 to the n-th repository Bn) (step S440).

[0019] Assume that the access target of the access request of the first execution unit 310_1 is in the first repository B1. In response to the first splitting circuit 320_1 dispatching the access information corresponding to the access request of the first execution unit 310_1 to the first arbitration circuit 330_1 based on the access target of the access request of the first execution unit 310_1, while other splitting circuits (such as the e-th splitting circuit 320_e) do not dispatch access information to the first arbitration circuit 330_1, the first arbitration circuit 330_1 executes the access information dispatched by the first splitting circuit 320_1 to access the first repository B1, and sends back the access result information to the first splitting circuit 320_1.

[0020] Assume that the access target of the access request of the e-th execution unit 310_e is in the second repository B2. In response to the e-th splitting circuit 320_e dispatching the access information corresponding to the access request of the e-th execution unit 310_e to the second arbitration circuit 330_2 based on the access target of the access request of the e-th execution unit 310_e, while other splitting circuits (such as the first splitting circuit 320_1) do not dispatch access information to the second arbitration circuit 330_2, the second arbitration circuit 330_2 executes the access information dispatched by the e-th splitting circuit 320_e to access the second repository B2, and sends back the access result information to the e-th splitting circuit 320_e.

[0021] In summary, the first splitting circuit 320_1 to the e-th splitting circuit 320_e dispatch the access information corresponding to the access request to the corresponding arbitration circuit based on the access target of the access request of the corresponding execution unit, so as to access the corresponding repository in the shared memory 340. Each of the first repository B1 to the n-th repository Bn is configured with an arbitration circuit to arbitrate the access requests from different execution units of the first execution unit 310_1 to the e-th execution unit 310_e. When an execution unit accesses the corresponding repository in the shared memory 340, other execution units can access other repositories in the shared memory 340 without waiting. In other words, different execution units among the first execution unit 310_1 to the e-th execution unit 310_e can access the same shared memory 340 simultaneously. Therefore, the second artificial intelligence chip 300 can efficiently access the shared memory 340 in the computing unit.

[0022] Figure 5 With Figure 6 is a circuit block diagram of the splitting circuit and the arbitration circuit shown according to an embodiment of the present invention. Figure 5 With Figure 6 The first execution unit 310_1 to the e-th execution unit 310_e, the first splitting circuit 320_1 to the e-th splitting circuit 320_e, the first arbitration circuit 330_1, and the shared memory 340 shown can be referred to Figure 3the relevant descriptions and make analogies. Although Figure 5 and Figure 6 only shows the first arbitration circuit 330_1, however, other arbitration circuits (such as the nth arbitration circuit 330_n) can refer to the relevant descriptions of the first arbitration circuit 330_1 and make analogies, so in Figure 5 and Figure 6 the embodiments shown are not elaborated. Figure 5 shows a schematic diagram of the situation where the execution unit issues a write request, while Figure 6 shows a schematic diagram of the situation where the execution unit issues a read request.

[0023] Please refer to Figure 5 , in response to the first splitting circuit (such as one of the first splitting circuit 320_1 to the e-th splitting circuit 320_e) dispatching the access information corresponding to the first access request including the write request to the first arbitration circuit (such as the first arbitration circuit 330_1) and the second splitting circuit (such as another one of the first splitting circuit 320_1 to the e-th splitting circuit 320_e) not dispatching access information to the first arbitration circuit (such as the first arbitration circuit 330_1), the first arbitration circuit (such as the first arbitration circuit 330_1) writes the data corresponding to the write request into the first storage repository (such as the first storage repository B1) based on the access information corresponding to the write request, then the first arbitration circuit (such as the first arbitration circuit 330_1) sends the access result information indicating the completion of the write back to the first splitting circuit, and the first splitting circuit sends the access result information back to the first execution unit (such as one of the first execution unit 310_1 to the e-th execution unit 310_e).

[0024] In detail, in Figure 5In the illustrated embodiment, the first splitting circuit 320_1 includes a first write splitting circuit 321_1, a second_1 sideband memory 322_1, and a plurality of first-in-first-out (FIFO) buffers, such as the 11th FIFO buffer F11, the 12th FIFO buffer F12, …, the 1nth FIFO buffer F1n. The 11th FIFO buffer F11 to the 1nth FIFO buffer F1n are coupled to the first arbitration circuit 330_1 to the nth arbitration circuit 330_n in a one-to-one manner. For example, the 11th FIFO buffer F11 is coupled to the first arbitration circuit 330_1. The first write splitting circuit 321_1 is coupled to the first execution unit 310_1 and the 11th FIFO buffer F11 to the 1nth FIFO buffer F1n. In response to an access request including a write request issued by the first execution unit 310_1, the first write splitting circuit 321_1 distributes the access information corresponding to the access request to a corresponding one of the 11th FIFO buffer F11 to the 1nth FIFO buffer F1n based on the access target of the access request. For example, assuming that the access target of the access request of the first execution unit 310_1 is in the first repository B1, the first write splitting circuit 321_1 distributes the access information corresponding to the access request to the corresponding 11th FIFO buffer F11. The second_1 sideband memory 322_1 is coupled to the first execution unit 310_1 and the first arbitration circuit 330_1 to the nth arbitration circuit 330_n. The first arbitration circuit 330_1 to the nth arbitration circuit 330_n send the write request result information back to the second_1 sideband memory 322_1 to notify the first execution unit 310_1.

[0025] The 11th first-in first-out buffer F11 to the 1nth first-in first-out buffer F1n are used to store the data and addresses requested by the 1st execution unit 310_1. The 1st write splitting circuit 321_1 receives write requests from the 1st execution unit 310_1. The 1st write splitting circuit 321_1 splits the write requests into small requests (access information), and then writes the corresponding addresses (the addresses of the 1st repository B1 to the nth repository Bn) and data into one of the 11th first-in first-out buffer F11 to the 1nth first-in first-out buffer F1n. For example, assuming that the access target of a write request is the 1st repository B1 to the 8th repository (the 8th repository is one of the other repositories among the 1st repository B1 to the nth repository Bn except the 1st repository B1, the 2nd repository B2, and the nth repository Bn), then the write request will be split into small requests (access information), and the corresponding addresses and data will be pushed into the corresponding 11th first-in first-out buffer F11 to the 18th first-in first-out buffer (the 18th first-in first-out buffer is one of the other first-in first-out buffers among the 11th first-in first-out buffer F11 to the 1nth first-in first-out buffer F1n except the 11th first-in first-out buffer F11, the 12th first-in first-out buffer F12, and the 1nth first-in first-out buffer F1n). The 2_1 sideband memory 322_1 records the request information, including which repository to write to and the return information after the write is completed. The 1st write splitting circuit 321_1 writes the sideband information into the 2_1 sideband memory 322_1 while writing the data into the 11th first-in first-out buffer F11 to the 18th first-in first-out buffer.

[0026] The e-th splitting circuit 320_e includes an e-th write splitting circuit 321_e, a 2_e-th sideband memory 322_e, and a plurality of first-in first-out (FIFO) buffers, such as an e1-th FIFO buffer Fe1, an e2-th FIFO buffer Fe2, …, an en-th FIFO buffer Fen. The e1-th FIFO buffer Fe1 to the en-th FIFO buffer Fen are coupled to the 1-st arbitration circuit 330_1 to the n-th arbitration circuit 330_n in a one-to-one manner. For example, the e1-th FIFO buffer Fe1 is coupled to the 1-st arbitration circuit 330_1. The e-th write splitting circuit 321_e is coupled to the e-th execution unit 310_e and the e1-th FIFO buffer Fe1 to the en-th FIFO buffer Fen. In response to an access request including a write request issued by the e-th execution unit 310_e, the e-th write splitting circuit 321_e distributes the access information corresponding to the access request to a corresponding one of the e1-th FIFO buffer Fe1 to the en-th FIFO buffer Fen based on the access target of the access request. For example, assuming that the access target of the access request of the e-th execution unit 310_e is in the 2-nd repository B2, the e-th write splitting circuit 321_e distributes the access information corresponding to the access request to the corresponding e2-th FIFO buffer Fe2. The 2_e-th sideband memory 322_e is coupled to the e-th execution unit 310_e and the 1-st arbitration circuit 330_1 to the n-th arbitration circuit 330_n. The 1-st arbitration circuit 330_1 to the n-th arbitration circuit 330_n send the write request result information back to the 2_e-th sideband memory 322_e to notify the e-th execution unit 310_e.

[0027] The e1st first-in-first-out buffer Fe1 to the en-th first-in-first-out buffer Fen are used to store the data and addresses requested from the e-th execution unit 310_e. The e-th write splitting circuit 321_e receives a write request from the e-th execution unit 310_e. The e-th write splitting circuit 321_e splits the write request into small requests (access information), and writes the corresponding addresses (the addresses of the respective first memory banks B1 to the n-th memory bank Bn) and data into one of the e1st first-in-first-out buffer Fe1 to the en-th first-in-first-out buffer Fen. For example, assuming that the access target of a write request is the first memory bank B1 to the eighth memory bank, the write request will be split into small requests (access information), and the corresponding addresses and data will be pushed into the corresponding e1st first-in-first-out buffer Fe1 to the e8th first-in-first-out buffer (the e8th first-in-first-out buffer is one of the first-in-first-out buffers other than the e1st first-in-first-out buffer Fe1, the e2nd first-in-first-out buffer Fe2, and the en-th first-in-first-out buffer Fen among the e1st first-in-first-out buffer Fe1 to the en-th first-in-first-out buffer Fen). When the e-th write splitting circuit 321_e writes data into the e1st first-in-first-out buffer Fe1 to the e8th first-in-first-out buffer, the e-th write splitting circuit 321_e also writes sideband information into the 2_e sideband memory 322_e.

[0028] The first arbitration circuit 330_1 includes a first arbiter 331. Each of the first repository B1 to the nth repository Bn can serve one read and one write simultaneously within one cycle. For the first repository B1, requests are obtained from the first FIFO buffer F11 and sent to the first arbiter 331 of the first repository B1, and requests are obtained from the e1th FIFO buffer Fe1 to the en th FIFO buffer Fen and sent to the first arbiter 331 of the first repository B1. The first arbiter 331 arbitrates between the requests of the first execution unit 310_1 and the requests of the e execution unit 310_e. The authorization request for the first repository B1 from the first execution unit 310_1 or the e execution unit 310_e will be sent to the first repository B1 for a write operation. In addition, the first arbiter 331 sends out authorization information. The authorization information is sent to the 2_1 sideband memories 322_1 to the 2_e sideband memories 322_e of the first splitting circuit 320_1 to the e splitting circuits 320_e. The 2_1 sideband memories 322_1 to the 2_e sideband memories 322_e record the completion signals of each request. When all the data of a write request of the first execution unit 310_1 are written into the shared memory 340, indicating the completion of the write request, the 2_1 sideband memory 322_1 sends a completion signal to the first execution unit 310_1. When all the data of a write request of the e execution unit 310_e are written into the shared memory 340, indicating the completion of the write request, the 2_e sideband memory 322_e sends a completion signal to the e execution unit 310_e.

[0029] Please refer to Figure 6 , in response to the first splitting circuit (such as one of the first splitting circuit 320_1 to the e splitting circuits 320_e) dispatching the access information corresponding to the first access request including a read request to the first arbitration circuit (such as the first arbitration circuit 330_1) while the second splitting circuit (such as another one of the first splitting circuit 320_1 to the e splitting circuits 320_e) does not dispatch access information to the first arbitration circuit (such as the first arbitration circuit 330_1), the first arbitration circuit (such as the first arbitration circuit 330_1) reads out the data corresponding to the read request from the first repository (such as the first repository B1) based on the access information corresponding to the read request, then the first arbitration circuit (such as the first arbitration circuit 330_1) sends the data back to the first splitting circuit, and the first splitting circuit sends the data back to the first execution unit (such as one of the first execution unit 310_1 to the e execution unit 310_e).

[0030] Specifically, in Figure 6In the illustrated embodiment, the first splitting circuit 320_1 includes a first read splitting circuit 323_1, a fifth_1 sideband memory 325_1, and a plurality of first-in-first-out buffers, such as a first-in-first-out buffer C11 of C_1_1, a first-in-first-out buffer C12 of C_1_2, …, a first-in-first-out buffer C1n of C_1_n. The first-in-first-out buffer C11 of C_1_1 to the first-in-first-out buffer C1n of C_1_n are coupled to the first arbitration circuit 330_1 to the nth arbitration circuit 330_n in a one-to-one manner. For example, the first-in-first-out buffer C11 of C_1_1 is coupled to the first arbitration circuit 330_1. The first read splitting circuit 323_1 is coupled to the first execution unit 310_1 and the first-in-first-out buffer C11 of C_1_1 to the first-in-first-out buffer C1n of C_1_n. The first read splitting circuit 323_1 receives a read request from the first execution unit 310_1. In response to an access request including a read request issued by the first execution unit 310_1, the first read splitting circuit 323_1 distributes the access information corresponding to the access request to a corresponding one of the first-in-first-out buffer C11 of C_1_1 to the first-in-first-out buffer C1n of C_1_n based on the access target of the access request. That is, the first read splitting circuit 323_1 splits and stores the read request issued by the first execution unit 310_1 into the corresponding first-in-first-out buffer C11 of C_1_1 to the first-in-first-out buffer C1n of C_1_n. For example, assuming that the access target of the access request of the first execution unit 310_1 is in the first repository B1, the first read splitting circuit 323_1 distributes the access information corresponding to the access request to the corresponding first-in-first-out buffer C11 of C_1_1. The first read splitting circuit 323_1 also stores the sideband information of the read request into the fifth_1 sideband memory 325_1.

[0031] The first splitting circuit 320_1 further includes a first data collection circuit 324_1 and a plurality of first-in-first-out buffers, such as the first-in-first-out buffer D11 of D_1_1, the first-in-first-out buffer D12 of D_1_2, …, the first-in-first-out buffer D1n of D_1_n. The first-in-first-out buffer D11 of D_1_1 to the first-in-first-out buffer D1n of D_1_n are used to store the data returned from the first repository B1 to the first splitting circuit 320_1. The first-in-first-out buffer D11 of D_1_1 to the first-in-first-out buffer D1n of D_1_n are coupled to the first arbitration circuit 330_1 to the nth arbitration circuit 330_n in a one-to-one manner to receive data. For example, the first-in-first-out buffer D11 of D_1_1 is coupled to the first arbitration circuit 330_1. The first data collection circuit 324_1 is coupled to the first execution unit 310_1 and the first-in-first-out buffer D11 of D_1_1 to the first-in-first-out buffer D1n of D_1_n. In response to an access request including a read request issued by the first execution unit 310_1, the first data collection circuit 324_1 reads out the data corresponding to the read request from a corresponding one of the first-in-first-out buffer D11 of D_1_1 to the first-in-first-out buffer D1n of D_1_n based on the access target of the access request, and the first data collection circuit 324_1 feeds back the data read out from a corresponding one of the first-in-first-out buffer D11 of D_1_1 to the first-in-first-out buffer D1n of D_1_n to the first execution unit 310_1.

[0032] The e-th splitting circuit 320_e includes an e-th read splitting circuit 323_e, a 5_e-th sideband memory 325_e, and a plurality of first-in-first-out buffers, such as a first C_e_1 first-in-first-out buffer Ce1, a first C_e_2 first-in-first-out buffer Ce2, …, a first C_e_n first-in-first-out buffer Cen. The first C_e_1 first-in-first-out buffer Ce1 to the first C_e_n first-in-first-out buffer Cen are coupled to the first arbitration circuit 330_1 to the n-th arbitration circuit 330_n in a one-to-one manner. For example, the first C_e_1 first-in-first-out buffer Ce1 is coupled to the first arbitration circuit 330_1. The e-th read splitting circuit 323_e is coupled to the e-th execution unit 310_e and the first C_e_1 first-in-first-out buffer Ce1 to the first C_e_n first-in-first-out buffer Cen. The e-th read splitting circuit 323_e receives a read request from the e-th execution unit 310_e. In response to an access request including a read request issued by the e-th execution unit 310_e, the e-th read splitting circuit 323_e distributes the access information corresponding to the access request to a corresponding one of the first C_e_1 first-in-first-out buffer Ce1 to the first C_e_n first-in-first-out buffer Cen based on the access target of the access request. That is, the e-th read splitting circuit 323_e splits and stores the request issued by the e-th execution unit 310_e into the corresponding first C_e_1 first-in-first-out buffer Ce1 to the first C_e_n first-in-first-out buffer Cen. For example, assuming that the access target of the access request of the e-th execution unit 310_e is in the second repository B2, the e-th read splitting circuit 323_e distributes the access information corresponding to the access request to the corresponding first C_e_2 first-in-first-out buffer Ce2. The e-th read splitting circuit 323_e also stores the sideband information of the read request into the 5_e-th sideband memory 325_e.

[0033] The e-th splitting circuit 320_e further includes an e-th data collection circuit 324_e and a plurality of first-in-first-out buffers, such as the D_e_1 first-in-first-out buffer De1, the D_e_2 first-in-first-out buffer De2, …, the D_e_n first-in-first-out buffer Den. The D_e_1 first-in-first-out buffer De1 to the D_e_n first-in-first-out buffer Den are used to store the data returned from the first repository B1 to the e-th splitting circuit 320_e. The D_e_1 first-in-first-out buffer De1 to the D_e_n first-in-first-out buffer Den are coupled to the first arbitration circuit 330_1 to the n-th arbitration circuit 330_n in a one-to-one manner to receive data. For example, the D_e_1 first-in-first-out buffer De1 is coupled to the first arbitration circuit 330_1. The e-th data collection circuit 324_e is coupled to the e-th execution unit 310_e and the D_e_1 first-in-first-out buffer De1 to the D_e_n first-in-first-out buffer Den. In response to an access request including a read request issued by the e-th execution unit 310_e, the e-th data collection circuit 324_e reads the data corresponding to the read request from a corresponding one of the D_e_1 first-in-first-out buffer De1 to the D_e_n first-in-first-out buffer Den based on the access target of the access request, and the e-th data collection circuit 324_e returns the data read from a corresponding one of the D_e_1 first-in-first-out buffer De1 to the D_e_n first-in-first-out buffer Den to the e-th execution unit 310_e.

[0034] The first arbitration circuit 330_1 includes a second arbiter 332 and a selector 333. The second arbiter 332 is coupled to the first repository B1 and the first-in-first-out buffers C11 to Ce1 of the first splitting circuit 320_1 to the e-th splitting circuit 320_e. The selector 333 is coupled to the second arbiter 332 to receive the access result. The selector 333 is coupled to the first repository B1 to receive the data corresponding to the read request. The selector 333 is also coupled to the first-in-first-out buffers D11 to De1 of the first splitting circuit 320_1 to the e-th splitting circuit 320_e. In response to the first splitting circuit 320_1 dispatching the access information corresponding to the read request to the first arbitration circuit 330_1 while the e-th splitting circuit 320_e does not dispatch the access information to the first arbitration circuit 330_1, the second arbiter 332 dispatches the access information corresponding to the read request to the first repository B1, and the selector 333 returns the data to the first-in-first-out buffer D11 corresponding to the first splitting circuit 320_1. Similarly, in response to the e-th splitting circuit 320_e dispatching the access information corresponding to the read request to the first arbitration circuit 330_1 while the first splitting circuit 320_1 does not dispatch the access information to the first arbitration circuit 330_1, the second arbiter 332 dispatches the access information corresponding to the read request to the first repository B1, and the selector 333 returns the data to the first-in-first-out buffer De1 corresponding to the e-th splitting circuit 320_e.

[0035] The read request of the first execution unit 310_1 for the first repository B1 will be sent to the second arbiter 332 serving the first repository B1, and the read request of the e-th execution unit 310_e for the first repository B1 will be sent to the second arbiter 332 serving the first repository B1. The second arbiter 332 selects whether to serve the read request of the first execution unit 310_1 or the read request of the e-th execution unit 310_e. The approved read request will be sent to the first repository B1 of the shared memory 340. The data read from the first repository B1 is sent to the selector 333.

[0036] In addition, the second arbiter 332 also sends the authorization information to the selector 333. Based on the authorization information provided by the second arbiter 332, the selector 333 determines whether the data returned from the first repository B1 is for the first execution unit 310_1 or the e-th execution unit 310_e. For example, in response to the first splitting circuit 320_1 dispatching the access information corresponding to the read request to the first arbitration circuit 330_1, the selector 333 sends the data returned from the first repository B1 to the D_1_1 first-in-first-out buffer D11 of the first splitting circuit 320_1. Similarly, in response to the e-th splitting circuit 320_e dispatching the access information corresponding to the read request to the first arbitration circuit 330_1, the selector 333 sends the data returned from the first repository B1 to the D_e_1 first-in-first-out buffer De1 of the e-th splitting circuit 320_e.

[0037] The first data collection circuit 324_1 obtains sideband information from the 5_1 sideband memory 325_1 to check whether all the required data has been returned. In response to the data required by the first execution unit 310_1 having been returned from the D_1_1 first-in-first-out buffer D11 to the D_1_n first-in-first-out buffer D1n, the first data collection circuit 324_1 sends the data back to the first execution unit 310_1. Similarly, the e-th data collection circuit 324_e obtains sideband information from the 5_e sideband memory 325_e to check whether all the required data has been returned. In response to the data required by the e-th execution unit 310_e having been returned from the D_e_1 first-in-first-out buffer De1 to the D_e_n first-in-first-out buffer Den, the e-th data collection circuit 324_e sends the data back to the e-th execution unit 310_e.

[0038] According to different designs, in some embodiments, the implementation of at least one of the above-mentioned first write splitting circuit 321_1, first read splitting circuit 323_1, first data collection circuit 324_1, e-th read splitting circuit 323_e, and e-th data collection circuit 324_e can be a hardware circuit, firmware, software, or a combination of the foregoing.

[0039] In terms of hardware, at least one of the above-mentioned first write splitting circuit 321_1, first read splitting circuit 323_1, first data collection circuit 324_1, e-th read splitting circuit 323_e, and e-th data collection circuit 324_e can be implemented as a logic circuit on an integrated circuit. For example, the related functions of at least one of the first write splitting circuit 321_1, first read splitting circuit 323_1, first data collection circuit 324_1, e-th read splitting circuit 323_e, and e-th data collection circuit 324_e can be implemented in various logic blocks, modules, and circuits of one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), and / or other processing units. The related functions of at least one of the first write splitting circuit 321_1, first read splitting circuit 323_1, first data collection circuit 324_1, e-th read splitting circuit 323_e, and e-th data collection circuit 324_e can be implemented as a hardware circuit, such as various logic blocks, modules, and circuits in an integrated circuit, using hardware description languages (such as Verilog HDL or VHDL) or other suitable programming languages.

[0040] In terms of software form and / or firmware form, the related functions of at least one of the above-mentioned first write splitting circuit 321_1, first read splitting circuit 323_1, first data collection circuit 324_1, e-th read splitting circuit 323_e, and e-th data collection circuit 324_e can be implemented as programming codes. For example, the first write splitting circuit 321_1, first read splitting circuit 323_1, first data collection circuit 324_1, e-th read splitting circuit 323_e, and e-th data collection circuit 324_e are implemented using general programming languages (such as C, C++, or assembly language) or other suitable programming languages. The programming codes can be recorded / stored in a "non-transitory machine-readable storage medium". In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memory and / or storage devices. An electronic device (such as a computer, CPU, hardware controller, microcontroller, hardware processor, or microprocessor) can read and execute the programming codes from the non-transitory machine-readable storage medium to implement the related functions of at least one of the first write splitting circuit 321_1, first read splitting circuit 323_1, first data collection circuit 324_1, e-th read splitting circuit 323_e, and e-th data collection circuit 324_e.

[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An artificial intelligence chip, characterized in that, The artificial intelligence chip includes: A shared memory, wherein the shared memory includes a plurality of repositories; A plurality of arbitration circuits, wherein the plurality of arbitration circuits are coupled to the plurality of repositories in a one-to-one manner: A first execution unit; A second execution unit; A first splitting circuit, coupled to the first execution unit and the plurality of arbitration circuits, wherein in response to a first access request issued by the first execution unit, the first splitting circuit distributes the access information corresponding to the first access request to a corresponding one of the plurality of arbitration circuits based on a first access target of the first access request; and A second splitting circuit, coupled to the second execution unit and the plurality of arbitration circuits, wherein in response to a second access request issued by the second execution unit, the second splitting circuit distributes the access information corresponding to the second access request to a corresponding one of the plurality of arbitration circuits based on a second access target of the second access request, wherein each of the plurality of arbitration circuits selectively executes one of the access information distributed by the first splitting circuit and the access information distributed by the second splitting circuit to access a corresponding one of the plurality of repositories.

2. The artificial intelligence chip according to claim 1, wherein One of the first execution unit and the second execution unit is a tensor core, and the other of the first execution unit and the second execution unit is a vector core.

3. The artificial intelligence chip according to claim 1, characterized in that The shared memory, the plurality of arbitration circuits, the first execution unit, the second execution unit, the first splitting circuit, and the second splitting circuit are disposed in the same computing unit of the artificial intelligence chip.

4. The artificial intelligence chip according to claim 1, wherein The plurality of repositories include a first repository, and the plurality of arbitration circuits include a first arbitration circuit, and the first arbitration circuit is coupled to the first repository, the first splitting circuit, and the second splitting circuit, in response to the first splitting circuit distributing the access information corresponding to the first access request to the first arbitration circuit based on the first access target of the first access request and the second splitting circuit not distributing access information to the first arbitration circuit, the first arbitration circuit executes the access information distributed by the first splitting circuit to access the first repository, and returns the access result information to the first splitting circuit; and and in response to the second splitting circuit distributing the access information corresponding to the second access request to the first arbitration circuit based on the second access target of the second access request and the first splitting circuit not distributing access information to the first arbitration circuit, the first arbitration circuit executes the access information distributed by the second splitting circuit to access the first repository, and returns the access result information to the second splitting circuit.

5. The artificial intelligence chip according to claim 4, wherein, In response to the first splitting circuit dispatching the access information corresponding to the first access request including a write request to the first arbitration circuit while the second splitting circuit does not dispatch access information to the first arbitration circuit, the first arbitration circuit writes the data corresponding to the write request into the first repository based on the access information corresponding to the write request, the first arbitration circuit returns the access result information indicating the completion of the write to the first splitting circuit, and the first splitting circuit returns the access result information to the first execution unit.

6. The artificial intelligence chip according to claim 4, wherein In response to the first splitting circuit dispatching the access information corresponding to the first access request including a read request to the first arbitration circuit while the second splitting circuit does not dispatch access information to the first arbitration circuit, the first arbitration circuit reads out the data corresponding to the read request from the first repository based on the access information corresponding to the read request, the first arbitration circuit returns the data corresponding to the read request to the first splitting circuit, and the first splitting circuit returns the data corresponding to the read request to the first execution unit.

7. The artificial intelligence chip according to claim 6, wherein The first arbitration circuit includes: An arbiter, coupled to the first repository, the first splitting circuit, and the second splitting circuit, wherein in response to the first splitting circuit dispatching the access information corresponding to the read request to the first arbitration circuit while the second splitting circuit does not dispatch access information to the first arbitration circuit, the arbiter dispatches the access information corresponding to the read request to the first repository; and A selector, coupled to the arbiter to receive access results, and coupled to the first repository to receive the data corresponding to the read request, wherein in response to the first splitting circuit dispatching the access information corresponding to the read request to the first arbitration circuit while the second splitting circuit does not dispatch access information to the first arbitration circuit, the selector returns the data corresponding to the read request to the first splitting circuit.

8. The artificial intelligence chip according to claim 1, characterized in that, The first splitting circuit includes: A plurality of first-in-first-out buffers, wherein the plurality of first-in-first-out buffers are coupled to the plurality of arbitration circuits in a one-to-one manner; and A write splitting circuit, coupled to the first execution unit and the plurality of first-in-first-out buffers, wherein in response to the first execution unit issuing the first access request including a write request, the write splitting circuit dispatches the access information corresponding to the first access request to a corresponding one of the plurality of first-in-first-out buffers based on the first access target of the first access request.

9. The artificial intelligence chip according to claim 8, characterized in that, The first splitting circuit further includes: Sideband memory, coupled to the first execution unit and the plurality of arbitration circuits, wherein the plurality of arbitration circuits return write request result information to the sideband memory.

10. The artificial intelligence chip according to claim 1, characterized in that, The first splitting circuit includes: A plurality of first first-in-first-out buffers, wherein the plurality of first first-in-first-out buffers are coupled to the plurality of arbitration circuits in a one-to-one manner; A read splitting circuit, coupled to the first execution unit and the plurality of first-in-first-out (FIFO) buffers, wherein in response to the first access request including a read request issued by the first execution unit, the read splitting circuit distributes the access information corresponding to the first access request to a corresponding one of the plurality of first-in-first-out buffers based on the first access target of the first access request; A plurality of second-in-first-out buffers, wherein the plurality of second-in-first-out buffers are coupled to the plurality of arbitration circuits in a one-to-one manner to receive data; and A data collection circuit, coupled to the plurality of second-in-first-out buffers, wherein in response to the first access request including the read request issued by the first execution unit, the data collection circuit reads the data corresponding to the read request from a corresponding one of the plurality of second-in-first-out buffers based on the first access target of the first access request, and the data collection circuit returns the read data corresponding to the read request to the first execution unit.

11. A method for operating an artificial intelligence chip, characterized in that, The operation method includes: Providing a plurality of repositories by a shared memory of the artificial intelligence chip, wherein a plurality of arbitration circuits of the artificial intelligence chip are coupled to the plurality of repositories in a one-to-one manner, a first splitting circuit of the artificial intelligence chip is coupled to a first execution unit and the plurality of arbitration circuits of the artificial intelligence chip, and a second splitting circuit of the artificial intelligence chip is coupled to a second execution unit and the plurality of arbitration circuits of the artificial intelligence chip; In response to a first access request issued by the first execution unit, distributing, by the first splitting circuit, the access information corresponding to the first access request to a corresponding one of the plurality of arbitration circuits based on the first access target of the first access request; In response to a second access request issued by the second execution unit, distributing, by the second splitting circuit, the access information corresponding to the second access request to a corresponding one of the plurality of arbitration circuits based on the second access target of the second access request; and Selectively executing, by each of the plurality of arbitration circuits, one of the access information distributed by the first splitting circuit and the access information distributed by the second splitting circuit to access a corresponding one of the plurality of repositories.

12. The operating method according to claim 11, wherein, One of the first execution unit and the second execution unit is a tensor core, and the other of the first execution unit and the second execution unit is a vector core.

13. The operating method according to claim 11, wherein The shared memory, the plurality of arbitration circuits, the first execution unit, the second execution unit, the first splitting circuit, and the second splitting circuit are disposed in the same computing unit of the artificial intelligence chip.

14. The operating method according to claim 11, characterized in that, The plurality of repositories include a first repository, the plurality of arbitration circuits include a first arbitration circuit, the first arbitration circuit is coupled to the first repository, the first splitting circuit, and the second splitting circuit, and the operation method further includes: In response to the first splitting circuit dispatching the access information corresponding to the first access request to the first arbitration circuit based on the first access target of the first access request and the second splitting circuit not dispatching access information to the first arbitration circuit, the first arbitration circuit executes the access information dispatched by the first splitting circuit to access the first repository, and returns the access result information to the first splitting circuit; and In response to the second splitting circuit dispatching the access information corresponding to the second access request to the first arbitration circuit based on the second access target of the second access request and the first splitting circuit not dispatching access information to the first arbitration circuit, the first arbitration circuit executes the access information dispatched by the second splitting circuit to access the first repository, and returns the access result information to the second splitting circuit.

15. The operating method according to claim 14, characterized in that, The operation method further includes: In response to the first splitting circuit dispatching the access information corresponding to the first access request including a write request to the first arbitration circuit and the second splitting circuit not dispatching access information to the first arbitration circuit, the first arbitration circuit writes the data corresponding to the write request into the first repository based on the access information corresponding to the write request, the first arbitration circuit returns the access result information indicating the completion of the writing to the first splitting circuit, and the first splitting circuit returns the access result information to the first execution unit.

16. The operating method according to claim 14, characterized in that, The operation method further includes: In response to the first splitting circuit dispatching the access information corresponding to the first access request including a read request to the first arbitration circuit and the second splitting circuit not dispatching access information to the first arbitration circuit, the first arbitration circuit reads out the data corresponding to the read request from the first repository based on the access information corresponding to the read request, the first arbitration circuit returns the read data corresponding to the read request to the first splitting circuit, and the first splitting circuit returns the data corresponding to the read request read by the first arbitration circuit to the first execution unit.

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