Real-time circulating storage system and method applied to high-speed data acquisition system

Abstract

The invention relates to a system and a method applied to real-time circulating storage of a high-speed data acquisition system, which are mainly used for solving the technical problems of huge fan-out quantity of a core clock, more cross clock domains and lack of accurate description of sampling data trigger time information in the prior art when the use amount of core clock resources is reduced. The device comprises a control logic unit, a first buffer, a second buffer, a memory, a time measurement unit and at least one clock manager, a double-cache structure of a small-capacity first cache and a large-capacity second cache is adopted, only one clock manager is needed at least, and the problem that a time sequence is not converged in time information of a high-speed sampling data waveform is solved. The double-cache structure can reduce the stored core clock resource quantity, the distributed clock domain and the like as much as possible, time sequence convergence with high robustness is realized, and stable and reliable sampling data storage is ensured.

Description

Technical Field

[0001] The present invention relates to a data acquisition system storage structure and storage method, and particularly to a system and method for real-time cyclic storage applied to a high-speed data acquisition system. Background Art

[0002] Data acquisition systems are widely used in electronic measuring instruments. Whether it is in scientific research, engineering applications, or social life, medical and health fields, high-speed / mid-speed / low-speed data acquisition is used. Among them, high-speed data acquisition systems are widely used in high-tech fields such as scientific research, aerospace, and military. Triggering is a basic function of data acquisition, used to control the start time of data acquisition. Triggering has functions such as stably capturing waveforms of interest, stably displaying captured waveforms, and isolating abnormal signals.

[0003] Generally, high-speed data acquisition systems adopt an "ADC + FPGA" architecture design. The analog-to-digital conversion function of analog signals is realized through an analog-to-digital converter (ADC); digital operations on sampled data are realized through a field programmable gate array (FPGA). It can also be realized through application special integrated circuits (ASICs), digital signal processing (DSP) chips, etc. For example, sampled data is stored in real-time cyclic under the timing control of the corresponding clock; after the arrival of the trigger signal or other control logic, the trigger jitter measurement result is obtained by the corresponding clock, and a new timing control signal is generated to control subsequent sampled data operations. After all actions are completed, an operation ends and the next operation is started.

[0004] To accurately obtain the time information of the high-speed sampled data waveform, the following operations are usually taken: shortening the time of the sampled data, that is, increasing the real-time sampling rate, improving the measurement accuracy of the trigger jitter time, etc. However, these operations all require a large amount of clock resources. Generally, the clock resources inside the FPGA chip are limited, and the clock resources are greatly affected by external factors (such as process, temperature, voltage, etc., processing, temperature, voltage, PVT). If a large amount of clock resources are occupied for implementation, it may lead to timing non-convergence and instability, and ultimately result in incorrect time information of the sampled data waveform or oscillation of the sampled data. For example, the typical manifestation of the timing non-convergence problem is that the timing control logic successfully compiled by the editor has a certain timing margin. When downloaded to the FPGA and run, problems such as inconsistent / oscillating time information of the sampled data after single / multiple power-on, inconsistent / oscillating time information of the sampled data under different temperature and humidity conditions, and inconsistent / oscillating time information of the sampled data during long / short-term operation occur. In high-tech application fields, the above problems need to be eliminated urgently.

[0005] To ensure the stability of the high-speed sampled data waveform and the accuracy of the waveform time information, it is necessary to design a sampled data cache structure to achieve the timing convergence of the sampled data. It is required that the sampled data not only converges in timing theoretically but also converges in timing during engineering operation, that is, it is required to be able to cope with the influence of noise, delay, etc. in the actual hardware. The most feasible method is to reduce the usage of core clock resources and reduce the number of distributed clock domains. In the prior art, most high-speed data acquisition systems adopt a first-level buffer structure to directly complete the caching of the sampled data, occupying more than 40% or even more of the FPGA clock resources, and the clock resources span 20 or more clock domains. For example: Li Haitao, Li Binkang, Ruan Linbo, etc. Research on the Sampled Data Receiving Buffer System of High-Speed ADC [J]. Process Automation Instrumentation, 2020, 41(08): 42-45+50. uses a first-level blockRAM to store the sampled data; see Jiang Shijian. Design and Implementation of a 12.5GSPS High-Speed Data Acquisition Module [D]. Chengdu: University of Electronic Science and Technology of China, 2020. It uses a first-level asynchronous FIFO to store the sampled data; see Chen Lan. Design and Implementation of a Dual-Channel 6.4GSPS High-Speed Data Acquisition Module [D]. Chengdu: University of Electronic Science and Technology of China, 2021. directly caches the sampled data into an external DDR3 chip and then reads the sampled data from the DDR3 chip into the FIFO. The control logic of the above technical solutions is simple; however, its disadvantage is that the core clock fan-out is huge, and it spans many clock domains, lacking an accurate description of the trigger time information of the sampled data. Summary of the Invention

[0006] The object of the present invention is to solve the technical problems existing in the prior art when reducing the usage amount of core clock resources, including a huge core clock fan-out amount, many clock domains being crossed, and the lack of accurate description of the trigger time information of sampled data, and to propose a system and method for real-time cyclic storage applied to a high-speed data acquisition system.

[0007] To solve the above technical problems, the technical solution provided by the present invention is as follows:

[0008] A system for real-time cyclic storage applied to a high-speed data acquisition system, which is characterized in that it includes a control logic unit, a first buffer, a second buffer, a memory, a time measurement unit, and a clock manager;

[0009] The control logic unit is respectively connected to the first buffer and the second buffer, and is used for receiving an external trigger signal, sending a first write enable signal and a first read enable signal to the first buffer, sending a second write enable signal and a second read enable signal to the second buffer, and respectively setting the write data width of the first buffer, the read data width of the first buffer, and the write data width of the second buffer according to the width of the sampled data;

[0010] The data input end of the first buffer is used to be connected to the front-end module of the data acquisition system to receive sampled data; the data output end of the first buffer is connected to the data input end of the second buffer, and the data output end of the second buffer is connected to the memory; the storage capacity of the first buffer is smaller than that of the second buffer;

[0011] The time measurement unit is respectively connected to the control logic unit, and is used for measuring the jitter time of the trigger signal in the control logic unit and sending a flag signal to the control logic unit;

[0012] The input end of the clock manager is used to be connected to the front-end module of the data acquisition system to receive a reference clock signal, and the output end of the clock manager is respectively connected to the first buffer, the time measurement unit, the control logic unit, the second buffer, and the memory, and is used for respectively providing a first write clock signal with 0 delay and a time measurement clock signal to the first buffer and the time measurement unit, and respectively providing a control logic clock signal, a first read clock signal, a second write clock signal, a second read clock signal, and a storage clock signal to the control logic unit, the first buffer, the second buffer, and the memory; wherein the first write clock signal and the time measurement clock signal are of the same source, the same frequency, and the same phase, and the first read clock signal and the second write clock signal are of the same frequency.

[0013] Further, the clock manager is one clock manager or multiple clock managers;

[0014] The first buffer is a FIFO buffer or a RAM, and the second buffer is a FIFO buffer or a RAM.

[0015] Further, a first global clock buffer is further included. The clock manager is connected to the input end of the first global clock buffer, and the output end of the first global clock buffer is connected to the write clock input end of the first buffer and the clock input end of the time measurement unit.

[0016] Further, a clock buffer is further included. The clock manager is connected to the input end of the clock buffer, and the output end of the clock buffer is connected to the read clock input end of the first buffer, the write clock input end and the read clock input end of the second buffer.

[0017] Further, the memory uses a double data rate memory DDRx, SDRAM, static random access memory SRAM, FLASH memory or a hard disk.

[0018] The present invention also provides a method for real-time cyclic storage applied to a high-speed data acquisition system. Based on the system for real-time cyclic storage applied to a high-speed data acquisition system described above, the special features are as follows: including the following steps:

[0019] S1. The clock manager sends a first write clock signal with 0 delay to the first buffer and a time measurement clock signal with 0 delay to the time measurement unit; the first write clock signal and the time measurement clock signal are of the same source, same frequency and same phase as the sampled data;

[0020] The clock manager sends a control logic clock signal to the control logic unit, and the control logic unit sets the write data width of the first buffer to be the same as the width of the sampled data;

[0021] S2. The control logic unit sends a first write enable open signal to the first buffer and starts the cyclic storage mode. The first buffer starts to receive the sampled data in real time and writes it into the buffer area for cyclic storage operation;

[0022] S3. When an external trigger signal arrives, the time measurement unit starts to measure the jitter time of the trigger signal and performs synchronous correction; the time measurement unit simultaneously outputs a flag signal to the control logic unit;

[0023] S4. The clock manager sends a first read clock signal to the first buffer and a second write clock signal to the second buffer; the first read clock signal and the second write clock signal have the same frequency;

[0024] Meanwhile, the control logic unit sends a first read enable open signal to the first buffer, and the first buffer starts to read the sampled data from the buffer area and transmits it to the second buffer; the control logic unit sets the read data width of the first buffer to be the same as the write data width of the second buffer;

[0025] Meanwhile, the control logic unit preset the maximum amount of sampled data that the second buffer can receive in advance, and sends a second write enable open signal to the second buffer, and the sampled data is written into the second buffer;

[0026] S5. When the sampled data written into the second buffer reaches the maximum amount, the control logic unit sends a first read enable close signal to the first buffer and a second write enable close signal to the second buffer;

[0027] S6. The clock manager sends a second read clock signal and a storage clock signal to the second buffer and the memory. Meanwhile, the control logic unit sends a second read enable open signal to the second buffer, and the second buffer reads the sampled data and transmits it to the memory;

[0028] S7. The control logic unit sends a second read enable close signal to the second buffer, completes the real-time storage of the sampled data once, and waits for the next trigger signal to arrive.

[0029] Further, in step S1, one or two clock managers generate and fan out one or two 0-delay clock signals, which are sent to the write clock input terminal of the first buffer and the clock input terminal of the time measurement unit through the first global clock buffer, and are used as the first write clock signal and the time measurement clock signal simultaneously or respectively; one of the clock managers also generates a clock signal and directly fans it out to the control logic unit as the control logic clock signal.

[0030] Further, in step S3, a time-to-digital converter or a phased clock method is used to measure the jitter time of the trigger signal.

[0031] Further, in step S4, the sampled data written into the second buffer is the sampled data written into the first buffer after the trigger signal arrives.

[0032] Further, in step S4, one or two clock managers generate and fan out one or two clock signals, which are sent to the read clock input terminal of the first buffer and the write clock input terminal of the second buffer through the clock manager, and are used as the first read clock signal and the second write clock signal simultaneously or respectively;

[0033] In step S6, a clock signal generated and fanned out by one of the clock managers is sent to the read clock input terminal of the second buffer through the clock manager as the second read clock signal.

[0034] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0035] 1. The present invention is applied to a system for real-time cyclic storage in a high-speed data acquisition system, which includes a control logic unit, a first buffer, a second buffer, a memory, a time measurement unit, and at least one clock manager; a dual-buffer structure of a small-capacity first buffer and a large-capacity second buffer is adopted. The first buffer records the sampled data before the arrival of the trigger signal, and the second buffer records the sampled data after the arrival of the trigger signal. With at least one clock manager, the problem of non-convergent timing in the time information of the high-speed sampled data waveform can be solved. The dual-buffer structure can minimize the core clock resources for storage and distributed clock domains, etc., achieve robust timing convergence, and ensure stable and reliable storage of sampled data.

[0036] 2. The present invention is applied to a system for real-time cyclic storage in a high-speed data acquisition system. A time measurement unit is set to accurately measure the jitter time of the trigger signal to ensure the reliability and accuracy of the trigger signal. The time measurement unit outputs a flag signal to the control logic unit during measurement, realizing synchronization and coordination between modules and improving the overall efficiency of the system.

[0037] 3. The present invention is applied to a method for real-time cyclic storage in a high-speed data acquisition system. The first buffer writes the sampled data in a real-time cyclic mode. After the arrival of the trigger signal, the first buffer reads the sampled data and transfers it to the second buffer for writing, and finally the second buffer transfers the sampled data to the memory; the first buffer and the second buffer process in parallel, effectively improving the data processing efficiency; at the same time, independent clocks are used for processing in different stages, and the frequencies and data widths between the independent clocks match, solving the problem of clock domain crossing.

[0038] 4. The present invention is applied to a method for real-time cyclic storage in a high-speed data acquisition system. One clock manager is used in steps S1, S4, and S6, reducing the fan-out requirement for clock resources. The 0-delay fan-out clock signal ensures the phase locking of the input clock and the output clock of the clock management unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a connection block diagram of an embodiment of the system of the present invention applied to real-time cyclic storage in a high-speed data acquisition system;

[0040] Figure 2 It is a schematic diagram of core clock generation and 0-delay fan-out in an embodiment of the method of the present invention applied to real-time cyclic storage in a high-speed data acquisition system;

[0041] Figure 3 It is a schematic diagram of other clock generation and fan-out in an embodiment of the method of the present invention applied to real-time cyclic storage in a high-speed data acquisition system;

[0042] Figure 4 This is a schematic diagram of the cyclic storage in the method embodiment of the present invention applied to a high-speed data acquisition system for real-time cyclic storage. Detailed implementation manners

[0043] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0044] A system of the present invention applied to real-time cyclic storage in a high-speed data acquisition system, as Figure 1 shown, includes a control logic unit, a first buffer, a second buffer, a memory, and a time measurement unit, as well as a clock manager, a first global clock buffer BUFG, and a clock buffer.

[0045] The first buffer is a FIFO buffer or a RAM, the second buffer is a FIFO buffer or a RAM, and the storage capacity of the first buffer is less than that of the second buffer. In this embodiment, the first buffer adopts a FIFO buffer. A FIFO buffer is a data storage structure, and data is stored and read in the order of first in first out. The second buffer adopts a RAM. The RAM can be an on-chip RAM, such as the internal blockRAM or distributedRAM of an FPGA chip; it can be an external RAM chip, such as an SRAM chip, DDRx, SDRAM chip, etc. The type of RAM used is determined according to the amount of sampled data.

[0046] The control logic unit is respectively connected to the first buffer and the second buffer, and is used for receiving an external trigger signal, and sending a first write enable signal and a first read enable signal to the first buffer, sending a second write enable signal and a second read enable signal to the second buffer, and respectively setting the write data width of the first buffer, the read data width of the first buffer, and the write data width of the second buffer according to the width of the sampled data; the data input end of the first buffer is used for connecting to the front-end module of the data acquisition system to receive sampled data; the data output end of the first buffer is connected to the data input end of the second buffer, and the data output end of the second buffer is connected to the memory;

[0047] The time measurement unit is connected to the control logic unit, and is used for measuring the jitter time of the trigger signal in the control logic unit, and sending a flag signal to the control logic unit;

[0048] The number of clock managers is one or more. One clock manager can generate multiple clock signals, but can only generate and fan out one clock signal with zero delay. The input terminal of the clock manager is used to connect to the front-end module to receive the reference clock signal sent by the front-end module; the output terminal of the clock manager is connected to the input terminal of the first global clock buffer, and the output terminal of the first global clock buffer is connected to the write clock input terminal of the first buffer and the clock input terminal of the time measurement unit. The first global clock buffer is a BUFG (Buffer for Global Clock), which is specifically used to drive and distribute clock signals in digital circuits. The main function of the BUFG is to enhance the driving ability of the clock signal, ensure that the clock signal can be stably transmitted to each module on the entire chip or circuit board, and at the same time reduce the attenuation and delay of the signal during transmission.

[0049] The output terminal of the clock manager is also connected to the input terminal of the clock buffer BUFx, and the output terminal of the clock buffer is connected to the read clock input terminal of the first buffer, the write clock input terminal and the read clock input terminal of the second buffer, which is used to enhance the driving ability of the clock signal. The clock buffer uses the second global clock buffer BUFG or the regional clock buffer BUFR or the semi-global clock buffer BFH, which is used to enhance the driving ability of the clock signal and reduce clock skew. By fanning out the clock signal through the clock buffer, it can be ensured that the clock signal has consistent delay and driving ability when distributed to each module. As Figure 3 shown, the feedback line of the clock manager can be omitted. The output terminal of the clock manager is also directly connected to the control logic unit and the memory or connected through a clock buffer, which is used to provide the control logic clock signal and the storage clock signal.

[0050] The memory uses a double data rate memory DDRx, SDRAM, static random access memory SRAM, FLASH memory or hard disk.

[0051] The present invention also provides a method applied to real-time cyclic storage in a high-speed data acquisition system, as Figure 4 shown, including the following steps:

[0052] S1. In this embodiment, one clock manager is used to generate and fan out one clock signal with zero delay, which is sent to the write clock input terminal of the first buffer and the clock input terminal of the time measurement unit through the first global clock buffer, and at the same time serves as the first write clock signal and the time measurement clock signal. Zero delay means that during the distribution of the clock signal, the signal remains synchronized. The clock manager also generates one clock signal, which is directly fanned out to the control logic unit and serves as the control logic clock signal; as Figure 2As shown, the input port clockin of the clock manager receives the reference clock signal provided externally, and one of the output ports clockout outputs the processed clock signal and transmits it to the BUFG for buffering and distribution; the feedback input port clockFBin of the clock manager is used to receive the clock signal (clockFBout) buffered by the BUFG to form a closed-loop control to output a stable 0-delay clock signal.

[0053] The control logic unit sets the write data width of the first buffer to be the same as the sampling data width output by the front-end module; sets the depth of the first buffer according to the length of the sampling data to be recorded;

[0054] In other embodiments, two homologous clock managers are used to fan out two 0-delay clock signals, which are sent to the write clock input terminal of the first buffer and the clock input terminal of the time measurement unit through the first global clock buffer as the first write clock signal and the time measurement clock signal respectively; one of the clock managers also generates a clock signal that is directly fanned out to the control logic unit as the control logic clock signal. The first write clock signal and the time measurement clock signal have the same frequency and the same phase as the sampling data;

[0055] S2. The control logic unit sends a first write enable open signal to the first buffer and starts the circular storage mode. The first buffer starts to receive the sampling data output by the front-end module in real time and writes it into the buffer area for circular storage operation. When the buffer capacity of the first buffer is full, the new data will overwrite the data that entered the FIFO buffer structure earliest.

[0056] Real-time caching can ensure the timeliness of data and avoid data loss. The advantage of the circular storage mode is that even if the buffer capacity of the buffer area is limited, the data acquisition system can continuously receive new sampling data and avoid stopping working due to the full buffer capacity.

[0057] The FIFO buffer isolates the trigger signal, the core clock signal and the subsequent other clock signals, completes the first-level buffering of the sampling data, and ensures that the clock signals fanned out to each point have strong driving ability and small clock jitter;

[0058] S3. When an external trigger signal arrives, the time measurement unit measures the jitter time of the trigger signal using a time-to-digital converter (TDC) or the phased clock method and performs synchronous correction; at the same time, the time measurement unit outputs a flag signal to the control logic unit;

[0059] The arrival time of the trigger signal has a random relationship with the rising edge time of the first write clock signal or the time measurement clock signal. Therefore, when the trigger signal arrives, unstable or jitter phenomena may occur, that is, wobbling is generated. The time measurement unit measures the time interval Δt1 of the trigger signal relative to the rising edge of the first write clock signal or the time measurement clock signal, that is, the wobbling time.

[0060] S4. A clock signal generated and fanned out by the clock manager is sent to the read clock input terminal of the first buffer and the write clock input terminal of the second buffer through the clock manager, and serves as the first read clock signal and the second write clock signal at the same time; the first read clock signal and the second write clock signal have the same frequency;

[0061] At the same time, the control logic unit sends a first read enable open signal to the first buffer, and the first buffer starts to read the sampled data from its internal buffer area and transmits it to the second buffer; the control logic unit sets the read data width of the first buffer to be the same as the write data width of the second buffer;

[0062] The control logic unit presets the maximum amount of sampled data received by the second buffer in advance, sends a second write enable open signal to the second buffer, and the sampled data is written into the second buffer; in this embodiment, only the sampled data after the arrival of the trigger signal is recorded, and a FIFO with a smaller depth can be used, and the cyclic storage time is very short, further reducing the usage amount of the internal resources of the FPGA and the distributed clock domain.

[0063] In other embodiments, two clock managers can be additionally used to fan out two clock signals, which are sent to the read clock input terminal of the first buffer and the write clock input terminal of the second buffer through the clock buffer, and serve as the first read clock signal and the second write clock signal respectively;

[0064] As Figure 3 shown, the input port clockin of the clock manager receives the reference clock signal provided by the front-end module, and one of the output ports clockout outputs the processed clock signal and transmits it to the BUX for buffering and distribution; the feedback input port clockFBin of the clock manager is used to receive the passed clock signal (clockFBout) to form a closed-loop control. Among them, the BUX and the feedback line can both be omitted. Other clock signals refer to the first read clock signal, the second write clock signal, and the second read clock signal.

[0065] S5. When the sampled data written into the second buffer reaches the maximum amount, the control logic unit sends a first read enable close signal to the first buffer and a second write enable close signal to the second buffer;

[0066] S6. A clock signal generated and fanned out by the clock manager is sent to the read clock input terminal of the second buffer and the clock input terminal of the memory through the clock manager, and serves as the second read clock signal and the storage clock signal at the same time;

[0067] At the same time, the control logic unit sends a second read enable open signal to the second buffer, allowing the second buffer to read the sampled data, and the second buffer transfers the sampled data to the memory;

[0068] In other embodiments, an additional clock manager can be used to fan out a clock signal, which is sent to the read clock input terminal of the second buffer through the clock buffer as the second read clock signal.

[0069] In other embodiments, the control logic unit sending the second read enable open signal to the second buffer can be at the moment when the control logic unit sends the second write enable open signal to the second buffer in step S4, or at the moment when the control logic unit sends the second write enable close signal to the second buffer in step S5, or between the two moments. The clock manager sending the second read clock signal to the second buffer and the control logic unit sending the second read enable open signal to the second buffer are synchronized.

[0070] S7. The control logic unit sends a second read enable close signal to the second buffer, completing the real-time storage of a sampled data, and waiting for the arrival of the next trigger signal.

[0071] This embodiment is based on the FPGA platform and the Hardware Design Language (HDL), adopts the "small FIFO + large RAM" dual-buffer structure, uses FIFO to achieve pre-trigger recording, and uses RAM to record the sampled data before and after the trigger. The present invention can similarly be used on other types of chips such as ASIC and DSP.

Claims

1. A system for real-time cyclic storage of high-speed data acquisition system, characterized in that: comprising a control logic unit, a first buffer, a second buffer, a memory and a time measurement unit, and a clock manager; The control logic unit is connected to the first buffer and the second buffer respectively, and is used to receive an external trigger signal, and send a first write enable signal and a first read enable signal to the first buffer, send a second write enable signal and a second read enable signal to the second buffer, and set the write data width of the first buffer, the read data width of the first buffer, and the write data width of the second buffer respectively according to the width of the sampled data; The data input terminal of the first buffer is used to connect to the front-end module of the data acquisition system to receive the sampled data; The data output terminal of the first buffer is connected to the data input terminal of the second buffer, and the data output terminal of the second buffer is connected to the memory; The storage capacity of the first buffer is smaller than the storage capacity of the second buffer; The time measurement units are respectively connected to the control logic units, and are used to measure the shaking time of the trigger signal in the control logic unit, and send a flag signal to the control logic unit; The input end of the clock manager is used to connect with the front-end module of the data acquisition system to receive the reference clock signal, and the output end of the clock manager is respectively connected with the first buffer, the time measurement unit, the control logic unit, the second buffer, and the memory, and is used to provide a first write clock signal and a time measurement clock signal with zero delay to the first buffer and the time measurement unit, and to provide a control logic clock signal, a first read clock signal, a second write clock signal, a second read clock signal, and a storage clock signal to the control logic unit, the first buffer, the second buffer, and the memory, respectively; The first write clock signal and the time measurement clock signal have the same source, frequency and phase, and the first read clock signal and the second write clock signal have the same frequency.

2. The system for real-time cyclic storage of high-speed data acquisition system according to claim 1, characterized in that: The clock manager is one clock manager or multiple clock managers; The first buffer is a FIFO buffer or a RAM, and the second buffer is a FIFO buffer or a RAM.

3. The system for real-time cyclic storage of high-speed data acquisition system according to claim 2, characterized in that: It also includes a first global clock buffer, the clock manager is connected to the input end of the first global clock buffer, and the output end of the first global clock buffer is connected to the write clock input end of the first buffer and the clock input end of the time measurement unit.

4. The system for real-time cyclic storage of high-speed data acquisition system according to claim 3, characterized in that: A clock buffer is also included. The clock manager is connected to the input end of the clock buffer. The output end of the clock buffer is connected to the read clock input end of the first buffer, the write clock input end and the read clock input end of the second buffer.

5. The system for real-time cyclic storage of high-speed data acquisition system according to claim 4, characterized in that: The memory is a double data rate memory DDRx, SDRAM, a static random access memory SRAM, a FLASH memory or a hard disk.

6. A method for real-time cyclic storage in a high-speed data acquisition system, based on the system for real-time cyclic storage in a high-speed data acquisition system according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1, the clock manager sends a first write clock signal with zero delay to the first buffer, and sends a time measurement clock signal with zero delay to the time measurement unit; The first writing clock signal and the time measurement clock signal have the same source, frequency and phase as the sampling data; The clock manager sends a control logic clock signal to the control logic unit, and the control logic unit sets the write data width of the first buffer to be the same as the width of the sampling data; S2, the control logic unit sends a first write enable signal to the first buffer and starts a cyclic storage mode, the first buffer starts to receive the sampled data in real time and writes it to the buffer area for cyclic storage operation; S3, when an external trigger signal arrives, the time measurement unit starts to measure the shaking time of the trigger signal and performs synchronization correction; the time measurement unit simultaneously outputs a flag signal to the control logic unit; S4, the clock manager sends a first read clock signal to the first buffer, and sends a second write clock signal to the second buffer; The first read clock signal and the second write clock signal have the same frequency; At the same time, the control logic unit sends a first read enable opening signal to the first buffer, and the first buffer starts to read the sampled data from the buffer area and transmits it to the second buffer; the control logic unit sets the read data width of the first buffer to be the same as the write data width of the second buffer; At the same time, the control logic unit pre-sets the maximum amount of sampled data received by the second buffer, and sends a second write enable opening signal to the second buffer, and the sampled data is written into the second buffer; S5, when the sampled data written into the second buffer reaches the maximum amount, the control logic unit sends a first read enable shutdown signal to the first buffer and sends a second write enable shutdown signal to the second buffer; S6, the clock manager sends a second read clock signal and a storage clock signal to the second buffer and the memory, and the control logic unit sends a second read enable opening signal to the second buffer, and the second buffer reads the sampled data and transmits it to the memory; S7. The control logic unit sends a second read enable off signal to the second buffer, completes real-time storage of a sampling data, and waits for the next trigger signal to arrive.

7. The method for real-time cyclic storage in a high-speed data acquisition system according to claim 6, characterized in that: In step S1, one or two clock managers are used to generate and fan out one or two zero-delay clock signals, which are sent to the write clock input terminal of the first buffer and the clock input terminal of the time measurement unit through the first global clock buffer, and are used as the first write clock signal and the time measurement clock signal simultaneously or separately; One of the clock managers also generates a clock signal and fans out directly to the control logic unit as the control logic clock signal.

8. The method for real-time cyclic storage in a high-speed data acquisition system according to claim 7, characterized in that: In step S3, a time-to-digital converter or a phase-split clock method is used to measure the jitter time of the trigger signal.

9. The method for real-time cyclic storage in a high-speed data acquisition system according to claim 8, characterized in that: In step S4, the sampling data written into the second buffer is the sampling data written into the first buffer after the trigger signal arrives.

10. The method for real-time cyclic storage in a high-speed data acquisition system according to claim 9, characterized in that: In step S4, one or two clock managers generate and fan out one or two clock signals, and send them to the read clock input terminal of the first buffer and the write clock input terminal of the second buffer through the clock manager, and serve as the first read clock signal and the second write clock signal simultaneously or separately; In step S6, one clock signal generated and fanned out by one of the clock managers is sent to the read clock input terminal of the second buffer through the clock manager as the second read clock signal.

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