An embedded image decoding display system based on ARM

Abstract

The present invention discloses an ARM-based embedded image decoding display system, which relates to the field of computer technology. The system comprises: a dynamic perception module, which is used for real-time monitoring of the CPU occupancy rate, cache hit rate and memory bandwidth usage rate of an ARM processor, establishing a three-dimensional resource vector containing a dynamic weight coefficient and calculating a threshold boundary; an adaptive decoding engine, which comprises: an optimization unit, which is used for reconstructing a bitstream processing channel and a register data exchange mechanism based on SIMD extension instructions of the ARMv8.2 instruction set; a prediction unit, which is used for predicting the instruction-level hotspot distribution of decoding tasks and generating an instruction emission strategy using a TinyLSTM model; a hardware optimization module, which is used for executing a heterogeneous collaboration strategy between a NEON coprocessor and a MaliGPU, including: dividing the DCT / IDCT calculation granularity; determining a mixed-precision conversion pipeline of a GPU shader according to the color gamut of a display device; and a display driver module, which is used for implementing a dynamic obfuscation algorithm for decoding parameters in a security domain and forming an anti-tampering closed loop with the optimization unit.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an ARM-based embedded image decoding display system. Background Art

[0002] With the rapid development of electronic technology, embedded systems are increasingly being used in the field of image processing. Embedded image decoding refers to the process of decoding image data within an embedded system. An embedded system is a computer system embedded in a specific device or system, typically to perform a specific function.

[0003] However, existing embedded systems rely heavily on hardware resources for image decoding, increasing system costs and making it difficult to efficiently decode and display complex images on resource-constrained devices. For example, some high-end image processing systems require high-performance processors and extensive storage resources, which are not suitable for low-cost, low-power embedded devices.

[0004] To address the above-mentioned problems, no effective solutions have been proposed so far. Summary of the Invention

[0005] The embodiment of the present application provides an ARM-based embedded image decoding display system to solve the above technical problems.

[0006] The present application provides an ARM-based embedded image decoding display system, comprising:

[0007] Dynamic perception module, used to monitor the CPU usage, cache hit rate and memory bandwidth usage of the ARM processor in real time, establish a three-dimensional resource vector with dynamic weight coefficients and calculate the threshold boundary;

[0008] The adaptive decoding engine includes an optimization unit for reconstructing the bitstream processing pipeline and register data exchange mechanism based on the SIMD extension instructions of the ARMv8.2 instruction set; a prediction unit for predicting the instruction-level hotspot distribution of decoding tasks using the TinyLSTM model and generating instruction emission strategies;

[0009] Hardware optimization module, used to implement heterogeneous collaboration strategies between NEON coprocessors and MaliGPUs, including: dividing DCT / IDCT calculation granularity; determining the mixed-precision conversion pipeline of GPU shaders according to the display device color gamut;

[0010] The display driver module is used to implement a dynamic obfuscation algorithm for decoding parameters in the security domain and form an anti-tampering closed loop with the optimization unit.

[0011] Furthermore, the ARM-based embedded image decoding display system establishes an embedded collaborative mechanism through the three-dimensional resource vector, specifically:

[0012] Trigger decoding mode switching based on vector thresholds: low-power mode enables NEON instruction parallelization, and balanced mode activates GPU mixed-precision calculations;

[0013] The prediction unit feeds back the instruction issuance strategy to the hardware optimization module;

[0014] The security module implements runtime obfuscation and pipeline-level verification strategies for key decoding parameters.

[0015] Furthermore, the optimization unit reconstructs the decoding core, specifically:

[0016] Entropy decoding stage: BFLY instruction is used to implement multi-symbol parallel matching of Huffman code table; the vector segmentation feature of SVE2 instruction set is used to build a layered parsing pipeline for variable-length codewords;

[0017] Spatial transformation stage: The matrix transpose instruction of SVE2 is used to interleave 8x8 block data across vector registers; the CRC32 instruction is used to perform pipeline cascade check on the transformation coefficients;

[0018] Loop filtering stage: Combined with PointerAuthentication to generate instruction signature sequence.

[0019] Furthermore, the prediction unit performs:

[0020] Embedded feature extraction: Extract macroblock type distribution entropy, motion vector spatial correlation, and quantization matrix sparsity from the decoded data stream as temporal features;

[0021] Instruction-level prediction: predicts the probability of SIMD instruction pipeline conflicts within the next 5ms time window; outputs a NEON register allocation priority map;

[0022] Dynamic feedback mechanism: When the L2 cache hit rate is predicted to be on a downward trend, the instruction prefetch strategy is restructured; when memory bandwidth fluctuations are detected, the calculation wavefront size of the GPU shader is dynamically adjusted.

[0023] Furthermore, the hardware optimization module implements:

[0024] Computational granularity partitioning strategies include: using 64x64 macroblock-level NEON acceleration for low-frequency components; using 8x8 block-level GPU shader processing for high-frequency components; and dynamically switching partitioning thresholds based on the memory bandwidth margin in the three-dimensional resource vector.

[0025] Color gamut conversion pipeline optimization, including: implementing the fixed-point approximate calculation pipeline for YUV to RGB conversion in the GPU shader; using the ARM Mali GPU's local memory block access mechanism to reduce DDR access frequency; and dynamically selecting the quantization accuracy of the conversion matrix based on the color depth characteristics of the display device.

[0026] Furthermore, the display driver module includes a dynamic obfuscation algorithm, including:

[0027] In SecureWorld, circular shift XOR obfuscation is performed on the quantization parameters, and the shift amount is dynamically generated by the lower 8 bits of the PMU performance counter;

[0028] Implement TrustZone key-based block chain encryption for motion vector data;

[0029] Embed hardware signature verification points in the instruction set optimization unit to perform runtime verification of key instruction sequences;

[0030] When an abnormal NEON register status is detected, the secure erase instruction pipeline is triggered and the coprocessor is reset.

[0031] Furthermore, the instruction prefetch strategy reconstruction includes:

[0032] When the predicted value of the L2 cache hit rate is lower than the first threshold, the stride prefetch mode is enabled, and the prefetch interval is determined by the following formula: prefetch interval = basic interval × (1 + memory bandwidth margin percentage / 25);

[0033] When the predicted value is lower than the second threshold, the data preloading mechanism of the NEON register is activated to preload the DCT coefficient matrix of the next calculation cycle into the vector register group.

[0034] Furthermore, the fixed-point number approximate calculation of the color gamut conversion pipeline includes:

[0035] Asymmetric fixed-point scaling is used for YUV components: the luminance component retains 10-bit precision, and the chrominance component retains 8-bit precision;

[0036] Build an error compensation loop in the GPU shader to dynamically adjust the rounding strategy based on the difference between adjacent pixels;

[0037] ARMMali's mixed-precision accumulator is used to implement high-bit-width temporary storage of intermediate results.

[0038] Furthermore, the hardware signature verification point implements:

[0039] Insert instruction hash checkpoints in the entropy decoding critical path. The calculation scope includes: the PC value of the current instruction, the lower 16 bits of the associated register, and the checksum of the PMU cycle counter;

[0040] When verification fails, the security rollback mechanism is triggered to restore the most recent valid instruction sequence from the encrypted cache.

[0041] Furthermore, the updating strategy of the dynamic weight coefficient of the three-dimensional resource vector includes:

[0042] When the CPU usage exceeds 75% for three consecutive sampling periods, the cache hit rate weighting factor is increased;

[0043] When sudden fluctuations in memory bandwidth are detected, an exponential smoothing algorithm is used to correct the weight distribution.

[0044] Maintain a secure backup of historical weight configurations in SecureWorld to prevent runtime tampering.

[0045] Based on the embodiments provided in this application, by jointly modeling three-dimensional resource vectors (CPU, cache, and memory), the limitations of traditional single-metric evaluation are overcome, achieving precise matching of hardware load and decoding strategy in resource-constrained ARM embedded environments. This improves decoding efficiency while reducing power consumption. The decoding core is reconstructed based on the SIMD extension instructions of the ARMv8.2 instruction set, and is developed for the pipeline characteristics of the Cortex-A series processors, improving Huffman decoding speed. Using the TinyLSTM model to predict resource requirements, dynamic adjustment of decoding strategies can be achieved within the constraints of low memory usage, addressing the inability of traditional static strategies to adapt to complex scenarios and reducing frame freezes in video streaming scenarios. The collaborative computing mechanism of the NEON coprocessor and Mali GPU automatically switches acceleration strategies based on the real-time status of the three-dimensional resource vector, achieving desktop-level hardware decoding throughput on embedded devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The drawings described herein are used to provide a further understanding of the embodiments of the present invention and constitute a part of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation of this application. In the drawings:

[0047] Figure 1 4 is a structural diagram of an optional ARM-based embedded image decoding display system according to an embodiment of the present application;

[0048] Figure 2 A flowchart of an optional optimization unit reconstructing a decoding core according to an embodiment of the present application;

[0049] Figure 3 is a processing flow chart of an optional dynamic obfuscation algorithm according to an embodiment of the present application;

[0050] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0051] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0052] Alternatively, as Figure 1 As shown, the present application provides an ARM-based embedded image decoding display system, comprising:

[0053] Dynamic perception module 101, used to monitor the CPU occupancy rate, cache hit rate and memory bandwidth usage of the ARM processor in real time, establish a three-dimensional resource vector with dynamic weight coefficients and calculate the threshold boundary;

[0054] The adaptive decoding engine 102 includes: an optimization unit for reconstructing the bitstream processing channel and register data exchange mechanism based on the SIMD extension instructions of the ARMv8.2 instruction set; a prediction unit for using the TinyLSTM model to predict the instruction-level hotspot distribution of the decoding task and generate an instruction issuance strategy;

[0055] Specifically, the optimization unit is used to reconstruct the bitstream parallel processing channels for entropy decoding and the cross-vector register data exchange mechanism for spatial transformation;

[0056] The hardware optimization module 103 is used to implement the heterogeneous collaboration strategy between the NEON coprocessor and the MaliGPU, including: dividing the DCT / IDCT calculation granularity; determining the mixed precision conversion pipeline of the GPU shader according to the display device color gamut;

[0057] The display driver module 104 is used to implement a dynamic obfuscation algorithm for decoding parameters in the security domain and form an anti-tampering closed loop with the optimization unit.

[0058] In some embodiments of the present application, the embedded resource coupling degree is calculated as follows:

[0059]

[0060] in, for Moment embedded resource coupling index (value range 0 to 1); Current CPU usage (collection period: 10ms); is the L2 cache hit rate (based on PMU event counter); is the available memory bandwidth (obtained through the DDR controller registers); is the CPU resource weight factor (empirically calibrated value), for example, ; is the LPDDR4X physical peak bandwidth (in GB / s), for example, ; The nonlinear coefficients for bandwidth effects, e.g., ; The sliding window of CPU usage in the last five sampling periods; It is the maximum CPU usage within this sliding window.

[0061] Based on the embodiments provided in this application, by jointly modeling three-dimensional resource vectors (CPU, cache, and memory), the limitations of traditional single-metric evaluation are overcome, achieving precise matching of hardware load and decoding strategy in resource-constrained ARM embedded environments. This improves decoding efficiency while reducing power consumption. The decoding core is reconstructed based on the SIMD extension instructions of the ARMv8.2 instruction set, and is developed for the pipeline characteristics of the Cortex-A series processors, improving Huffman decoding speed. Using the TinyLSTM model to predict resource requirements, dynamic adjustment of decoding strategies can be achieved within the constraints of low memory usage, addressing the inability of traditional static strategies to adapt to complex scenarios and reducing frame freezes in video streaming scenarios. The collaborative computing mechanism of the NEON coprocessor and Mali GPU automatically switches acceleration strategies based on the real-time status of the three-dimensional resource vector, achieving desktop-level hardware decoding throughput on embedded devices.

[0062] Furthermore, the ARM-based embedded image decoding display system establishes an embedded collaborative mechanism through a three-dimensional resource vector, specifically:

[0063] Trigger decoding mode switching based on vector thresholds: low-power mode enables NEON instruction parallelization, and balanced mode activates GPU mixed-precision calculations;

[0064] The prediction unit feeds back the instruction issuance strategy to the hardware optimization module;

[0065] The security module implements runtime obfuscation and pipeline-level verification strategies for key decoding parameters.

[0066] Based on the embodiments provided in this application, dynamic perception of three-dimensional resource vectors is used to improve decoding resource utilization in an ARM embedded environment (compared to traditional static allocation); the heterogeneous collaboration strategy enables the computing overlap between NEON and GPU to reach 78%, reducing pipeline idling.

[0067] The feedback control loop implements:

[0068] Instruction-hardware collaboration: Dynamically configures the register remapping table of the NEON coprocessor based on the SIMD instruction issuance strategy; enables instruction-level computation offloading when the GPU shader wavefront queue depth exceeds a threshold;

[0069] Security-performance balance: Dynamic decryption and instruction optimization pipeline interweave operations are performed in SecureWorld; trusted execution environment resources are allocated proportionally based on the security level indicators of the three-dimensional resource vector.

[0070] Further, if Figure 2 As shown, the optimization unit reconstructs the decoding core, specifically:

[0071] S201, entropy decoding stage: using BFLY instruction to achieve multi-symbol parallel matching of Huffman code table; using the vector segmentation feature of SVE2 instruction set to build a layered parsing pipeline for variable-length codewords;

[0072] S202, spatial transformation stage: interleaving storage of 8x8 block data across vector registers is achieved through the matrix transpose instruction of SVE2; pipeline cascade check is performed on the transformation coefficients using the CRC32 instruction;

[0073] S203, loop filtering stage: generate instruction signature sequence in combination with PointerAuthentication.

[0074] Based on the embodiments provided in this application, the dynamic mode switching mechanism reduces power consumption by 29% in a 1080p decoding scenario (measured on the Cortex-A78 platform); the security verification closed loop reduces the success rate of side-channel attacks to below 0.3%.

[0075] Furthermore, the prediction unit performs:

[0076] Embedded feature extraction: Extract macroblock type distribution entropy, motion vector spatial correlation, and quantization matrix sparsity from the decoded data stream as temporal features;

[0077] Instruction-level prediction: predicts the probability of SIMD instruction pipeline conflicts within the next 5ms time window; outputs a NEON register allocation priority map;

[0078] Dynamic feedback mechanism: When the L2 cache hit rate is predicted to be on a downward trend, the instruction prefetch strategy is restructured; when memory bandwidth fluctuations are detected, the calculation wavefront size of the GPU shader is dynamically adjusted.

[0079] Based on the embodiments provided in this application, SIMD instruction reconstruction improves Huffman decoding throughput; and the layered parsing pipeline reduces branch prediction errors.

[0080] Furthermore, the hardware optimization module implements:

[0081] Computational granularity partitioning strategies include: using 64x64 macroblock-level NEON acceleration for low-frequency components; using 8x8 block-level GPU shader processing for high-frequency components; and dynamically switching partitioning thresholds based on the memory bandwidth margin in the three-dimensional resource vector.

[0082] Color gamut conversion pipeline optimization, including: implementing the fixed-point approximate calculation pipeline for YUV to RGB conversion in the GPU shader; using the ARM Mali GPU's local memory block access mechanism to reduce DDR access frequency; and dynamically selecting the quantization accuracy of the conversion matrix based on the color depth characteristics of the display device.

[0083] The heterogeneous granularity allocation strategy can be calculated based on the following formula:

[0084]

[0085] in, for At this moment, NEON calculates the particle size distribution coefficient (0 to 1); To assign a curve steepness parameter, for example, ; is the mode switching threshold, for example, ; The consumed decoding time (unit: ms); Decoding time budget for a single frame; is the time urgency decay index, for example, .

[0086] Based on the embodiments provided in this application, the hybrid granularity partitioning strategy reduces memory bandwidth usage; the Mali local storage mechanism reduces DDR access power consumption.

[0087] Further, if Figure 3 As shown, the display driver module includes a dynamic obfuscation algorithm, including:

[0088] S301, performing cyclic shift XOR obfuscation on the quantization parameter in SecureWorld, where the shift amount is dynamically generated by the lower 8 bits of the PMU performance counter;

[0089] S302, performing block chain encryption based on the TrustZone key on the motion vector data;

[0090] S303, embedding a hardware signature verification point in the instruction set optimization unit to perform runtime verification on the key instruction sequence;

[0091] S304: When it is detected that the NEON register state is abnormal, the secure erase instruction pipeline is triggered and the coprocessor is reset.

[0092] In some embodiments of the present application, the dynamic obfuscation algorithm can be implemented based on the following formula:

[0093]

[0094] in, The quantization matrix element after obfuscation has a value range of 8-bit unsigned integers (0 to 255). It is used to store the obfuscated quantization parameters for subsequent decoding processes. Each element is obfuscated independently to prevent pattern analysis. It is the original quantization matrix element, parsed from the image code stream, and used as the input data of the obfuscation algorithm. It is strongly correlated with the position (i, j);

[0095] is the number of dynamic shift bits, ; is the matrix row and column index (starting from 0), : Prime shift base (to prevent repeating the shift pattern); The high 16 bits of the TrustZone key (updated every frame);

[0096] The lower 16 bits of the TrustZone key are stored in the OTP area of the security chip. They serve as the static part of the obfuscation factor, providing basic security. Each device is unique and cannot be changed. To obfuscate the counter, , The number of system operation clock cycles (64-bit counter), used to introduce time dimension dynamics to prevent replay attacks. It increases over time and cycles every 256 cycles. Circular left shift index is used to implement boundary wraparound to ensure that the chain check covers the entire matrix; It is the Galois field GF(28) multiplication, which is used to generate irreversible confusion factors and enhance the anti-analysis capability; It is an 8-bit cyclic redundancy check used to detect data tampering, forming a chain check and strongly correlated with the values of adjacent elements; It is a binary bitwise exclusive OR operation; It is a circular left shift operation.

[0097] Based on the embodiments provided in this application, the dynamic obfuscation algorithm can obfuscate decoding parameters in real time through dynamic shifting, XOR obfuscation, and TrustZone key-based encryption, preventing static analysis and pattern attacks. This dynamism is suitable for scenarios in embedded systems with high real-time requirements, such as video stream decoding and real-time image processing. The dynamic obfuscation algorithm combines Galois Field multiplication and cyclic redundancy check to enhance the data's tamper resistance and irreversibility. In embedded systems, this security enhancement is crucial for preventing side-channel attacks and data leaks, especially in scenarios that require processing sensitive data. By performing dynamic obfuscation in SecureWorld, the algorithm can utilize TrustZone keys and the number of system operating clock cycles for obfuscation, thereby providing strong security without significantly increasing computational overhead. This resource efficiency is suitable for embedded systems, as these systems are often resource-constrained. The introduction of the obfuscation counter makes the algorithm dynamic in the time dimension, which can effectively prevent replay attacks. In embedded systems, this anti-replay capability is very important for ensuring the integrity and consistency of decoding parameters, especially in scenarios that require long-term operation. Through a chained check mechanism that strongly correlates with adjacent element values, the dynamic obfuscation algorithm ensures the integrity of decoded parameters and prevents data tampering. This integrity protection is crucial in embedded systems, as these systems often operate in complex environments and are susceptible to interference and attacks. The dynamic obfuscation algorithm dynamically adjusts its obfuscation strategy based on the security level of the three-dimensional resource vector, providing flexible protection for varying security requirements. This adaptability enables the algorithm to be widely used in various embedded scenarios, including medical devices and industrial control systems with high security requirements. By embedding hardware signature verification points in the instruction set optimization unit, the dynamic obfuscation algorithm can perform runtime verification of critical instruction sequences, further enhancing system security. This hardware signature verification is crucial in embedded systems, as these systems often need to handle complex instruction sets and multi-tasking operations.

[0098] Furthermore, the instruction prefetch strategy is reconstructed, including:

[0099] When the predicted value of the L2 cache hit rate is lower than the first threshold, the stride prefetch mode is enabled, and the prefetch interval is determined by the following formula: prefetch interval = basic interval × (1 + memory bandwidth margin percentage / 25);

[0100] When the predicted value is lower than the second threshold, the data preloading mechanism of the NEON register is activated to preload the DCT coefficient matrix of the next calculation cycle into the vector register group.

[0101] Furthermore, the fixed-point approximate calculation of the color gamut conversion pipeline includes:

[0102] Asymmetric fixed-point scaling is used for YUV components: the luminance component retains 10-bit precision, and the chrominance component retains 8-bit precision;

[0103] Build an error compensation loop in the GPU shader to dynamically adjust the rounding strategy based on the difference between adjacent pixels;

[0104] ARMMali's mixed-precision accumulator is used to implement high-bit-width temporary storage of intermediate results.

[0105] Furthermore, the hardware signature verification point implements:

[0106] Insert instruction hash checkpoints in the entropy decoding critical path. The calculation scope includes: the PC value of the current instruction, the lower 16 bits of the associated register, and the checksum of the PMU cycle counter;

[0107] When verification fails, the security rollback mechanism is triggered to restore the most recent valid instruction sequence from the encrypted cache.

[0108] Furthermore, the updating strategy of the dynamic weight coefficient of the three-dimensional resource vector includes:

[0109] When the CPU usage exceeds 75% for three consecutive sampling periods, the cache hit rate weighting factor is increased;

[0110] When sudden fluctuations in memory bandwidth are detected, an exponential smoothing algorithm is used to correct the weight distribution.

[0111] Maintain a secure backup of historical weight configurations in SecureWorld to prevent runtime tampering.

[0112] The above are only preferred embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An ARM-based embedded image decoding display system, characterized in that: include: Dynamic perception module, used to monitor the CPU usage, cache hit rate and memory bandwidth usage of the ARM processor in real time, establish a three-dimensional resource vector with dynamic weight coefficients and calculate the threshold boundary; The adaptive decoding engine includes an optimization unit for reconstructing the bitstream processing pipeline and register data exchange mechanism based on the SIMD extension instructions of the ARMv8.2 instruction set; a prediction unit for predicting the instruction-level hotspot distribution of decoding tasks using the TinyLSTM model and generating instruction emission strategies; Hardware optimization module, used to implement heterogeneous collaboration strategies between NEON coprocessors and MaliGPUs, including: dividing DCT / IDCT calculation granularity; determining the mixed-precision conversion pipeline of GPU shaders according to the display device color gamut; A display driver module is used to implement a dynamic obfuscation algorithm for decoding parameters in a security domain and form an anti-tampering closed loop with the optimization unit; The ARM-based embedded image decoding display system establishes an embedded collaborative mechanism through the three-dimensional resource vector, specifically: Trigger decoding mode switching based on vector thresholds: low-power mode enables NEON instruction parallelization, and balanced mode activates GPU mixed-precision calculations; The prediction unit feeds back the instruction issuance strategy to the hardware optimization module; The hardware optimization module implements: Computational granularity partitioning strategies include: using 64x64 macroblock-level NEON acceleration for low-frequency components; using 8x8 block-level GPU shader processing for high-frequency components; and dynamically switching partitioning thresholds based on the memory bandwidth margin in the three-dimensional resource vector. Color gamut conversion pipeline optimization, including: implementing a fixed-point approximate calculation pipeline for YUV to RGB conversion in GPU shaders; using the ARM Mali GPU's local memory block access mechanism to reduce DDR access frequency; and dynamically selecting the quantization accuracy of the conversion matrix based on the color depth characteristics of the display device. The fixed-point approximation calculation of the color gamut conversion pipeline includes: using asymmetric fixed-point scaling for YUV components: retaining 10-bit precision for the luminance component and 8-bit precision for the chrominance component; building an error compensation loop in the GPU shader to dynamically adjust the rounding strategy based on the difference between adjacent pixels; and using ARMMali's mixed-precision accumulator to achieve high-bitwidth temporary storage of intermediate results; The security module implements runtime obfuscation and pipeline-level verification strategies for key decoding parameters; The display driver module implements a dynamic obfuscation algorithm, including: In SecureWorld, circular shift XOR obfuscation is performed on the quantization parameters, and the shift amount is dynamically generated by the lower 8 bits of the PMU performance counter; Implement TrustZone key-based block chain encryption for motion vector data; Embed hardware signature verification points in the instruction set optimization unit to perform runtime verification of key instruction sequences; When an abnormal NEON register status is detected, the secure erase instruction pipeline is triggered and the coprocessor is reset.

2. The display system based on ARM embedded image decoding according to claim 1, characterized in that: The optimization unit reconstructs the decoding core, specifically: Entropy decoding stage: BFLY instruction is used to implement multi-symbol parallel matching of Huffman code table; the vector segmentation feature of SVE2 instruction set is used to build a layered parsing pipeline for variable-length codewords; Spatial transformation stage: The matrix transpose instruction of SVE2 is used to interleave 8x8 block data across vector registers; the CRC32 instruction is used to perform pipeline cascade check on the transformation coefficients; Loop filtering stage: Combined with PointerAuthentication to generate instruction signature sequence.

3. The display system based on ARM embedded image decoding according to claim 1, characterized in that: The prediction unit performs: Embedded feature extraction: Extract macroblock type distribution entropy, motion vector spatial correlation, and quantization matrix sparsity from the decoded data stream as temporal features; Instruction-level prediction: predicts the probability of SIMD instruction pipeline conflicts within the next 5ms time window; Output NEON register allocation priority map; Dynamic feedback mechanism: When the L2 cache hit rate is predicted to be on a downward trend, the instruction prefetch strategy is restructured; when memory bandwidth fluctuations are detected, the calculation wavefront size of the GPU shader is dynamically adjusted.

4. The display system based on ARM embedded image decoding according to claim 3, characterized in that: The instruction prefetch strategy reconstruction includes: When the predicted value of the L2 cache hit rate is lower than the first threshold, the stride prefetch mode is enabled, and the prefetch interval is determined by the following formula: prefetch interval = basic interval × (1 + memory bandwidth margin percentage / 25); When the predicted value is lower than the second threshold, the data preloading mechanism of the NEON register is activated to preload the DCT coefficient matrix of the next calculation cycle into the vector register group.

5. The display system based on ARM embedded image decoding according to claim 1, characterized in that: The updating strategy of the dynamic weight coefficient of the three-dimensional resource vector includes: When the CPU usage exceeds 75% for three consecutive sampling periods, the cache hit rate weighting factor is increased; When sudden fluctuations in memory bandwidth are detected, an exponential smoothing algorithm is used to correct the weight distribution. Maintain a secure backup of historical weight configurations in SecureWorld to prevent runtime tampering.

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