Gate driving circuit and display device including same

Abstract

The embodiment relates to a gate driving circuit and a display device including the same. The present invention relates to a gate driving circuit capable of improving an output deviation of a first output buffer circuit and an output deviation of a last output buffer circuit among a plurality of output buffer circuits included in one stage circuit, respectively, and a display device including the same.

Description

Technical Field

[0001] This embodiment relates to a gating drive circuit and a display device including the same. Background Art

[0002] The drive circuit of a flat panel display (FPD) includes a data drive circuit that supplies data signals to data lines, a gating drive circuit that supplies gating signals (or scan signals) to gating lines (or scan lines), and the like. The gating drive circuit can be directly formed on the same substrate together with the circuit elements of the pixel array that constitutes the screen.

[0003] The circuit elements of the pixel array constitute pixel circuits formed in each pixel defined in a matrix form by the data lines and gating lines of the pixel array. Each of the gating drive circuit and the circuit elements of the pixel array includes a plurality of transistors. Here, the gating drive circuit can be directly formed on the substrate of the display panel together with the circuit elements of the pixel array. Such a gating drive circuit can be referred to as a gate-in-panel (GIP) circuit.

[0004] In order to reduce the size of the gating drive circuit, a method of outputting gating signals to multiple pixel lines through one output terminal is being considered. Summary of the Invention

[0005] The present disclosure provides a gating drive circuit and a display including the same, which can respectively improve the output deviation of the first output buffer circuit and the output deviation of the last output buffer circuit among the multiple output buffer circuits included in a first-stage circuit.

[0006] The problems to be solved by this embodiment are not limited to the above problems, and those skilled in the art will clearly understand other problems not mentioned here from the following description.

[0007] This embodiment provides a gating drive circuit, which includes: at least one stage circuit configured to supply gating signals to multiple gating lines and including a first node, wherein the stage circuit includes N output buffer circuits (where N is a natural number greater than or equal to 2), and the N output buffer circuits are configured to sequentially output pulses of gating signals in response to pulses of corresponding clock signals while the first node is in a precharged state; and an output improvement circuit configured to improve the output deviation of the first output buffer circuit that outputs the first gating signal among the N output buffer circuits, and improve the output deviation of the Nth output buffer circuit that outputs the last gating signal among the N output buffer circuits.

[0008] The output improvement circuit may include: a first output improvement circuit configured to enhance the voltage of the first node in response to a previous clock signal whose phase is earlier than the phase of the clock signal input to the first output buffer circuit; and a second output improvement circuit configured to attenuate the voltage of the first node in response to a next clock signal whose phase is later than the phase of the clock signal input to the Nth output buffer circuit.

[0009] The first output improvement circuit may enhance the voltage of the first node through the rising edge of the previous clock signal before the first output buffer circuit outputs a strobe signal, and the second output improvement circuit may attenuate the voltage of the first node through the falling edge of the next clock signal after the Nth output buffer circuit outputs a strobe signal.

[0010] The first output improvement circuit may include: a first transistor including a gate terminal inputting the voltage of the first node, a first terminal inputting the previous clock signal, and a second terminal outputting the previous clock signal; and a first capacitor connected between the gate terminal and the second terminal to enhance the voltage of the first node.

[0011] The second output improvement circuit may include: a second transistor including a gate terminal applied with the voltage of the first node, a first terminal inputting the next clock signal, and a second terminal outputting the next clock signal; and a second capacitor connected between the gate terminal and the second terminal to attenuate the voltage of the first node.

[0012] The first output improvement circuit may include: a first capacitor having one end connected to the first node and the other end connected to a clock line inputting the previous clock signal.

[0013] The second output improvement circuit may include: a second capacitor having one end connected to the first node and the other end connected to a clock line inputting the next clock signal.

[0014] When the length of the high voltage level of the clock signal corresponds to M horizontal periods (where M is a natural number greater than or equal to 2), the stage circuit may include M - 1 first output improvement circuits and M - 1 second output improvement circuits.

[0015] In another aspect, the present embodiment provides a gate driving circuit including: a first stage circuit, a second stage circuit, and a third stage circuit configured to supply strobe signals to a plurality of gate lines and including a first node, wherein the second stage circuit includes first to Nth output buffer circuits (where N is a natural number greater than or equal to 2), and these output buffer circuits are configured to sequentially output pulses of the strobe signal in response to pulses of corresponding clock signals while the first node is in a precharged state; and an output improvement circuit configured to improve the output deviation of the first output buffer circuit and the output deviation of the Nth output buffer circuit.

[0016] The output improvement circuit may include: a first output improvement circuit configured to enhance the voltage of the first node in response to a previous stage strobe signal that is a strobe signal output from the last output buffer circuit of the first stage circuit; and a second output improvement circuit configured to attenuate the voltage of the first node in response to a next stage strobe signal that is a strobe signal output from the first output buffer circuit of the third stage circuit.

[0017] The first output improvement circuit may enhance the voltage of the first node through the rising edge of the previous stage strobe signal before the first output buffer circuit outputs the strobe signal, and the second output improvement circuit may attenuate the voltage of the first node through the falling edge of the next stage strobe signal after the Nth output buffer circuit outputs the strobe signal.

[0018] The first output improvement circuit may include: a first transistor including a gate terminal to which the voltage of the first node is applied, a first terminal for inputting the previous stage strobe signal, and a second terminal for outputting the previous stage strobe signal; and a first capacitor connected between the gate terminal and the second terminal to enhance the voltage of the first node.

[0019] The second output improvement circuit may include: a second transistor including a gate terminal to which the voltage of the first node is applied, a first terminal for inputting the next stage strobe signal, and a second terminal for outputting the next stage strobe signal; and a second capacitor connected between the gate terminal and the second terminal to attenuate the voltage of the first node.

[0020] The first output improvement circuit may include: a first capacitor having one end connected to the first node and the other end connected to a signal line for inputting the previous stage strobe signal.

[0021] The second output improvement circuit may include: a second capacitor having one end connected to the first node and the other end connected to a signal line for inputting the next stage strobe signal.

[0022] On the other hand, the present embodiment provides a display device including: a display panel including a plurality of pixel circuits, wherein the pixel circuits are connected to corresponding data lines and gate lines; a data driving circuit configured to output data signals applied to the data lines; a gate driving circuit configured to receive a clock signal and supply the generated gate signals to the gate lines; and a timing controller configured to control the driving of the data driving circuit and the gate driving circuit, wherein the gate driving circuit is configured to supply gate signals to a plurality of gate lines and includes a first-stage circuit, a second-stage circuit, and a third-stage circuit, the first-stage circuit, the second-stage circuit, and the third-stage circuit including a first node, the second-stage circuit including first to Nth output buffer circuits configured to sequentially output pulses of the gate signals using pulses of a corresponding clock signal while the first node is in a pre-charged state; and an output improvement circuit configured to improve output deviation of the first output buffer circuit and output deviation of the Nth output buffer circuit.

[0023] The output improvement circuit may include: a first output improvement circuit configured to enhance the voltage of the first node before the gate signal is output from the first output buffer circuit; and a second output improvement circuit configured to decay the voltage of the first node after the gate signal is output from the Nth output buffer circuit.

[0024] The first output improvement circuit may enhance the voltage of the first node in response to a pulse of a previous clock signal whose phase is earlier than the phase of the clock signal input to the first output buffer circuit, and the second output improvement circuit may decay the voltage of the first node in response to a pulse of a next clock signal whose phase is later than the phase of the clock signal input to the Nth output buffer circuit.

[0025] The first output improvement circuit may enhance the voltage of the first node through the rising edge of the previous clock signal, and the second output improvement circuit may decay the voltage of the first node through the falling edge of the next clock signal.

[0026] The first output improvement circuit may enhance the voltage of the first node in response to a pulse of a previous gate signal that is a gate signal output from the last output buffer circuit of the first-stage circuit, and the second output improvement circuit may decay the voltage of the first node in response to a pulse of a next gate signal that is a gate signal output from the first output buffer circuit of the third-stage circuit.

[0027] The first output improvement circuit may enhance the voltage of the first node through the rising edge of the previous gate signal, and the second output improvement circuit may decay the voltage of the first node through the falling edge of the next gate signal.

[0028] As described above, according to this embodiment, an output improvement circuit for the output deviation between the first output buffer circuit and the last output buffer circuit of the improvement stage circuit can be added to the stage circuit to improve the output deviation between the first output buffer circuit and the last output buffer circuit.

[0029] Various useful advantages and effects of these embodiments are not limited to the above, and will be more easily understood from the description of the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] By referring to the drawings and describing in detail its exemplary embodiments, the above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art, wherein:

[0031] Figure 1 is a block diagram showing a display according to one embodiment;

[0032] Figure 2 is a diagram showing an example of a pixel circuit;

[0033] Figure 3 is a diagram schematically showing a shift register of a conventional gate driving circuit;

[0034] Figure 4 is a diagram showing the configuration of a stage circuit according to the first embodiment;

[0035] Figure 5 is a diagram for explaining the output deviation occurring in the stage circuit according to the first embodiment;

[0036] Figure 6 is a diagram showing the configuration of a stage circuit according to the second embodiment;

[0037] Figure 7 is a diagram showing the configuration of a node control circuit in the stage circuit according to the second embodiment;

[0038] Figures 8 to 11 is a diagram for describing the configuration of an output improvement circuit in the stage circuit according to the second embodiment;

[0039] Figure 12 is a diagram for describing the configuration for improving the output deviation in the stage circuit according to the second embodiment;

[0040] Figure 13 is a diagram showing the Q-node voltage change and the gate signal of the stage circuit according to the first embodiment;

[0041] Figure 14 and Figure 15 is a diagram showing the Q-node voltage change and the gate signal of the stage circuit according to the second embodiment;

[0042] Figure 16 is a diagram showing the output improvement rate of the stage circuit according to the second embodiment;

[0043] Figure 17 and Figure 18 is a diagram for explaining the correlation between the output improvement circuit and the 1H overlap drive in the gate drive circuit according to the second embodiment;

[0044] Figure 19 and Figure 20 is a diagram for explaining the correlation between the output improvement circuit and the 2H overlap drive in the gate drive circuit according to the second embodiment; and

[0045] Figure 21 and Figure 22 is a diagram for explaining the correlation between the output improvement circuit and the 3H overlap drive in the gate drive circuit according to the second embodiment.

[0046] Description of reference numerals

[0047] 100: Display panel 110: Data drive circuit

[0048] 120: Gate drive circuit 130: Timing controller

[0049] 200: Host system 300: Power supply

[0050] 610: Node control circuit 620: First to Nth output buffer circuits

[0051] 630: First output improvement circuit 640: Second output improvement circuit Detailed implementation manners

[0052] The advantages and features of the present disclosure and the methods for implementing them will be more clearly understood from the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments, but can be implemented in various different forms. On the contrary, these embodiments will make the disclosure of the present disclosure complete and allow those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is only defined within the scope of the appended claims.

[0053] Terms such as "including", "comprising", "having", and "consisting of" used herein generally intend to allow the addition of other components, unless these terms are used together with the term "only". Any reference to the singular may include the plural unless otherwise explicitly stated.

[0054] Even if not explicitly stated, components are interpreted as including the ordinary error range.

[0055] For the description of positional relationships, for example, when the positional relationship and interconnection relationship between two components are described as "on", "above", "below", "next to", "connected or coupled", "crossed or intersected with", etc., unless the term "immediately" or "directly" is used in the expression, one or more other components may be interposed therebetween.

[0056] The terms "first", "second", etc. may be used to distinguish components from each other, but the functions or structures of the components are not limited by the ordinal numbers or component names in front of the components. Since the claims are written around the basic components, the serial numbers in front of the component names in the claims may not match the serial numbers in front of the component names in the embodiments.

[0057] The following embodiments may be partially or fully joined or combined with each other, and may be linked and operated in various ways technically. These embodiments may be implemented independently of each other or in association with each other.

[0058] In the display device of the present disclosure, a display panel driving circuit, a pixel array, a level shifter, etc. may include transistors. The transistors may be implemented by oxide thin film transistors (TFTs) including oxide semiconductors, LTPS TFTs including low temperature polycrystalline silicon (LTPS), etc.

[0059] A transistor is a three-terminal element including a gate, a source, and a drain. The source is the terminal that supplies carriers to the transistor. In a transistor, the carriers start to flow from the source. The drain is the terminal where the carriers flow out of the transistor. The flow of carriers in the transistor is from the source to the drain. In the case of an N-channel transistor, since the carriers are electrons, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In the case of an N-channel transistor, the direction of the current is from the drain to the source. In the case of a P-channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a P-channel transistor, since the holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain may change according to the applied voltage. Therefore, the present invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first terminal and the second terminal.

[0060] The strobe signal swings between a gate-on voltage and a gate-off voltage. The gate-off voltage can be interpreted as a first voltage, and the gate-on voltage can be interpreted as a second voltage. The transistor conducts in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an N-channel transistor, the gate-on voltage can be a gate-high voltage (VGH), and the gate-off voltage can be a gate-low voltage (VGL). In the case of a P-channel transistor, the gate-on voltage can be a gate-low voltage (VGL), and the gate-off voltage can be a gate-high voltage (VGH).

[0061] The present disclosure is applicable to any flat panel display device that requires integrated circuits and power circuits for driving pixels, such as a liquid crystal display (LCD), an organic light emitting display (OLED), and the like.

[0062] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0063] Figure 1 is a block diagram showing a display device according to an embodiment.

[0064] Referring to Figure 1 , a display device according to an embodiment includes a display panel 100 and a display panel driving circuit.

[0065] The display panel 100 includes a pixel array AA that displays pixel data of an input image. The pixel data of the input image is displayed in the pixels of the pixel array AA. The pixel array AA includes data lines DL, a plurality of gate lines GL intersecting the data lines DL, and pixels arranged in a matrix form. Here, in addition to the matrix form, the arrangement form of the pixels can be formed in various ways (for example, a shape that shares pixels emitting the same color, a stripe shape, a diamond shape, etc.).

[0066] When the resolution of the pixel array AA is n (where n is a natural number) × m (where m is a natural number), the pixel array AA includes n pixel columns and m pixel rows L1 to Lm intersecting these pixel columns. The pixel rows include pixels arranged along a first direction X. The pixel columns include pixels arranged along a second direction Y. Generally, one horizontal period 1H can be a time period obtained by dividing one frame period by m (the number of pixel rows L1 to Lm). In one horizontal period 1H, pixel data can be written into the pixels of one pixel row.

[0067] Each pixel includes two or more sub-pixels 101 for color implementation. For example, each pixel may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Each pixel may also include a white sub-pixel. Each sub-pixel 101 includes a pixel circuit. The pixel circuit is connected to a data line DL and a gate line GL. In one embodiment, when the display device is an organic light-emitting display device, the pixel circuit is shown in Figure 2 in.

[0068] Referring to Figure 2 , the pixel circuit may include a light-emitting element EL, a driving element DT that supplies current to the light-emitting element EL, a switching element ST that supplies a data signal Vdata to the gate terminal of the driving element DT in response to a gate signal GATE1, and a capacitor Cst connected between the gate terminal and the source terminal of the driving element DT. The driving element DT and the switching element ST may be implemented as N-channel transistors.

[0069] A pixel driving voltage EVDD may be applied to the drain terminal of the driving element DT. The driving element DT drives the light-emitting element EL by supplying current to the light-emitting element EL according to the gate-source voltage Vgs. The switching element ST turns on in response to the gate conduction voltage VGH of the gate signal GATE1. When the forward voltage between the anode terminal and the cathode terminal is greater than or equal to the threshold voltage, the light-emitting element EL turns on and emits light. A pixel base voltage EVSS lower than the pixel driving voltage EVDD is applied to the cathode terminal of the light-emitting element EL.

[0070] The capacitor Cst is connected between the gate terminal and the source terminal of the driving element DT to maintain the gate-source voltage Vgs of the driving element DT.

[0071] In addition, the light-emitting element EL may be implemented as an inorganic light-emitting diode (LED) (e.g., a micro-LED) or an organic light-emitting diode (e.g., an organic light-emitting diode (OLED) including an organic compound layer formed between an anode and a cathode)), but is not limited thereto. Here, the organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL), but is not limited thereto. When a voltage is applied to the anode terminal and the cathode terminal of the OLED, holes that have passed through the hole transport layer (HTL) and electrons that have passed through the electron transport layer (ETL) move to the light-emitting layer (EML) to form excitons, and visible light is emitted from the light-emitting layer (EML). The OLED used as the light-emitting element (EL) may have a tandem structure in which a plurality of light-emitting layers are stacked. The OLED having a tandem structure may improve the brightness and lifetime of the pixel.

[0072] In addition, the display panel 100 may further include a touch sensor. Here, the touch sensor may be disposed on the screen of the display panel 100 in a cover surface type or an external attachment type.

[0073] In addition, the touch sensor may be implemented in an embedded type embedded in the pixel array AA.

[0074] In one embodiment, the display panel driving circuit writes the data of the input image into the pixels of the display panel 100 under the control of the timing controller 130. The display panel driving circuit may include a data driving circuit 110, a gate driving circuit 120, a timing controller 130 for controlling the operation timing of the data driving circuit 110 and the gate driving circuit 120, and a level shifter 140 connected between the timing controller 130 and the gate driving circuit 120. Here, the display panel driving circuit may further include a power supply 300. Here, the level shifter 140 may be included in the timing controller 130.

[0075] The data driving circuit 110 outputs data signals Vdata1 to Vdata3 by converting the pixel data of each frame of the input image received from the timing controller 130 as a digital signal into an analog gamma compensation voltage. As Figure 1 shown by the circles in, the first data signal Vdata1 to the third data signal Vdata3 output from the data driving circuit 110 are supplied to the corresponding first data line DL1 to the third data line DL3. The data driving circuit 110 uses a digital-to-analog converter (hereinafter referred to as "DAC") that converts a digital signal into an analog gamma compensation voltage to output the data signals Vdata1 to Vdata3.

[0076] The data driving circuit 110 may be integrated in a source driver integrated circuit (SDIC). The source driver IC may be connected to the bonding pads of the display panel 100 using a tape automated bonding (TAB) method or a chip on glass (COG) method. In addition, the source driver IC may be implemented using a chip on film (COF) method.

[0077] When the display panel 100 further includes a touch sensor, the source driver IC may include a touch sensor driving circuit for driving the touch sensor.

[0078] The gate driving circuit 120 may be formed in the border area BZ where no image is displayed in the display panel 100, or at least a part thereof may be disposed in the pixel array AA. The gate driving circuit 120 receives a clock signal received from the level shifter 140 and outputs a gate signal GATE. The gate signal GATE is supplied to the gate line GL.

[0079] As Figure 1As shown by the circles, the gate signals GATE1 to GATE3 applied to the first gate line GL1 to the third gate line GL3 turn on the switching elements of the sub-pixel 101 to select the pixels charged with the voltages of the data signals Vdata1 to Vdata3. The switching elements of the sub-pixel 101 can be turned on in response to the gate-on voltages VGH of the corresponding gate signals GATE1 to GATE3, and can be turned off according to the gate-off voltage VGL. The gate signals GATE1 to GATE3 swing between the gate-on voltage VGH and the gate-off voltage VGL.

[0080] The gate driving circuit 120 shifts the gate signals by using a shift register or an edge trigger. Here, the shift register and the edge trigger include a plurality of stage circuits connected dependently to each other.

[0081] The timing controller 130 can control the operation timing of the data driving circuit 110 and the gate driving circuit 120 at a frame rate of input frame rate × i Hz by multiplying the input frame rate by a factor i (where i is a natural number). In the National Television Standards Committee (NTSC) system, the input frame rate can be 60 Hz, and in the Phase Alternating Line (PAL) system, the input frame rate can be 50 Hz.

[0082] The timing controller 130 receives the pixel data of the input image and the timing signal synchronized therewith from the host system 200. The pixel data of the input image received by the timing controller 130 is a digital signal. The timing controller 130 sends the pixel data to the data driving circuit 110. Here, the timing signal can include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, a data enable signal DE, etc. Since the vertical period and the horizontal period can be known by the method of counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of one horizontal period 1H.

[0083] The timing controller 130 can generate a data timing control signal for controlling the data driving circuit 110 and a gate timing control signal for controlling the gate driving circuit 120 based on the timing signal received from the host system 200. The gate timing control signal can be generated as a clock of a digital signal voltage level.

[0084] The host system 200 may be any one of a television (TV), a set-top box, a navigation system, a personal computer (PC), a home theater, a mobile system, and a wearable system. In mobile and wearable devices, the data driving circuit 110, the timing controller 130, the level shifter 140, etc. may be integrated in a single driving IC (not shown). In a mobile system, the host system 200 may be implemented as an application processor (AP). The host system 200 may send the pixel data of the input image to the driving IC through a Mobile Industry Processor Interface (MIPI). The host system 200 may be connected to the driving IC through a flexible printed circuit board (FPCB).

[0085] The clock signal output from the level shifter 140 swings between the gate-on voltage VGH and the gate-off voltage VGL, and is supplied to the gate driving circuit 120 through the clock lines CL1 to CLn. The clock signal output from the level shifter 140 may be applied to at least one of the gate driving circuit 120, the data driving circuit 110, and the touch sensor driving circuit.

[0086] The power supply 300 uses a DC-DC converter to generate the voltages required for the display panel driving circuit and the pixel array that drive the display panel 100. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, a buck-boost converter, etc. The power supply 300 may generate DC voltages such as a gamma reference voltage VGMA, a gate-on voltage VGH, a gate-off voltage VGL, a common voltage of pixels, etc. by adjusting the DC input voltage from the host system 200. The gamma reference voltage VGMA is supplied to the data driving circuit 110. The gamma reference voltage VGMA is divided for each gray level by a voltage dividing circuit of the data driving circuit 110 and then supplied to the DAC of the data driving circuit 110. The power supply 300 may generate a constant voltage (e.g., a pixel driving voltage EVDD and a pixel base voltage EVSS) that is commonly applied to the pixels.

[0087] As described above, the display device including the display panel 100 and the display panel driving circuit may be a narrow-bezel display device that applies a bezel area BZ minimization application.

[0088] In addition, the gate driving circuit 120 may output a plurality of gate signals in one stage circuit to minimize the size of the circuit. In other words, one stage circuit may include a plurality of output buffer circuits, and each of the plurality of output buffer circuits may output a gate signal.

[0089] Hereinafter, a configuration for outputting a plurality of gate signals from one stage circuit will be described.

[0090] Figure 3 is a diagram schematically showing a shift register of a gate driving circuit.

[0091] Refer to Figure 3 , the shift register of the gating drive circuit 120 may include stage circuits ST1, ST2, ST3, etc. that are connected dependently on each other.

[0092] The shift register may receive a start signal VST or a carry signal CAR, and may receive clock signals CLK1 to CLKn from the level shifter 140. Here, the gating start signal VST may be input to the first stage circuit ST1. And the carry signal CAR may be output from the previous stage circuit.

[0093] The stage circuits ST1 to ST3 may sequentially receive a plurality of clock signals through the clock lines CL1 to CLn. In other words, the stage circuits ST1 to ST3 may receive a plurality of clock signals that are phase-shifted by a predetermined period (or horizontal period).

[0094] The stage circuits ST1 to ST3 may sequentially output a plurality of gating signals using the plurality of sequentially input clock signals. Here, the stage circuits ST1 to ST3 may output the carry signal CAR and supply it to the next stage circuit.

[0095] In Figure 3 , it shows that one stage circuit outputs four gating signals. However, the present disclosure is not limited thereto, two or three gating signals may be output from one stage circuit, and five or more gating signals may be output.

[0096] Figure 4 is a diagram showing the configuration of the stage circuit according to the first embodiment.

[0097] Figure 5 is a diagram for explaining the output deviation that occurs in the stage circuit according to the first embodiment.

[0098] Although Figure 4 the pull-up transistor Tu and the pull-down transistor Td are shown as N-channel transistors, this embodiment is not limited thereto. In other words, the pull-up transistor Tu and the pull-down transistor Td may also be P-channel transistors.

[0099] Figure 5 The waveforms of the clock signal, the gating signal, and the Q-node voltage when the pull-up transistor Tu and the pull-down transistor Td are N-channel transistors are also shown, but this embodiment is not limited thereto. In other words, the waveforms of the clock signal, the gating signal, and the Q-node voltage may be when the pull-up transistor Tu and the pull-down transistor Td are P-channel transistors.

[0100] Refer to Figure 4, the stage circuits ST1, ST2, or ST3 according to the first embodiment may include a node control circuit NCC and a plurality of output buffer circuits OBC. A carry signal output circuit (not shown) for outputting a carry signal may also be included.

[0101] Here, the output buffer circuit may include a pull-up transistor Tu, a pull-down transistor Td, and a boost capacitor Cb.

[0102] The node control circuit NCC controls the voltages of the Q node and the QB node.

[0103] The voltage of the Q node may be input to the gate terminal of the pull-up transistor Tu included in each of the plurality of output buffer circuits OBC, and a clock signal may be input to the first terminal. A strobe signal having a high voltage level may be output from the second terminal.

[0104] In other words, while the Q node is in the pre-charge state, the plurality of output buffer circuits OBC may output a strobe signal using the corresponding clock signal. Here, the plurality of output buffer circuits OBC may output the strobe signal in sequence from the first output buffer circuit to the last output buffer circuit.

[0105] In Figure 4 , when four clock signals CLK[n] to [n + 3] or CLK[n + 4] to [n + 7] or CLK[n + 8] to [n + 11] are input to Tu of the node control circuit NCC, it may be interpreted that the four clock signals are sequentially input to the plurality of output buffer circuits OBC.

[0106] For example, in Figure 4 the first stage circuit ST1, four clock signals CLK[n] to [n + 3] are input to Tu of the node control circuit NCC, and it may be interpreted that the clock signals CLK[n], CLK[n + 1], CLK[n + 2], and CLK[n + 3] are sequentially input to the first output buffer circuit, the second output buffer circuit, the third output buffer circuit, and the fourth output buffer circuit. Here, n is a natural number greater than or equal to 1.

[0107] In addition, the voltage of the QB node may be input to the gate terminal of the pull-down transistor Td included in each of the plurality of output buffer circuits OBC, and a strobe signal having a low voltage level may be output from the first terminal. A low voltage power supply may be input to the second terminal.

[0108] The boost capacitor Cb included in each of the plurality of output buffer circuits OBC may be connected between the gate terminal of the pull-up transistor Tu and the second terminal to boost the voltage of the Q node. Here, when the voltage of the Q node is boosted, the strobe signal may be output quickly.

[0109] Using the above configuration, multiple strobe signals can be sequentially output from one stage circuit.

[0110] Here, as Figure 5 shown, the multiple strobe signals output sequentially can have an overlapping part. For example, when the conduction duration (high voltage level length) of the strobe signal is 2 horizontal periods 2H, two strobe signals can overlap by up to 1 horizontal period 1H.

[0111] In other words, the stage circuit can perform overlapping driving. Here, overlapping driving can mean that when the stage circuit sequentially outputs multiple strobe signals, the stage circuit outputs them in such a way that the partial conduction durations of two or more strobe signals overlap. When the stage circuit performs overlapping driving, the voltage charging rate of the sub-pixel can be improved.

[0112] On the other hand, in the overlapping driving of the stage circuit according to the first embodiment, since the voltage of the Q node is enhanced in the first output buffer circuit, an output deviation appears in the strobe signal output from the first output buffer circuit.

[0113] And since the voltage of the Q node is attenuated in the last output buffer circuit, an output deviation also appears in the strobe signal output from the last output buffer circuit.

[0114] Specifically, in Figure 5 the intervals t1 to t3, the node control circuit NCC pre-charges the voltage of the Q node to the first high voltage level GVDD.

[0115] Thereafter, the first output buffer circuit enhances the voltage of the Q node at time point t3. Here, the first output buffer circuit enhances the voltage Q of the Q node through the rising edge of the nth clock signal CLK[n].

[0116] In other words, at time point t3, the first output buffer circuit enhances the voltage of the Q node from the first high voltage level GVDD to the first boosted voltage level BL1.

[0117] At time point t4, the second output buffer circuit enhances the voltage of the Q node again. Here, the second output buffer circuit enhances the voltage of the Q node through the rising edge of the (n + 1)th clock signal CLK[n + 1].

[0118] In other words, at time point t4, the second output buffer circuit enhances the voltage of the Q node from the first boosted voltage level BL1 to the second boosted voltage level BL2.

[0119] At time point t5, when the (n + 2)th clock signal CLK[n + 2] is input to the third output buffer circuit, the rising edge of the (n + 2)th clock signal CLK[n + 2] overlaps with the falling edge of the nth clock signal CLK[n] to cancel the voltage change of the Q node.

[0120] In other words, during the interval from t4 to t5, the voltage of the Q node is maintained at the second boosted voltage level BL2.

[0121] At time point t6 when the (n+3)th clock signal CLK[n+3] is input to the fourth output buffer circuit, the rising edge of the (n+3)th clock signal CLK[n+3] and the falling edge of the (n+1)th clock signal CLK[n+1] overlap to offset the voltage change of the Q node.

[0122] In other words, in the interval from t5 to t6, the voltage of the Q node is maintained at the second boosted voltage level BL2.

[0123] At time point t7 , the voltage of the Q node decays from the second boosted voltage level BL2 to the first boosted voltage level BL1 by the falling edge of the (n+2)th clock signal CLK[n+2] input to the third output buffer circuit.

[0124] At time point t8 , the voltage of the Q node decays from the first boosted voltage level BL1 to the first high voltage level GVDD by the falling edge of the (n+3)th clock signal CLK[n+3] input to the fourth output buffer circuit.

[0125] Then, at time point t9, the node control circuit NCC resets the voltage of the Q node to the first low voltage level GVSS.

[0126] Here, enhancement may be interpreted as raising or increasing the pressure, and attenuation may be interpreted as lowering the pressure.

[0127] Generally, when a voltage change of the Q node occurs, an output deviation occurs in the strobe signal.

[0128] exist Figure 5 In the embodiment, since the voltage change (dashed circle) of the Q node occurs in the interval t3 to t4 when the first output buffer circuit outputs the selection signal GATE[n], the rising edge (interval t3 to t4) of the selection signal GATE(n) becomes longer than the rising edges of other selection signals.

[0129] In addition, since a voltage change (dashed square mark) of the Q node occurs when the fourth output buffer circuit, which is the last output buffer circuit, outputs the selection signal GATE[n+3] in the interval t7 to t8, the falling edge of the selection signal GATE[n+3] (interval t7 to t8) is longer than the falling edges of other selection signals.

[0130] As described above, when the output deviation of the rising edge extension of the strobe signal and the output deviation of the falling edge extension of the strobe signal occur, the transistors (for example, Figure 2Failures of the switching elements ST, etc. in it may cause deterioration of the image quality of the display device.

[0131] In the second embodiment, the output deviation of the first output buffer circuit and the output deviation of the last output buffer circuit can be improved by the following configuration.

[0132] Figure 6 FIG. is a diagram showing the configuration of the stage circuit according to the second embodiment.

[0133] Referring to Figure 6 , the gate driving circuit 120 may include one or more stage circuits (e.g., ST1, ST2, ST3, etc.).

[0134] Each stage circuit includes a node control circuit 610, N output buffer circuits (where N is a natural number greater than or equal to 2), i.e., the first output buffer circuit to the Nth output buffer circuit 620. Each stage circuit further includes an output improvement circuit. Here, the output improvement circuit includes a first output improvement circuit 630 and a second output improvement circuit 640.

[0135] In other words, in the second embodiment, the gate driving circuit 120 (i.e., the stage circuit) can add an output improvement circuit to the node control circuit 610 and the first to Nth output buffer circuits 620 to improve the output deviation of the first output buffer circuit and the output deviation of the last output buffer circuit.

[0136] Here, the first output buffer circuit to the Nth output buffer circuit are arranged in sequence. Although Figure 6 FIG. shows that the first output improvement circuit 630 and the second output improvement circuit 640 are arranged in front of the first output buffer circuit, this embodiment is not limited thereto. In other words, the first output improvement circuit 630 and the second output improvement circuit 640 can be arranged between the first output buffer circuit 620 and the Nth output buffer circuit 620, or can be arranged behind the Nth output buffer circuit.

[0137] In addition, in one embodiment, each stage circuit may further include a carry signal output circuit (not shown) for outputting a carry signal.

[0138] The node control circuit 610 controls the charging and discharging (resetting) of the Q node as the first node and the charging and discharging of the QB node as the second node.

[0139] In other words, the node control circuit 610 controls the voltages of the first node and the second node.

[0140] As Figure 7As shown, the node control circuit 610 may include a row selection and Q charging circuit LSQCC, a Q discharging circuit QDC, a Q charging circuit QCC, a Q discharging and holding circuit QDHC, a QB charging circuit QBCC, a first QB discharging circuit QBDC1, and a second QB discharging circuit QBDC2.

[0141] Here, when the display device has a sensing function of the pixel circuit, the row selection and Q charging circuit LSQCC, the Q discharging circuit QDC, and the second QB discharging circuit QBDC2 may be included in the node control circuit NCC.

[0142] The row selection and Q charging circuit LSQCC may be a circuit that selects any one pixel row as the row for performing sensing driving and charges the first node when sensing is driven. During sensing driving, the row selection and Q charging circuit LSQCC may charge the first node to a high voltage level (e.g., GVDD).

[0143] In Figure 7 where LSP may mean a row selection signal and RESET may mean a reset signal.

[0144] The Q discharging circuit QDC may be a circuit that discharges the first node during sensing driving. During sensing driving, the Q discharging circuit QDC may discharge (reset) the first node to a low voltage level (e.g., GVSS).

[0145] The Q charging circuit QCC may be a circuit for charging the first node when display driving. When display driving, the Q charging circuit QCC may charge the first node to a high voltage level (e.g., GVDD). Here, the Q charging circuit QCC may charge the first node through the previous carry signal CAR[n - 1] supplied from the previous stage circuit.

[0146] The Q discharging and holding circuit QDHC may be a circuit that discharges the first node during display driving and stably maintains the voltage state of the first node. During display driving, the Q discharging and holding circuit QDHC may discharge (reset) the first node to a low voltage level (e.g., GVSS). Here, the Q discharging and holding circuit QDHC may discharge the first node through the next carry signal CAR[n + 1] supplied from the next stage circuit.

[0147] The first QB discharging circuit QBDC1 may be a circuit that discharges the second node when display driving. When display driving, the first QB discharging circuit QBDC1 may discharge (reset) the second node to a low voltage level (e.g., GVSS).

[0148] The second QB discharge circuit QBDC2 can be a circuit for discharging the first node during sense driving. During sense driving, the second QB discharge circuit QBDC2 can discharge (reset) the second node to a low voltage level (e.g., GVSS).

[0149] While the first node is in a pre-charged state, the first to Nth output buffer circuits 620 (i.e., N output buffer circuits) sequentially output strobe signals in response to pulses of corresponding clock signals.

[0150] Here, the voltage of the first node can be input to the gate terminals of pull-up transistors Tu included in each of the first to Nth output buffer circuits 620, and the corresponding clock signal can be input to the first terminal. A strobe signal with a high voltage level can be output from the second terminal. Boost capacitors Cb included in each of the first to Nth output buffer circuits 620 can be connected between the gate terminals of the pull-up transistors Tu and the second terminal to boost the voltage of the first node.

[0151] The first to Nth output buffer circuits 620 can sequentially output strobe signals from the first output buffer circuit (the first output buffer circuit) to the last buffer circuit (the Nth output buffer circuit).

[0152] In addition, the output improvement circuit improves the output deviation of the first output buffer circuit that outputs the first strobe signal and the output deviation of the Nth output buffer circuit that outputs the last strobe signal. The output improvement circuit can include a first output improvement circuit 630 and a second output improvement circuit 640.

[0153] The first output improvement circuit 630 enhances the voltage of the first node in response to a pulse of a previous clock signal (a clock signal with a phase earlier than the phase of the clock signal input to the first output buffer circuit). Here, before the strobe signal is output from the first output buffer circuit, the first output improvement circuit 630 can enhance the voltage of the first node through the rising edge of the previous clock signal.

[0154] As Figure 8 shown, the first output improvement circuit 630 using the previous clock signal can include a first transistor Tr and a first capacitor C_pre. In other words, the first output improvement circuit 630 can be implemented as a buffer circuit. Here, the first transistor Tr can include a gate terminal for inputting the voltage of the first node, a first terminal for inputting the previous clock signal (e.g., CLK[n - 1]), and a second terminal for outputting the previous clock signal. The first capacitor C_pre can be connected between the gate terminal of the first transistor Tr and the second terminal to enhance the voltage of the first node.

[0155] In one embodiment, as Figure 9As shown, the first output improvement circuit 630 may include a first capacitor Cpre. One end of the first capacitor Cpre is connected to the first node, and the other end is connected to the clock line. In other words, the first output improvement circuit 630 may be implemented as a capacitor circuit. Here, the previous clock signal (e.g., CLK[n - 1]) is input to the clock line.

[0156] The first output improvement circuit 630 as described above only enhances the voltage of the first node and does not output a strobe signal like the output buffer circuit.

[0157] In other words, the output buffer circuit is connected to the strobe line and outputs a strobe signal to the strobe line, but the first output improvement circuit 630 only enhances the voltage of the first node and is not connected to the strobe line.

[0158] When four clock signals CLK[n] to [n + 3] or CLK[n + 4] to [n + 7] or CLK[n + 8] to [n + 11] are input to Figure 8 and Figure 9 Tu of the node control circuit 610 in

[0159] it can be interpreted that four clock signals are sequentially input to the first output buffer circuit 620 to the Nth output buffer circuit 620.

[0160] For example, when four clock signals CLK[n] to [n + 3] are input to Tu of the node control circuit 610 in the first-stage circuit ST1, it can be interpreted that the clock signals CLK[n], CLK[n + 1], CLK[n + 2], and CLK[n + 3] are sequentially input to the first output buffer circuit, the second output buffer circuit, the third output buffer circuit, and the fourth output buffer circuit.

[0161] In addition, when the clock signal CLK[n + 11] is input to Tr of the node control circuit 610 in the first-stage circuit ST1, it can be interpreted that the clock signal CLK[n - 1] is input to the first output improvement circuit 630. Here, when the clock signal CLK[n] is the first clock signal, the previous clock signal CLK[n - 1] of the first clock signal can be the last clock signal CLK[n + 11].

[0162] In addition, the first output improvement circuit 630 may enhance the voltage of the first node by using the previous-stage strobe signal (the strobe signal output from the last output buffer circuit of the previous-stage circuit).

[0163] For example, the first output improvement circuit 630 of the second-stage circuit ST2 can enhance the voltage of the first node by using the previous-stage strobe signal GATE[n+3] output from the last output buffer circuit of the first-stage circuit ST1.

[0164] Here, the first output improvement circuit 630 can enhance the voltage of the first node through the rising edge of the previous-stage strobe signal.

[0165] As Figure 10 shown, the first output improvement circuit 630 using the previous-stage strobe signal can include a first transistor Tr and a first capacitor C_pre. Here, the first transistor Tr can include a gate terminal for inputting the voltage of the first node, a first terminal for inputting the previous-stage strobe signal (e.g., GATE[n-1]), and a second terminal for outputting the previous-stage strobe signal. The first capacitor C_pre can be connected between the gate terminal and the second terminal of the first transistor Tr to enhance the voltage of the first node.

[0166] In one embodiment, as Figure 11 shown, the first output improvement circuit 630 can include a first capacitor Cpre, one end of the first capacitor Cpre is connected to the first node, and the other end is connected to a signal line. Here, the previous-stage strobe signal (e.g., GATE[n-1]) is input to the signal line.

[0167] For example, the previous-stage strobe signal GATE[n+3] can be input to the first capacitor Cpre of the second-stage circuit ST2 through a signal line connected to the last output buffer circuit of the first-stage circuit ST1.

[0168] In Figure 10 and Figure 11 when four clock signals CLK[n] to [n+3], CLK[n+4] to [n+7], or CLK[n+8] to [n+11] are input to Tu of the node control circuit 610, it can be interpreted that the four clock signals are sequentially input to the first output buffer circuit 620 to the Nth output buffer circuit 620.

[0169] The second output improvement circuit 640 attenuates the voltage of the Q node by using the next clock signal (a clock signal with a phase later than the phase of the clock signal input to the last output buffer circuit (i.e., the Nth output buffer circuit)). Here, the second output improvement circuit 640 can attenuate the voltage of the first node through the falling edge of the next clock signal after the strobe signal is output from the Nth output buffer circuit.

[0170] As Figure 8As shown, the second output improvement circuit 640 using the next clock signal may include a second transistor Tf and a second capacitor C_post. In other words, the second output improvement circuit 640 may be implemented as a buffer circuit. Here, the second transistor Tf may include a gate terminal for inputting the voltage of the first node, a first terminal for inputting the next clock signal (e.g., CLK[n+4]), and a second terminal for outputting the next clock signal. The second capacitor C_post may be connected between the gate terminal and the second terminal of the second transistor Tf to attenuate the voltage of the first node.

[0171] In one embodiment, as Figure 9 shown, the second output improvement circuit 640 may include a second capacitor (Cpost) with one end connected to the first node and the other end connected to the clock line. In other words, the second output improvement circuit 640 may be implemented as a capacitor circuit. Here, the next clock signal (e.g., CLK[n+4]) is input to the clock line.

[0172] The above-mentioned second output improvement circuit 640 only attenuates the voltage of the first node and does not output a strobe signal like an output buffer circuit.

[0173] In other words, the output buffer circuit is connected to the strobe line and outputs a strobe signal to the strobe line, but the second output improvement circuit 640 only attenuates the voltage of the first node and is not connected to the strobe line.

[0174] In Figure 8 and Figure 9 , when the next clock signal CLK[n+4], CLK[n+8] or CLK[n] is input to Tf of the node control circuit 610, it can be interpreted that the next clock signal is input to the second output improvement circuit 640. Here, n is a natural number greater than or equal to 1.

[0175] For example, when the clock signal CLK[n+4] is input to Tf of the node control circuit 610 in the first-stage circuit ST1, it can be interpreted that the clock signal CLK[n+4] is input to the second output improvement circuit 640. Here, in Figure 8 and Figure 9 , since there are first to N output buffer circuits, that is, N output buffer circuits, where N is 4, the clock signal CLK[n+4] can be used as the next clock signal.

[0176] When there are 2 output buffer circuits among the multiple output buffer circuits, the clock signal CLK[n+2] can be used as the next clock signal.

[0177] In addition, the second output improvement circuit 640 may use the next-stage strobe signal (the strobe signal output from the first output buffer circuit of the next-stage circuit) to attenuate the voltage of the first node.

[0178] For example, the second output improvement circuit 640 of the second-stage circuit ST2 can use the next-stage strobe signal GATE[n+8] output from the first output buffer circuit of the third-stage circuit to attenuate the voltage of the first node.

[0179] Here, the second output improvement circuit 640 can attenuate the voltage of the first node through the falling edge of the next-stage strobe signal.

[0180] As Figure 10 shown, the second output improvement circuit 640 using the next-stage strobe signal may include a second transistor Tf and a second capacitor C_post. Here, the second transistor Tf may include a gate terminal for inputting the voltage of the first node, a first terminal for inputting the next-stage strobe signal (e.g., GATE[n+4]), and a second terminal for outputting the next-stage strobe signal. In addition, the second capacitor C_post may be connected between the gate terminal and the second terminal of the second transistor Tf to attenuate the voltage of the first node.

[0181] In one embodiment, as Figure 11 shown, the second output improvement circuit 640 may include a second capacitor (Cpost), one end of which is connected to the first node and the other end is connected to the signal line. Here, the next-stage strobe signal (e.g., GATE[n+4]) is input to the signal line.

[0182] For example, the next-stage strobe signal GATE[n+8] may be input to the second capacitor Cpost of the second-stage circuit ST2 through the signal line connected to the first output buffer circuit of the third-stage circuit ST3.

[0183] As described above, before the strobe signal is output from the first output buffer circuit, the first output improvement circuit 630 enhances the voltage of the first node through the rising edge of the previous clock signal so that the output deviation in the strobe signal output from the first output buffer circuit of the slave-stage circuit can be improved.

[0184] After the strobe signal is output from the last output buffer circuit (i.e., the Nth output buffer circuit), since the second output improvement circuit 640 attenuates the voltage of the first node through the falling edge of the next clock signal, the output deviation in the strobe signal output from the Nth output buffer circuit can be improved.

[0185] Specifically, in the overlapping drive of the stage circuit, the node control circuit 610 pre-charges the voltage of the first node to the first high voltage level GVDD during the Figure 12 interval t1 to t2.

[0186] At time point t2 before the first output buffer circuit outputs a strobe signal, the first output improvement circuit 630 enhances the voltage Q of the first node through the rising edge of the (n - 1)th clock signal CLK[n - 1] which is the previous clock signal.

[0187] In other words, before the first output buffer circuit outputs a strobe signal, the first output improvement circuit 630 enhances the voltage of the first node from the first high voltage level GVDD to the first boosted voltage level BL1.

[0188] Thereafter, at time point t3, the first output buffer circuit enhances the voltage of the first node again. Here, the first output buffer circuit enhances the voltage of the first node through the rising edge of the nth clock signal CLK[n].

[0189] In other words, at time point t3, the first output buffer circuit enhances the voltage of the first node from the first boosted voltage level BL1 to the second boosted voltage level BL2.

[0190] At time point t4 when the (n + 1)th clock signal CLK[n + 1] is input to the second output buffer circuit, the rising edge of the (n + 1)th clock signal CLK[n + 1] and the falling edge of the (n - 1)th clock signal CLK[n - 1] overlap to cancel the voltage change of the first node.

[0191] In other words, during the interval from t3 to t4, the voltage of the first node is maintained at the second boosted voltage level BL2.

[0192] At time point t5 when the (n + 2)th clock signal CLK[n + 2] is input to the third output buffer circuit, the rising edge of the (n + 2)th clock signal CLK[n + 2] and the falling edge of the nth clock signal CLK[n] overlap to cancel the voltage change of the first node.

[0193] At time point t6 when the (n + 3)th clock signal CLK[n + 3] is input to the Nth output buffer circuit which is the last output buffer circuit, the rising edge of the (n + 3)th clock signal CLK[n + 3] overlaps with the falling edge of the (n + 1)th clock signal CLK[n + 1] to cancel the voltage change of the first node.

[0194] In other words, during the interval from t5 to t6, the voltage of the first node is maintained at the second boosted voltage level BL2.

[0195] In addition, even at time point t7 when the (n + 4)th clock signal CLK[n + 4] which is the next clock signal is input to the second output improvement circuit 640, the rising edge of the (n + 4)th clock signal CLK[n + 4] and the falling edge of the (n + 2)th clock signal CLK[n + 2] also overlap to cancel the voltage change of the first node.

[0196] In other words, during the interval from t6 to t7, the voltage of the first node is maintained at the second boosted voltage level BL2.

[0197] At time point t8, the voltage of the first node decays from the second boosted voltage level BL2 to the first boosted voltage level BL1 by the falling edge of the (n + 3)-th clock signal CLK[n + 3] input to the N-th output buffer circuit.

[0198] In other words, during the interval from t7 to t8, the voltage of the first node is maintained at the second boosted voltage level BL2.

[0199] In addition, at time point t9, the voltage of the first node can decay from the first boosted voltage level BL1 to the first high voltage level GVDD by the falling edge of the (n + 4)-th clock signal CLK[n + 4] input to the second output improvement circuit 640.

[0200] Thereafter, the node control circuit 610 can reset the voltage of the first node to the first low voltage level GVSS.

[0201] Generally, when a voltage change of the first node occurs, an output deviation appears in the strobe signal.

[0202] In the second embodiment, before the first output buffer circuit outputs the strobe signal GATE(n), as Figure 12 shown, the first output improvement circuit 630 boosts the voltage of the first node to the first boosted voltage level BL1, and at time point t3, the first output buffer circuit boosts the voltage of the first node to the second boosted voltage level BL2.

[0203] Since the voltage of the first node is maintained at the second boosted voltage level BL2 starting from time point t3, no voltage change of the first node (dotted circle) occurs during the interval t3 to t4 when the first output buffer circuit outputs the strobe signal GATE[n] at a high voltage level.

[0204] Therefore, the length difference between the rising edge of the strobe signal GATE[n] output from the first output buffer circuit and the rising edges of the remaining strobe signals is significantly reduced.

[0205] On the other hand, since after the N-th output buffer circuit, which is the last output buffer circuit, outputs the strobe signal GATE[n + 3], the second output improvement circuit 640 decays the voltage of the Q node to the first high voltage level GVDD at time point t9, no voltage change of the Q node (sharp dotted line) occurs even during the interval t7 to t8 when the N-th output buffer circuit outputs the strobe signal GATE[n + 3].

[0206] In other words, in the first embodiment, at the time point t7 when the N-th output buffer circuit outputs the strobe signal GATE[n+3], the voltage of the Q node changes from the second boosted voltage level BL2 to the first boosted voltage level BL1 through the falling edge of the (n+2)-th clock signal CLK[n+2] input to the third output buffer circuit.

[0207] However, in the second embodiment, since the rising edge of the (n+4)-th clock signal CLK[n+4] and the falling edge of the (n+2)-th clock signal CLK[n+2] overlap at the time point t7, the voltage change of the first node is canceled, so the voltage change of the Q node does not occur until the time point t8 when the falling edge of the strobe signal GATE[n+3] is output. In addition, since the second output improvement circuit 640 attenuates the voltage of the first node after the N-th output buffer circuit outputs the strobe signal GATE[n+3], the voltage of the first node can be gradually discharged (reset) starting from the time point t8 when the falling edge of the strobe signal GATE[n+3] is output.

[0208] Therefore, the length difference between the falling edge of the strobe signal GATE[n+3] output from the N-th output buffer circuit and the falling edges of the remaining strobe signals is significantly reduced.

[0209] Hereinafter, the effects of the output of the improvement stage circuit according to one embodiment will be described.

[0210] Figure 13 is a diagram showing the voltage change of the Q node and the strobe signal of the stage circuit according to the first embodiment.

[0211] Figure 14 and Figure 15 is a diagram showing the voltage change of the Q node, which is the first node of the stage circuit, and the strobe signal according to the second embodiment. Here, Figure 14 is the waveform when the first output improvement circuit 630 and the second output improvement circuit 640 are implemented as buffer circuits. Figure 15 is the waveform when the first output improvement circuit 630 and the second output improvement circuit 640 are implemented as capacitor circuits.

[0212] In the stage circuit of the first embodiment, since the voltage of the Q node is enhanced or attenuated when the strobe signal is output as Figure 13 shown, the voltage change (i.e., voltage deviation) of the Q node when the strobe signal is output seems large.

[0213] As a result, in the stage circuit of the first embodiment, as Figure 16 shown, the rising edge time (time_r) of the strobe signal output from the first output buffer circuit becomes 1.21 μs longer than the rising edge time (average time) of the remaining strobe signals.

[0214] The falling edge time (time_f) of the strobe signal output from the fourth output buffer circuit, which is the last output buffer circuit, becomes 0.15 μs longer than the falling edge times (average time) of the remaining strobe signals.

[0215] However, in the stage circuit of the second embodiment, it can be seen that, as Figure 14 and Figure 15 shown, since the voltage of the Q node is pre-boosted before the output of the strobe signal and the voltage of the Q node is attenuated after the output of the strobe signal, the voltage deviation of the Q node seems to be smaller than that of the stage circuit of the first embodiment.

[0216] Therefore, it can be seen that the waveform of the strobe signal seems to be constant.

[0217] Specifically, as Figure 16 shown, the rising edge time of the strobe signal output from the first output buffer circuit becomes 0.09 μs or 0.22 μs longer than the rising edge times (average time) of the remaining strobe signals.

[0218] In other words, it can be seen that the difference between the rising edge time of the strobe signal output from the first output buffer circuit and the rising edge times of the remaining strobe signals is very small.

[0219] The falling edge time of the strobe signal output from the fourth output buffer circuit is 0.05 μs or 0.06 μs longer than the falling edge times (average time) of the remaining strobe signals.

[0220] In other words, it can be seen that the difference between the falling edge time of the strobe signal output from the fourth output buffer circuit and the falling edge times of the remaining strobe signals is very small.

[0221] In summary, when the stage circuit of the second embodiment is implemented as a buffer circuit, the output improvement rate of the first output buffer circuit can be 92.86%, and the output improvement rate of the last output buffer circuit can be 62.39%.

[0222] When the stage circuit of the second embodiment is implemented as a capacitor circuit, the output improvement rate of the first output buffer circuit can be 82.14%, and the output improvement rate of the last output buffer circuit can be 60.87%.

[0223] As described above, in the stage circuit of the second embodiment, compared with the output of the stage circuit of the first embodiment, the outputs of the first output buffer circuit and the last output buffer circuit are significantly improved so that the image quality of the display device does not deteriorate due to output deviation.

[0224] In addition, in the stage circuit according to the second embodiment, the number of the first output improvement circuit 630 and the second output improvement circuit 640 can be adjusted according to the length of the high voltage level of the clock signal.

[0225] In other words, when the length of the high voltage level of the clock signal corresponds to M horizontal periods (where M is a natural number greater than or equal to 2), the stage circuit may include M - 1 first output improvement circuits and M - 1 second output improvement circuits.

[0226] For example, when the stage circuit Figure 17 as shown includes one first output improvement circuit 630 and one second output improvement circuit 640, as Figure 18 shown, the length of the high voltage level of the clock signal may be two horizontal periods 2H, and the stage circuit may perform 1H overlapping driving.

[0227] Before the strobe signal of the first output buffer circuit is output, the stage circuit may enhance the voltage Q of the Q node as the first node once. After the strobe signal of the last output buffer circuit is output, the voltage Q of the first node may be attenuated once. In Figure 18 it, the waveform of the voltage Q of the first node is a waveform that does not include the step of pre - charging the voltage of the first node.

[0228] As another example, when the stage circuit Figure 19 as shown includes two first output improvement circuits 630 and two second output improvement circuits 640, as Figure 20 shown, the length of the high voltage level of the clock signal is three horizontal periods 3H, and the stage circuit may perform 2H overlapping driving.

[0229] Before the strobe signal of the first output buffer circuit is output, the stage circuit may enhance the voltage Q of the Q node as the first node twice. After the strobe signal of the last output buffer circuit is output, the voltage Q of the Q node may be attenuated twice. In Figure 20 it, the waveform of the voltage Q of the first node is a waveform that does not include the step of pre - charging the voltage of the first node.

[0230] As another example, when the stage circuit Figure 21 as shown includes three first output improvement circuits 630 and three second output improvement circuits 640, as Figure 22 shown, the length of the high voltage level of the clock signal is four horizontal periods 4H, and the stage circuit may perform 3H overlapping driving.

[0231] Before the strobe signal of the first output buffer circuit is output, the stage circuit may enhance the voltage Q of the Q node as the first node three times. After the strobe signal of the last output buffer circuit is output, the voltage Q of the Q node may be attenuated three times. In Figure 22Among them, the waveform of the voltage Q of the first node is a waveform that does not include the step of pre-charging the voltage of the first node.

[0232] As described above, in the second embodiment, the stage circuit can enhance or attenuate the voltage of the Q node as the first node according to the number of horizontal periods of the overlapping drive.

[0233] Therefore, the output deviation between the first output buffer circuit and the last output buffer circuit can be improved.

[0234] The objects to be achieved by the present disclosure, the means for achieving these objects, and the effects of the present disclosure do not specify the basic features of the claims. Therefore, the scope of the claims is not limited to the disclosure of the present disclosure.

[0235] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto. Without departing from the technical concept of the present disclosure, it can be specifically implemented in many different forms. Therefore, the embodiments disclosed in the present disclosure are provided only for illustrative purposes and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure. The protection scope of the present disclosure should be interpreted based on the following claims, and all technical concepts within the equivalent scope should be interpreted as falling within the scope of the present disclosure.

[0236] Cross-reference to related applications

[0237] This application claims the priority and benefits of Korean Patent Application No. 10-2023-0197411, filed on December 29, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A gate drive circuit, the gate drive circuit comprising: at least one stage circuit configured to supply a gate signal to a plurality of gate lines and including a first node, Wherein, the at least one stage circuit comprises: N output buffer circuits configured to sequentially output pulses of the selection signal in response to pulses of a corresponding clock signal while the first node is in a precharge state, wherein N is a natural number greater than or equal to 2; and An output improvement circuit is configured to improve an output deviation of a first output buffer circuit outputting a first strobe signal among the N output buffer circuits and to improve an output deviation of an Nth output buffer circuit outputting a last strobe signal among the N output buffer circuits.

2. The gate drive circuit according to claim 1, wherein: The output improvement circuit comprises: a first output improvement circuit configured to enhance a voltage of the first node in response to a previous clock signal having an earlier phase than a clock signal input to the first output buffer circuit; and A second output improvement circuit is configured to attenuate a voltage of the first node in response to a next clock signal having a later phase than the clock signal input to the Nth output buffer circuit.

3. The gate drive circuit according to claim 2, wherein: The first output improvement circuit enhances the voltage of the first node through the rising edge of the previous clock signal before the first output buffer circuit outputs the first selection signal, and the second output improvement circuit attenuates the voltage of the first node through the falling edge of the next clock signal after the Nth output buffer circuit outputs the first selection signal.

4. The gate drive circuit according to claim 2, wherein: The first output improvement circuit includes: a first transistor, which includes a gate terminal to which the voltage of the first node is applied, a first terminal to which the previous clock signal is input, and a second terminal to which the previous clock signal is output; and a first capacitor, which is connected to the gate terminal and the second terminal to enhance the voltage of the first node.

5. The gate drive circuit according to claim 2, wherein: The second output improvement circuit includes: a second transistor, which includes a gate terminal to which the voltage of the first node is applied, a first terminal for inputting the next clock signal, and a second terminal for outputting the next clock signal; and a second capacitor, which is connected to the gate terminal and the second terminal to attenuate the voltage of the first node.

6. The gate drive circuit according to claim 2, wherein: The first output improving circuit includes a first capacitor, one end of which is connected to the first node, and the other end of which is connected to a clock line to which the previous clock signal is input.

7. The gate drive circuit according to claim 2, wherein: The second output improving circuit includes a second capacitor, one end of which is connected to the first node, and the other end of which is connected to a clock line to which the next clock signal is input.

8. The gate drive circuit according to claim 2, wherein: When the length of the high voltage level of the clock signal corresponds to M horizontal periods, the stage circuit includes M-1 first output improving circuits and M-1 second output improving circuits, where M is a natural number greater than or equal to 2.

9. A gate drive circuit, the gate drive circuit comprising: a first-stage circuit, a second-stage circuit, and a third-stage circuit, wherein the first-stage circuit, the second-stage circuit, and the third-stage circuit are configured to supply a gating signal to a plurality of gating lines and include a first node, Wherein, the second stage circuit comprises: a first output buffer circuit to an N-th output buffer circuit, the first output buffer circuit to the N-th output buffer circuit being configured to sequentially output pulses of a strobe signal in response to a pulse of a corresponding clock signal while the first node is in a precharge state, wherein N is a natural number greater than or equal to 2; and An output improvement circuit is configured to improve an output deviation of the first output buffer circuit and an output deviation of the Nth output buffer circuit.

10. The gate drive circuit according to claim 9, wherein: The output improvement circuit comprises: a first output improving circuit configured to enhance the voltage of the first node in response to a previous stage gating signal, the previous stage gating signal being a gating signal output from a last output buffer circuit of the first stage circuit; and A second output improvement circuit is configured to attenuate the voltage of the first node in response to a next-stage gating signal, the next-stage gating signal being a gating signal output from the first output buffer circuit of the third-stage circuit.

11. The gate driving circuit according to claim 10, wherein: The first output improvement circuit enhances the voltage of the first node through the rising edge of the previous stage selection signal before the first output buffer circuit outputs the selection signal, and the second output improvement circuit attenuates the voltage of the first node through the falling edge of the next stage selection signal after the Nth output buffer circuit outputs the selection signal.

12. The gate drive circuit according to claim 10, wherein: The first output improvement circuit includes: a first transistor, which includes a gate terminal to which the voltage of the first node is applied, a first terminal to which the previous stage selection signal is input, and a second terminal to which the previous stage selection signal is output; and a first capacitor, which is connected to the gate terminal and the second terminal to enhance the voltage of the first node.

13. The gate driving circuit according to claim 10, wherein: The second output improvement circuit includes: a second transistor, which includes a gate terminal to which the voltage of the first node is applied, a first terminal for inputting the next-level selection signal, and a second terminal for outputting the next-level selection signal; and a second capacitor, which is connected to the gate terminal and the second terminal to attenuate the voltage of the first node.

14. The gate driving circuit according to claim 10, wherein: The first output improvement circuit includes a first capacitor, one end of which is connected to the first node, and the other end of which is connected to a signal line to which the previous stage gating signal is input.

15. The gate driving circuit according to claim 10, wherein: The second output improvement circuit includes a second capacitor, one end of which is connected to the first node, and the other end of which is connected to a signal line for inputting the next stage gating signal.

16. A display device, comprising: A display panel, the display panel comprising a plurality of pixel circuits, wherein the plurality of pixel circuits are connected to corresponding data lines and gate lines; a data driving circuit configured to output a data signal applied to one of the data lines; a gate driving circuit configured to receive a clock signal and supply a gate signal to one of the gate lines; and a timing controller configured to control driving of the data driving circuit and the gate driving circuit, and Wherein, the gate drive circuit is configured as follows: A gate signal is supplied to the gate line, and includes a first-stage circuit, a second-stage circuit, and a third-stage circuit, wherein the first-stage circuit, the second-stage circuit, and the third-stage circuit include a first node, The second stage circuit comprises: a first output buffer circuit to an N-th output buffer circuit, the first output buffer circuit to the N-th output buffer circuit being configured to sequentially output pulses of the selection signal using pulses of a corresponding clock signal while the first node is in a precharge state, wherein N is a natural number greater than or equal to 2; and An output improvement circuit is configured to improve an output deviation of the first output buffer circuit and an output deviation of the Nth output buffer circuit.

17. The display device according to claim 16, wherein: The output improvement circuit comprises: a first output improvement circuit configured to enhance a voltage of the first node before a strobe signal is output from the first output buffer circuit; and A second output improvement circuit is configured to attenuate a voltage of the first node after the strobe signal is output from the Nth output buffer circuit.

18. The display device according to claim 17, wherein: The first output improvement circuit enhances the voltage of the first node in response to a pulse of a previous clock signal having a phase earlier than that of a clock signal input to the first output buffer circuit, and The second output improving circuit attenuates the voltage of the first node in response to a pulse of a next clock signal having a later phase than a clock signal input to the Nth output buffer circuit.

19. The display device according to claim 18, wherein: The first output improvement circuit enhances the voltage of the first node by a rising edge of the previous clock signal, and the second output improvement circuit attenuates the voltage of the first node by a falling edge of the next clock signal.

20. The display device according to claim 17, wherein: The first output improvement circuit enhances the voltage of the first node in response to a pulse of a previous stage gating signal, the previous stage gating signal being a gating signal output from a last output buffer circuit of the first stage circuit, and The second output improving circuit attenuates the voltage of the first node in response to a pulse of a next-stage gating signal, the next-stage gating signal being a gating signal output from the first output buffer circuit of the third-stage circuit.

21. The display device according to claim 20, wherein: The first output improvement circuit enhances the voltage of the first node by a rising edge of the previous stage selection signal, and the second output improvement circuit attenuates the voltage of the first node by a falling edge of the next stage selection signal.

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