Display driving circuit, driving method thereof and display panel

Abstract

The invention discloses a display driving circuit, a driving method thereof and a display panel, and the display driving circuit comprises an Nth row of pixel capacitors, wherein N is a positive integer; the (N + 1) th row of pixel capacitors are cascaded with the Nth row of pixel capacitors; the switching control circuit is connected with the Nth row of pixel capacitors and the (N + 1) th row of pixel capacitors and is used for realizing switching between a first display mode and a second display mode; wherein in the first display mode, data signals input to the Nth row of pixel capacitors and the (N + 1) th row of pixel capacitors are written line by line; and in a second display mode, data signals input to the Nth row of pixel capacitors and the (N + 1) th row of pixel capacitors are simultaneously written in. Through the circuit, the switching between the first display mode and the second display mode is realized, and the display switching power consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the field of display panels, and particularly to a display driving circuit, a driving method thereof, and a display panel. Background Art

[0002] With the continuous development of TFT display technology, the market demand for higher refresh rate applications will be increasing, especially in the field of game displays. Some e-sports players will highly favor high-refresh-rate displays, which can make games smoother. However, at the same time, as the refresh rate increases, the power consumption will also become higher. To solve the problem of high power consumption in high-refresh scenarios, on the basis of some existing display technologies in the current industry, such as Normal (conventional display mode), a frequency doubling display technology has been introduced. The frequency doubling display technology includes DLG (Dual Line Gate, dual-line gate technology) and HSR (Hardware Super Resolution, hardware super resolution). The DLG technology changes the original progressive scanning method to scanning two lines at a time, that is, two Gates are opened simultaneously, and the same data is output for two Source lines (the content of the two lines is the same), thereby doubling the pixel charging time and doubling the refresh rate. The HSR technology is also a kind of frequency doubling technology, mainly achieving differential display through timing adjustment, that is, in each frame of image, only the pixels of odd rows or even rows are rendered, and the other row is displayed by fusing the information of adjacent two rows.

[0003] Taking a UHD (Ultra High Definition, ultra-high definition) 3840*2160 resolution 240Hz refresh rate product as an example, the frequency doubling display technology reduces the display resolution to half of the original, that is, the same data is displayed for the pixels of two rows, and the refresh rate will rise to 480Hz, which is twice the original, but the total data transmission rate remains unchanged.

[0004] Although this solution reduces the total amount of data logic by half, the two rows of the same data still need to be sent out twice, so there is still room for power consumption reduction. Summary of the Invention

[0005] The main technical problem to be solved by this application is to provide a display driving circuit, a driving method thereof, and a display panel, which can realize the switching between the first display mode and the second display mode, reduce the power consumption of DLG display switching, and specifically reduce the power consumption in the DLG display mode.

[0006] To solve the above problems, the present application provides a display driving circuit in a first aspect. Wherein, the display driving circuit includes: the Nth row of pixel capacitors, where N is a positive integer; the (N + 1)th row of pixel capacitors cascaded with the Nth row of pixel capacitors; a switching control circuit connected to the Nth row of pixel capacitors and the (N + 1)th row of pixel capacitors for switching between a first display mode and a second display mode. Wherein, in the first display mode, data signals input to the Nth row of pixel capacitors and the (N + 1)th row of pixel capacitors are written row by row; in the second display mode, data signals input to the Nth row of pixel capacitors and the (N + 1)th row of pixel capacitors are written simultaneously.

[0007] Wherein, the switching control circuit is used to switch the polarity of the Nth row of pixel capacitors or the (N + 1)th row of pixel capacitors, thereby realizing the switching between the first display mode and the second display mode.

[0008] Wherein, the first electrode plate of the Nth row of pixel capacitors is connected to the Nth row of data lines and the common electrode line through the switching control circuit, and the second electrode plate of the Nth row of pixel capacitors is connected to the common electrode line; the first electrode plate of the (N + 1)th row of pixel capacitors is connected to the (N + 1)th row of data lines and the second electrode plate of the Nth row of pixel capacitors through the switching control circuit, and the second electrode plate of the (N + 1)th row of pixel capacitors is connected to the common electrode line.

[0009] Wherein, the switching control circuit includes: a first switch unit disposed between the first electrode plate of the Nth row of pixel capacitors and the common electrode line for controlling the common electrode line to charge the first electrode plate of the Nth row of pixel capacitors with a common voltage in the second display mode; a second switch unit disposed between the second electrode plate of the Nth row of pixel capacitors, the first electrode plate of the (N + 1)th row of pixel capacitors and the (N + 1)th row of data lines for controlling the (N + 1)th row of data lines to charge the second electrode plate of the Nth row of pixel capacitors with the same data voltage as the (N + 1)th row of pixel capacitors in the second display mode.

[0010] Wherein, the switching control circuit further includes: a control unit connected to the control terminals of the first switch unit and the second switch unit for controlling the on / off of the first switch unit and the second switch unit.

[0011] Wherein, the control unit is disposed between the (N + 1)-th row data line and the control ends of the first switch unit and the second switch unit. The control end of the control unit is connected to a switching signal line, the first path end is connected to the (N + 1)-th row data line, and the second path end is connected to the control ends of the first switch unit and the second switch unit, and is configured to control the on / off states of the first switch unit and the second switch unit according to the switching signal on the switching signal line and the data signal on the (N + 1)-th row data line.

[0012] Wherein, the display driving circuit further includes: data writing transistors; the N-th row data writing transistor is disposed between the first electrode plate of the N-th row pixel capacitor and the N-th row data line, and is configured to control the N-th row data line to write a data signal to the first electrode plate of the N-th row pixel capacitor; the (N + 1)-th row data writing transistor is disposed between the first electrode plate of the (N + 1)-th row pixel capacitor and the (N + 1)-th row data line, and is configured to control the (N + 1)-th row data line to write a data signal to the first electrode plate of the (N + 1)-th row pixel capacitor.

[0013] Wherein, the control end of the N-th row data writing transistor is connected to the N-th row scanning line, and is configured to control the N-th row data line to write a data signal to the first electrode plate of the N-th row pixel capacitor according to the scanning signal on the N-th row scanning line; the control end of the (N + 1)-th row data writing transistor is connected to the (N + 1)-th row scanning line, and is configured to control the (N + 1)-th row data line to write a data signal to the first electrode plate of the (N + 1)-th row pixel capacitor according to the scanning signal on the (N + 1)-th row scanning line.

[0014] To solve the above problems, in a second aspect, the present application provides a driving method for a display driving circuit. Wherein, the driving method for the display driving circuit includes: in a first display mode, writing data voltages to each row of pixel capacitors in sequence to cause each row of pixels to be displayed in sequence; in a second display mode, writing the same data voltage to every two rows of pixel capacitors through a switching control circuit to cause adjacent two rows of pixels to be displayed simultaneously.

[0015] To solve the above problems, in a third aspect, the present application provides a display panel, wherein the display panel includes the display driving circuit according to any one of the embodiments in the first aspect.

[0016] The beneficial effect of the present application is that: by cascading the pixel capacitors of adjacent two rows through a switching control circuit, the switching of the display polarity signal and the display data of one of the pixels in the adjacent two rows of pixels can be realized, and further the switching between the first display mode and the second display mode of the entire display panel can be realized. Description of the Drawings

[0017] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0018] Figure 1 Schematic diagram of the structure of an embodiment of the display driving circuit provided by the present application; Figure 2 Timing diagram of an embodiment of the first display mode provided by the present application; Figure 3 Timing diagram of an embodiment of the second display mode provided by the present application; Figure 4 Schematic diagram of the structure of the first specific embodiment of the display driving circuit provided by the present application; Figure 5 Schematic diagram of the structure of the second specific embodiment of the display driving circuit provided by the present application; Figure 6 Schematic diagram of the structure of the third specific embodiment of the display driving circuit provided by the present application; Figure 7 Schematic diagram of the structure of the fourth specific embodiment of the display driving circuit provided by the present application; Figure 8 Schematic diagram of the structure of the fifth specific embodiment of the display driving circuit provided by the present application; Figure 9 Schematic diagram of the circuit structure of a specific embodiment of the display driving circuit provided by the present application; Figure 10 Driving timing diagram of a specific embodiment of the display driving circuit provided by the present application; Figure 11 Circuit diagram of the first driving stage of the display driving circuit provided by the present application in the first display mode; Figure 12 Circuit diagram of the second driving stage of the display driving circuit provided by the present application in the first display mode; Figure 13 Circuit diagram of the third driving stage of the display driving circuit provided by the present application in the first display mode; Figure 14 Circuit diagram of the first driving stage of the display driving circuit provided by the present application in the second display mode; Figure 15 Circuit diagram of the second driving stage of the display driving circuit provided by the present application in the second display mode; Figure 16 Circuit diagram of the third driving stage of the display driving circuit provided by the present application in the second display mode.

[0019] Symbol description: The pixel capacitor Cst(n) of the Nth row; the pixel capacitor Cst(n+1) of the (N+1)th row; the switching control circuit 11; the data line Data(n) of the Nth row; the data line Data(n+1) of the (N+1)th row; the common electrode line COM; the scan line Scan(n) of the Nth row; the scan line Scan(n+1) of the (N+1)th row; the first switch unit 111; the second switch unit 112; the third switch unit 113; the control unit 110; the switching signal line DLG; the data writing transistor T(n) of the Nth row; the data writing transistor T(n+1) of the (N+1)th row; the common electrode transistor Q(n) of the Nth row; the common electrode transistor Q(n+1) of the (N+1)th row; the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4. Detailed implementation manners

[0020] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0021] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "the" and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless clearly indicated otherwise in the foregoing. "Plurality" generally includes at least two, but does not exclude the case of including at least one.

[0022] It should be understood that the term " / and" used herein is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after. The terms "first", "second", etc. in the description and claims of the present application and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0023] It should be understood that the terms "including", "comprising" or any other variation used herein are intended to cover non-exclusive inclusion, such that a process, method, article or apparatus comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

[0024] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of the present application, then such directional indications are only used to explain the relative positional relationship, movement conditions, etc. between components in a specific posture (as shown in the drawings). If this specific posture changes, then the directional indications will also change accordingly.

[0025] The mention of "embodiment" in this document means that the specific features, structures or characteristics described in connection with the embodiment may be included in at least one embodiment of the present application. The appearance of this phrase at each position in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.

[0026] The present application provides a display driving circuit, the display driving circuit includes: pixel capacitors cascaded between adjacent two rows and a switching control circuit for controlling the display switching of pixel capacitors between adjacent two rows. For details, please refer to Figure 1 , Figure 1 is a schematic structural diagram of an embodiment of the display driving circuit provided by the present application. Taking the Nth row of pixels and the (N + 1)th row of pixels as an example for illustration. As Figure 1 shown, the display driving circuit includes a connected Nth row pixel capacitor Cst(n) and an (N + 1)th row pixel capacitor Cst(n + 1). Among them, the Nth row pixel capacitor Cst(n) is the capacitor in the Nth row of pixels, and the (N + 1)th row pixel capacitor Cst(n) is the capacitor in the (N + 1)th row of pixels. It should be noted that in the pixel circuit, the storage capacitor and the liquid crystal capacitor are in parallel, and the storage capacitor and the liquid crystal capacitor together constitute the pixel capacitor Cst.

[0027] In this embodiment, the display driving circuit further includes a switching control circuit 11, and the switching control circuit 11 is connected to the Nth row pixel capacitor Cst(n) and the (N + 1)th row pixel capacitor Cst(n + 1) for realizing the switching between the first display mode and the second display mode.

[0028] In the first display mode, the switching control circuit 11 controls the data signals input to the pixel capacitors Cst(n) of the Nth row and the pixel capacitors Cst(n + 1) of the (N + 1)th row to be written row by row. In the second display mode, the switching control circuit 11 controls the data signals input to the pixel capacitors Cst(n) of the Nth row and the pixel capacitors Cst(n + 1) of the (N + 1)th row to be written simultaneously, and the polarities of the data signals written to the pixel capacitors Cst(n) of the Nth row and the pixel capacitors Cst(n + 1) of the (N + 1)th row are opposite.

[0029] Specifically, the switching control circuit 11 is used to implement the polarity switching of the pixel capacitors Cst(n) of the Nth row or the pixel capacitors Cst(n + 1) of the (N + 1)th row, so as to realize the switching between the first display mode and the second display mode.

[0030] It should be noted that the first display mode is the normal mode, that is, progressive scanning display. For details, please refer to Figure 2 , Figure 2 which is the timing diagram of an embodiment of the first display mode provided by this application. Among them, STV is the start scanning signal, G1 is the scanning signal of the pixel unit of the first row, G2 is the scanning signal of the pixel unit of the second row, and so on. In the first display mode, the scanning signal controls each row of pixel units to be opened row by row, so as to realize charging the data signal into each row of pixel capacitors Cst(n) row by row, so as to realize progressive scanning and progressive display.

[0031] The second display mode is the DLG mode. For details, please refer to Figure 3 , Figure 3 which is the timing diagram of an embodiment of the second display mode provided by this application. As Figure 3 shown, in the second display mode, every two rows of pixel units are opened simultaneously, and the same data is charged into every two rows of pixel units, so that the display brightness of every two rows of pixel units is the same. The second display mode can reduce the display resolution to half of the original and double the refresh rate. For example, in the first display mode, the refresh rate of the display panel is 240 Hz, and in the second display mode, the refresh rate of the display panel will rise to 480 Hz, which is twice the original, but the total data transmission rate remains unchanged.

[0032] Specifically, the first electrode of the pixel capacitor Cst(n) of the Nth row is connected to the data line Data(n) of the Nth row and the common electrode line COM through the switching control circuit 11, and the second electrode of the pixel capacitor Cst(n) of the Nth row is connected to the common electrode line COM.

[0033] The first electrode plate of the pixel capacitor Cst(n+1) in the (N+1)-th row is connected to the data line Data(n+1) in the (N+1)-th row and, through the switching control circuit 11, to the second electrode plate of the pixel capacitor Cst(n) in the N-th row. The second electrode plate of the pixel capacitor Cst(n+1) in the (N+1)-th row is connected to the common electrode line COM.

[0034] For details, please further refer to Figure 4 , Figure 4 which is a schematic structural diagram of the first specific embodiment of the display driving circuit provided by this application. As Figure 4 shown, the switching control circuit 11 includes a first switching unit 111 and a second switching unit 112. Specifically, the first switching unit 111 is disposed between the second electrode plate of the pixel capacitor Cst(n) in the N-th row and the first electrode plate of the pixel capacitor Cst(n+1) in the (N+1)-th row. Since the first electrode plate of the pixel capacitor Cst(n+1) in the (N+1)-th row is also connected to the data line Data(n+1) in the (N+1)-th row, therefore, the first switching unit 111 is also disposed between the second electrode plate of the pixel capacitor Cst(n) in the N-th row and the data line Data(n+1) in the (N+1)-th row. The first switching unit 111 is used to control the data line Data(n+1) in the (N+1)-th row to charge the data signal into the second electrode plate of the pixel capacitor Cst(n) in the N-th row, or to control the data signal stored in the first electrode plate of the pixel capacitor Cst(n+1) in the (N+1)-th row to be charged into the second electrode plate of the pixel capacitor Cst(n) in the N-th row. It should be noted that the data line Data(n+1) in the (N+1)-th row can first charge the data voltage into the first electrode plate of the pixel capacitor Cst(n+1) in the (N+1)-th row, and then the data signal stored in the first electrode plate of the pixel capacitor Cst(n+1) in the (N+1)-th row is charged into the second electrode plate of the pixel capacitor Cst(n) in the N-th row. It can be charged simultaneously or successively, and this is not limited herein.

[0035] The second switching unit 112 is disposed between the first electrode plate of the pixel capacitor Cst(n) in the N-th row and the common electrode line COM, and is used to control the common electrode line COM to charge the common voltage Vcom into the first electrode plate of the pixel capacitor Cst(n) in the N-th row in the second display mode.

[0036] Furthermore, the switching control circuit 11 further includes a third switching unit 113. The third switching unit 113 is disposed between the second electrode plate of the pixel capacitor Cst(n) in the N-th row and the common electrode line COM, and is used to control the common electrode line COM to charge the common voltage Vcom into the second electrode plate of the pixel capacitor in the N-th row in the first display mode and the second display mode. For details, please refer to Figure 5 , Figure 5Schematic diagram of the second specific embodiment of the display driving circuit provided by the present application. In this embodiment, when the first switch unit 111 and the second switch unit 112 are operating, the third switch unit 113 is not operating; when the first switch unit 111 and the second switch unit 112 are not operating, the third switch unit 113 is operating; "operating" means that the transistors in the unit are conducting. In a specific embodiment, the driving characteristics of the transistors in the first switch unit 111 and the second switch unit 112 are opposite to those of the third switch unit 113. Specifically, the transistors in the first switch unit 111 and the second switch unit 112 are Pmos transistors, and the transistors in the third switch unit 113 are Nmos transistors. In other embodiments, the transistors in the first switch unit 111 and the second switch unit 112 are Nmos transistors, and the transistors in the third switch unit 113 are Pmos transistors, which are not specifically limited herein, and the level signals on the corresponding scan lines are also opposite.

[0037] Further, the switching control circuit 11 further includes a control unit 110. The control unit 110 is connected to the control terminals of the first switch unit 111 and the second switch unit 112, and is used to control the first switch unit 111 and the second switch unit 112 to operate to achieve the switching of the display mode. For details, please refer to Figure 6 , Figure 6 Schematic diagram of the third specific embodiment of the display driving circuit provided by the present application. As Figure 6 shown, the switching control circuit 11 includes a control unit 110. The control unit 110 is disposed between the (N + 1)-th row scan line Scan(n + 1) and the control terminals of the first switch unit 111 and the second switch unit 112. Specifically, the control terminal of the control unit 110 is connected to the switching signal line DLG, the first path terminal is connected to the (N + 1)-th row scan line Scan(n + 1), and the second path terminal is connected to the control terminals of the first switch unit 111 and the second switch unit 112, and is used to control the on / off of the first switch unit 111 and the second switch unit 112 according to the switching signal on the switching signal line DLG and the scan signal on the (N + 1)-th row scan line Scan(n + 1). Among them, the switching signal and the scan signal refer to high / low levels. It should be noted that the first path terminal can also be referred to as the input terminal, the second path terminal can also be referred to as the output terminal, specifically the source / drain of the transistor, and the control terminal is also the gate of the transistor.

[0038] In this preferred embodiment, the control terminal of the third switching unit 113 is connected to the (N + 1)-th row scanning line Scan(n + 1), so that the third switching unit 113 is always in an on state during the non-scanning phase of the pixels in the (N + 1)-th row (i.e., when Scan(n + 1) is at a low potential), thereby controlling the writing of the common voltage on the second electrode plate of the pixel capacitor Cst(n) in the N-th row. In other embodiments, the control terminal of the third switching unit 113 can also be connected to the control unit 110, and the switching signal on the switching signal line DLG connected to the control terminal of the control unit 110 is a jump signal, which can be specifically designed according to actual situations.

[0039] In a preferred embodiment, the display driving circuit further includes a data writing transistor. Among them, each row of pixels includes a data writing transistor. For details, please refer to Figure 7 , Figure 7 which is a schematic structural diagram of the fourth specific embodiment of the display driving circuit provided by this application. The N-th row of pixels includes the N-th row data writing transistor T(n), and the (N + 1)-th row of pixels includes the N-th row data writing transistor T(n + 1). Among them, the gate of the data writing transistor is connected to the scanning line, the source is connected to the data line, and the drain is connected to the pixel capacitor. Specifically, the gate of the data writing transistor in each row is connected to the scanning line in each row, the source is connected to the data line in each row, and the drain is connected to the pixel capacitor in each row.

[0040] Specifically, the N-th row data writing transistor T(n) is disposed between the first electrode plate of the N-th row pixel capacitor Cst(n) and the N-th row data line Data(n). The control terminal of the N-th row data writing transistor T(n) is connected to the N-th row scanning line Scan(n), the input terminal is connected to the N-th row data line Data(n), and the output terminal is connected to the first electrode plate of the N-th row pixel capacitor Cst(n), and is used to control the writing of the data signal Vdata from the N-th row data line Data(n) to the first electrode plate of the N-th row pixel capacitor Cst(n).

[0041] The (N + 1)-th row data writing transistor T(n + 1) is disposed between the first electrode plate of the (N + 1)-th row pixel capacitor Cst(n + 1) and the (N + 1)-th row data line Data(n + 1). The control terminal of the (N + 1)-th row data writing transistor T(n + 1) is connected to the (N + 1)-th row scanning line Scan(n + 1), the input terminal is connected to the (N + 1)-th row data line Data(n + 1), and the output terminal is connected to the first electrode plate of the (N + 1)-th row pixel capacitor Cst(n + 1), and is used to control the writing of the data signal Vdata from the (N + 1)-th row data line Data(n + 1) to the first electrode plate of the (N + 1)-th row pixel capacitor Cst(n + 1).

[0042] It should be noted that the present application may also not be provided with data writing transistors, and the signals on the data line Data are controlled by a driver (IC) to be transmitted in sequence according to the timing, and then the data voltages are written in sequence, which is not limited herein.

[0043] In another preferred embodiment, the display driving circuit further includes common electrode transistors. Figure 8 It is a schematic structural diagram of the fifth specific embodiment of the display driving circuit provided by the present application. As Figure 8 shown, each row of common electrode transistors is arranged between the second electrode plates of each row of pixel capacitors and each row of data lines, and is used to control the writing of the common voltage of the pixel capacitors. Among them, the gates of each row of common electrode transistors are connected to the next row of scanning signals, and the driving characteristics of the common electrode transistors are opposite to those of the data writing transistors, so that there is a simultaneous conduction timing between the common electrode transistors and the data writing transistors, so that data voltages and common voltages can be written into the storage capacitors in the first display mode.

[0044] Specifically, the Nth row of common electrode transistors Q(n) is arranged between the second electrode plate of the Nth row of pixel capacitors Cst(n) and the common electrode line COM. The gate of the Nth row of common electrode transistors Q(n) is connected to the (N + 1)th row of scanning lines Scan(n + 1). The first path end is connected to the common electrode line COM, and the second path end is connected to the second electrode plate of the Nth row of pixel capacitors Cst(n), and is used to control the common electrode line COM to write the common voltage Vcom to the second electrode plate of the Nth row of pixel capacitors Cst(n); The (N + 1)th row of common electrode transistors Q(n + 1) is arranged between the second electrode plate of the (N + 1)th row of pixel capacitors Cst(n + 1) and the common electrode line COM. The gate of the (N + 1)th row of common electrode transistors Q(n + 1) is connected to the (N + 2)th row of scanning lines Scan(n + 2). The first path end is connected to the common electrode line COM, and the second path end is connected to the second electrode plate of the (N + 1)th row of pixel capacitors Cst(n + 1), and is used to control the common electrode line COM to write the common voltage Vcom to the second electrode plate of the (N + 1)th row of pixel capacitors Cst(n + 1).

[0045] It should be noted that the third switch unit 113 in the fourth specific embodiment is equivalent to the Nth row common electrode transistor Q(n) in the fifth embodiment, and the fourth specific embodiment omits the (N + 1)th row common electrode transistor Q(n + 1) compared with the fifth specific embodiment. The fifth specific embodiment can be a solution for realizing display mode switching by adding a first switch unit 111, a second switch unit 112, and a control unit 110 to two adjacent pixel units in the basic pixel unit. Among them, in the basic pixel unit, each row of pixel units includes a data writing transistor and a common electrode transistor to control the writing of the display signal on the pixel capacitor through the data writing transistor and the common electrode transistor, and further control the display of the pixel.

[0046] The present application also provides a schematic circuit diagram of a display driving circuit. Specifically, please refer to Figure 9 , Figure 9 which is a schematic circuit diagram of a specific embodiment of the display driving circuit provided by the present application. As Figure 9 shown.

[0047] The first switch unit 111 includes a first transistor Q1; the second switch unit 112 includes a second transistor Q2; the third switch unit 113 includes a third transistor Q3; the control unit 110 includes a fourth transistor Q4.

[0048] Please refer to Figure 10 , Figure 10 which is a driving timing diagram of a specific embodiment of the display driving circuit provided by the present application. Further, please refer to Figures 11 - 16 , wherein, Figures 11 - 13 is a driving stage circuit diagram of the display driving circuit provided by the present application in the first display mode. Specifically, Figure 11 is the first driving stage circuit diagram of the display driving circuit provided by the present application in the first display mode. Figure 12 is the second driving stage circuit diagram of the display driving circuit provided by the present application in the first display mode. Figure 13 is the third driving stage circuit diagram of the display driving circuit provided by the present application in the first display mode. Figures 14 - 16 is a driving stage circuit diagram of the display driving circuit provided by the present application in the second display mode. Specifically, Figure 14 is the first driving stage circuit diagram of the display driving circuit provided by the present application in the second display mode. Figure 15 is the second driving stage circuit diagram of the display driving circuit provided by the present application in the second display mode. Figure 16 is the third driving stage circuit diagram of the display driving circuit provided by the present application in the second display mode.

[0049] The first display mode includes the Nth row pixel sampling stage, the (N + 1)th row pixel sampling stage, and the holding stage.

[0050] In the Nth row pixel sampling stage of the first display mode, the switching signal line DLG transmits a low potential signal. At this time, the Nth row scan line Scan(n) transmits a high potential, and the (N + 1)th row scan line Scan(n + 1) transmits a low potential. Only the Nth row data writing transistor T(n) and the third transistor Q3 are turned on. The Nth row data line Data(n) charges the Nth row pixel capacitor Cst(n) with a data voltage. The potential of point Q (the first plate of the Nth row pixel capacitor Cst(n)) is Vdata(n). Please refer to Figure 11 .

[0051] In the (N + 1)th row pixel sampling stage of the first display mode, at this time, the Nth row scan line Scan(n) transmits a low potential, and the (N + 1)th row scan line Scan(n + 1) transmits a high potential. Only the Nth row data writing transistor T(n) is turned on. The (N + 1)th row data line Data(n + 1) charges the (N + 1)th row pixel capacitor Cst(n + 1) with a data voltage. The potential of point P (the first plate of the (N + 1)th row pixel capacitor Cst(n + 1)) is Vdata(n + 1). Please refer to Figure 12 .

[0052] In the holding stage of the first display mode, at this time, the scan signals transmitted by the Nth row scan line Scan(n) and the (N + 1)th row scan line Scan(n + 1) are both low potentials. At this time, only the fourth transistor Q4 in the circuit is turned on. The potential of point Q is maintained at Vdata(n), and the potential of point P is maintained at Vdata(n + 1), so as to keep the display panel in a display state. Please refer to Figure 13 .

[0053] The second display mode also includes the Nth row pixel sampling stage, the (N + 1)th row pixel sampling stage, and the holding stage.

[0054] In the Nth row pixel sampling stage of the second display mode, the switching signal line DLG transmits a high potential, and the second transistor Q2 in the circuit is turned on. When entering the sampling stage of the Nth row scan line Scan(n), at this time, the Nth row scan line Scan(n) transmits a high potential, and the (N + 1)th row scan line Scan(n + 1) transmits a low potential. Only the Nth row data writing transistor T(n), the second transistor Q2, and the fourth transistor Q4 are turned on. According to the scheme design, at this time, the Nth row data line Data(n) has no action (that is, no data signal), and neither the Nth row pixel capacitor Cst(n) nor the (N + 1)th row pixel capacitor Cst(n + 1) is charged. Please refer to Figure 14 .

[0055] In the pixel sampling stage of the (N + 1)-th row in the second display mode, when entering the pixel sampling stage of the (N + 1)-th row, at this time, the (N)-th scan line Scan(n) transmits a low potential, and the (N + 1)-th scan line Scan(n + 1) transmits a high potential. At this time, the first transistor Q1, the second transistor Q2, and the data writing transistor T(n + 1) of the (N + 1)-th row are turned on, and the fourth transistor Q4 and the data writing transistor T(n) of the (N)-th row are turned off. At this time, the potential at point Q is Vcom, and the data line Data(n + 1) of the (N + 1)-th row charges point P. At this time, the potentials at point P and the second electrode plate of the pixel capacitor Cst(n) of the (N)-th row are Vdata, and the potential difference between the first electrode plate and the second electrode plate of the pixel capacitor Cst(n) of the (N)-th row is Vcom - Vdata, as Figure 15 shown.

[0056] In the holding stage in the second display mode, when entering the holding stage, at this time, the scan signals transmitted by the (N)-th scan line Scan(n) and the (N + 1)-th scan line Scan(n + 1) are both low potentials. At this time, only the fourth transistor Q4 and the second transistor Q2 are turned on in the circuit, and the potential at point P is Vdata(n + 1). According to the KVL (Kirchhoff's voltage law) formula, at this time, the potential at point Q is VQ = 2 × Vcom - Vdata(n + 1), as Figure 16 . At this time, the potential difference across the liquid crystal of the (N + 1)-th row is Vdata(n + 1) - Vcom, and the potential difference across the liquid crystal of the (N)-th row is Vcom - Vdata(n + 1). By the above circuit, the same data voltage is charged into the pixels of adjacent two rows, and the polarities of the pixels of adjacent two rows are opposite, so as to realize the polarity inversion of the pixels of the (N)-th row, and further realize that the display data of the pixels of adjacent two rows is the same and the display polarities are opposite, so as to achieve the design goal.

[0057] This application also provides a display panel, wherein the display panel includes pixel units arranged in an array, and each row of pixel units includes a pixel capacitor, and the pixel capacitors of adjacent two rows are connected by using the display driving circuit described in any of the above embodiments.

[0058] It should be noted that in the above embodiments, the third transistor Q3 is a Pmos transistor, and the rest are Nmos transistors. Scan is a high-potential pulse with a normal low potential, and VCOM is a common potential. In other embodiments, it may also be that the third transistor Q3 is an Nmos transistor, and the rest are Pmos transistors, and Scan is a low-potential pulse with a normal high potential, which is not limited herein.

[0059] The beneficial effect of the present application is that by cascading the pixel capacitors of adjacent two rows through a switching control circuit, the switching of the display polarity signal and the display data of one of the pixels in adjacent two rows of pixels can be realized, and further the switching between the first display mode and the second display mode of the entire display panel can be realized. Moreover, this display mode switching is automatically achieved through a switching signal line, reducing the power consumption in the second display mode.

[0060] The above are only embodiments of the present application, and thus do not limit the patent scope of the present application. All equivalent structural or equivalent process transformations made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, are equally included in the patent protection scope of the present application.

Claims

1. A display driving circuit, characterized in that, Including: The pixel capacitors of the Nth row; where N is a positive integer; The pixel capacitors of the (N + 1)th row, cascaded with the pixel capacitors of the Nth row; A switching control circuit, connected to the pixel capacitors of the Nth row and the pixel capacitors of the (N + 1)th row, for realizing the switching between the first display mode and the second display mode; Wherein, in the first display mode, the data signals input to the pixel capacitors of the Nth row and the pixel capacitors of the (N + 1)th row are written row by row; In the second display mode, the data signals input to the pixel capacitors of the Nth row and the pixel capacitors of the (N + 1)th row are written simultaneously.

2. The display driving circuit according to claim 1, wherein The switching control circuit is used to realize the polarity switching of the pixel capacitors of the Nth row or the pixel capacitors of the (N + 1)th row, so as to realize the switching between the first display mode and the second display mode.

3. The display driving circuit according to claim 1, wherein The first electrode plate of the pixel capacitors of the Nth row is connected to the data line of the Nth row and the common electrode line through the switching control circuit, and the second electrode plate of the pixel capacitors of the Nth row is connected to the common electrode line; The first electrode plate of the pixel capacitors of the (N + 1)th row is connected to the data line of the (N + 1)th row and the second electrode plate of the pixel capacitors of the Nth row through the switching control circuit, and the second electrode plate of the pixel capacitors of the (N + 1)th row is connected to the common electrode line.

4. The display driving circuit according to claim 3, wherein The switching control circuit includes: A first switch unit, arranged between the second electrode plate of the pixel capacitors of the Nth row, the first electrode plate of the pixel capacitors of the (N + 1)th row and the data line of the (N + 1)th row, for controlling the data line of the (N + 1)th row to charge the second electrode plate of the pixel capacitors of the Nth row with the same data voltage as the pixel capacitors of the (N + 1)th row in the second display mode; A second switch unit, arranged between the first electrode plate of the pixel capacitors of the Nth row and the common electrode line, for controlling the common electrode line to charge the first electrode plate of the pixel capacitors of the Nth row with the common voltage in the second display mode.

5. The display driving circuit according to claim 4, wherein The switching control circuit includes: A third switching transistor, arranged between the second electrode plate of the pixel capacitors of the Nth row and the common electrode line, for controlling the common electrode line to charge the second electrode plate of the pixel capacitors of the Nth row with the common voltage in the first display mode and the second display mode.

6. The display driving circuit according to claim 4, wherein The switching control circuit further includes: A control unit, connected to the control ends of the first switch unit and the second switch unit, for controlling the first switch unit and the second switch unit to work.

7. The display driving circuit according to claim 6, wherein The control unit is disposed between the (N + 1)-th row scanning line and the control ends of the first switching unit and the second switching unit. The control end of the control unit is connected to a switching signal line. The first path end of the control unit is connected to the (N + 1)-th row scanning line. The second path end of the control unit is connected to the control ends of the first switching unit and the second switching unit, and is configured to control the on / off states of the first switching unit and the second switching unit according to a switching signal on the switching signal line and a scanning signal on the (N + 1)-th row scanning line.

8. The display driving circuit according to claim 3, wherein The display driving circuit further includes: a data writing transistor; The N-th row data writing transistor is disposed between the first electrode plate of the N-th row pixel capacitor and the N-th row data line, and is configured to control the N-th row data line to write a data signal to the first electrode plate of the N-th row pixel capacitor. The (N + 1)-th row data writing transistor is disposed between the first electrode plate of the (N + 1)-th row pixel capacitor and the (N + 1)-th row data line, and is configured to control the (N + 1)-th row data line to write a data signal to the first electrode plate of the (N + 1)-th row pixel capacitor.

9. The display driving circuit according to claim 8, wherein The control end of the N-th row data writing transistor is connected to the N-th row scanning line, and is configured to control the N-th row data line to write a data signal to the first electrode plate of the N-th row pixel capacitor according to a scanning signal on the N-th row scanning line. The control end of the (N + 1)-th row data writing transistor is connected to the (N + 1)-th row scanning line, and is configured to control the (N + 1)-th row data line to write a data signal to the first electrode plate of the (N + 1)-th row pixel capacitor according to a scanning signal on the (N + 1)-th row scanning line.

10. A driving method for a display driving circuit according to any one of claims 1 to 9, characterized in that, The driving method of the display driving circuit includes: In a first display mode, the display driving circuit sequentially writes data voltages to each row of pixel capacitors, so that each row of pixels is sequentially displayed. In a second display mode, the display driving circuit writes the same data voltage to every two rows of pixel capacitors through a switching control circuit, so that adjacent two rows of pixels are simultaneously displayed.

11. A display panel, characterized in that, The display panel includes the display driving circuit according to any one of claims 1 to 9.

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