Gate driver and display device including same

Abstract

A gate driver according to an embodiment of the present disclosure may include: a plurality of dependently connected stages; and at least one of gate input circuits configured to selectively output one of a first start pulse corresponding to a high-frequency operation and a second start pulse corresponding to a low-frequency operation, in which at least one of the plurality of stages is connected to the gate input circuits, and at least one of the gate input circuits is configured to selectively output one of a first start pulse corresponding to the high-frequency operation and a second start pulse corresponding to the low-frequency operation. And receive one of the first start pulse and the second start pulse output by the gate input circuit.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0195513, filed with the Korean Intellectual Property Office on December 28, 2023, the disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a gate driver and a display device including the gate driver.

[0004] Description of related art

[0005] With the advent of the information age, the display field for visually expressing electrical information signals has developed rapidly. Accordingly, various display devices having a thin thickness, a light weight, and excellent properties such as low power consumption have been developed. Examples of display devices may include a liquid crystal display (LCD) device, an organic light - emitting display (OLED) device, and the like.

[0006] A display device may include driving circuits such as a data driver, a gate driver, and a timing controller. The data driver is configured to supply data signals to a display panel having a pixel array for displaying an image thereon and data lines provided on the display panel. The gate driver is configured to sequentially supply gate signals to gate lines provided in a display area, and the timing controller is configured to control the data driver and the gate driver. Summary of the invention

[0007] An object to be achieved by the present disclosure is to provide a gate driver capable of independently controlling a driving frequency of a display area and a display device including the gate driver.

[0008] Another object to be achieved by the present disclosure is to provide a gate driver capable of reducing (e.g., minimizing) power consumption and a display device including the gate driver.

[0009] The objects of the present disclosure are not limited to the above - mentioned objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0010] To achieve the above - mentioned objects, a gate driver according to an embodiment of the present disclosure may include at least one of gate input circuits, the at least one of the gate input circuits being configured to selectively output a first start pulse corresponding to a high - frequency operation and a second start pulse corresponding to a low - frequency operation to any one of a plurality of dependent - connected stages.

[0011] To achieve the above-mentioned purpose, a display device according to another embodiment of the present disclosure may include: a display panel including a display area; a plurality of dependently connected stages; at least one of gate input circuits, at least one of the gate input circuits being configured to selectively output any one of a first start pulse corresponding to a high-frequency operation and a second start pulse corresponding to a low-frequency operation; and a controller configured to control the gate driver. In this case, at least one of the plurality of stages may be connected to the gate input circuit and receive any one of the first start pulse and the second start pulse output by the gate input circuit.

[0012] Other details of the exemplary embodiments are included in the detailed description and the drawings.

[0013] According to the present disclosure, two or more gate input circuits are connected to the gate driver and operated such that the gate driver can operate at different frequencies. For example, the gate input circuit operates some of the gate drivers at a high frequency and some of the remaining gate drivers at a low frequency, so that the driving frequencies of the blocks included in the display area can be independently controlled.

[0014] According to the present disclosure, when the driving frequencies of the blocks included in the display area are independently controlled, the driving frequencies of some blocks are controlled to be low frequencies, so that the power consumption for displaying an image can be reduced (e.g., minimized).

[0015] The effects according to the present disclosure are not limited to the above-exemplified content, and more various effects are included in this specification. Description of the Drawings

[0016] The above aspects and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure;

[0018] Figure 2 is a cross-sectional view showing a hierarchical shape of a display device according to an embodiment;

[0019] Figure 3 is a view showing a configuration of a gate driver of a display device according to an embodiment of the present disclosure;

[0020] Figure 4 is a view showing a pixel circuit of a display device according to an embodiment of the present disclosure;

[0021] Figure 5A and Figure 5B is for explaining Figure 4View of operations of scan signals and light emission control signals during a refresh period and a holding period in the pixel circuit shown;

[0022] Figure 6 View showing the structure in which a gate input circuit of a display device according to an embodiment of the present disclosure is connected to a gate driver;

[0023] Figure 7 View showing a gate input circuit of a display device according to an embodiment of the present disclosure;

[0024] Figures 8A to 8C Waveform diagram showing divided driving of a display device according to an embodiment of the present disclosure; and

[0025] Figures 9A to 9D View for explaining an operation sequence of a gate input circuit according to an embodiment of the present disclosure. Detailed Description of Specific Embodiments

[0026] Advantages and features of the present disclosure and methods for achieving these advantages and features will be clear by referring to the exemplary embodiments described in detail below together with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0027] The shapes, sizes, ratios, angles, numbers, etc. shown in the drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. In addition, in the following description of the present disclosure, detailed descriptions of known related arts may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "comprising", "having", and "consisting of" used herein are generally intended to allow addition of other components, unless these terms are used together with the term "only". Any reference to the singular may include the plural unless otherwise explicitly stated.

[0028] Even if not explicitly stated, components are interpreted to include a normal error range.

[0029] When using terms such as "on", "above", "below", and "next to" to describe the positional relationship between two parts, at least one part may be positioned between the two parts, unless these terms are used together with the terms "immediately" or "directly".

[0030] When an element or layer is disposed "on" another element or layer, the other layer or element can be directly disposed on the other element or directly disposed therebetween.

[0031] Although terms such as "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below can be the second component in the technical concept of the present disclosure.

[0032] Throughout the specification, the same reference numerals generally denote the same elements.

[0033] For ease of description, the dimensions and thicknesses of each component shown in the drawings are shown, and the present disclosure is not limited to the dimensions and thicknesses of the components shown.

[0034] The features of the various embodiments of the present disclosure can be partially or completely attached to or combined with each other, and can be interlocked and operated in various ways technically, and these embodiments can be executed independently or in association with each other.

[0035] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the drawings.

[0036] Figure 1 is a block diagram schematically showing a display device according to an embodiment of the present disclosure.

[0037] Referring to Figure 1 , the display device 10 includes: a display panel 100 including a plurality of pixels P, a controller 200, a gate driver 300 configured to supply a gate signal to the plurality of pixels P, a data driver 400 configured to supply a data signal to the plurality of pixels P, and a power supply 500 configured to supply power required to operate the plurality of pixels P.

[0038] The display panel 100 includes a display area AA (see Figure 2 ) in which the pixels P are located and a non-display area NA (see Figure 2 ) provided to surround the display area AA, and the gate driver 300 and the data driver 400 are provided in the non-display area NA.

[0039] In the display panel 100, a plurality of gate lines GL and a plurality of data lines DL cross each other, and the plurality of pixels P are respectively connected to the gate lines GL and the data lines DL. Specifically, one pixel P is supplied with a gate signal from the gate driver 300 through the gate line GL, a data signal from the data driver 400 through the data line DL, and a high-potential driving voltage EVDD and a low-potential driving voltage EVSS from the power supply 500.

[0040] In this case, the gate line GL supplies a scan signal SC and an emission control signal EM, and the data line DL supplies a data voltage Vdata. In addition, according to various embodiments, the gate line GL may include a plurality of gate lines SCL configured to supply the scan signal SC, and an emission control signal line EML configured to supply the emission control signal EM. In addition, the plurality of pixels P may additionally include a power line VL, and are supplied with a bias voltage Vobs and initialization voltages Var and Vini.

[0041] In addition, as Figure 2 shown, each pixel P includes a light-emitting element OLED and a pixel circuit configured to control the operation of the light-emitting element OLED. In this case, the light-emitting element OLED includes an anode electrode ANO, a cathode electrode CAT, and a light-emitting layer EL disposed between the anode electrode ANO and the cathode electrode CAT.

[0042] The pixel circuit includes a plurality of switching elements, driving elements, and capacitors. In this case, the switching elements and the driving elements may be configured as thin-film transistors. The driving element of the pixel circuit adjusts the light emission amount of the light-emitting element OLED by controlling the amount of current to be supplied to the light-emitting element OLED based on the data voltage. In addition, the plurality of switching elements operate the pixel circuit by receiving the scan signal SC supplied through the plurality of gate lines SCL and receiving the emission control signal EM supplied through the emission control line EML.

[0043] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on a screen and an actual object in the background is visible. The display panel 100 may be manufactured as a flexible display panel. The flexible display panel may be implemented as an OLED panel using a plastic substrate.

[0044] The pixels P may be divided into red pixels, green pixels, and blue pixels to achieve color. The pixels P may also include white pixels. Each of the pixels P includes a pixel circuit.

[0045] A touch sensor may be provided on the display panel 100. Touch input may be sensed by using a separate touch sensor, or may be sensed by the pixels P. The touch sensor may be provided on the screen of the display panel as an on-cell type touch sensor or an add-on type touch sensor. Alternatively, the touch sensor may be implemented as an in-cell type touch sensor embedded in the display panel 100.

[0046] The controller 200 processes the externally input image data RGB such that the image data RGB is suitable for the size and resolution of the display panel 100, and supplies it to the data driver 400. The controller 200 generates a gate control signal GCS and a data control signal DCS by using the externally input synchronization signals, such as a dot clock signal CLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync. The controller 200 controls the gate driver 300 and the data driver 400 by supplying the generated gate control signal GCS and the generated data control signal DCS to the gate driver 300 and the data driver 400.

[0047] The controller 200 may be configured by being coupled to various processors, such as a microprocessor, a mobile processor, an application processor, etc., according to the installed device.

[0048] The host system may be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system.

[0049] The controller 200 may control the operation timing of the display panel driver, where the frame frequency is an input frame frequency × i (i is a positive integer greater than 0) Hz obtained by multiplying the input frame frequency by a coefficient i. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) and 50 Hz in Phase Alternating Line (PAL).

[0050] The controller 200 generates signals to operate the pixel P at various refresh rates. That is, the controller 200 generates signals related to the operation of the pixel P such that the pixel P operates in a variable refresh rate (VRR) mode, or operates to be able to switch between a first refresh rate and a second refresh rate. For example, the controller 200 may operate the pixel P at various refresh rates by simply changing the rate of the clock signal, generating a synchronization signal to form a horizontal blank or a vertical blank, or operating the gate driver 300 in a masked manner.

[0051] Based on the timing signals Vsync, Hsync, and DE received from the host system, the controller 200 generates a gate control signal GCS for controlling the operation timing of the gate driver 300, and generates a data control signal DSC for controlling the operation timing of the data driver 400. The controller 200 synchronizes the gate driver 300 and the data driver 400 by controlling the operation timing of the display panel driver.

[0052] The voltage levels of the gate control signal GCS output from the controller 200 can be converted into a gate-on voltage VGL and VEL and a gate-off voltage VGH and VEH by a level shifter (not shown), and the gate-on voltage VGL and VEL and the gate-off voltage VGH and VEH can be supplied to the gate driver 300. The level shifter converts the low-level voltage of the gate control signal GCS into a low gate voltage VGL, and converts the high-level voltage of the gate control signal GCS into a high gate voltage VGH. The gate control signal GCS includes a start pulse and a shift clock.

[0053] The gate driver 300 supplies a scan signal SC to the gate lines GL in response to the gate control signal GCS supplied from the controller 200. The gate driver 300 can be disposed on one side or two opposite sides of the display panel 100 in a gate-in-panel (GIP) manner.

[0054] The gate driver 300 sequentially outputs gate signals to the plurality of gate lines GL under the control of the controller 200. The gate driver 300 can shift the gate signals by using a shift register and sequentially supply the signals to the gate lines GL.

[0055] In the organic light emitting display device, the gate signal can include a scan signal SC and a light emission control signal EM. The scan signal SC includes a scan pulse that swings between the gate-on voltage VGL and the gate-off voltage VGH. The light emission control signal EM can include a light emission control signal pulse that swings between the gate-on voltage VEL and the gate-off voltage VEH.

[0056] The scan pulse is synchronized with the data voltage Vdata and selects the pixels P on the line to which data is to be written. The light emission control signal EM defines the light emission time of the pixels P.

[0057] The gate driver 300 can include a light emission control signal driver 310 and at least one scan driver 320.

[0058] The light emission control signal driver 310 outputs a light emission control signal pulse in response to the start pulse and the shift clock from the controller 200, and sequentially shifts the light emission control signal pulse based on the shift clock.

[0059] At least one scan driver 320 outputs a scan pulse in response to the start pulse and the shift clock from the controller 200, and shifts the scan pulse according to the shift clock timing.

[0060] The data driver 400 converts the image data RGB into a data voltage Vdata in response to the data control signal DCS supplied from the controller 200, and supplies the converted data voltage Vdata to the pixels P through the data lines DL.

[0061] Figure 1 It is shown that the data driver 400 is disposed at one side of the display panel 100 in a certain shape. However, the number and the arrangement position of the data driver 400 are not limited thereto.

[0062] That is to say, the data driver 400 may include a plurality of integrated circuits (ICs), and the plurality of data drivers 400 may be separated and disposed at one side of the display panel 100.

[0063] The power supply 500 uses a DC-DC converter, and generates direct current (DC) power required to operate the pixel array and the display panel driver of the display panel 100. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 500 may receive a DC input voltage applied from a host system (not shown), and generate DC voltages such as a gate-on voltage VGL and VEL, a gate-off voltage VGH and VEH, a high-potential driving voltage EVDD and a low-potential driving voltage EVSS. The gate-on voltage VGL and VEL and the gate-off voltage VGH and VEH are supplied to a level shifter and the gate driver 300 (not shown). The high-potential driving voltage EVDD and the low-potential driving voltage EVSS are commonly supplied to the pixel P.

[0064] Figure 2 It is a cross-sectional view showing a hierarchical shape of a display device according to an embodiment.

[0065] Figure 2 It is a cross-sectional view including two switching thin film transistors TFT1 and TFT2 and one capacitor CST. The two thin film transistors TFT1 and TFT2 include: any one of the switching thin film transistors or driving transistors including a polycrystalline semiconductor material, and an oxide thin film transistor TFT2 including an oxide semiconductor material. In this case, the thin film transistor including a polycrystalline semiconductor material is called a polycrystalline thin film transistor TFT1, and the thin film transistor including an oxide semiconductor material is called an oxide thin film transistor TFT2.

[0066] Figure 2 The polycrystalline thin film transistor TFT1 shown in is an emission switching thin film transistor connected to the light-emitting element OLED, and the oxide thin film transistor TFT2 is any one of the switching thin film transistors connected to the capacitor CST.

[0067] A pixel P includes a light-emitting element OLED and a pixel driving circuit configured to apply a driving current to the light-emitting element OLED. The pixel driving circuit is disposed on a substrate 111, and the light-emitting element OLED is disposed on the pixel driving circuit. Further, a packaging layer 120 is disposed on the light-emitting element OLED. The packaging layer 120 protects the light-emitting element OLED.

[0068] The pixel driving circuit may refer to an array portion of a pixel P including a thin-film driving transistor, a switching thin-film transistor, and a capacitor. Further, the light-emitting element OLED may refer to an array portion configured to emit light and including an anode electrode, a cathode electrode, and a light-emitting layer disposed between the anode electrode and the cathode electrode.

[0069] In an embodiment, the thin-film driving transistor and at least one switching thin-film transistor use an oxide semiconductor as an active layer. Compared with a thin-film transistor using a polycrystalline semiconductor material as an active layer, a thin-film transistor using an oxide semiconductor material as an active layer provides an excellent effect of blocking leakage current and requires a relatively low manufacturing cost. Therefore, the pixel driving circuit according to the embodiment includes a thin-film driving transistor and at least one switching thin-film transistor made of an oxide semiconductor material in order to reduce power consumption and manufacturing cost.

[0070] All thin-film transistors constituting the pixel driving circuit may be implemented by using an oxide semiconductor material. Alternatively, only some of the switching thin-film transistors may be implemented by using an oxide semiconductor material.

[0071] However, a thin-film transistor using an oxide semiconductor material has difficulty in ensuring reliability, while a thin-film transistor using a polycrystalline semiconductor material provides a high operation speed and excellent reliability. Therefore, the present embodiment includes both a switching thin-film transistor using an oxide semiconductor material and a switching thin-film transistor using a polycrystalline semiconductor material.

[0072] The substrate 111 may be implemented as a multilayer by alternately stacking an organic film and an inorganic film. For example, the substrate 111 may be implemented by alternately stacking an organic film such as polyimide and an inorganic film such as silicon oxide (SiO2).

[0073] A lower buffer layer 112a is formed on the substrate 111. The lower buffer layer 112a may be used to block moisture and the like that may penetrate from the outside. The lower buffer layer 112a may be fabricated by stacking a silicon oxide (SiO2) film or the like as a multilayer. An auxiliary buffer layer 112b may also be disposed on the lower buffer layer 112a to protect the elements from moisture penetration.

[0074] A polycrystalline thin-film transistor TFT1 is formed on a substrate 111. The polycrystalline thin-film transistor TFT1 may use a polycrystalline semiconductor as an active layer. The polycrystalline thin-film transistor TFT1 includes a first active layer ACT1 including a channel through which electrons or holes move, a first gate electrode GE1, a first source electrode SD1, and a first drain electrode SD2.

[0075] The first active layer ACT1 includes a first channel region, a first source region provided on one side, and a first drain region provided on the other side, with the first channel region interposed therebetween.

[0076] The first source region and the first drain region are regions where a true polycrystalline semiconductor material is doped with pentavalent or trivalent impurity ions, such as phosphorus (P) or boron (B), at a predetermined concentration so that the polycrystalline semiconductor material becomes a conductor. The first channel region maintains the true state of the polycrystalline semiconductor material and provides a path through which electrons or holes move.

[0077] Meanwhile, the polycrystalline thin-film transistor TFT1 includes a first gate electrode GE1 overlapping the first channel region of the first active layer ACT1. A first gate insulating layer 113 is provided between the first gate electrode GE1 and the first active layer ACT1. The first gate insulating layer 113 can be made by stacking inorganic layers such as a silicon oxide (SiO2) film and a silicon nitride (SiNx) film as a single layer or multiple layers.

[0078] In an embodiment, the polycrystalline thin-film transistor TFT1 has a top-gate structure in which the first gate electrode GE1 is positioned above the first active layer ACT1. Accordingly, a first electrode CST1 included in a capacitor CST and a light-blocking layer LS included in an oxide thin-film transistor TFT2 can be made of the same material as the first gate electrode GE1. The first gate electrode GE1, the first electrode CST1, and the light-blocking layer LS are formed by a single mask process, so that the number of mask processes can be reduced.

[0079] The first gate electrode GE1 is made of a metal material. For example, the first gate electrode GE1 may be configured as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, the present disclosure is not limited thereto.

[0080] A first interlayer insulating layer 114 is provided on the first gate electrode GE1. The first interlayer insulating layer 114 can be made of silicon oxide (SiO2), silicon nitride (SiNx), etc.

[0081] The display panel 100 may further include an upper buffer layer 115, a second gate insulating layer 116, and a second interlayer insulating layer 117 that are sequentially disposed on the first interlayer insulating layer 114. The polycrystalline thin film transistor TFT1 includes a first source electrode SD1 and a first drain electrode SD2 that are formed on the second interlayer insulating layer 117 and are respectively connected to a first source region and a first drain region.

[0082] The first source electrode SD1 and the first drain electrode SD2 may each be configured as a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. However, the present disclosure is not limited thereto.

[0083] The upper buffer layer 115 may provide a base that can form a second active layer ACT2 by spacing the second active layer ACT2 of the oxide thin film transistor TFT2 implemented by an oxide semiconductor material from the first active layer ACT1 implemented by a polycrystalline semiconductor material.

[0084] The second gate insulating layer 116 covers the second active layer ACT2 of the oxide thin film transistor TFT2. Since the second gate insulating layer 116 is formed on the second active layer ACT2 implemented by an oxide semiconductor material, the second gate insulating layer 116 is implemented by an inorganic film. For example, the second gate insulating layer 116 may be made of silicon oxide (SiO2), silicon nitride (SiNx), etc.

[0085] The second gate electrode GE2 is made of a metal material. For example, the second gate electrode GE2 may be configured as a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. However, the present disclosure is not limited thereto.

[0086] Meanwhile, the oxide thin film transistor TFT2 includes a second active layer ACT2 that is formed on the upper buffer layer 115 and is implemented by an oxide semiconductor material, a second gate electrode GE2 that is disposed on the second gate insulating layer 116, and a second source electrode SD3 and a second drain electrode SD4 that are disposed on the second interlayer insulating layer 117.

[0087] The second active layer ACT2 includes a true second channel region implemented by an oxide semiconductor material and not doped with impurities, and a second source region and a second drain region that become conductors by being doped with impurities.

[0088] The oxide thin film transistor TFT2 further includes a light blocking layer LS positioned below the upper buffer layer 115 and configured to overlap with the second active layer ACT2. The light blocking layer LS can block light from entering the second active layer ACT2, thereby ensuring the reliability of the oxide thin film transistor TFT2. The light blocking layer LS can be made of the same material as the first gate electrode GE1 and is formed on the top surface of the first gate insulating layer 113. The light blocking layer LS can be electrically connected to the second gate electrode GE2 and constitutes a double gate.

[0089] The second source electrode SD3 and the second drain electrode SD4 can be formed on the second interlayer insulating layer 117 and are made of the same material as the first source electrode SD1 and the first drain electrode SD2, thereby reducing the number of mask processes.

[0090] Meanwhile, the second electrode CST2 can be disposed on the first interlayer insulating layer 114 and overlap with the first electrode CST1, thereby constituting the capacitor CST. For example, the second electrode CST2 can be configured as a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys.

[0091] The capacitor CST stores the data voltage applied through the data line DL for a predetermined period of time and supplies the data voltage to the light emitting element OLED. The capacitor CST includes two electrodes corresponding to each other and a dielectric material between the two electrodes. The first interlayer insulating layer 114 is positioned between the first electrode CST1 and the second electrode CST2.

[0092] The first electrode CST1 or the second electrode CST2 of the capacitor CST can be electrically connected to the oxide thin film transistor TFT2, the second source electrode SD3, or the second drain electrode SD4. However, the present disclosure is not limited thereto. The connection relationship of the capacitor CST can vary according to the pixel driving circuit.

[0093] Meanwhile, a first planarization layer 118 and a second planarization layer 119 are sequentially provided on the pixel driving circuit to flatten the upper end of the pixel driving circuit. The first planarization layer 118 and the second planarization layer 119 can each be an organic film made of polyimide or acrylic resin.

[0094] In addition, a light emitting element OLED is formed on the second planarization layer 119.

[0095] The light-emitting element OLED includes an anode electrode ANO, a cathode electrode CAT, and a light-emitting layer EL disposed between the anode electrode ANO and the cathode electrode CAT. When the pixel driving circuit is implemented to commonly use a low-potential voltage connected to the cathode electrode CAT, the anode electrode ANO is provided as a separate electrode in each of the sub-pixels. When the pixel driving circuit is implemented to commonly use a high-potential voltage, the cathode electrode CAT can be provided as a separate electrode in each of the sub-pixels.

[0096] The light-emitting element OLED is electrically connected to the driving element through an intermediate electrode CNE disposed on the first planarization layer 118. Specifically, the anode electrode ANO of the light-emitting element OLED and the first source electrode SD1 of the polycrystalline thin-film transistor TFT1 constituting the pixel driving circuit are connected to each other through the intermediate electrode CNE.

[0097] The anode electrode ANO is connected to the intermediate electrode CNE exposed through a contact hole formed by penetrating the second planarization layer 119. In addition, the intermediate electrode CNE is connected to the first source electrode SD1 exposed through a contact hole formed by penetrating the first planarization layer 118.

[0098] The intermediate electrode CNE can be used as a medium for connecting the first source electrode SD1 and the anode electrode ANO. The intermediate electrode CNE can be made of a conductive material such as copper (Cu), silver (Ag), molybdenum (Mo), or titanium (Ti).

[0099] The anode electrode ANO can have a multilayer structure including a transparent conductive film and an opaque conductive film having a high reflection efficiency. The transparent conductive film can be made of a material such as indium tin oxide (ITO) or indium zinc oxide (IZO) having a relatively large work function value. The opaque conductive film can be configured as a single layer or multiple layers including aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or their alloys. For example, the anode electrode ANO can have a structure made by sequentially stacking a transparent conductive film, an opaque conductive film, and a transparent conductive film. Alternatively, the anode electrode ANO can have a structure made by sequentially stacking a transparent conductive film and an opaque conductive film.

[0100] The light-emitting layer EL is formed by stacking a hole-related layer, an organic light-emitting layer, and an electron-related layer in this order or in the reverse order on the anode electrode ANO.

[0101] The bank layer BNK may be a pixel defining film that exposes the anode electrode ANO of each of the pixels P. The bank layer BNK may be made of an opaque material (e.g., black) to suppress light interference between adjacent pixels P. In this case, the bank layer BNK includes a light-blocking material made of at least any one of a coloring pigment, an organic black, and carbon. A spacer may also be provided on the bank layer BNK.

[0102] The cathode electrode CAT is formed on the top surface and the side surface of the light-emitting layer EL while facing the anode electrode ANO, with the light-emitting layer EL therebetween. The cathode electrode CAT may be integrally formed in the entire display area AA. In the case where the cathode electrode CAT is applied to a top-emission organic light-emitting display device, the cathode electrode CAT may be configured of a transparent conductive film made of indium tin oxide (ITO) or indium zinc oxide (IZO).

[0103] An encapsulation layer 120 for suppressing moisture penetration may also be provided on the cathode electrode CAT.

[0104] The encapsulation layer 120 may suppress the penetration of external moisture or oxygen into the light-emitting element OLED that is vulnerable to external moisture or oxygen. To this end, the encapsulation layer 120 may have at least one inorganic encapsulation layer and at least one organic encapsulation layer. However, the present disclosure is not limited thereto. In the present disclosure, the structure of the encapsulation layer 120 in which a first encapsulation layer 121, a second encapsulation layer 122, and a third encapsulation layer 123 are sequentially stacked will be described as an example.

[0105] The first encapsulation layer 121 is formed on the substrate 111 on which the cathode electrode CAT is formed. The third encapsulation layer 123 is formed on the substrate 111 on which the second encapsulation layer 122 is formed. The third encapsulation layer 123 may be formed together with the first encapsulation layer 121 to surround the top surface, the bottom surface, and the side surface of the second encapsulation layer 122. The first encapsulation layer 121 and the third encapsulation layer 123 may minimize or suppress the penetration of external moisture or oxygen into the light-emitting element OLED. The first encapsulation layer 121 and the third encapsulation layer 123 may be made of an inorganic insulating material that can be deposited at a low temperature, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). The first encapsulation layer 121 and the third encapsulation layer 123 are deposited in a low-temperature environment so that damage to the light-emitting element OLED that is vulnerable to a high-temperature environment can be suppressed during the deposition of the first encapsulation layer 121 and the third encapsulation layer 123.

[0106] The second encapsulation layer 122 can flatten the step difference between the layers and at the same time serve as a buffer to relieve the stress between the layers caused when the display device 10 is bent. The second encapsulation layer 122 can be formed on the substrate 111 on which the first encapsulation layer 121 is formed, and is made of a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or silicon oxycarbide (SiOC), or a photosensitive organic insulating material such as photoacrylic. However, the present disclosure is not limited thereto. In the case where the second encapsulation layer 122 is formed by an inkjet method, a dam DAM can be provided to inhibit the liquid-phase second encapsulation layer 122 from spreading to the edge of the substrate 111. The dam DAM can be provided closer to the edge of the substrate 111 than the second encapsulation layer 122. The dam DAM can inhibit the second encapsulation layer 122 from spreading to the pad region where the conductive pads provided at the outermost periphery of the substrate 111 are provided.

[0107] The dam DAM is designed to inhibit the spread of the second encapsulation layer 122. In the case where the second encapsulation layer 122 is formed to exceed the height of the dam DAM during the process, the second encapsulation layer 122, which is an organic layer, may be exposed to the outside, and moisture and the like may easily penetrate into the light-emitting element. Therefore, at least ten or more dams DAM can be repeatedly formed to inhibit moisture penetration.

[0108] The dam DAM can be provided on the second interlayer insulating layer 117 in the non-display area NA.

[0109] In addition, the dam DAM can be formed simultaneously with the first planarization layer 118 and the second planarization layer 119. When the first planarization layer 118 is formed, the lower layer of the dam DAM can be formed together with the first planarization layer 118. When the second planarization layer 119 is formed, the upper layer of the dam DAM is formed together with the second planarization layer 119. Therefore, the lower layer and the upper layer of the dam DAM can be stacked as a double structure.

[0110] Therefore, the dam DAM can be made of the same material as the first planarization layer 118 and the second planarization layer 119. However, the present disclosure is not limited thereto.

[0111] The dam DAM can be formed to overlap with the low-potential driving power line VSS. For example, the low-potential driving power line VSS can be formed on the lower layer in the region where the dam DAM is located in the non-display area NA.

[0112] The low-potential driving power line VSS and the gate driver 300 configured in the shape of an in-panel gate (GIP) are formed in a shape surrounding the outer periphery of the display panel. The low-potential driving power line VSS may be positioned closer to the outer periphery than the gate driver 300. In addition, the low-potential driving power line VSS may be connected to the cathode electrode CAT and apply a common voltage. The gate driver 300 is simply shown in a top plan view and a cross-sectional view. However, the gate driver 300 may be configured by using thin-film transistors having the same structure as the thin-film transistors in the display area AA.

[0113] The low-potential driving power line VSS is disposed outside the gate driver 300. The low-potential driving power line VSS is disposed outside the gate driver 300 and surrounds the display area AA. For example, the low-potential driving power line VSS may be made of the same material as the first gate electrode GE1. However, the present disclosure is not limited thereto. The low-potential driving power line VSS may be made of the same material as the second electrode CST2 or the first source electrode SD1 and the first drain electrode SD2. However, the present disclosure is not limited thereto.

[0114] In addition, the low-potential driving power line VSS may be electrically connected to the cathode electrode CAT. The low-potential driving power line VSS may supply a low-potential driving voltage EVSS to the plurality of pixels P in the display area AA.

[0115] A touch layer may be provided on the encapsulation layer 120. The touch buffer film 151 on the touch layer may be positioned between the cathode electrode CAT of the light-emitting element OLED and the touch sensor metal including the touch electrode connection lines 152 and 154 and the touch electrodes 155 and 156.

[0116] The touch buffer film 151 may prevent external moisture or liquid chemicals (developer, etching solution, etc.) of the process for manufacturing the touch sensor metal provided on the touch buffer film 151 from being introduced into the light-emitting layer EL including an organic material. Therefore, the touch buffer film 151 may prevent damage to the light-emitting layer EL vulnerable to liquid chemicals or moisture.

[0117] In order to prevent damage to the light-emitting layer EL including an organic material vulnerable to high temperature, the touch buffer film 151 may be made of an organic insulating material that can be formed at a predetermined low temperature (e.g., 100 °C) or lower and has a low dielectric constant of 1 to 3. For example, the touch buffer film 151 may be formed of an acrylic-based, epoxy-based, or siloxane-based material. The touch buffer film 151 made of an organic insulating material and having a planarization property may prevent damage to the encapsulation layer 120 and breakage of the touch sensor metal formed on the touch buffer film 151 when the organic light-emitting display device is bent.

[0118] According to the mutual capacitance-based touch sensor structure, touch electrodes 155 and 156 can be disposed on the touch buffer film 151, and the touch electrodes 155 and 156 can be disposed to cross each other.

[0119] Touch electrode connection lines 152 and 154 can electrically connect the touch electrodes 155 and 156. The touch electrode connection lines 152 and 154 and the touch electrodes 155 and 156 can be positioned on different layers, with the touch insulation film 153 interposed therebetween.

[0120] The touch electrode connection lines 152 and 154 can be disposed to overlap with the bank layer BNK and suppress deterioration of the aperture ratio.

[0121] Meanwhile, in the touch electrodes 155 and 156, a part of the touch electrode connection line 152 can pass through the upper and side surfaces of the encapsulation layer 120 and the upper and side surfaces of the dam DAM, and is electrically connected to a touch driving circuit (not shown) through the touch pad PAD.

[0122] A part of the touch electrode connection line 152 can be supplied with a touch driving signal from the touch driving circuit and transmit the touch driving signal to the touch electrodes 155 and 156, and a part of the touch electrode connection line 152 can transmit a touch sensing signal from the touch electrodes 155 and 156 to the touch driving circuit.

[0123] A touch protection film 157 can be disposed on the touch electrodes 155 and 156. In the figure, the touch protection film 157 is shown as being disposed only on the touch electrodes 155 and 156. However, the present disclosure is not limited thereto. The touch protection film 157 can extend to the front or back surface of the dam DAM and can even be disposed on the touch electrode connection line 152.

[0124] In addition, a color filter (not shown) can be disposed on the encapsulation layer 120. The color filter can be positioned on the touch layer or between the encapsulation layer 120 and the touch layer.

[0125] Figure 3 It is a view showing the configuration of a gate driver of a display device according to an embodiment of the present disclosure.

[0126] Referring to Figure 3 , the gate driver 300 includes a light emission control signal driver 310 and a scan driver 320. The scan driver 320 can include first to fourth scan drivers 321, 322, 323, and 324. In addition, the second scan driver 322 can include an odd second scan driver 322_O and an even second scan driver 322_E.

[0127] In the gate driver 300, the shift registers may be symmetrically disposed at two opposite sides of the display area AA. In addition, the gate driver 300 may be configured such that: the shift registers located at one side of the display area AA include second scan drivers 322_O and 322_E, a fourth scan driver 324, and a light emission control signal driver 310, and the shift registers located at the other side of the display area AA include a first scan driver 321, second scan drivers 322_O and 322_E, and a third scan driver 323. However, the present disclosure is not limited thereto. The light emission control signal driver 310 and the first to fourth scan drivers 321, 322, 323, and 324 may be differently arranged according to embodiments.

[0128] The stages STG1 to STGN of the shift register may include first scan signal generators SC1(1) to SC1(n), second scan signal generators SC2_O(1) to SC2_O(n) and SC2_E(1) to SC2_E(n), third scan signal generators SC3(1) to SC3(n), fourth scan signal generators SC4(1) to SC4(n), and light emission control signal generators EM(1) to EM(n).

[0129] The first scan signal generators SC1(1) to SC1(n) output first scan signals SC1(1) to SC1(n) through the first gate lines SCL1 of the display panel 100. The second scan signal generators SC2(1) to SC2(n) output second scan signals SC2(1) to SC2(n) through the second gate lines SCL2 of the display panel 100. The third scan signal generators SC3(1) to SC3(n) output third scan signals SC3(1) to SC3(n) through the third gate lines SCL3 of the display panel 100. The fourth scan signal generators SC4(1) to SC4(n) output fourth scan signals SC4(1) to SC4(n) through the fourth gate lines SCL4 of the display panel 100. The light emission control signal generators EM(1) to EM(n) output light emission control signals EM(1) to EM(n) through the light emission control lines EML of the display panel 100.

[0130] The first scan signals SC1(1) to SC1(n) can be used as signals for operating the A-th transistor (e.g., a compensation transistor, etc.) included in the pixel circuit. The second scan signals SC2(1) to SC2(n) can be used as signals for operating the B-th transistor (e.g., a data supply transistor, etc.) included in the pixel circuit. The third scan signals SC3(1) to SC3(n) can be used as signals for operating the C-th transistor (e.g., a bias transistor, etc.) included in the pixel circuit. The fourth scan signals SC4(1) to SC4(n) can be used as signals for operating the D-th transistor (e.g., an initialization transistor, etc.) included in the pixel circuit. The emission control signals EM(1) to EM(n) can be used as signals for operating the E-th transistor (e.g., an emission control transistor, etc.) included in the pixel circuit. For example, when controlling the emission control transistor of the pixel by using the emission control signals EM(1) to EM(n), the emission time of the light-emitting element changes.

[0131] Referring to Figure 3 , the bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL can be provided between the gate driver 300 and the display area AA.

[0132] The bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL can supply the bias voltage Vobs, the first initialization voltage Var, and the second initialization voltage Vini from the power supply 500 to the pixel circuit.

[0133] In the figure, the bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL are shown as being located only at one of the left and right sides of the display area AA. However, the present disclosure is not limited thereto. The bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL can be located at two opposite sides, or at one side without being limited to the left or right side.

[0134] Referring to Figure 3 , at least one optical region OA1 and OA2 can be provided in the display area AA.

[0135] At least one optical region OA1 and OA2 can be provided to overlap with at least one optoelectronic device, such as an image capturing device such as a camera device (image sensor) and detection sensors such as a proximity sensor and an illuminance sensor.

[0136] At least one of the optical regions OA1 and OA2 may have a light-transmitting structure and have a light transmittance equal to or higher than a predetermined level in order to operate the electro-optical device. In other words, in at least one of the optical regions OA1 and OA2, the number of pixels P per unit area may be smaller than the number of pixels P per unit area in a general region in the display area AA other than the optical regions OA1 and OA2. That is, the resolution of at least one of the optical regions OA1 and OA2 may be lower than the resolution of the general region in the display area AA.

[0137] In at least one of the optical regions OA1 and OA2, the light-transmitting structure may be configured by patterning a cathode electrode on a portion where the pixel P is not provided. In this case, the patterned cathode electrode may be removed by using a laser. Alternatively, the cathode electrode may also be selectively formed and patterned by using a material such as a cathode deposition inhibiting layer.

[0138] In addition, in at least one of the optical regions OA1 and OA2, the light-transmitting structure may be configured by forming and separating a light-emitting element OLED and a pixel circuit in the pixel P. In other words, the light-emitting element OLED of the pixel P may be positioned in the optical regions OA1 and OA2, and a plurality of transistors TFT constituting the pixel circuit are provided around the optical regions OA1 and OA2 such that the light-emitting element OLED and the pixel circuit may be electrically connected through a transparent metal layer.

[0139] Figure 4 is a view showing a pixel circuit of a display device according to an embodiment of the present disclosure.

[0140] Figure 4 Exemplarily, the pixel circuit is shown for illustrative purposes only. The pixel circuit is not limited as long as it has a structure capable of controlling the light emission of the light-emitting element OLED by applying an EM signal EM(n). For example, the pixel circuit may include an additional scan signal, a switching thin-film transistor connected to the additional scan signal. An additional initialization voltage may be applied to the switching thin-film transistor. The connection relationship between the switching elements and the connection position of the capacitor may be set differently. Hereinafter, for ease of description, a display device having the Figure 4 pixel circuit structure in will be described.

[0141] Referring to Figure 4 , a plurality of pixels P may each include a pixel circuit having a driving transistor DT and a light-emitting element OLED connected to the pixel circuit.

[0142] The pixel circuit can operate the light-emitting element OLED by controlling the driving current flowing through the light-emitting element OLED. The pixel circuit can include a driving transistor DT, first to seventh transistors T1, T2, T3, T4, T5, T6, and T7, and a capacitor Cst. The transistors DT, T1, T2, T3, T4, T5, T6, and T7 can each include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode can be a source electrode, and the other of the first electrode and the second electrode can be a drain electrode.

[0143] The transistors DT, T1, T2, T3, T4, T5, T6, and T7 can each be a P-type thin film transistor or an N-type thin film transistor. In Figure 4 an embodiment, the first transistor T1 and the seventh transistor T7 are each configured as an N-type thin film transistor, and the remaining transistors DT, T2, T3, T4, T5, and T6 are each configured as a P-type thin film transistor. However, the present disclosure is not limited thereto. According to an embodiment, all or some of the transistors DT, T1, T2, T3, T4, T5, T6, and T7 can be P-type thin film transistors or N-type thin film transistors. In addition, the N-type thin film transistor can be an oxide thin film transistor, and the P-type thin film transistor can be a polysilicon thin film transistor.

[0144] Hereinafter, an example will be described in which the first transistor T1 and the seventh transistor T7 are each an N-type thin film transistor, and the remaining transistors DT, T2, T3, T4, T5, and T6 are each a P-type thin film transistor. Therefore, the first transistor T1 and the seventh transistor T7 are turned on by receiving a high voltage, and the remaining transistors DT, T2, T3, T4, T5, and T6 are turned on by receiving a low voltage.

[0145] For example, the first transistor T1 constituting the pixel circuit can be used as a compensation transistor, the second transistor T2 can be used as a data supply transistor, the third transistor T3 and the fourth transistor T4 can be used as light-emitting control transistors, the fifth transistor T5 can be used as a bias transistor, and the sixth transistor T6 and the seventh transistor T7 can be used as initialization transistors.

[0146] The light-emitting element OLED can include an anode electrode and a cathode electrode. The anode electrode of the light-emitting element OLED can be connected to the fifth node N5, and the cathode electrode can be connected to the low-potential driving voltage EVSS.

[0147] The driving transistor DT may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode connected to the first node N1. The driving transistor DT may supply a driving current Id to the light-emitting element OLED based on the voltage of the first node N1 (or the data voltage stored in the capacitor Cst described later).

[0148] The first transistor T1 may include a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate electrode configured to receive a first scan signal SC1(n). The first transistor T1 may be turned on in response to the first scan signal SC1(n) and, by means of a diode connection, be between the first node N1 and the third node N3, such that the first transistor T1 may sample the threshold voltage Vth of the driving transistor DT. The first transistor T1 may be a compensation transistor.

[0149] The capacitor Cst may be connected or formed between the first node N1 and the fourth node N4. The capacitor Cst may store or maintain the supplied high-potential driving voltage EVDD.

[0150] The second transistor T2 may include a first electrode connected to the data line DL (or configured to receive a data voltage Vdata), a second electrode connected to the second node N2, and a gate electrode configured to receive a second scan signal SC2(n). The second transistor T2 may be turned on in response to the second scan signal SC2(n) and transmit the data voltage Vdata to the second node N2. The second transistor T2 may be a data supply transistor.

[0151] The third transistor T3 and the fourth transistor T4 (or the first light-emitting control transistor and the second light-emitting control transistor) may be connected between the high-potential driving voltage EVDD and the light-emitting element OLED and define a current flow path through which the driving current Id generated by the driving transistor DT flows.

[0152] The third transistor T3 may include a first electrode connected to the fourth node N4 and configured to receive the high-potential driving voltage EVDD, a second electrode connected to the second node N2, and a gate electrode configured to receive a light-emitting control signal EM(n).

[0153] The fourth transistor T4 may include a first electrode connected to the third node N3, a second electrode connected to the fifth node N5 (or the anode electrode of the light-emitting element OLED), and a gate electrode configured to receive a light-emitting control signal EM(n).

[0154] The third transistor T3 and the fourth transistor T4 can be turned on in response to the light emission control signal EM(n). In this case, the drive current Id is supplied to the light emitting element OLED, and the light emitting element OLED can emit light having a brightness corresponding to the drive current Id.

[0155] The fifth transistor T5 can include a first electrode configured to receive a bias voltage Vobs, a second electrode connected to the second node N2, and a gate electrode configured to receive a third scan signal SC3(n). The fifth transistor T5 can be a bias transistor.

[0156] The sixth transistor T6 can include a first electrode configured to receive a first initialization voltage Var, a second electrode connected to the fifth node N5, and a gate electrode configured to receive a third scan signal SC3(n).

[0157] Before (or after) the light emitting element OLED emits light, the sixth transistor T6 can be turned on in response to the third scan signal SC3(n), and the anode electrode (or pixel electrode) of the light emitting element OLED can be initialized by using the first initialization voltage Var. The light emitting element OLED can have a parasitic capacitor formed between the anode electrode and the cathode electrode. In addition, when the light emitting element OLED emits light, the parasitic capacitor is charged so that the anode electrode of the light emitting element OLED can have a specific voltage. Therefore, the amount of charge accumulated in the light emitting element OLED can be initialized by applying the first initialization voltage Var to the anode electrode of the light emitting element OLED via the sixth transistor T6.

[0158] In the present disclosure, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 are configured to commonly receive the third scan signal SC3(n). However, the present disclosure is not necessarily limited thereto. The gate electrodes of the fifth transistor T5 and the sixth transistor T6 can be configured to be independently controlled by receiving separate scan signals.

[0159] The seventh transistor T7 can include a first electrode configured to receive a second initialization voltage Vini, a second electrode connected to the first node N1, and a gate electrode configured to receive a fourth scan signal SC4(n).

[0160] The seventh transistor T7 can be turned on in response to the fourth scan signal SC4(n), and the gate electrode of the drive transistor DT can be initialized by using the second initialization voltage Vini. Due to the high potential drive voltage EVDD stored in the capacitor Cst, unnecessary charge may remain on the gate electrode of the drive transistor DT. Therefore, the residual charge amount can be initialized by applying the second initialization voltage Vini to the gate electrode of the drive transistor DT via the seventh transistor T7.

[0161] Figure 5A and Figure 5B It is used to illustrate Figure 4 A view of the operation of the scanning signal and the light emission control signal in the refresh period and the holding period in the pixel circuit is shown.

[0162] The display device according to the embodiment of the present disclosure can be operated as a variable refresh rate (VRR) mode display device. The VRR mode operates at a predetermined frequency. At a time point when high-speed operation is required, the VRR mode can operate pixels by increasing the refresh rate of the update data voltage Vdata or reducing power consumption. At a time point when low-speed operation is required, the VRR mode can operate pixels by reducing the refresh rate.

[0163] A plurality of pixels P can each be operated within 1 second by means of a combination of a refresh frame and a hold frame. In the present disclosure, a setup is defined as a configuration in which a combination of a refresh period in which the data voltage Vdata is updated and a hold period in which the data voltage Vdata is not updated is repeated for 1 second. In addition, a setup period is a cycle in which a combination of a refresh period and a hold period is repeated.

[0164] In the case of performing an operation at a refresh rate of 120 Hz, the operation can be performed only in the refresh period. That is, the refresh period can be operated 120 times in 1 second. One refresh period is 1 / 120=8.33 ms, and one setup period is also 8.33 ms.

[0165] In the case of performing operation at a refresh rate of 60 Hz, the refresh period and the hold period can be operated alternately. The refresh period and the hold period can each be operated alternately 60 times within 1 second. One refresh period and one hold period are each 0.5 / 60=8.33 ms, and one setup period is 16.66 ms.

[0166] In the case of performing operation at a refresh rate of 1 Hz, one frame can operate within one refresh period and 119 hold periods after one refresh period. In addition, in the case of performing operation at a refresh rate of 1 Hz, one frame can operate within multiple refresh periods and multiple hold periods. In this case, one refresh period and one hold period are each 1 / 120=8.33 ms, and one setup period is 1 s.

[0167] During the refresh period, a new data voltage Vdata is charged and the new data voltage Vdata is applied to the driving transistor DT. In contrast, during the hold period, the data voltage Vdata of the previous frame is maintained and used in a sound manner. At the same time, the hold period is also referred to as a skip period, which means that the process of applying the new data voltage Vdata to the driving transistor DT is excluded.

[0168] During the refresh period, multiple pixels P can each initialize the charged voltage or the remaining voltage in the pixel circuit. Specifically, the multiple pixels P can remove the influence of the data voltage Vdata and the high-potential driving voltage EVDD stored in the previous frame during the refresh period. Therefore, during the hold period, the multiple pixels P can each display an image corresponding to the new data voltage Vdata.

[0169] During the hold period, by supplying a driving current corresponding to the data voltage Vdata to the light-emitting element OLED and maintaining the conduction state of the light-emitting element OLED, the multiple pixels P can each display an image.

[0170] First, the Figure 5A operation of the pixel circuit and the light-emitting element during the refresh period will be described. The refresh period can perform operations and includes at least one bias section Tobs1 and Tobs2, an initialization section Ti, a sampling section Ts, and a light-emitting section Te. However, this is only an embodiment, and the present disclosure is not necessarily limited to this order.

[0171] Referring to Figure 5A , the pixel circuit can operate during the refresh period and includes at least one bias section Tobs1 and Tobs2.

[0172] At least one of the bias sections Tobs1 and Tobs2 is a part that performs the on-bias stress OBS operation of applying the bias voltage Vobs. The light emission control signal EM(n) is a high voltage, and the third transistor T3 and the fourth transistor T4 are turned off. The first scan signal SC1(n) and the fourth scan signal SC4(n) are low voltages, and the first transistor T1 and the seventh transistor T7 are turned off. The second scan signal SC2 is a high voltage, and the second transistor T2 is turned off.

[0173] The third scan signal SC3(n) is input as a low voltage, and the fifth transistor T5 and the sixth transistor T6 are turned on. When the fifth transistor T5 is turned on, the bias voltage Vobs is applied to the first electrode of the driving transistor DT connected to the second node N2.

[0174] In this case, a bias voltage Vobs is supplied to a third node N3 that is a drain electrode of a driving transistor DT, such that a voltage charging time of a fifth node N5 that is an anode electrode of a light-emitting element OLED can be reduced during a light-emitting period, or a charging delay of a gate driver can be reduced. The driving transistor DT is maintained in a high saturation state.

[0175] For example, as the bias voltage Vobs increases, a voltage of the third node N3 that is a drain electrode of the driving transistor DT can increase, and a gate-source voltage or a drain-source voltage of the driving transistor DT can decrease. Accordingly, the bias voltage Vobs can be at least higher than a data voltage Vdata.

[0176] In this case, a magnitude of a drain-source current Id flowing through the driving transistor DT can be decreased, and in a positive bias stress case, by reducing a stress of the driving transistor DT, a charging delay of a voltage of the third node N3 can be eliminated. In other words, before sampling a threshold voltage Vth of the driving transistor DT, a turn-on bias stress OBS operation can be performed to mitigate a hysteresis of the driving transistor DT.

[0177] Accordingly, in at least one of bias sections Tobs1 and Tobs2, the turn-on bias stress OBS operation can be defined as an operation of directly applying an appropriate bias voltage to the driving transistor DT during a non-light-emitting period.

[0178] In addition, when a sixth transistor T6 is turned on in at least one of the bias sections Tobs1 and Tobs2, an anode electrode (or a pixel electrode) of the light-emitting element OLED connected to the fifth node N5 can be initialized to a first initialization voltage Var.

[0179] However, gate electrodes of a fifth transistor T5 and the sixth transistor T6 can be configured to be independently controlled by receiving separate scan signals. That is, it is not necessary to simultaneously apply a bias voltage to a first electrode of the driving transistor DT and an anode electrode of the light-emitting element OLED in the bias section.

[0180] Referring to Figure 5A , a pixel circuit can operate during a refresh period and includes an initialization section Ti. The initialization section Ti is a section for initializing a voltage of a gate electrode of the driving transistor DT.

[0181] The first scan signal to the fourth scan signals SC1(n), SC2(n), SC3(n), and SC4(n) and the light emission control signal EM(n) are high voltages, and the first transistor T1 and the seventh transistor T7 are turned on. The second transistor to the sixth transistors T2, T3, T4, T5, and T6 are turned off. When the first transistor T1 and the seventh transistor T7 are turned on, the gate electrode and the second electrode of the driving transistor DT connected to the first node N1 are initialized to the second initialization voltage Vini.

[0182] Referring to Figure 5A , the pixel circuit can operate during the refresh period and includes a sampling section Ts. The sampling section is a section for sampling the threshold voltage Vth of the driving transistor DT.

[0183] The first scan signal SC1(n), the third scan signal SC3(n), and the light emission control signal EM(n) are high voltages, and the second scan signal SC2(n) and the fourth scan signal SC4(n) are input as low voltages. Accordingly, the third transistor to the seventh transistors T3, T4, T5, T6, and T7 are turned off, the first transistor T1 remains in the on state, and the second transistor T2 is turned on. That is, the second transistor T2 is turned on so that the data voltage Vdata is applied to the driving transistor DT. The first transistor T1 can be diode-connected between the first node N1 and the third node N3 so that the threshold voltage Vth of the driving transistor DT can be sampled.

[0184] Referring to Figure 5A , the pixel circuit can operate during the refresh period and includes a light emission section Te. The light emission section Te is a section that shifts the sampled threshold voltage Vth and enables the light emitting element OLED to emit light with a driving current corresponding to the sampled data voltage.

[0185] The light emission control signal EM(n) is a low voltage, and the third transistor T3 and the fourth transistor T4 are turned on.

[0186] When the third transistor T3 is turned on, the high potential driving voltage EVDD connected to the fourth node N4 is applied to the first electrode of the driving transistor DT connected to the second node N2 through the third transistor T3. The driving current Id supplied from the driving transistor DT to the light emitting element OLED ( Figure 4 in which the light emitting element OLED is simply shown as a diode ED) is not related to the value of the threshold voltage Vth of the driving transistor DT, so that the threshold voltage Vth of the driving transistor DT is compensated and operated.

[0187] Next, the operations of the pixel circuit and the light emitting element during the holding period will be described with reference to Figure 5B ​

[0188] The holding period may include at least one bias portion Tobs3 and Tobs4 and a light-emitting portion Te'. A description of the operation of the pixel circuit that is the same as the operation of the refresh period will be omitted.

[0189] As described above, the difference is that during the refresh period, a new data voltage Vdata is charged and the new data voltage Vdata is applied to the gate electrode of the driving transistor DT, while during the holding period, the data voltage Vdata of the refresh period is maintained and used in a sound manner. Therefore, different from the refresh period, the holding period does not require an initialization portion Ti and a sampling portion Ts.

[0190] During the operation in the holding period, only one-time turn-on bias stress OBS operation may be sufficient. However, in the present embodiment, for the convenience of the driving circuit, the third scan signal SC3(n) in the holding period operates in the same manner as the third scan signal SC3(n) in the refresh period. Therefore, the turn-on bias stress OBS operation can be operated twice as in the refresh period.

[0191] Refer to Figure 5A The operation in the described refresh period is different from the driving signals in the Figure 5B holding period in terms of the second scan signal SC2(n) and the fourth scan signal SC4(n). Since the initialization portion Ti and the sampling portion Ts are not required in the holding period, different from the refresh period, the second scan signal SC2(n) is always a high voltage, and the fourth scan signal SC4(n) is always a low voltage. That is, the second transistor T2 and the seventh transistor T7 are always turned off.

[0192] Figure 6 is a view showing a gate driver including a gate input circuit according to an embodiment of the present disclosure.

[0193] According to this embodiment, the gate driver may include a plurality of in-panel gate circuits (GIP circuits). The GIP circuits may be formed at one side edge or two opposite side edges of the display panel. The GIP circuits include a plurality of stages to which a start pulse and a shift clock are input. These stages generate outputs in response to the start pulse and shift the outputs based on the shift clock. The plurality of stages are included in a shift register.

[0194] A stage of the shift register includes a Q node for charging a gate pulse, a QB node for discharging the gate pulse, and a switching circuit connected to the Q node and the QB node. The switching circuit increases the voltage of the gate pulse by charging the Q node in response to a start pulse or an output of a previous stage, and discharges the QB node in response to an output of a next stage or a reset signal. The switching circuit includes a TFT of a metal-oxide-semiconductor field-effect transistor (MOSFET) structure.

[0195] The shift register includes a plurality of stages connected dependently. These stages output first to nth scan pulses (n is a natural number of 2 or greater) respectively. The scan pulses also serve as carry signals applied to the gate lines of the display device and transmitted to the front stage and the back stage simultaneously. In the following description, the front stage is located above the stage as a reference stage, and the back stage is located below the stage as a reference stage.

[0196] Referring to Figure 6 , the shift register outputs scan pulses sequentially. The shift clocks delayed sequentially are input to the first to nth stages, and the scan pulses are output sequentially based on the shift clocks.

[0197] The stages of the shift register start to output scan pulses in response to a start pulse, and shift the scan pulses in response to the shift clocks. The scan pulses output from each stage are supplied to the gate lines and simultaneously input to the next stage as pre-carry signals. The pre-carry signals are used to pre-charge the Q nodes to generate outputs from each stage. In this case, the pre-carry signals are not input to the foremost stage of a group of stages, and the start pulse is input to the foremost stage. Additionally, after generating the output signals, each stage receives a post-carry signal for discharging the Q nodes. However, the post-carry signals are not input to the nth stage which is the rearmost stage.

[0198] According to an embodiment of the present disclosure, each of the plurality of GIP circuits may include a plurality of stages including a foremost stage and a rearmost stage. For example, the first GIP circuit may include a plurality of stages (e.g., the first to qth stages (q is a natural number of 2 or greater)), and the second GIP circuit may include another plurality of stages (e.g., the q + 1th to rth stages (r is a natural number of q + 2 or greater)). As a reference, in the following description, the front GIP circuit is located above the GIP circuit as a reference GIP circuit, and the back GIP circuit is located below the GIP circuit as a reference GIP circuit. The foremost GIP circuit is located at the uppermost end of the gate driver, and the rearmost GIP circuit is located at the lowermost end of the gate driver.

[0199] According to an embodiment of the present disclosure, the frontmost stage of the GIP circuit may receive a start pulse or a precharge signal, and the precharge signal may be provided from the rearmost stage of the front-end GIP circuit. At least some of the plurality of GIP circuits receive the start pulse, and some of the remaining GIP circuits receive the precharge signal from the rearmost stage of the front-end GIP circuit.

[0200] According to an embodiment of the present disclosure, the GIP circuit that can receive the start pulse is electrically connected to the gate input circuit. In contrast, the GIP circuit that can receive the precharge signal may be electrically connected to an adjacent GIP circuit and not to the gate input circuit.

[0201] The GIP circuit that can receive the start pulse may adjust the frequency for outputting the scan pulse based on the start pulse provided from the gate input circuit. As described above, when the frequency is adjusted, the display area corresponding to the GIP circuit fabricated before the frequency is adjusted by the gate input circuit may operate at a first driving frequency, and the display area corresponding to the GIP circuit fabricated after the frequency is adjusted may operate at a second driving frequency. In this application, a partial area of the display area may operate at a low frequency while another area may operate at a high frequency. Additionally, in this application, the area of the display area to operate at a specific frequency (e.g., high frequency, low frequency, or intermediate frequency) may be specified by controlling the gate input circuit.

[0202] According to an embodiment of the present disclosure, the gate input circuit may receive a high-frequency (HF) start pulse. In this specification, the HF start pulse may be referred to as the (first) start pulse corresponding to high-frequency operation. The gate input circuit may provide the HF start pulse to the GIP circuit based on a variable-frequency enable (VF enable) signal and an EM signal EM out. The GIP circuit that receives the HF start pulse supports high-frequency operation. The principle of supplying the HF start pulse in response to the VF enable signal and the EM signal will be described below with reference to Figures 7 to 9D Describe the principle of supplying the HF start pulse in response to the VF enable signal and the EM signal.

[0203] According to an embodiment of the present disclosure, the gate input circuit may receive a low-frequency (LF) start pulse. In this specification, the LF start pulse may be referred to as the (second) start pulse corresponding to low-frequency operation. The gate input circuit may provide the LF start pulse corresponding to VGH to the GIP circuit based on a low-frequency enable (LF enable) signal. In this specification, for ease of description, the term "start pulse" may be referred to as "VST".

[0204] A gate driver according to an embodiment of the present disclosure includes at least one of gate input circuits, and at least one of the gate input circuits is configured to selectively output a first start pulse HF VST corresponding to a high-frequency operation and a second start pulse LF VST corresponding to a low-frequency operation to any one of a plurality of dependent-connected stages. At least one of the plurality of stages may be connected to the gate input circuit and receive any one of the first start pulse HF VST and the second start pulse LF VST output by the gate input circuit. Based on the stage to which at least one of the gate input circuits is connected, at least one of the gate input circuits may be dependently connected to an output at the front end of the stage.

[0205] According to an embodiment of the present disclosure, the gate input circuit may be electrically connected to an HF VST line HVL that provides HF VST. The gate input circuit may supply the HF VST provided from the HF VST line HVL to the stage based on a VF enable signal and an EM signal.

[0206] According to an embodiment of the present disclosure, the gate input circuit may be provided within the same period as the turn-off of the EM signal. For example, when the turn-off of the EM signal is 4HT (horizontal time), the gate input circuit may be provided for four GIP lines. For example, when the turn-off of the EM signal is 4HT (horizontal time), the gate input circuit may be provided for four stages.

[0207] Hereinafter, a gate input circuit according to an embodiment of the present disclosure will be described. The gate input circuit is configured to output VST to a GIP circuit. The GIP circuit receives the VST and controls a corresponding display area at a driving frequency corresponding to the VST.

[0208] Figure 7 is a view showing a gate input circuit of a display device according to an embodiment of the present disclosure. Figures 8A to 8C is a waveform diagram showing a frequency division drive of a display device according to an embodiment of the present disclosure. Figures 9A to 9D is a view for explaining an operation sequence of a gate input circuit according to an embodiment of the present disclosure.

[0209] The gate input circuit includes a plurality of transistors and capacitors. A transistor is a three - electrode element including a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. In the transistor, carriers start to flow out from the source. The drain is the electrode through which carriers are released from the transistor to the outside. In the transistor, carriers flow from the source to the drain. Since carriers are electrons in the case of an n - channel transistor, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n - channel transistor, current flows from the drain to the source. Since carriers are positive holes in a p - channel transistor (PMOS), the source voltage is higher than the drain voltage so that positive holes can flow from the source to the drain. Since in a p - channel transistor, positive holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change according to the applied voltage. Therefore, the present disclosure is not limited by the source and drain of the transistor. In the present disclosure, for convenience, the source and drain can refer to the source - drain electrode (SD electrode) without distinguishing between them. The SD electrode can refer to either the source or the drain.

[0210] According to an embodiment of the present disclosure, the plurality of transistors may include a plurality of PMOS transistors and a plurality of NMOS transistors. For example, the plurality of transistors may include a first NMOS transistor to a fourth NMOS transistor NT1, NT2, NT3, and NT4 and a first PMOS transistor to a third PMOS transistor OT1, OT2, and OT3. The first NMOS transistor to the fourth NMOS transistor NT1, NT2, NT3, and NT4 may be implemented as PMOS transistors, and the first PMOS transistor to the third PMOS transistor OT1, OT2, and OT3 may be implemented as NMOS transistors. The present disclosure is not limited thereto. The PMOS transistor may be an oxide TFT. The present disclosure is not limited by the type of transistor.

[0211] Referring to Figure 7 , according to an embodiment of the present disclosure, at least one in the gate input circuit may be configured to receive a VF enable signal, an LF enable signal, and an EM signal, and output any one of a first start pulse HF VST and a second start pulse LF VST based on the VF enable signal, the LF enable signal, and the EM signal. Return to reference Figure 6 , at least one in the gate input circuit may be electrically connected to a VF enable line VEL configured to supply a VF enable signal, and electrically connected to an LF enable line LEL configured to supply an LF enable signal.

[0212] As described below, by synchronizing with the switching of the EM signal from a low level to a high level, the VF enable signal can be switched from a high level to a low level. According to this embodiment, the gate input circuit can output a first start pulse HF VST corresponding to a high-frequency operation in a portion before the potential of the LF enable signal decreases from the time point when the VF enable signal is switched. The gate input circuit can output a second start pulse LFVST corresponding to a low-frequency operation in a portion where the potential of the LF enable signal decreases. In addition, the gate input circuit can output a normal start pulse corresponding to a low-frequency operation before the VF enable signal is switched. The gate input circuit can output a first start pulse HFVST corresponding to a high-frequency operation in response to the switching of the VF enable signal.

[0213] Hereinafter, embodiments of the present disclosure will be described in detail with reference to detailed circuit diagrams. In this specification, the output VST supplied to the GIP circuit can be supplied to a stage connected to the gate input circuit.

[0214] Referring to Figure 7 , according to an embodiment of the present disclosure, a variable frequency enable (VF enable) signal VF ENABLE, a low frequency enable (LF enable) signal LF ENABLE, an HF start pulse HF VST, a front-end stage output voltage SRO, a gate low voltage VGL, a gate high voltage VGH, and / or an EM signal EM Out are input to the gate input circuit.

[0215] The gate electrode of the first NMOS transistor NT1 receives the VF enable signal and is turned on or off by the voltage level of the VF enable signal. Any one of the SD electrodes of the first NMOS transistor NT1 can receive the EM signal, and the other of the SD electrodes of the first NMOS transistor NT1 can be electrically connected to the second PMOS transistor OT2 and supply the EM signal to the gate electrode of the second PMOS transistor OT2.

[0216] The gate electrode of the first PMOS transistor OT1 receives the VF enable signal and is turned on or off by the voltage level of the VF enable signal. Any one of the SD electrodes of the first PMOS transistor OT1 can receive the gate low voltage VGL, and the other of the SD electrodes of the first PMOS transistor OT1 can be electrically connected to the second PMOS transistor OT2 and supply the gate low voltage VGL to the gate electrode of the second PMOS transistor OT2. At the same time, any one of the SD electrodes of the first PMOS transistor OT1 can also be electrically connected to the gate electrode of the second NMOS transistor NT2. Therefore, the gate low voltage VGL can be supplied to both the SD electrode of the first PMOS transistor OT1 and the gate electrode of the second NMOS transistor NT2.

[0217] The gate electrodes of the first NMOS transistor NT1 and the first PMOS transistor OT1 share a node and receive a VF enable signal from a node. The channel polarities of the first NMOS transistor NT1 and the first PMOS transistor OT1 are different. Therefore, when any one of the first NMOS transistor NT1 and the first PMOS transistor OT1 is turned on by the VF enable signal, the other of the first NMOS transistor NT1 and the first PMOS transistor OT1 is turned off.

[0218] The VF enable signal can be supplied through Figure 6 the VF enable line shown. The VF enable line can be electrically connected to the gate input circuit and supply the VF enable signal to the gate input circuit.

[0219] As described above, the gate electrode of the second NMOS transistor NT2 is connected to the gate low voltage VGL. When the gate low voltage is applied, the second NMOS transistor NT2 is maintained in the on state. Any one of the source-drain (SD) electrodes of the second NMOS transistor NT2 is electrically connected to the SD electrode of the first PMOS transistor OT1, and the other of the SD electrodes of the second NMOS transistor NT2 is connected to the gate electrode of the third NMOS transistor NT3. When the first PMOS transistor OT1 is maintained in the on state, the gate low voltage is transmitted through the first PMOS transistor OT1 to the SD electrode of the second NMOS transistor NT2. In this case, since the second NMOS transistor NT2 is maintained in the on state, the gate low voltage is finally supplied as the gate voltage of the third NMOS transistor NT3 through the first PMOS transistor OT1 and the second NMOS transistor NT2.

[0220] As described above, the gate electrode of the second PMOS transistor OT2 is connected to the SD electrode of the first PMOS transistor OT1 and the SD electrode of the first NMOS transistor NT1, and shares a node with the SD electrode of the first PMOS transistor OT1 and the SD electrode of the first NMOS transistor NT1. Additionally, any one of the SD electrodes of the second PMOS transistor OT2 is connected to HF VST, and the other of the SD electrodes of the second PMOS transistor OT2 is connected to the SD electrode of the third PMOS transistor OT3 and the SD electrode of the third NMOS transistor NT3, and shares a node with the SD electrode of the third PMOS transistor OT3 and the SD electrode of the third NMOS transistor NT3.

[0221] When the second PMOS transistor OT2 receives the low-level voltage of the EM signal EM out, the second PMOS transistor OT2 is maintained in the off state. When the second PMOS transistor OT2 is maintained in the off state, HF VST is blocked by the second PMOS transistor OT2.

[0222] The second PMOS transistor OT2 operates in an on state in response to receiving a high-level voltage EM signal EM out. When the second PMOS transistor OT2 is maintained in the on state, HF VST is supplied to the SD electrode of the third PMOS transistor OT3. When the third PMOS transistor OT3 is in the on state, HF VST can be supplied as output VST to the GIP circuit. When the third PMOS transistor OT3 is in the off state, the supply of HF VST can be cut off by the third PMOS transistor OT3.

[0223] HF VST can be supplied through Figure 6 the HF VST line HVL shown. The HF VST line can be electrically connected to the gate input circuit and supply HF VST to the gate input circuit.

[0224] As described above, the gate electrode of the third NMOS transistor NT3 is connected to the SD electrode of the second NMOS transistor NT2. Additionally, any one of the SD electrodes of the second NMOS transistor NT2 is connected to SRO, and the other of the SD electrodes of the second NMOS transistor NT2 is connected to the SD electrodes of the second PMOS transistor OT2 and the third PMOS transistor while sharing a node.

[0225] When the third NMOS transistor NT3 is maintained in the on state, the third NMOS transistor NT3 supplies a signal corresponding to SRO to the SD electrode of the third PMOS transistor OT3. When the third PMOS transistor OT3 is maintained in the on state, the signal corresponding to SRO can become VST through the third NMOS transistor NT3 (i.e., the signal can be supplied as output VST to the GIP circuit).

[0226] The gate electrode of the third PMOS transistor OT3 receives an LF enable signal and is turned on or off by the LF enable signal. Any one of the SD electrodes of the third PMOS transistor OT3 is connected to the SD electrodes of the second PMOS transistor OT2 and the third NMOS transistor NT3, and the other of the SD electrodes of the third PMOS transistor OT3 is connected to the GIP circuit (or any one of multiple stages of the GIP circuit).

[0227] The second PMOS transistor OT2 may supply a signal corresponding to HF VST to the SD electrode of the third PMOS transistor OT3, and the third NMOS transistor NT3 may supply a signal corresponding to SRO to the SD electrode of the third PMOS transistor OT3. When the third PMOS transistor OT3 is maintained in the on state, the third PMOS transistor OT3 may supply any one of the signal corresponding to HF VST or the signal corresponding to SRO as the output VST to the GIP circuit.

[0228] The gate electrode of the fourth NMOS transistor NT4 receives the LF enable signal and is turned on or off by the LF enable signal. Any one of the SD electrodes of the fourth NMOS transistor NT4 is connected to VGH, and the other of the SD electrodes of the fourth NMOS transistor NT4 is connected to the GIP circuit (or any one of multiple stages of the GIP circuit). The gate electrode of the fourth NMOS transistor NT4 may share substantially the same node with the gate electrode of the third PMOS transistor OT3. Accordingly, when the third PMOS transistor OT3 is on, the fourth NMOS transistor NT4 may be off, and when the third PMOS transistor OT3 is off, the fourth NMOS transistor NT4 may be on.

[0229] The LF enable signal may be supplied through Figure 6 the LF enable line LEL shown. The LF enable line may be electrically connected to the gate input circuit and supply the LF enable signal to the gate input circuit.

[0230] Referring to Figure 7 and Figure 8A , the display device according to an embodiment of the present disclosure operates with a normal VST in a first frame. In the first frame, the display device operates at a driving frequency corresponding to the normal VST from the first gate line to the last gate line.

[0231] Referring to Figure 7 , Figure 8A and Figure 9A , in the first frame, the VF enable signal and the LF enable signal are controlled by a DC high level voltage.

[0232] Since the VF enable signal is controlled by the DC high level voltage, the first NMOS transistor NT1 is turned off and the first PMOS transistor OT1 is turned on. The gate low voltage turns on the third NMOS transistor NT3 through the first PMOS transistor OT1 and the second NMOS transistor NT2. In this case, the second NMOS transistor NT2 is turned on by the gate low voltage. When the third NMOS transistor NT3 is turned on, the signal corresponding to SRO may be output as VST and supplied to the stage. The signal corresponding to SRO may be the output of the front stage of the stage to which VST is supplied.

[0233] In addition, in the first frame, the LF enable signal is controlled by a DC high-level voltage, causing the third PMOS transistor OT3 to conduct and the fourth NMOS transistor NT4 to turn off. When the fourth NMOS transistor NT4 is turned off, the signal corresponding to VGH cannot be output, and when the third PMOS transistor OT3 conducts, the signal corresponding to SRO is output as VST.

[0234] Refer to Figure 7 and Figure 8A , in the second frame, the potential of the VF enable signal in a specific gate line decreases (from high to low). As the potential of the VF enable signal in the specific gate line decreases, the gate input circuit operates as a logic circuit starting from the second frame. In the following description, it is assumed that the second frame operates at a low frequency from the first gate line to the M-1th gate line, at a high frequency from the Mth gate line to the N-1th gate line, and again at a low frequency from the Nth gate line to the last gate line.

[0235] Refer to Figure 7 , Figure 8A and Figure 9B , in the second frame, from the first gate line to the M-1th gate line, the VF enable signal is supplied as a high-level voltage, the LF enable signal is supplied as a high-level voltage, and the EM signal is supplied as a low-level voltage to the gate input circuit.

[0236] Through the VF enable signal of the high-level voltage, the first PMOS transistor OT1 conducts and the first NMOS transistor NT1 turns off. Through the LF enable signal of the high-level voltage, the third PMOS transistor OT3 conducts and the fourth NMOS transistor NT4 turns off.

[0237] The signal corresponding to the gate low voltage is input to the second PMOS transistor OT2 and the third NMOS transistor NT3 through the first PMOS transistor OT1. In addition, the signal corresponding to the gate low voltage is directly input to the second NMOS transistor NT2 without passing through the first PMOS transistor OT1. Through the signal corresponding to the gate low voltage, the second PMOS transistor OT2 turns off, the second NMOS transistor NT2 conducts, and the third NMOS transistor NT3 conducts.

[0238] When the second PMOS transistor OT2 turns off, the signal corresponding to HF VST is blocked, and when the fourth NMOS transistor NT4 turns off, the signal corresponding to the gate high voltage is blocked. When the third NMOS transistor NT3 conducts, the signal corresponding to SRO is output as VST through the third PMOS transistor OT3.

[0239] As described above, with respect to the stage before the VF enable signal switches from a high-level voltage to a low-level voltage, the gate input circuit outputs the output of the front-end stage as VST. Therefore, when the driving frequency of the gate line of the front-end stage is low, the driving frequency can be maintained in a complete manner.

[0240] Referring to Figure 7 、 Figure 8A and Figure 9C , in the second frame, in the M-th gate line, the VF enable signal is supplied as a low-level voltage, the LF enable signal is supplied as a high-level voltage, and the EM signal is supplied as a high-level voltage to the gate input circuit. The VF enable signal switches in synchronization with the switching of the EM signal. While the EM signal switches (potential increases) from a low-level voltage to a high-level voltage, the VF enable signal switches (potential decreases) from a high-level voltage to a low-level voltage.

[0241] Through the VF enable signal of low-level voltage, the first NMOS transistor NT1 is turned on, and the first PMOS transistor OT1 is turned off. Through the LF enable signal of high-level voltage, the third PMOS transistor OT3 is turned on, and the fourth NMOS transistor NT4 is turned off.

[0242] The second NMOS transistor NT2 is turned on by a signal corresponding to the gate low voltage.

[0243] The EM signal of high-level voltage is input to the second PMOS transistor OT2 and the third NMOS transistor NT3 through the first NMOS transistor NT1. The second PMOS transistor OT2 is turned on, and the third NMOS transistor NT3 is turned off. When the third NMOS transistor NT3 is turned off, the supply of the signal corresponding to SRO is cut off. When the second PMOS transistor OT2 is turned on, the signal corresponding to HF VST is output as the output VST through the third PMOS transistor OT3.

[0244] As described above, in response to the switching of the VF enable signal and the EM signal, the gate input circuit can block the signal corresponding to SRO that has been output to the front-end stage as the output VST, and re-output the signal corresponding to HF VST as the output VST. Therefore, before the potential of the LF enable signal decreases, the gate lines after the M-th gate line operate at a high frequency.

[0245] Return to reference Figure 7 、 Figure 8A and Figure 9B, in the second frame, before the potential of the LF enable signal decreases, the gate input circuit outputs a signal corresponding to the SRO signal of the front-end stage as output VST. From the (M + 1)-th gate line to the (N - 1)-th gate line, the VF enable signal is supplied as a high-level voltage, the LF enable signal is supplied as a high-level voltage, and the EM signal is supplied as a low-level voltage to the gate input circuit. Therefore, when the second PMOS transistor OT2 and the fourth NMOS transistor NT4 are turned off, the signal corresponding to HFVST and the signal corresponding to VGH are blocked, and the signal corresponding to SRO is supplied as output VST to the connected stage. Therefore, the display area from the (M + 1)-th gate line to the (N - 1)-th gate line operates at a high frequency.

[0246] Refer to Figure 7 , Figure 8A and Figure 9D , in the second frame, from the N-th gate line to the last gate line, the VF enable signal is supplied as a high-level voltage, the LF enable signal is supplied as a low-level voltage, and the EM signal is supplied as a low-level voltage to the gate input circuit. The potential of the LF enable signal decreases in the N-th gate line, and the LF enable signal is maintained as a low-level voltage from the N-th gate line to the last gate line.

[0247] Through the low-level voltage LF enable signal, the third PMOS transistor OT3 is turned off, and the fourth NMOS transistor NT4 is turned on. When the third PMOS transistor OT3 is turned off, the signal corresponding to the SRO output is blocked and cannot be output as output VST. When the fourth NMOS transistor NT4 is turned on, the signal corresponding to VGH is output as output VST. The display area of the N-th gate line to which the signal corresponding to VGH is input can operate at a low frequency.

[0248] As described above, the gate input circuit may include: a first PMOS transistor OT1 configured to provide a signal corresponding to the shift register output (SRO) of the front-end stage to a shared node in response to a high-level VF enable signal; and a first NMOS transistor NT1 configured to provide a first start pulse corresponding to high-frequency operation to the shared node in response to a low-level VF enable signal. When the LF enable signal is maintained at a high level, the signal corresponding to SRO or the first start pulse provided to the shared node may be output to the stage connected to the gate input circuit. In the portion where the LF enable signal is maintained at a low level, the signal corresponding to SRO or the first start pulse provided to the shared node may not be output to the stage, and a second start pulse corresponding to low-frequency operation may be output to the stage connected to the gate input circuit.

[0249] In this embodiment, in a portion where the LF enable signal is supplied to the gate electrodes of the third PMOS transistor OT3 and the fourth NMOS transistor NT4 and the LF enable signal is maintained at a high level, the third PMOS transistor OT3 may be turned on, and a start pulse output to the connected stage may be determined as a signal provided to the shared node. In addition, in a portion where the LF enable signal is maintained at a low level, the fourth NMOS transistor NT4 may be turned on, and a start pulse output to the connected stage may be determined as a second start pulse corresponding to a low frequency operation.

[0250] As described above, the gate input circuit according to an embodiment of the present disclosure can operate at a low frequency from the first gate line to the M-1th gate line, operate the display area corresponding to the portion from the M-1th gate line to the N-1th gate line at a high frequency by using a VF enable signal synchronized with the EM signal, and operate the display area corresponding to the portion from the N-1th gate line to the last gate line again at a low frequency by using a LF enable signal. The display device according to an embodiment of the present disclosure can change the display area operated at a high frequency and the display area operated at a low frequency as needed by using the gate input circuit.

[0251] Figure 8B The operation method of maintaining the LF enable signal at a DC high level is exemplarily shown. Figure 7 , Figure 8B as well as Figures 9A to 9D , in the case where the LF enable signal is maintained at a DC high level, the display area can be designated as a display area operating at a low frequency and a display area operating at a high frequency. Because the potential of the LF enable signal does not decrease, the display area can be operated at a high frequency from a specific gate line on which the VF enable signal and the EM signal are switched to the last gate line.

[0252] Meanwhile, in the above-mentioned embodiments, the case where the driving frequency corresponding to the normal VST is a low frequency has been exemplarily described. However, the driving frequency corresponding to the normal VST may be a high frequency. That is, in the first frame operated according to the normal VST, the display device may operate at a high frequency based on the normal VST. Figure 8C Describe the situation.

[0253] Figure 8C An operation method of continuously maintaining the VF enable signal at a DC high level is exemplarily shown. The display device according to the embodiment can operate the display area at a high frequency in response to supplying a normal VST to the GIP circuit.

[0254] Reference Figure 7 , Figure 8C as well as Figures 9A to 9D, in the entire gate line of the second frame, the VF enable signal is maintained at the DC high-level voltage. Accordingly, the first NMOS transistor NT1 and the second PMOS transistor OT2 are turned off, and the first PMOS transistor OT1, the second NMOS transistor NT2, and the third NMOS transistor NT3 are turned on. Accordingly, when the LF enable signal is supplied at the high-level voltage, the gate input circuit can output a signal corresponding to the SRO as the output VST. When the LF enable signal is lowered to the low-level voltage, the gate input circuit can output a signal corresponding to the VGH as the output VST. In the case where the potential of the LF enable signal is lowered in the Nth gate line, the display area corresponding to the portion from the first gate line to the (N-1)th gate line of the second frame can operate at a high frequency, and the display area corresponding to the portion from the Nth gate line to the last gate line can operate at a low frequency.

[0255] Exemplary embodiments of the present disclosure may also be described as follows:

[0256] A gate driver according to an embodiment of the present disclosure may include: a plurality of dependently connected stages; and at least one of gate input circuits, the at least one of the gate input circuits being configured to selectively output any one of a first start pulse corresponding to high-frequency operation and a second start pulse corresponding to low-frequency operation, wherein at least one of the plurality of stages is connected to the gate input circuit and receives any one of the first start pulse and the second start pulse output by the gate input circuit.

[0257] Based on the stage to which at least one of the gate input circuits can be connected, at least one of the gate input circuits can be dependently connected to the output at the front end of the stage.

[0258] At least one of the gate input circuits can receive a VF enable signal, an LF enable signal, and an EM signal, and can be configured to output any one of the first start pulse and the second start pulse based on the VF enable signal, the LF enable signal, and the EM signal.

[0259] At least one of the gate input circuits can be electrically connected to a VF enable line configured to supply a VF enable signal and an LF enable line configured to supply an LF enable signal.

[0260] In synchronization with the switching of the EM signal from the low level to the high level, the VF enable signal can be switched from the high level to the low level.

[0261] The gate input circuit can output the first start pulse corresponding to the high-frequency operation in a portion before the potential of the LF enable signal is lowered after the time point at which the VF enable signal can be switched.

[0262] The gate input circuit can output a second start pulse corresponding to the low-frequency operation in a portion where the potential of the LF enable signal decreases.

[0263] The gate input circuit can output a normal start pulse corresponding to the low-frequency operation before the VF enable signal can be switched, and the gate input circuit can output a first start pulse corresponding to the high-frequency operation in response to the switching of the VF enable signal.

[0264] The gate input circuit can include: a first PMOS transistor configured to provide a signal corresponding to the shift register output (SRO) of the front-end stage to a shared node in response to a high-level VF enable signal; and a first NMOS transistor configured to provide a first start pulse corresponding to the high-frequency operation to the shared node in response to a low-level VF enable signal, and wherein, when the LF enable signal can be maintained at a high level, the signal or the first start pulse corresponding to the SRO provided to the shared node can be output to the connected stage.

[0265] In a portion where the LF enable signal can be maintained at a low level, the signal or the first start pulse corresponding to the SRO provided to the shared node can not be output to the stage, and a second start pulse corresponding to the low-frequency operation can be output to the connected stage.

[0266] The LF enable signal can be supplied to the gate electrodes of a second PMOS transistor and a second NMOS transistor. The second PMOS transistor can be turned on in a portion where the LF enable signal can be maintained at a high level, and the start pulse output to the connected stage can be determined as the signal provided to the shared node.

[0267] The second NMOS transistor can be turned on in a portion where the LF enable signal can be maintained at a low level, and the start pulse output to the connected stage can be determined as the second start pulse corresponding to the low-frequency operation.

[0268] A display device according to another embodiment of the present disclosure can include: a display panel including a display area; a plurality of dependently connected stages; at least one of the gate input circuits, at least one of the gate input circuits being configured to selectively output any one of a first start pulse corresponding to the high-frequency operation and a second start pulse corresponding to the low-frequency operation; and a controller configured to control the gate driver, wherein at least one of the plurality of stages is connected to the gate input circuit and receives any one of the first start pulse and the second start pulse output by the gate input circuit.

[0269] At least one of the plurality of stages can control the corresponding display area at a driving frequency corresponding to the received start pulse.

[0270] Based on at least one connectable stage in the gate input circuit, at least one in the gate input circuit can be dependently connected to the output at the front end of the stage.

[0271] At least one in the gate input circuit can receive a VF enable signal, an LF enable signal, and an EM signal, and can be configured to output either a first start pulse or a second start pulse based on the VF enable signal, the LF enable signal, and the EM signal.

[0272] At least one in the gate input circuit can be electrically connected to a VF enable line configured to supply a VF enable signal and an LF enable line configured to supply an LF enable signal.

[0273] At least one of the gate input circuits includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a capacitor, wherein one of the source-drain (SD) electrodes of each of the first NMOS transistor, the first PMOS transistor, and the second NMOS transistor shares a first node, the first node is also connected to the gate of the second PMOS transistor, the other of the SD electrodes of the first NMOS transistor receives the EM signal, the other of the SD electrodes of the first PMOS transistor receives a low gate voltage, the low gate voltage is also provided to the gate of the second NMOS transistor, the other of the SD electrodes of the second NMOS transistor and one end of the capacitor share a second node, the second node is also connected to the gate of the third NMOS transistor, the other end of the capacitor is connected to a third node, one of the SD electrodes of each of the third NMOS transistor, the second PMOS transistor, and the third PMOS transistor shares the third node, the other of the SD electrodes of the third PMOS transistor and one of the SD electrodes of the fourth NMOS transistor share a fourth node, the other of the SD electrodes of the third NMOS transistor receives a normal start pulse corresponding to a low-frequency operation, the other of the SD electrodes of the second PMOS transistor receives a first start pulse corresponding to a high-frequency operation, the other of the SD electrodes of the fourth NMOS transistor receives a second start pulse corresponding to a low-frequency operation, and the fourth node serves as the output of the gate input circuit; and wherein the VF enable signal is provided to the gates of the first NMOS transistor and the first PMOS transistor, and the LF enable signal is provided to the gates of the fourth NMOS transistor and the third PMOS transistor.

[0274] The VF enable signal can be switched from a high level to a low level synchronously with the switching of the EM signal from a low level to a high level.

[0275] The gate input circuit can output a first start pulse corresponding to high-frequency operation in a portion before the potential of the LF enable signal decreases from the time point at which the VF enable signal can be switched.

[0276] The gate input circuit can output a second start pulse corresponding to low-frequency operation in a portion where the potential of the LF enable signal decreases.

[0277] The gate input circuit can output a normal start pulse corresponding to low-frequency operation before the VF enable signal can be switched, and the gate input circuit can output a first start pulse corresponding to high-frequency operation in response to the switching of the VF enable signal.

[0278] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto, and the present disclosure can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

Claims

1. A gate driver, comprising: multiple dependently connected levels; as well as at least one of the gate input circuits, the at least one of the gate input circuits being configured to selectively output one of a first start pulse corresponding to a high frequency operation and a second start pulse corresponding to a low frequency operation, At least one of the plurality of stages is connected to the gate input circuit and receives the one of the first start pulse and the second start pulse output by the gate input circuit.

2. The gate driver according to claim 1, in, Depending on the stage to which at least one of the gate input circuits is connected, at least one of the gate input circuits is dependently connected to an output of the stage at the front end.

3. The gate driver according to claim 1, in, At least one of the gate input circuits receives a VF enable signal, a LF enable signal, and an EM signal, and is configured to output one of the first start pulse and the second start pulse based on the VF enable signal, the LF enable signal, and the EM signal.

4. The gate driver according to claim 3, in, At least one of the gate input circuits is electrically connected to a VF enable line configured to supply the VF enable signal and a LF enable line configured to supply the LF enable signal.

5. The gate driver according to claim 3, in, The VF enable signal is switched from a high level to a low level in synchronization with the switching of the EM signal from a low level to a high level.

6. The gate driver according to claim 5, in, The gate input circuit outputs the first start pulse corresponding to the high-frequency operation in a section before the potential of the LF enable signal decreases from a time point when the VF enable signal is switched.

7. The gate driver according to claim 5, in, The gate input circuit outputs the second start pulse corresponding to the low-frequency operation in a section where the potential of the LF enable signal decreases.

8. The gate driver according to claim 5, in, The gate input circuit outputs a normal start pulse corresponding to the low frequency operation before the VF enable signal is switched, and the gate input circuit outputs the first start pulse corresponding to the high frequency operation in response to switching of the VF enable signal.

9. The gate driver according to claim 4, in, The gate input circuit comprises: a first PMOS transistor configured to provide a signal corresponding to a shift register output (SRO) of a front-end stage to a shared node in response to a high-level VF enable signal; and a first NMOS transistor configured to provide the first start pulse corresponding to the high frequency operation to the shared node in response to a low level VF enable signal, and When the LF enable signal is maintained at a high level, the signal corresponding to the SRO or the first start pulse provided to the shared node is output to the connected stage.

10. The gate driver according to claim 9, in, In the interval in which the LF enable signal is maintained at a low level, the signal corresponding to the SRO or the first start pulse supplied to the shared node is not output to the stage, and the second start pulse corresponding to the low frequency operation is output to the connected stage.

11. The gate driver according to claim 10, in, The LF enable signal is supplied to gate electrodes of the second PMOS transistor and the second NMOS transistor, the second PMOS transistor is turned on in a section where the LF enable signal is maintained at a high level, and a start pulse output to the connected stage is determined as a signal supplied to the shared node.

12. The gate driver according to claim 11, in, The second NMOS transistor is turned on in a section in which the LF enable signal is maintained at a low level, and a start pulse output to the connected stage is determined to be the second start pulse corresponding to the low frequency operation.

13. A display device, comprising: A display panel including a display area; multiple dependently connected levels; at least one of the gate input circuits, the at least one of the gate input circuits being configured to selectively output one of a first start pulse corresponding to a high frequency operation and a second start pulse corresponding to a low frequency operation; as well as a controller configured to control a gate driver, At least one of the plurality of stages is connected to the gate input circuit and receives the one of the first start pulse and the second start pulse output by the gate input circuit.

14. The display device according to claim 13, wherein: At least one of the plurality of stages controls a corresponding display area at a driving frequency corresponding to the received start pulse.

15. The display device according to claim 13, in, Depending on the stage to which at least one of the gate input circuits is connected, at least one of the gate input circuits is dependently connected to an output of the stage at the front end.

16. The display device according to claim 13, in, At least one of the gate input circuits receives a VF enable signal, a LF enable signal, and an EM signal, and is configured to output one of the first start pulse and the second start pulse based on the VF enable signal, the LF enable signal, and the EM signal.

17. The display device according to claim 16, wherein: At least one of the gate input circuits comprises: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a capacitor, wherein: One of the source-drain (SD) electrodes of the first NMOS transistor, the first PMOS transistor, and the second NMOS transistor shares a first node, and the first node is also connected to the gate of the second PMOS transistor. The other of the SD electrodes of the first NMOS transistor receives the EM signal, the other of the SD electrodes of the first PMOS transistor receives a gate low voltage, the gate low voltage is also provided to the gate of the second NMOS transistor, the other of the SD electrodes of the second NMOS transistor and one end of the capacitor share a second node, the second node is also connected to the gate of the third NMOS transistor, and the other end of the capacitor is connected to a third node, One of the SD electrodes of the third NMOS transistor, the second PMOS transistor and the third PMOS transistor respectively shares a third node, the other of the SD electrodes of the third PMOS transistor and one of the SD electrodes of the fourth NMOS transistor shares a fourth node, the other of the SD electrodes of the third NMOS transistor receives a normal start pulse corresponding to a low frequency operation, the other of the SD electrodes of the second PMOS transistor receives a first start pulse corresponding to a high frequency operation, the other of the SD electrodes of the fourth NMOS transistor receives a second start pulse corresponding to a low frequency operation, and the fourth node serves as an output of the gate input circuit; and The VF enable signal is provided to the gates of the first NMOS transistor and the first PMOS transistor, and the LF enable signal is provided to the gates of the fourth NMOS transistor and the third PMOS transistor.

18. The display device according to claim 16, in, At least one of the gate input circuits is electrically connected to a VF enable line configured to supply the VF enable signal and a LF enable line configured to supply the LF enable signal.

19. The display device according to claim 16, in, The VF enable signal is switched from a high level to a low level in synchronization with the switching of the EM signal from a low level to a high level.

20. The display device according to claim 19, in, The gate input circuit outputs the first start pulse corresponding to the high-frequency operation in a section before the potential of the LF enable signal decreases from a time point when the VF enable signal is switched.

21. The display device according to claim 19, in, The gate input circuit outputs the second start pulse corresponding to the low-frequency operation in a section where the potential of the LF enable signal decreases.

22. The display device according to claim 19, in, The gate input circuit outputs a normal start pulse corresponding to the low frequency operation before the VF enable signal is switched, and the gate input circuit outputs the first start pulse corresponding to the high frequency operation in response to switching of the VF enable signal.

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