Pixel circuit and display device including same

Abstract

The invention discloses a pixel circuit and a display device including the same. The pixel circuit includes: a driving element including a first electrode connected to a first power line, a gate electrode connected to a first node, and a second electrode connected to a second node; a switching element configured to supply a data voltage to the first node in response to a gate signal; a capacitor connected between the first node and the second node; and a first light-emitting element and a second light-emitting element connected in parallel between the second node and the second power line, in which the first light-emitting element and the second light-emitting element have different threshold voltages.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0197814, filed on December 29, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a pixel circuit and a display device including the pixel circuit. Background art

[0004] Display devices include liquid crystal display (LCD) devices, electroluminescent display devices, field emission display (FED) devices, plasma display panels (PDPs), etc.

[0005] According to the material of the light - emitting layer, electroluminescent display devices are classified into inorganic light - emitting display devices and organic light - emitting display devices. An active - matrix organic light - emitting display device includes an organic light - emitting diode that emits light by itself (hereinafter referred to as "OLED"), and has advantages such as a fast response speed, high luminous efficiency, high brightness, and a wide viewing angle.

[0006] Some display devices in display devices, such as liquid crystal display devices or organic light - emitting display devices, include: a display panel including a plurality of sub - pixels; a driver that outputs a driving signal for driving the display panel; a power supply that generates power to be supplied to the display panel or the driver, etc. The driver includes: a gate driver that supplies a gate signal such as a scan signal and an emission signal to the display panel; and a data driver that supplies a data signal to the display panel. Summary of the invention

[0007] Pixels may include red pixels, green pixels, and blue pixels. In this case, in order to efficiently improve the weak light emission caused by even slight leakage current in the low - brightness part of green pixels, or to improve the low lifetime of blue pixels, a pixel is composed of two pixel circuits so as to divide it into two pixels to form a light - emitting region.

[0008] However, it is necessary to configure a driving circuit for separately driving two light - emitting elements, as well as separate pixel data and wirings for each driving circuit, making the circuit relatively complex.

[0009] The present disclosure aims to solve all the above - mentioned inevitable situations and problems.

[0010] The present disclosure provides a pixel circuit having a simple structure and a display device including the pixel circuit.

[0011] It should be noted that the object of the present disclosure is not limited to the above objects, and according to the following description, other objects of the present disclosure will be apparent to those skilled in the art.

[0012] A pixel circuit according to an embodiment of the present disclosure may include: a driving element including a first electrode connected to a first power line, a gate electrode connected to a first node, and a second electrode connected to a second node; a switching element configured to supply a data voltage to the first node in response to a gate signal; a capacitor connected between the first node and the second node; and a first light-emitting element and a second light-emitting element connected in parallel between the second node and a second power line, wherein the first light-emitting element and the second light-emitting element have different threshold voltages.

[0013] A pixel circuit according to an embodiment of the present disclosure may include: a driving element including a first electrode connected to a first power line, a gate electrode connected to a first node, and a second electrode connected to a second node; a first switching element configured to supply a data voltage to the first node in response to a gate signal; a capacitor connected between the first node and the second node; a first light-emitting element and a second light-emitting element connected in parallel between the second node and a second power line; and a second switching element configured to selectively connect the second node to the second light-emitting element in response to a control signal.

[0014] A display device according to an embodiment of the present disclosure may include: a display panel in which a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixel circuits are arranged, wherein each of the plurality of pixel circuits includes: a driving element including a first electrode connected to a first power line, a gate electrode connected to a first node, and a second electrode connected to a second node; a switching element configured to supply a data voltage to the first node in response to a gate signal; a capacitor connected between the first node and the second node; and a first light-emitting element and a second light-emitting element connected in parallel between the second node and a second power line, wherein the first light-emitting element and the second light-emitting element have different threshold voltages.

[0015] A display device according to an embodiment of the present disclosure may include: a display panel in which a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixel circuits are arranged; a data driver configured to apply a data voltage to the data lines; a gate driver configured to apply a gate signal to the gate lines; and a timing controller configured to control the data driver and the gate driver, wherein each of the plurality of pixel circuits includes: a driving element including a first electrode connected to a first power line, a gate electrode connected to a first node, and a second electrode connected to a second node; a first switching element configured to supply a data voltage to the first node in response to a gate signal; a capacitor connected between the first node and the second node; a first light-emitting element and a second light-emitting element connected in parallel between the second node and a second power line; and a second switching element configured to selectively connect the second node to the second light-emitting element in response to a control signal.

[0016] According to the present disclosure, two light-emitting elements having different threshold voltages may be connected in parallel to allow one light-emitting element or both light-emitting elements to emit light based on the voltage level of a data voltage, thereby ensuring luminance uniformity at low gray levels.

[0017] According to the present disclosure, driving of two light-emitting elements may be controlled by adding one switching element, such that it is possible to freely determine whether to operate a pixel.

[0018] According to the present disclosure, stacked structures of two identical light-emitting elements are formed adjacent to each other, but an anode electrode is separated by a switch, such that a phenomenon of light emission due to leakage current may be reduced.

[0019] According to the present disclosure, anode electrodes of light-emitting elements composed of the same fine metal mask (FMM) are separated by a switch, such that it is possible to be freely designed without being affected by FMM alignment problems.

[0020] According to the present disclosure, power consumption may be reduced due to a simple circuit configuration.

[0021] The effects of this specification are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art by referring to the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0023] Figure 1is a block diagram showing a display device according to an embodiment of the present disclosure;

[0024] Figure 2 is showing Figure 1 a cross-sectional view showing a cross-sectional structure of the display panel shown;

[0025] Figure 3 is a diagram showing a pixel circuit according to a first embodiment of the present disclosure;

[0026] Figure 4 is showing Figure 3 a diagram showing the operating voltages of the first light-emitting element and the second light-emitting element shown;

[0027] Figures 5 to 6 is showing Figure 3 a diagram showing the operating principle of the pixel circuit shown;

[0028] Figure 7 is a diagram showing a pixel circuit according to a second embodiment of the present disclosure;

[0029] Figures 8 to 11 is showing Figure 7 a diagram showing the operating principle of the pixel circuit shown; and

[0030] Figures 12 to 14 is a diagram showing an OLED structure used as a light-emitting element. Detailed Embodiments

[0031] With reference to the preferred embodiments described in detail in conjunction with the accompanying drawings, the advantages and features of this specification and the methods for achieving them will become apparent. However, this specification is not limited to the embodiments to be described below and can be implemented in different forms. The embodiments are provided only to fully disclose the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art, and this specification is defined by the disclosed claims.

[0032] Since the shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present disclosure are only exemplary, the present disclosure is not limited to the items shown. Throughout the specification, the same reference numerals indicate the same components. In addition, when determining that a detailed description of related known technologies may unnecessarily obscure the gist of the present disclosure, the detailed description thereof will be omitted.

[0033] When using "comprising", "having", "consisting of", etc. mentioned in this specification, other parts can be added unless "only" is used. Unless otherwise clearly stated, the case of expressing components in the singular form includes the plural form.

[0034] When explaining components, it should be understood that even in the absence of a separate and explicit description, an error range is included.

[0035] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described as "on...", "upper part", "lower part", "adjacent to...", etc., unless "immediately" or "directly" is used, one or more other parts may be located between these two parts.

[0036] Although "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, within the technical spirit of the present disclosure, the first component mentioned below may also be the second component.

[0037] Throughout the present disclosure, the same reference numerals may refer to substantially the same elements.

[0038] The following embodiments may be partially or wholly joined or combined with each other and may be linked and operated in various technical ways. The embodiments may be executed independently or in association with each other.

[0039] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0040] In the display device of the present disclosure, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistors may be implemented as oxide thin film transistors (oxide TFTs) including oxide semiconductors, low temperature polysilicon (LTPS) TFTs including low temperature polysilicon, etc.

[0041] A transistor is a three - electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In a transistor, carriers flow starting from the source. The drain is an electrode through which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n - channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, so that electrons can flow from the source to the drain. The n - channel transistor has a current direction flowing from the drain to the source. In the case of a p - channel transistor (p - channel metal - oxide - semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p - channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed according to the applied voltage. Therefore, the present disclosure is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0042] The gate signal swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0043] The transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate-high voltage, and the gate-off voltage may be a gate-low voltage. In the case of a p-channel transistor, the gate-on voltage may be a gate-low voltage, and the gate-off voltage may be a gate-high voltage.

[0044] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure, and Figure 2 is a cross-sectional view showing Figure 1 the cross-sectional structure of the display panel shown.

[0045] Referring to Figure 1 and Figure 2 According to an embodiment of the present disclosure, a display device includes: a display panel 100; a display panel driving unit configured to write pixel data into pixels of the display panel 100; and a power supply unit 140 configured to generate power required to drive the pixels and the display panel driving unit.

[0046] The display panel 100 includes a pixel array AA that displays an input image. The pixel array AA includes: a plurality of data lines 102; a plurality of gate lines 103 intersecting the data lines 102; and pixels arranged in a matrix form.

[0047] The pixel array AA includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of pixels arranged in the pixel array AA of the display panel 100 in the row direction X. The pixels arranged in one pixel row share the gate line 103. The sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period 1H is a time obtained by dividing one frame period by the total number of the pixel rows L1 to Ln.

[0048] A touch sensor may be provided on the display panel 100. A separate touch sensor may be used to sense a touch input, or a touch input may be sensed through pixels. The touch sensor may be provided on the screen of the display panel as an on-cell type or an add-on type, or may be implemented as an in-cell type touch sensor embedded in the pixel array AA.

[0049] The display panel 100 can be implemented as a flexible display panel. The flexible display panel can be made of a plastic OLED panel. An organic film can be provided on the backplane of the plastic OLED panel, and a pixel array AA can be formed on the organic film.

[0050] The backplane of the plastic OLED can be a polyethylene terephthalate (PET) substrate. The organic film is formed on the backplane. The pixel array AA and the touch sensor array can be formed on the organic film. The backplane blocks moisture penetration so that the pixel array AA is not exposed to moisture. The organic film can be a thin polyimide (PI) film substrate. A multi-layer buffer film can be formed of an insulating material (not shown) on the organic film. Lines can be formed on the organic film to supply power or signals applied to the pixel array AA and the touch sensor array.

[0051] To achieve colors, each of the pixels can be divided into a red sub-pixel (hereinafter referred to as "R sub-pixel"), a green sub-pixel (hereinafter referred to as "G sub-pixel"), and a blue sub-pixel (hereinafter referred to as "B sub-pixel"). Each of the pixels can also include a white sub-pixel. Each of the sub-pixels 101 includes a pixel circuit. The pixel circuit is connected to a data line 102 and a gate line 103.

[0052] The cross-sectional structure of the display panel 100 can include a circuit layer CIR, a light-emitting element layer EMIL, and a packaging layer ENC stacked on a substrate SUBS, as Figure 2 shown.

[0053] The circuit layer CIR can include: a thin-film transistor (TFT) array that includes pixel circuits connected to wirings such as data lines, gate lines, power lines, etc.; and gate drivers 410 and 420. The circuit layer CIR includes a plurality of metal layers insulated by an interposed insulating layer, and a semiconductor material layer. All the transistors formed in the circuit layer CIR can be implemented as n-channel oxide TFTs.

[0054] The light-emitting element layer EMIL can include light-emitting elements driven by the pixel circuits. The light-emitting elements can include light-emitting elements of red sub-pixels, light-emitting elements of green sub-pixels, and light-emitting elements of blue sub-pixels. The light-emitting element layer EMIL can also include light-emitting elements of white sub-pixels. The light-emitting element layer EMIL corresponding to each of the sub-pixels can have a structure in which a light-emitting element and a color filter are stacked. The light-emitting elements EL in the light-emitting element layer EMIL can be covered by a plurality of protective layers including organic films and inorganic films.

[0055] The encapsulation layer ENC covers the light-emitting element layer EMIL to seal the circuit layer CIR and the light-emitting element layer EMIL. The encapsulation layer ENC may also have a multi-layer insulating film structure in which an organic film and an inorganic film are alternately stacked. The inorganic film blocks the penetration of moisture and oxygen. The organic film planarizes the surface of the inorganic film. When the organic layer and the inorganic layer are stacked in multiple layers, the movement path of moisture and oxygen becomes longer than that of a single layer, thereby effectively blocking the penetration of moisture and oxygen that affect the light-emitting element layer EMIL.

[0056] A touch sensor layer (not shown) may be formed on the encapsulation layer ENC, and a polarizing plate or a color filter layer may be provided thereon. The touch sensor layer may include a capacitive touch sensor that senses a touch input based on a change in capacitance before and after the touch input. The touch sensor layer may have a metal wiring pattern and an insulating film that form the capacitance of the touch sensor. The insulating film may insulate the area where the metal wiring patterns intersect and may planarize the surface of the touch sensor layer. The polarizing plate may improve visibility and contrast by converting the polarization of external light reflected by the metal in the touch sensor layer and the circuit layer. The polarizing plate may be implemented as a circular polarizing plate or a polarizing plate in which a linear polarizing plate and a phase retardation film are joined together. A cover glass may be attached to the polarizing plate. The color filter layer may include red, green, and blue color filters. The color filter layer may also include a black matrix pattern. The color filter layer may replace the polarizing plate by absorbing a part of the wavelength of the light reflected from the circuit layer and the touch sensor layer and may increase the color purity of the image reproduced in the pixel array.

[0057] The power supply unit 140 generates direct current (DC) power required to drive the display panel driving unit and the pixel array of the display panel 100 by using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply unit 140 may adjust the level of the input DC voltage applied from a host system (not shown) to generate a constant voltage (or DC voltage), such as a gamma reference voltage VGMA, a gate-on voltage VGH and VEH, a gate-off voltage VGL and VEL, a pixel driving voltage EVDD, a low-potential power voltage EVSS, an initialization voltage VINIT, and a reference voltage VREF. The gamma reference voltage VGMA is supplied to the data driver 110. The gate-on voltage VGH and VEH and the gate-off voltage VGL and VEL are supplied to the gate driver 120. Constant voltages such as the pixel driving voltage EVDD, the low-potential power voltage EVSS, the initialization voltage VINIT, and the reference voltage VREF may be supplied to the pixel 101 through a power line commonly connected to the pixel 101.

[0058] The display panel driving unit writes the pixel data of the input image into the pixels of the display panel 100 under the control of the timing controller (TCON) 130.

[0059] The display panel driving unit includes a data driver 110 and a gate driver 130.

[0060] A demultiplexer (DEMUX) may be provided between the data driver 110 and the data lines 102. Figure 1 The demultiplexer is omitted therefrom. The demultiplexer sequentially connects one channel of the data driver 110 to a plurality of data lines 102, and distributes the data voltage output from one channel of the data driver 110 to the data lines 102 in a time-division manner, thereby reducing the number of channels of the data driver 110.

[0061] The display panel driving circuit may further include a touch sensor driver for driving a touch sensor. Figure 1 The touch sensor driver is omitted therefrom. In a mobile device, the timing controller 130, the power supply unit 140, the data driver 110, etc. may be integrated into one driving integrated circuit (IC).

[0062] The data driver 110 generates a data voltage Vdata by converting the pixel data of the input image received from the timing controller 130 with a gamma compensation voltage using a digital-to-analog converter (DAC) in each frame period. The gamma reference voltage VGMA is divided for each gray level by a voltage divider circuit. The gamma compensation voltage divided from the gamma reference voltage VGMA is provided to the DAC of the data driver 110. The data voltage Vdata is output through an output buffer in each channel of the data driver 110.

[0063] In the data driver 110, the output buffer included in one channel may be connected to adjacent data lines 102 through a demultiplexer array 112 (not shown). The demultiplexer array 112 may be directly formed on the substrate of the display panel 100, or integrated with the data driver 110 into one driving IC.

[0064] The gate driver 120 may be implemented as an in-panel gate (GIP) circuit directly formed on the bezel BZ area of the display panel 100 together with the TFT array of the pixel array AA. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 may sequentially supply the gate signals to the gate lines 103 by shifting the gate signals using a shift register.

[0065] The timing controller 130 receives digital video data DATA of an input image and a timing signal synchronized with the digital video data DATA from a host system (not shown). The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock CLK, a data enable signal DE, etc. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of one horizontal period (1H).

[0066] The timing controller 130 multiplies the input frame frequency by i, and controls the operation timing of the display panel driving circuit at a frame frequency of input frame frequency × i (i is a positive integer greater than 0) Hz. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Phase Alternating Line) scheme.

[0067] Based on the timing signals Vsync, Hsync, and DE received from the host system, the timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a MUX signal for controlling the operation timing of the demultiplexer array 112, and a gate timing control signal for controlling the operation timing of the gate driver 120.

[0068] The voltage levels of the gate timing control signals output from the timing controller 130 can be converted into a gate-on voltage VGH and VEH and a gate-off voltage VGL and VEL by a level shifter (not shown), and then supplied to the gate driver 120. That is, the level shifter converts the low-level voltage of the gate timing control signal into the gate-off voltage VGL and VEL, and converts the high-level voltage of the gate timing control signal into the gate-on voltage VGH and VEH. The gate timing signal includes a start pulse and a shift clock.

[0069] The host system may include a motherboard of one of a television system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a vehicle system, and a mobile device system. In this case, the data driver 110, the gate driver 120, the timing controller 130, etc. may be integrated into one driving IC (DIC) in a mobile device or a wearable device.

[0070] Figure 3 is a diagram showing a pixel circuit according to a first embodiment of the present disclosure, and Figure 4 is a diagram showing Figure 3 the operating voltages of the first light-emitting element and the second light-emitting element shown.

[0071] Refer to Figure 3, a pixel circuit according to a first embodiment of the present disclosure includes a first light-emitting element EL1, a second light-emitting element EL2, a driving element DT for supplying current to the first light-emitting element EL1 and the second light-emitting element EL2, a switching element T1 for applying a data voltage Vdata to the gate electrode of the driving element DT, and a capacitor Cst for storing the gate-source voltage Vgs of the driving element DT. The driving element DT and the switching element T1 may be implemented as N-channel TFTs, but are not limited thereto.

[0072] The first light-emitting element EL1 and the second light-emitting element EL2 emit light by the current applied through the channel of the driving element DT, and this current is based on the gate-source voltage Vgs of the driving element DT that changes with the data voltage Vdata. The first light-emitting element EL1 and the second light-emitting element EL2 may be implemented as OLEDs, and the OLEDs include an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, a light-emitting layer EML, an electron transport layer ETL, an electron injection layer EIL, etc., but is not limited thereto. The anodes of the first light-emitting element EL1 and the second light-emitting element EL2 are connected to the driving element DT through a second node n2, and the cathodes of the first light-emitting element EL1 and the second light-emitting element EL2 are connected to a low-potential power voltage line or a second power line 42 to which a low-potential power voltage EVSS is applied.

[0073] The first light-emitting element EL1 and the second light-emitting element EL2 are connected in parallel between the second node n2 and the second power line 42.

[0074] The first light-emitting element EL1 and the second light-emitting element EL2 may have different threshold voltages. For example, the threshold voltage Vth1 of the first light-emitting element is lower than the threshold voltage Vth2 of the second light-emitting element EL2. Therefore, as Figure 4 shown, for example, in a low voltage region below 5.2V, the first light-emitting element EL1 emits light, and in a high voltage region above 5.2V, both the first light-emitting element EL1 and the second light-emitting element EL2 emit light.

[0075] The threshold voltage of the first light-emitting element EL1 and the threshold voltage of the second light-emitting element EL2 may be changed by changing the doping concentration of the light-emitting layer EML (such as the concentration of p-doping, n-doping, EML dopant, etc.) or by changing the material, ratio, etc. of the light-emitting layer EML by configuring different stacked structures, and the stacked structures include the hole transport layer HTL, the hole blocking layer HBL, the electron transport layer ETL, and the electron blocking layer EBL shown below and Figures 12 to 14 shown.

[0076] The driving element DT supplies current to the first light-emitting element EL1 and the second light-emitting element EL2 based on the gate-source voltage Vgs, thereby driving the first light-emitting element EL1 and the second light-emitting element EL2. The driving element DT includes a gate electrode connected to the first node n1, a first electrode (or drain) connected to the pixel driving voltage line 41 through which the pixel driving voltage EVDD is applied, and a second electrode (or source) connected to the second node n2.

[0077] The switching element T1 is turned on in response to the gate conduction voltage of the gate signal SCAN, and applies the data voltage Vdata to the first node n1 through the data line DL. The switching element T1 includes a gate electrode to which the gate signal SCAN is applied, a first electrode connected to the data line DL, and a second electrode connected to the first node n1.

[0078] A capacitor Cst may be connected between the first node n1 and the second node n2. The capacitor Cst can be charged with the gate-source voltage Vgs of the driving element DT.

[0079] Figures 5 to 6 is a diagram showing Figure 3 the operating principle of the pixel circuit shown.

[0080] Referring to Figure 3 、 Figure 5 and Figure 6 , the currents I OLED1 and I OLED2 flowing through the first light-emitting element EL1 and the second light-emitting element EL2 can be changed according to the voltage level of the data voltage Vdata.

[0081] In section ④, when a low-gray-scale data voltage is applied, no current flows through the second light-emitting element. That is, as Figure 6 shown, when the voltage at point “a” is applied, the first light-emitting element with a relatively low threshold voltage emits light, but the second light-emitting element does not emit light.

[0082] In section ②, when a data voltage higher than the data voltage in section ④ is applied, current flows through the first light-emitting element and the second light-emitting element. That is, as Figure 6 shown, when the voltage at point “b” is applied, both the first light-emitting element and the second light-emitting element emit light.

[0083] In the remaining sections ①, ③, and ⑤, when a high-gray-scale data voltage higher than the data voltage in section ② is applied, current flows through the first light-emitting element and the second light-emitting element. That is, as Figure 6 shown, when the voltage at point “c” is applied, both the first light-emitting element and the second light-emitting element emit light.

[0084] Figure 7It is a diagram showing a pixel circuit according to a second embodiment of the present disclosure.

[0085] Referring Figure 7 , the pixel circuit according to the second embodiment of the present disclosure includes a first light-emitting element EL1, a second light-emitting element EL2, a driving element DT for supplying current to the first light-emitting element EL1 and the second light-emitting element EL2, a first switching element T1 for applying a data voltage Vdata to the gate electrode of the driving element DT, a second switching element T2 for supplying current to the second light-emitting element EL2 or blocking the current to the second light-emitting element EL2, and a capacitor Cst for storing the gate-source voltage Vgs of the driving element DT. The driving element DT and the first switching element T1 and the second switching element T2 may be implemented as N-channel TFTs, but are not limited thereto.

[0086] The first light-emitting element EL1 and the second light-emitting element EL2 emit light by the current applied through the channel of the driving element DT, and the current is based on the gate-source voltage Vgs of the driving element DT that changes with the data voltage Vdata.

[0087] The first light-emitting element EL1 and the second light-emitting element EL2 are connected in parallel between the second node n2 and the second power line 42.

[0088] The driving element DT supplies current to the first light-emitting element EL1 and the second light-emitting element EL2 based on the gate-source voltage Vgs, thereby driving the first light-emitting element EL1 and the second light-emitting element EL2. The driving element DT includes a gate electrode connected to the first node n1, a first electrode (or drain) connected to the pixel driving voltage line 41 through which the pixel driving voltage EVDD is applied, and a second electrode (or source) connected to the second node n2.

[0089] The first switching element T1 is turned on in response to the gate conduction voltage of the gate signal SCAN to apply the data voltage Vdata to the first node n1 through the data line DL. The switching element T1 includes a gate electrode to which the gate signal SCAN is applied, a first electrode connected to the data line DL, and a second electrode connected to the first node n1.

[0090] The second switching element T2 is turned on in response to the gate conduction voltage of the control signal CS to connect the second light-emitting element EL2 to the second node n2, thereby transmitting current to the second light-emitting element EL2. The second switching element T2 includes a gate electrode to which the control signal CS is applied, a first electrode connected to the second node n2, and a second electrode connected to the anode electrode of the second light-emitting element EL2.

[0091] The control signal CS can be applied from a timing controller. For example, the timing controller can analyze the image data to apply the control signal based on, for example, the luminance of the entire area of the displayed image or the luminance of each of a plurality of separated areas.

[0092] A capacitor Cst can be connected between the first node n1 and the second node n2. The gate-source voltage Vgs of the driving element DT can be charged to the capacitor Cst.

[0093] Figures 8 to 11 is a diagram showing Figure 7 the operating principle of the pixel circuit shown.

[0094] Referring to Figure 7 and Figure 8 , when the data voltage Vdata is applied, if the second switching element T2 is turned on by the gate conduction voltage of the control signal CS, both the first light-emitting element EL1 and the second light-emitting element EL2 emit light. On the other hand, when the data voltage Vdata is applied, if the second switching element T2 is turned off by the gate cut-off voltage of the control signal CS, the first light-emitting element EL1 emits light while the second light-emitting element EL2 does not emit light.

[0095] In the first embodiment, whether the second light-emitting element emits light is determined by the voltage level of the data voltage, while in the second embodiment, whether the second light-emitting element emits light is determined by the on / off state of the second switching element T2, regardless of the voltage level of the data voltage.

[0096] Referring to Figure 7 and Figure 9 , since the section where the gate conduction voltage of the control signal CS is applied or the section where the gate cut-off voltage of the control signal CS is applied can be adjusted, the time when the second light-emitting element EL2 emits light or the time when the second light-emitting element EL2 does not emit light can be adjusted.

[0097] Therefore, in the second embodiment, the second switching elements of all pixels can be turned on or off in consideration of the average luminance of the image displayed on the screen.

[0098] For example, as Figure 10 shown, the control signal CS is applied to all pixels in the entire area AA so that the second light-emitting elements of all pixels do not emit light when the average luminance is low, and the second light-emitting elements emit light when the average luminance is high.

[0099] In addition, in the second embodiment, the screen can be divided into a plurality of areas, and the average luminance of the image displayed in each area can be checked, and in consideration of the checked average luminance, the second switching elements of the pixels in the corresponding area can be turned on or off.

[0100] In another example, as Figure 11 shown, control signals CS1, CS2, CS3, and CS4 are applied to the pixels of each region AA1, AA2, AA3, AA4 so that the second light-emitting elements of the pixels in the region with low average luminance do not emit light, and the second light-emitting elements of the pixels in the region with high average luminance emit light.

[0101] As described above, in the second embodiment, since one switching element is added to control the driving of two light-emitting elements, it is possible to freely determine whether to operate the pixels.

[0102] Figures 12 to 14 is a diagram showing the structure of an OLED used as a light-emitting element.

[0103] Referring to Figure 12 , each of the light-emitting element layers serving as the first light-emitting element EL1 and the second light-emitting element EL2 according to the embodiment may have a tandem stack structure in which a plurality of light-emitting layers are stacked. The OLED having a tandem stack structure can improve the luminance and lifespan of the pixels.

[0104] Each of the light-emitting element layers may include an anode electrode ANO, organic light-emitting layers OLED1 and OLED2, a cathode electrode CAT, and a cover layer CPL. The cover layer CPL may be a functional layer added for various functions.

[0105] The first organic light-emitting layer OLED1 serving as the first light-emitting element EL1 may include a first-first hole injection layer HIL1-1, a first-first hole transport layer HTL1-1, a first-first electron blocking layer EBL1-1, a first-first emission layer EML1-1, a first-first hole blocking layer HBL1-1, a first-first electron transport layer ETL1-1, an N-type charge generation layer N-CGL, a P-type charge generation layer P-CGL, a first-second hole transport layer HTL1-2, a first-second electron blocking layer EBL1-2, a first-second emission layer EML1-2, a first-second hole blocking layer HBL1-2, a first-second electron transport layer ETL1-2, and a first electron injection layer EIL1.

[0106] The second organic light-emitting layer OLED2 serving as the second light-emitting element EL2 may include a second-first hole injection layer HIL2-1, a second-first hole transport layer HTL2-1, a second-first electron blocking layer EBL2-1, a second-first emission layer EML2-1, a second-first hole blocking layer HBL2-1, a second-first electron transport layer ETL2-1, an N-type charge generation layer N-CGL, a P-type charge generation layer P-CGL, a second-second hole transport layer HTL2-2, a second-second electron blocking layer EBL2-2, a second-second emission layer EML2-2, a second-second hole blocking layer HBL2-2, a second-second electron transport layer ETL2-2, and a second electron injection layer EIL2.

[0107] The hole transport layer HTL is an organic layer that transfers holes from the anode electrode to the emission layer EML. The electron transport layer ETL is a layer that transfers electrons from the cathode electrode to the emission layer EML. In the emission layer EML, holes supplied through the anode electrode and electrons supplied through the cathode electrode are recombined to generate excitons. The electron blocking layer EBL is a layer that prevents electrons injected into the emission layer EML from transferring to the hole transport layer HTL. The hole blocking layer HBL is a layer that prevents holes injected into the emission layer EML from transferring to the electron transport layer ETL.

[0108] Referring to Figure 13 , each of the OLEDs serving as the first light-emitting element EL1 and the second light-emitting element EL2 according to an embodiment may have a single stacked structure.

[0109] Each of the light-emitting element layers may include an anode electrode ANO, an organic light-emitting layer OLED, a cathode electrode CAT, and a cover layer CPL.

[0110] The first organic light-emitting layer OLED1 serving as the first light-emitting element EL1 may include a first hole injection layer HIL1, a first hole transport layer HTL1, a first electron blocking layer EBL1, a first emission layer EML1, a first hole blocking layer HBL1, a first electron transport layer ETL1, and a first electron injection layer EIL1.

[0111] The second organic light-emitting layer OLED2 serving as the second light-emitting element EL2 may include a second hole injection layer HIL2, a second hole transport layer HTL2, a second electron blocking layer EBL2, a second emission layer EML2, a second hole blocking layer HBL2, a second electron transport layer ETL2, and a second electron injection layer EIL2.

[0112] Referring to Figure 14 , the light-emitting element layers serving as the first light-emitting element EL1 and the second light-emitting element EL2 according to an embodiment may have a single stacked structure and a tandem stacked structure, respectively.

[0113] The first organic light-emitting layer OLED1 serving as the first light-emitting element EL1 may include a first hole injection layer HIL1, a first hole transport layer HTL1, a first electron blocking layer EBL1, a first light-emitting layer EML1, a first hole blocking layer HBL1, a first electron transport layer ETL1, and a first electron injection layer EIL1.

[0114] The second organic light-emitting layer OLED2 serving as the second light-emitting element EL2 may include a second-first hole injection layer HIL2-1, a second-first hole transport layer HTL2-1, a second-first electron blocking layer EBL2-1, a second-first light-emitting layer EML2-1, a second-first hole blocking layer HBL2-1, a second-first electron transport layer ETL2-1, an N-type charge generation layer N-CGL, a P-type charge generation layer P-CGL, a second-second hole transport layer HTL2-2, a second-second electron blocking layer EBL2-2, a second-second light-emitting layer EML2-2, a second-second hole blocking layer HBL2-2, a second-second electron transport layer ETL2-2, and a second electron injection layer EIL2.

[0115] As described above, in the second embodiment, two identical light-emitting elements are formed adjacent to each other, but the anode electrodes are separated by switches, so that the phenomenon of light emission due to leakage current can be reduced.

[0116] In the second embodiment, the anode electrodes of the light-emitting elements composed of the same fine metal mask (FMM) are separated by switches, so that they can be freely designed without being affected by the FMM alignment problem.

[0117] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and do not limit the present disclosure.

Claims

1. A pixel circuit, comprising: a driving element including a first electrode connected to a first power line, a gate electrode connected to a first node, and a second electrode connected to a second node; a switching element configured to supply a data voltage to the first node in response to a gate signal; a capacitor connected between the first node and the second node; as well as a first light emitting element and a second light emitting element connected in parallel between the second node and a second power line, The first light emitting element and the second light emitting element have different threshold voltages.

2. The pixel circuit according to claim 1, wherein: A threshold voltage of the first light emitting element is lower than a threshold voltage of the second light emitting element, and the second light emitting element selectively emits light based on a voltage level of the data voltage.

3. The pixel circuit according to claim 1, wherein: The threshold voltage of the first light emitting element and the threshold voltage of the second light emitting element vary according to constituent materials and stack structures of organic light emitting layers used as the first light emitting element and the second light emitting element.

4. The pixel circuit according to claim 1, wherein: The switch element comprises: a gate electrode to which the gate signal is applied, a first electrode connected to a data line through which the data voltage is applied, and a second electrode connected to the first node.

5. A pixel circuit comprising: a driving element including a first electrode connected to a first power line, a gate electrode connected to a first node, and a second electrode connected to a second node; a first switching element configured to supply a data voltage to the first node in response to a gate signal; a capacitor connected between the first node and the second node; a first light emitting element and a second light emitting element connected in parallel between the second node and a second power line; as well as A second switching element is configured to selectively connect the second node to the second light emitting element in response to a control signal.

6. The pixel circuit according to claim 5, wherein: The first switching element includes a gate electrode to which the gate signal is applied, a first electrode connected to a data line through which the data voltage is applied, and a second electrode connected to the first node, and The second switching element includes a gate electrode to which the control signal is applied, a first electrode connected to the second node, and a second electrode connected to an anode of the second light emitting element.

7. A display device, comprising: A display panel, in which a plurality of data lines, a plurality of gate lines intersecting the plurality of data lines, and a plurality of pixel circuits are arranged, Wherein, each of the plurality of pixel circuits comprises: a driving element including a first electrode connected to a first power line, a gate electrode connected to a first node, and a second electrode connected to a second node; a switching element configured to supply a data voltage to the first node in response to a gate signal; a capacitor connected between the first node and the second node; and a first light emitting element and a second light emitting element connected in parallel between the second node and the second power line, The first light emitting element and the second light emitting element have different threshold voltages.

8. The display device according to claim 7, wherein: A threshold voltage of the first light emitting element is lower than a threshold voltage of the second light emitting element, and the second light emitting element selectively emits light based on a voltage level of the data voltage.

9. The display device according to claim 7, wherein: The threshold voltage of the first light emitting element and the threshold voltage of the second light emitting element vary according to constituent materials and stack structures of organic light emitting layers used as the first light emitting element and the second light emitting element.

10. The display device according to claim 7, wherein: The switch element comprises: a gate electrode to which the gate signal is applied, a first electrode connected to a data line through which the data voltage is applied, and a second electrode connected to the first node.

11. A display device, comprising: a display panel in which a plurality of data lines, a plurality of gate lines intersecting the plurality of data lines, and a plurality of pixel circuits are arranged; a data driver configured to apply data voltages to the plurality of data lines; a gate driver configured to apply a gate signal to the plurality of gate lines; as well as a timing controller configured to control the data driver and the gate driver, Wherein, each of the plurality of pixel circuits comprises: a driving element including a first electrode connected to a first power line, a gate electrode connected to a first node, and a second electrode connected to a second node; a first switching element configured to supply a data voltage to the first node in response to the gate signal; a capacitor connected between the first node and the second node; a first light emitting element and a second light emitting element connected in parallel between the second node and a second power line; and A second switching element is configured to selectively connect the second node to the second light emitting element in response to a control signal.

12. The display device according to claim 11, wherein: The timing controller is configured to apply the control signal to the plurality of pixel circuits.

13. The display device according to claim 12, wherein: The timing controller is configured to apply the control signal to the plurality of pixel circuits based on an average brightness of an entire region where an image is displayed or an average brightness of each of a plurality of regions where the image is displayed.

14. The display device according to claim 11, wherein: The first switching element includes a gate electrode to which the gate signal is applied, a first electrode connected to a data line through which the data voltage is applied, and a second electrode connected to the first node, and The second switching element includes a gate electrode to which the control signal is applied, a first electrode connected to the second node, and a second electrode connected to an anode of the second light emitting element.

15. The display device according to claim 11, wherein: The gate driver is configured to apply the gate signal to the plurality of gate lines by shifting the gate signal using a shift register.

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