Pixel circuit and display device including same

Abstract

The invention relates to a pixel circuit and a display device including the same. The pixel circuit includes: a driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switching element supplying a pixel driving voltage to a first node in response to a first gate signal; a second switching element connecting the fourth node to the second node in response to a second gate signal; a third switching element supplying a data voltage to the second node in response to a third gate signal; a fourth switching element supplying a reference voltage to the second node in response to a fourth gate signal; a fifth switching element connecting the fourth node to the third node in response to a third gate signal; a first capacitor connected between the second node and the third node; a second capacitor connected between the first power line and the fourth node; and a light emitting element connected between the third node and the second power line.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0195990, filed on December 29, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a pixel circuit and a display device including the pixel circuit. Background art

[0004] Display devices include liquid crystal display (LCD) devices, electroluminescent display devices, field emission display (FED) devices, plasma display panels (PDPs), etc.

[0005] Electroluminescent display devices are classified into inorganic electroluminescent display devices and organic electroluminescent display devices according to the material of the light - emitting layer. An active - matrix organic light - emitting display device includes an organic light - emitting diode (hereinafter referred to as "OLED") that emits light by itself, and has advantages such as a fast response speed, high luminous efficiency, high brightness, and a large viewing angle.

[0006] Some display devices in display devices, such as liquid crystal display devices or organic light - emitting display devices, include: a display panel including a plurality of sub - pixels; a driver that outputs a driving signal for driving the display panel; a power supply device that generates power to be supplied to the display panel or the driver, etc. The driver includes: a gate driver that supplies gate signals such as a scan signal and a light - emitting signal to the display panel; and a data driver that supplies data signals to the display panel. Summary of the invention

[0007] Each of a plurality of pixels includes a driving element that controls a driving current flowing in the OLED according to a voltage (Vgs) applied between a gate electrode and a source electrode. The electrical characteristics of the driving element deteriorate with driving time and may vary for each pixel. Therefore, an organic light - emitting display device compensates for the deterioration of the driving element through an internal compensation technique or an external compensation technique.

[0008] The internal compensation technique senses the threshold voltage (Vth) of the driving element for each sub - pixel by using an internal compensation circuit embedded in each pixel, and compensates the gate - source voltage (Vgs) of the driving element through the threshold voltage.

[0009] The gate - source voltage (Vgs) of the driving element affects the gamma curve of gray - scale expression, and due to the gamma curve, power consumption may increase or low - gray - scale expression may be difficult.

[0010] The present disclosure aims to solve all of the above needs and problems.

[0011] The present disclosure provides a pixel circuit and a display device including the pixel circuit.

[0012] It should be noted that the object of the present disclosure is not limited to the above object, and according to the following description, other objects of the present disclosure will be apparent to those skilled in the art.

[0013] The pixel circuit according to an embodiment of the present disclosure may include: a driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switching element configured to supply a pixel driving voltage to the first node in response to a first gate signal; a second switching element configured to connect a fourth node to the second node in response to a second gate signal; a third switching element configured to supply a data voltage to the second node in response to a third gate signal; a fourth switching element configured to supply a reference voltage to the second node in response to a fourth gate signal; a fifth switching element configured to connect the fourth node to the third node in response to the third gate signal; a first capacitor connected between the second node and the third node; a second capacitor connected between a first power line and the fourth node; and a light-emitting element connected between the third node and a second power line.

[0014] The display device according to an embodiment of the present disclosure may include: a display panel in which a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixel circuits are provided, each of the plurality of pixel circuits including: a driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switching element configured to supply a pixel driving voltage to the first node in response to a first gate signal; a second switching element configured to connect a fourth node to the second node in response to a second gate signal; a third switching element configured to supply a data voltage to the second node in response to a third gate signal; a fourth switching element configured to supply a reference voltage to the second node in response to a fourth gate signal; a fifth switching element configured to connect the fourth node to the third node in response to the third gate signal; a first capacitor connected between the second node and the third node; a second capacitor connected between a first power line and the fourth node; and a light-emitting element connected between the third node and a second power line.

[0015] The present disclosure uses a capacitor with a large capacitance without adding a capacitor by further including two switching elements for selectively connecting the capacitor for writing the data voltage to the gate electrode and the source electrode of the driving element, and thus can improve the gamma characteristic at low gray levels.

[0016] According to the present disclosure, in the threshold voltage sensing of a driving element, the voltage charging speed of the source node increases, and this can shorten the sensing time.

[0017] According to the present disclosure, a driving element having a double-gate structure can facilitate high-resolution and high-refresh-rate driving by reducing the time required to sense the threshold voltage of the driving element.

[0018] According to the present disclosure, the data voltage for high-brightness output can be reduced, thereby reducing the current stress on the driving element, and not only improving the lifespan of the element but also enhancing its reliability.

[0019] According to the present disclosure, the data voltage for high-brightness output can be reduced, and thus the power consumption can be reduced.

[0020] The effects of this specification are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art according to the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art by referring to the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0022] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure;

[0023] Figure 2 shows Figure 1 a cross-sectional view of the cross-sectional structure of the display panel shown;

[0024] Figure 3 is a diagram showing a pixel circuit according to a first embodiment of the present disclosure;

[0025] Figure 4 shows Figure 3 a driving timing diagram of the pixel circuit shown;

[0026] Figures 5A to 5E is for explaining Figure 4 the operation of the pixel circuit;

[0027] Figure 6 shows Figure 3 a gamma curve generated by the pixel circuit;

[0028] Figure 7 is a diagram showing a pixel circuit according to a second embodiment of the present disclosure;

[0029] Figure 8 is a diagram showing Figure 7 the driving timing of the pixel circuit shown;

[0030] Figures 9A to 9E is a diagram for explaining Figure 7 the operation of the pixel circuit; and

[0031] Figure 10A and Figure 10B is a diagram showing the gamma curve generated by Figure 7 the pixel circuit. DETAILED DESCRIPTION

[0032] With reference to the preferred embodiments described in detail in conjunction with the accompanying drawings, the advantages and features of this specification and the methods for realizing them will become apparent. However, this specification is not limited to the embodiments to be described below and can be implemented in different forms. The embodiments are provided only to fully disclose the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art, and this specification is defined by the disclosed claims.

[0033] Since the shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present disclosure are only exemplary, the present disclosure is not limited to the items shown. Throughout the specification, the same reference numerals indicate the same components. In addition, when determining that the detailed description of related known technologies may unnecessarily obscure the gist of the present disclosure, the detailed description thereof will be omitted.

[0034] When using terms such as "including", "having", "consisting of", etc. mentioned in this specification, unless "only" is used, other parts can be added. Unless otherwise clearly stated, the case of indicating a component in the singular form includes the plural form.

[0035] When interpreting a component, it should be understood that even if there is no separate explicit description, the error range is included.

[0036] In the case of describing the positional relationship, for example, when the positional relationship between two parts is described as "on...", "on the upper part", "on the lower part", "next to...", etc., unless "immediately" or "directly" is used, one or more other parts may be located between these two parts.

[0037] Although "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, within the technical spirit of the present disclosure, the first component mentioned below may also be the second component.

[0038] Throughout this disclosure, the same reference numerals may refer to substantially the same elements.

[0039] The following embodiments may be joined or combined with each other partially or entirely and may be linked and operated in various technical ways. The embodiments may be executed independently of or in association with each other.

[0040] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0041] In the display device of the present disclosure, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistors may be implemented as oxide thin film transistors (oxide TFTs) including oxide semiconductors, low temperature polycrystalline silicon (LTPS) TFTs including low temperature polycrystalline silicon, and the like.

[0042] A transistor is a three - electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In a transistor, carriers flow starting from the source. The drain is an electrode through which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n - channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, so that electrons can flow from the source to the drain. The n - channel transistor has a current direction from the drain to the source. In the case of a p - channel transistor (p - channel metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p - channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed according to the applied voltage. Therefore, the present disclosure is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0043] The gate signal swings between a gate - on voltage and a gate - off voltage. The gate - on voltage is set to a voltage higher than the threshold voltage of the transistor, while the gate - off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0044] The transistor conducts in response to the gate - on voltage and turns off in response to the gate - off voltage. In the case of an n - channel transistor, the gate - on voltage may be a gate - high voltage, and the gate - off voltage may be a gate - low voltage. In the case of a p - channel transistor, the gate - on voltage may be a gate - low voltage, and the gate - off voltage may be a gate - high voltage.

[0045] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure, and Figure 2 is showingFigure 1 A cross-sectional view of the cross-sectional structure of the display panel shown, that is, a cross-sectional view in the Z-axis direction in the XYZ coordinate system.

[0046] Referring to Figure 1 and Figure 2 According to an embodiment of the present disclosure, a display device includes: a display panel 100; a display panel driving unit configured to write pixel data into pixels of the display panel 100; and a power supply unit 140 configured to generate power required to drive the pixels and the display panel driving unit.

[0047] The display panel 100 includes a pixel array AA that displays an input image. The pixel array AA includes a plurality of data lines DL, a plurality of gate lines GL intersecting the data lines DL, and pixels arranged in a matrix form.

[0048] The pixel array AA includes a plurality of pixel rows L1 to Ln. Each pixel row among the pixel rows L1 to Ln includes a row of pixels arranged in the row direction X in the pixel array AA of the display panel 100. The pixels arranged in one pixel row share the gate line GL. Sub-pixels arranged in the column direction Y along the data line direction share the same data line DL. One horizontal period 1H is a time obtained by dividing one frame period by the total number of the pixel rows L1 to Ln.

[0049] A touch sensor may be provided on the display panel 100. A separate touch sensor may be used to sense a touch input, or a touch input may be sensed through pixels. The touch sensor may be provided on the screen of the display panel as an on-cell type or an add-on type, or may be implemented as an in-cell type touch sensor embedded in the pixel array AA.

[0050] The display panel 100 may be implemented as a flexible display panel. The flexible display panel may be made of a plastic OLED panel. An organic film may be provided on the backplane of the plastic OLED panel, and the pixel array AA may be formed on the organic film.

[0051] The backplane of the plastic OLED may be a polyethylene terephthalate (PET) substrate. The organic film is formed on the backplane. The pixel array AA and the touch sensor array may be formed on the organic film. The backplane blocks moisture penetration so that the pixel array AA is not exposed to moisture. The organic film may be a thin polyimide (PI) film substrate. A multi-layer buffer film may be formed on the organic film by an insulating material (not shown). Lines may be formed on the organic film to supply power or signals applied to the pixel array AA and the touch sensor array.

[0052] To achieve color, each of the pixels can be divided into a red sub-pixel (hereinafter referred to as "R sub-pixel"), a green sub-pixel (hereinafter referred to as "G sub-pixel"), and a blue sub-pixel (hereinafter referred to as "B sub-pixel"). Each of the pixels can also include a white sub-pixel. Each of the sub-pixels 101 includes a pixel circuit. The pixel circuit is connected to a data line DL and a gate line GL.

[0053] The cross-sectional structure of the display panel 100 may include a circuit layer CIR, a light-emitting element layer EMIL, and a packaging layer ENC stacked on a substrate SUBS, as Figure 2 shown.

[0054] The circuit layer CIR may include a thin-film transistor (TFT) array, which includes pixel circuits connected to wirings such as data lines, gate lines, and power lines, and gate drivers 410 and 420. The circuit layer CIR includes: a plurality of metal layers insulated by an intervening insulating layer; and a semiconductor material layer. All transistors formed in the circuit layer CIR can be implemented as n-channel oxide TFTs.

[0055] The light-emitting element layer EMIL may include light-emitting elements driven by the pixel circuits. The light-emitting elements may include light-emitting elements of red sub-pixels, light-emitting elements of green sub-pixels, and light-emitting elements of blue sub-pixels. The light-emitting element layer EMIL may also include light-emitting elements of white sub-pixels. The light-emitting element layer EMIL corresponding to each sub-pixel in the sub-pixels may have a structure in which light-emitting elements and color filters are stacked. The light-emitting elements EL in the light-emitting element layer EMIL may be covered by a plurality of protective layers including organic films and inorganic films.

[0056] The packaging layer ENC covers the light-emitting element layer EMIL to seal the circuit layer CIR and the light-emitting element layer EMI. The packaging layer ENC may also have a multi-insulating film structure in which organic films and inorganic films are alternately stacked. The inorganic film blocks the penetration of moisture and oxygen. The organic film planarizes the surface of the inorganic film. When the organic layer and the inorganic layer are stacked in multiple layers, the movement paths of moisture and oxygen become longer than those of a single layer, so that the penetration of moisture and oxygen affecting the light-emitting element layer EMIL can be effectively blocked.

[0057] A touch sensor layer (not shown) may be formed on the encapsulation layer ENC, and a polarizing plate or a color filter layer may be disposed thereon. The touch sensor layer may include a capacitive touch sensor that senses a touch input based on a change in capacitance before and after the touch input. The touch sensor layer may have a metal wiring pattern and an insulating film that form the capacitance of the touch sensor. The insulating film may insulate the regions where the metal wiring patterns intersect and may flatten the surface of the touch sensor layer. The polarizing plate may improve visibility and contrast by converting the polarization of external light reflected by the metal in the touch sensor layer and the circuit layer. The polarizing plate may be implemented as a circular polarizing plate or a polarizing plate in which a linear polarizing plate and a phase retardation film are joined together. A cover glass may be adhered to the polarizing plate. The color filter layer may include a red color filter, a green color filter, and a blue color filter. The color filter layer may further include a black matrix pattern. The color filter layer may replace the polarizing plate by absorbing a part of the wavelength of the light reflected from the circuit layer and the touch sensor layer, and may increase the color purity of the image reproduced in the pixel array.

[0058] The power supply unit 140 generates direct current (DC) power required to drive the display panel driving unit and the pixel array AA of the display panel 100 by using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply unit 140 may adjust the level of the input DC voltage applied from a host system (not shown) to generate a constant voltage (or DC voltage), such as a gamma reference voltage VGMA, a gate-on voltage VGH and VEH, a gate-off voltage VGL and VEL, a pixel driving voltage EVDD, a low-potential power voltage EVSS, an initialization voltage VINIT, and a reference voltage VREF. The gamma reference voltage VGMA is supplied to the data driver 110. The gate-on voltage VGH and VEH and the gate-off voltage VGL and VEL are supplied to the gate driver 120. Constant voltages such as the pixel driving voltage EVDD, the low-potential power voltage EVSS, the initialization voltage VINIT, and the reference voltage VREF are commonly supplied to the pixels.

[0059] The display panel driving unit writes the pixel data of the input image into the pixels of the display panel 100 under the control of the timing controller (TCON) 130.

[0060] The display panel driving unit includes a data driver 110 and a gate driver 120.

[0061] A demultiplexer (DEMUX) may be provided between the data driver 110 and the data line DL. Figure 1The demultiplexer is omitted. The demultiplexer sequentially connects one channel of the data driver 110 to a plurality of data lines DL, and distributes the data voltage output from one channel of the data driver 110 to the data lines DL in a time-division manner, thereby reducing the number of channels of the data driver 110.

[0062] The display panel driving unit may further include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted. In the mobile device, the timing controller 130, the power supply unit 140, the data driver 110, etc. may be integrated into one driving integrated circuit (IC).

[0063] The data driver 110 generates a data voltage Vdata by converting the pixel data of the input image received from the timing controller 130 in each frame period into a gamma compensation voltage using a digital-to-analog converter (DAC). The gamma reference voltage VGMA is divided into respective gray levels by a voltage divider circuit. The gamma compensation voltage divided from the gamma reference voltage VGMA is provided to the DAC of the data driver 110. The data voltage Vdata is output through an output buffer in each channel of the data driver 110.

[0064] In the data driver 110, the output buffer included in one channel may be connected to adjacent data lines DL through a demultiplexer array (not shown). The demultiplexer array may be directly formed on the substrate of the display panel 100, or integrated with the data driver 110 into one driving IC.

[0065] The gate driver 120 may be implemented as an in-panel gate (GIP) circuit directly formed on the border BZ area of the display panel 100 together with the TFT array of the pixel array AA. The gate driver 120 sequentially outputs gate signals to the gate lines GL under the control of the timing controller 130. The gate driver 120 may sequentially supply the gate signals to the gate lines GL by shifting the gate signals using a shift register.

[0066] The gate driver 120 may include a first gate driver 121 that outputs a scan signal and a second gate driver 122 that outputs a light emission signal, but is not limited thereto.

[0067] The timing controller 130 receives digital video data DATA of an input image and a timing signal synchronized therewith from a host system (not shown). The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock CLK, a data enable signal DE, etc. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of one horizontal period (1H).

[0068] The timing controller 130 multiplies the input frame frequency by i and controls the operation timing of the display panel driving unit at a frame frequency of input frame frequency × i (i is a positive integer greater than 0) Hz. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Phase-Alternating Line) scheme.

[0069] Based on the timing signals Vsync, Hsync, and DE received from the host system, the timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a MUX signal for controlling the operation timing of the demultiplexer array, and a gate timing control signal for controlling the operation timing of the gate driver 120.

[0070] The voltage levels of the gate timing control signals output from the timing controller 130 can be converted into a gate-on voltage VGH and VEH and a gate-off voltage VGL and VEL by a level shifter (not shown), and then supplied to the gate driver 120. That is, the level shifter converts the low-level voltage of the gate timing control signal into the gate-off voltage VGL and VEL, and converts the high-level voltage of the gate timing control signal into the gate-on voltage VGH and VEH. The gate timing signal includes a start pulse and a shift clock.

[0071] The host system may include a motherboard of one of a television system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a vehicle system, and a mobile device system. In this case, the data driver 110, the gate driver 120, the timing controller 130, etc. may be integrated into a driving IC (DIC) in a mobile device or a wearable device.

[0072] Figure 3 is a diagram showing a pixel circuit according to a first embodiment of the present disclosure, Figure 4 is a diagram showing Figure 3 the driving timing of the pixel circuit shown, and Figures 5A to 5Eis a diagram for explaining Figure 4 the operation of the pixel circuit.

[0073] Referring to Figure 3 , the pixel circuit according to the first embodiment of the present disclosure includes a light-emitting element EL, a driving element DT for supplying current to the light-emitting element EL, a plurality of switching elements T1 to T7 for switching a current path connected to the driving element DT, a first capacitor Cst for storing a gate-source voltage of the driving element DT, and a second capacitor C2. The driving element DT and the switching elements T1 to T7 may be implemented as n-channel oxide TFTs, but are not limited thereto.

[0074] The data voltage Vdata applied to the pixel circuit may be 4V to 12V, the pixel driving voltage EVDD may be 16V, the pixel base voltage EVSS may be 3V, the reference voltage Vref may be 4.3V, and the initialization voltage may be 0V.

[0075] The light-emitting element EL emits light through the current applied through the channel of the driving element DT according to the gate-source voltage Vgs of the driving element DT, and the gate-source voltage Vgs of the driving element DT varies according to the data voltage Vdata. The light-emitting element EL may be implemented as an OLED including an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the light-emitting element EL is connected to the driving element DT through a third node n3, and the cathode of the light-emitting element EL is connected to a low-potential power supply voltage line or a second power line PL2 to which a low-potential power voltage EVSS is applied.

[0076] The OLED serving as the light-emitting element EL may have a tandem structure in which a plurality of light-emitting layers are stacked. The OLED having a tandem structure may improve the brightness and lifetime of the pixel.

[0077] The driving element DT drives the light-emitting element EL by supplying current to the light-emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to a second node n2, a first electrode (or drain) connected to a first node n1, and a second electrode (or source) connected to a third node n3.

[0078] The first switching element T1 is turned on according to the gate conduction voltage of the first gate signal EM1, and supplies the pixel driving voltage EVDD to the driving element DT. The first switching element T1 includes a gate electrode to which the first gate signal EM1 is applied, a first electrode connected to the pixel driving voltage line or the first power line PL1 to which the pixel driving voltage is applied, and a second electrode connected to the first electrode of the driving element DT.

[0079] The second switching element T2 is turned on according to the gate conduction voltage of the second gate signal EM2, and connects the fourth node n4 to the second node n2. The second switching element T2 includes a gate electrode to which the second gate signal EM2 is applied, a first electrode connected to the second node n2, and a second electrode connected to the fourth node n4.

[0080] The third switching element T3 is turned on according to the gate conduction voltage of the third gate signal SCAN1, and connects the data line DL to the second node n2 to apply the data voltage Vdata. The third switching element T3 includes a gate electrode to which the third gate signal SCAN1 is applied, a first electrode connected to the data line DL, and a second electrode connected to the second node n2.

[0081] The fourth switching element T4 is turned on according to the gate conduction voltage of the fourth gate signal SCAN2, and connects the reference voltage line or the third power line PL3 to the second node n2 to apply the reference voltage Vref. The fourth switching element T4 includes a gate electrode to which the fourth gate signal SCAN2 is applied, a first electrode connected to the third power line PL3, and a second electrode connected to the second node n2.

[0082] The fifth switching element T5 is turned on according to the gate conduction voltage of the third gate signal SCAN1, and connects the third node n3 and the fourth node n4. The fifth switching element T4 includes a gate electrode to which the third gate signal SCAN1 is applied, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4.

[0083] The sixth switching element T6 is turned on according to the gate conduction voltage of the second gate signal EM2, and connects the third node n3 and the fifth node n5. The sixth switching element T6 includes a gate electrode to which the second gate signal EM2 is applied, a first electrode connected to the third node n3, and a second electrode connected to the fifth node n5.

[0084] The seventh switching element T7 is turned on according to the gate conduction voltage of the fifth gate signal SCAN3, and connects the initialization voltage line or the fourth power line PL4 to the fifth node n5 to apply the initialization voltage. The seventh switching element T7 includes a gate electrode to which the fifth gate signal SCAN3 is applied, a first electrode connected to the fifth node n5, and a second electrode connected to the fourth power line PL4.

[0085] The first capacitor Cst can be connected between the second node n2 and the third node n3. The first capacitor Cst can be charged with the gate-source voltage Vgs of the driving element DT.

[0086] The second capacitor C2 can be connected between the fourth node n4 and the first power line PL1.

[0087] At this time, the second capacitor C2 is required to write the data voltage. The reasons are as follows. When the fifth switching element T5 conducts after sensing the threshold voltage Vth of the driving element DT, the voltage of the first node n1 changes from the reference voltage to the data voltage, and thus the data voltage is written. At this time, if the second node is in a floating state and there is no second capacitor C2, the voltage change in the first node is directly sent to the second node. That is, the voltage of the second node changes from Vref - Vth to Vref - Vth+(Vdata - Vref), such that Vgs = Vth, and thus the data voltage disappears. Therefore, the second capacitor C2 is used to suppress the voltage change of the second node n2, so that the data voltage Vdata is maintained at Vgs.

[0088] Refer to Figure 4 , the pixel circuit according to the first embodiment of the present disclosure can be driven in the order of an initialization step Tini, a sensing step Ts, a data writing step Tw, a reset step Trst, and a light emitting step Tem.

[0089] Refer to Figure 4 and Figure 5A , in the initialization step Tini, the first switching element T1, the third switching element T3, and the fifth switching element T5 are turned off, while the second switching element T2, the fourth switching element T4, and the sixth switching element T6 and the seventh switching element T7 are turned on, so that the reference voltage Vref is applied to the second node n2 for initialization, and the initialization voltage Vinit is applied to the third node n3 for initialization. Therefore, the voltage of the second node n2 becomes Vref, and the voltage of the third node n3 becomes Vinit.

[0090] Refer to Figure 4 and Figure 5B , in the sensing step Ts, the second switching element T2, the third switching element T3, and the fifth switching element T5 to the seventh switching element T7 are turned off, while the first switching element T1 and the fourth switching element T4 are turned on, so that the threshold voltage Vth of the driving element DT is sensed and stored in the first capacitor Cst. Therefore, the voltage of the third node n3 becomes Vinit - Vth.

[0091] Refer to Figure 4 and Figure 5C, in the data writing step Tw, the first switching element T1, the second switching element T2, the fourth switching element T4, and the sixth switching element T6 and the seventh switching element T7 are turned off, and the third switching element T3 and the fifth switching element T5 are turned on, so that the data voltage Vdata of the pixel data is applied to the second node n2. Therefore, the voltage of the second node n2 changes from Vref to Vdata. At this time, a change equal to the ratio Cst / (Cst + C2) of the voltage change of the second node n2 is added to the third node n3.

[0092] Referring to Figure 4 and Figure 5D , in the reset step Trst, the first switching element T1 and the third switching element T3 to the fifth switching element T5 are turned off, and the second switching element T2 and the sixth switching element T6 and the seventh switching element T7 are turned on, so that the initialization voltage Vinit is applied to the third node n3. Therefore, the voltage of the third node n3 becomes Vinit.

[0093] Referring to Figure 4 and Figure 5E , in the light emitting step Tem, the third switching element T3 to the fifth switching element T5 and the seventh switching element T7 are turned off, while the first switching element T1, the second switching element T2, and the sixth switching element T6 are turned on, so that the voltage of the second node n2 and the voltage of the third node n3 increase, and then the light emitting element EL can emit light with a brightness corresponding to the gray value of the pixel data.

[0094] At this time, during the boosting period, the second capacitor C2 is connected to the second node n2. Due to the voltage distribution effect of the second capacitor C2, the increase in the voltage of the second node n2 is delayed compared to the increase in the voltage of the third node n3. Therefore, Vgs decreases, and thus the brightness decreases. In high grayscales, the boosting speed is very fast, so the effect of the decrease in Vgs of the second capacitor C2 is small, but in low grayscales, the effect of the decrease in Vgs is relatively large, enabling the improvement of gamma characteristics.

[0095] Figure 6 is a diagram showing Figure 3 the gamma curve generated by the pixel circuit.

[0096] Referring to Figure 6 , it can be seen that, compared with the pixel circuit of the comparative example, the embodiment of the pixel circuit in which two switching elements are additionally configured to selectively connect the second capacitor to the gate electrode and the source electrode of the driving element has a reduced gamma curve slope at low grayscales.

[0097] If the slope of the gamma curve decreases at low grayscales, it can be beneficial for low grayscale expression.

[0098] Figure 7FIG. is a diagram showing a pixel circuit according to a second embodiment of the present disclosure, Figure 8 is a diagram showing Figure 7 the driving timing of the pixel circuit shown, and Figures 9A to 9E is a diagram for explaining Figure 7 the operation of the pixel circuit.

[0099] Referring to Figure 7 , the pixel circuit according to the second embodiment of the present disclosure includes a light-emitting element EL, a driving element DT for supplying current to the light-emitting element EL, a plurality of switching elements T1 to T7 for switching a current path connected to the driving element DT, a first capacitor Cst for storing the gate-source voltage of the driving element DT, a second capacitor C2, and a third capacitor C3. The driving element DT and the switching elements T1 to T7 may be implemented as n-channel oxide TFTs, but are not limited thereto.

[0100] The light-emitting element EL emits light by a current applied through a channel of the driving element DT according to the gate-source voltage Vgs of the driving element DT, and the gate-source voltage Vgs of the driving element DT varies according to the data voltage Vdata. The light-emitting element EL may be implemented as an OLED including an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the light-emitting element EL is connected to the driving element DT through a third node n3, and the cathode of the light-emitting element EL is connected to a low-potential power supply voltage line or a second power line PL2 to which a low-potential power voltage EVSS is applied.

[0101] The OLED serving as the light-emitting element EL may have a tandem structure in which a plurality of light-emitting layers are stacked. The OLED having a tandem structure may improve the brightness and lifetime of the pixel.

[0102] The driving element DT drives the light-emitting element EL by supplying current to the light-emitting element EL according to the gate-source voltage Vgs. The driving element DT may be a MOSFET having a dual-gate structure. The driving element DT includes a first gate electrode connected to a second node n2, a second gate electrode connected to a pixel driving voltage line or a first power line PL1 to which a pixel driving voltage is applied, a first electrode (or drain) connected to a first node n1, and a second electrode (or source) connected to a third node n3.

[0103] At this time, by using a driving element DT having a double-gate structure, it is possible to reduce the data voltage for high-brightness output, and thereby reduce power consumption, but the mobility can be increased. As the mobility increases, the data voltage for high-brightness output decreases, thereby reducing power consumption, the stress on the driving element DT decreases, so the device life and reliability are increased, and the time required for threshold voltage sensing is reduced, which is beneficial for higher-resolution and high-refresh-rate driving. However, the gamma curve changes rapidly, thereby reducing the data voltage range at low gray levels and reducing the accuracy of low-gray-level expression.

[0104] To solve this problem, this embodiment aims to add a third capacitor C3.

[0105] The first switching element T1 is turned on according to the gate conduction voltage of the first gate signal EM1, and supplies the pixel driving voltage EVDD to the driving element DT. The first switching element T1 includes a gate electrode to which the first gate signal EM1 is applied, a first electrode connected to a pixel driving voltage line or a first power line PL1 to which the pixel driving voltage is applied, and a second electrode connected to the first electrode of the driving element DT.

[0106] The second switching element T2 is turned on according to the gate conduction voltage of the second gate signal EM2, and connects the fourth node n4 to the second node n2. The second switching element T2 includes a gate electrode to which the second gate signal EM2 is applied, a first electrode connected to the second node n2, and a second electrode connected to the fourth node n4.

[0107] The third switching element T3 is turned on according to the gate conduction voltage of the third gate signal SCAN1, and connects the data line DL to the second node n2 to apply the data voltage Vdata. The third switching element T3 includes a gate electrode to which the third gate signal SCAN1 is applied, a first electrode connected to the data line DL, and a second electrode connected to the second node n2.

[0108] The fourth switching element T4 is turned on according to the gate conduction voltage of the fourth gate signal SCAN2, and connects the reference voltage line or the third power line PL3 to the second node n2 to apply the reference voltage Vref. The fourth switching element T4 includes a gate electrode to which the fourth gate signal SCAN2 is applied, a first electrode connected to the third power line PL3, and a second electrode connected to the second node n2.

[0109] The fifth switching element T5 is turned on according to the gate conduction voltage of the third gate signal SCAN1, and connects the third node n3 and the fourth node n4. The fifth switching element T4 includes a gate electrode to which the third gate signal SCAN1 is applied, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4.

[0110] The sixth switching element T6 turns on according to the gate turn-on voltage of the second gate signal EM2, and connects the third node n3 and the fifth node n5. The sixth switching element T6 includes a gate electrode to which the second gate signal EM2 is applied, a first electrode connected to the third node n3, and a second electrode connected to the fifth node n5.

[0111] The seventh switching element T7 turns on according to the gate turn-on voltage of the fifth gate signal SCAN3, and connects the initialization voltage line or the fourth power line PL4 to the fifth node n5 to apply the initialization voltage. The seventh switching element T7 includes a gate electrode to which the fifth gate signal SCAN3 is applied, a first electrode connected to the fifth node n5, and a second electrode connected to the fourth power line PL4.

[0112] The first capacitor Cst may be connected between the second node n2 and the third node n3. The first capacitor Cst may be charged with the gate-source voltage Vgs of the driving element DT.

[0113] The second capacitor C2 may be connected between the fourth node n4 and the first power line PL1.

[0114] The third capacitor C3 is connected between the gate electrode of the fourth switching element T4 and the third node n3.

[0115] The third capacitor C3 can shift the data voltage range without changing the gamma characteristic, thereby reducing the data voltage for high-brightness output, improving power consumption, and increasing the device lifetime.

[0116] Refer to Figure 8 , the pixel circuit according to the second embodiment of the present disclosure can be driven in the order of an initialization step Tini, a sensing step Ts, a data writing step Tw, a reset step Trst, and a light emitting step Tem.

[0117] Refer to Figure 8 and Figure 9A , in the initialization step Tini, the first switching element T1, the third switching element T3, and the fifth switching element T5 are turned off, while the second switching element T2, the fourth switching element T4, and the sixth switching element T6 and the seventh switching element T7 are turned on, so that the reference voltage Vref is applied to the second node n2, and the initialization voltage Vinit is applied to the third node n3. Therefore, the voltage of the second node n2 becomes Vref, and the voltage of the third node n3 becomes Vinit.

[0118] Refer to Figure 8 and Figure 9B, in the sensing step Ts, the second switching element T2, the third switching element T3, and the fifth to seventh switching elements T5 to T7 are turned off, while the first switching element T1 and the fourth switching element T4 are turned on, so that the threshold voltage Vth of the sensing driving element DT is sensed and stored in the first capacitor Cst. Therefore, the voltage of the third node n3 becomes Vinit - Vth.

[0119] At this time, when polling the fourth gate signal SCAN2, the kickback effect is transmitted to the third node n3 through the third capacitor C3, causing the voltage of the third node n3 to decrease and Vgs to increase.

[0120] Referring to Figure 8 and Figure 9C , in the data writing step Tw, the first switching element T1, the second switching element T2, the fourth switching element T4, and the sixth and seventh switching elements T6 and T7 are turned off, and the third switching element T3 and the fifth switching element T5 are turned on, so that the data voltage Vdata of the pixel data is applied to the second node n2. Therefore, the voltage of the second node n2 changes from Vref to Vdata. At this time, a change equal to the ratio Cst / (Cst + C2) of the voltage change of the second node n2 is added to the third node n3.

[0121] Referring to Figure 8 and Figure 9D , in the reset step Trst, the first switching element T1 and the third to fifth switching elements T3 to T5 are turned off, and the second switching element T2 and the sixth and seventh switching elements T6 and T7 are turned on, so that the initialization voltage Vinit is applied to the third node n3. Therefore, the voltage of the third node n3 becomes Vinit.

[0122] Referring to Figure 8 and Figure 9E , in the light emitting step Tem, the third to fifth switching elements T3 to T5 and the seventh switching element T7 are turned off, while the first switching element T1, the second switching element T2, and the sixth switching element T6 are turned on, so that the voltages of the second node n2 and the third node n3 increase, and then the light emitting element EL can emit light with a brightness corresponding to the gray value of the pixel data.

[0123] Figure 10A and Figure 10B is a diagram showing the gamma curve generated by the Figure 7 pixel circuit.

[0124] Referring to Figure 10A, it can be seen that, compared with the comparative example of the pixel circuit using a driving element with a single-gate structure, in the embodiment of the pixel circuit using a driving element with a dual-gate structure, the data voltage for high gray-scale (e.g., 255G) expression is reduced from about 7.45V to 6.5V, and the data voltage range for low gray-scale (e.g., near 0G) expression is significantly reduced from about 0.7V to 0.4V.

[0125] Referring to Figure 10B , when only the second capacitor C2 is added to the embodiment of the pixel circuit using a driving element with a dual-gate structure, the data voltage range for low gray-scale expression is 0.75V, which is equivalent to Figure 10A the comparative example, but the data voltage range for all gray-scales (i.e., 0G to 255G) increases by about 1V. It can be seen that when both the second capacitor C2 and the third capacitor C3 are added, the data voltage range for the entire gray-scale increases.

[0126] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and do not limit the present disclosure.

Claims

1. A pixel circuit, comprising: a driving element including a first electrode connected to the first node, a gate electrode connected to the second node, and a second electrode connected to a third node; a first switching element configured to supply a pixel driving voltage to the first node in response to a first gate signal; a second switching element configured to connect a fourth node to the second node in response to a second gate signal; a third switching element configured to supply a data voltage to the second node in response to a third gate signal; a fourth switching element configured to supply a reference voltage to the second node in response to a fourth gate signal; a fifth switching element configured to connect the fourth node to the third node in response to the third gate signal; a first capacitor connected between the second node and the third node; a second capacitor connected between the first power line and the fourth node; as well as A light emitting element is connected between the third node and the second power line.

2. The pixel circuit according to claim 1, further comprising: a sixth switching element configured to connect the third node to a fifth node, to which the anode electrode of the light emitting element is connected, in response to the second gate signal; as well as A seventh switching element is configured to apply an initialization voltage to the fifth node in response to a fifth gate signal.

3. The pixel circuit according to claim 2, wherein: The pixel circuit is driven in the order of an initialization step, a sensing step, a data writing step, a resetting step, and a light emitting step, and Wherein, in the sensing step, the first switch element and the fourth switch element are turned on.

4. The pixel circuit according to claim 3, wherein: In the light emitting step, the first switching element, the second switching element, and the sixth switching element are turned on.

5. The pixel circuit according to claim 3, wherein: The first switching element includes a gate electrode to which the first gate signal is applied, a first electrode connected to the first power line to which a pixel driving voltage is applied, and a second electrode connected to the first node. The second switching element includes a gate electrode to which the second gate signal is applied, a first electrode connected to the second node, and a second electrode connected to the fourth node. The third switching element includes a gate electrode to which the third gate signal is applied, a first electrode connected to a data line to which the data voltage is applied, and a second electrode connected to the second node. The fourth switching element includes a gate electrode to which the fourth gate signal is applied, a first electrode connected to a reference voltage line to which the reference voltage is applied, and a second electrode connected to the second node, and The fifth switching element includes a gate electrode to which the third gate signal is applied, a first electrode connected to the third node, and a second electrode connected to the fourth node.

6. The pixel circuit according to claim 5, wherein: The sixth switching element includes a gate electrode to which the second gate signal is applied, a first electrode connected to the third node, and a second electrode connected to the fifth node, and The seventh switching element includes a gate electrode to which the fifth gate signal is applied, a first electrode connected to the fifth node, and a second electrode connected to an initialization voltage line to which the initialization voltage is applied.

7. The pixel circuit according to claim 2, wherein: The gate electrode of the driving element includes a first gate electrode connected to the second node and a second gate electrode connected to the first power line.

8. The pixel circuit according to claim 7, further comprising: A third capacitor is connected between the gate electrode of the fourth switching element and the third node.

9. The pixel circuit according to claim 2, wherein: The light-emitting element has a tandem structure in which a plurality of light-emitting layers are stacked.

10. A display device, comprising: A display panel, in which a plurality of data lines, a plurality of gate lines crossing the data lines, and a pixel circuit according to any one of claims 1 to 9 are arranged, wherein a plurality of the pixel circuits are arranged.

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