Display device and method of driving same

Abstract

The present disclosure relates to a display device and a method of driving the display device. More specifically, the present disclosure provides a display device that improves noise characteristics by outputting inverted switching signals from a first power IC and a second power IC that are respectively included in a first power driver and a second power driver configured to supply power to a display panel.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0195428, filed on December 28, 2023, the entire contents of which are incorporated herein by reference for all purposes. Technical field

[0003] The present disclosure relates to a display device, and more particularly, to a display device that improves noise characteristics by outputting inverted switching signals from a first power IC (Integrated Circuit) and a second power IC. Background art

[0004] Recently, with the advent of the information age, the display field for visually expressing electrical information signals has developed rapidly, and in response thereto, various display devices having excellent performance such as thinness, lightness, and low power consumption have been developed.

[0005] Examples of display devices may include liquid crystal display (LCD) devices, organic light - emitting diode (OLED) display devices, quantum dot display devices, and the like.

[0006] Such display devices use a timing controller, a frequency generator, a power driver, etc. for their operation. Summary of the invention

[0007] The present disclosure relates to providing a display device that improves noise characteristics by outputting inverted switching signals from a first power IC and a second power IC of the display device.

[0008] A display device according to an embodiment may include: a timing controller configured to output image data, a command signal, and a data enable signal; a display panel on which a plurality of pixels connected to data lines are provided; and a first power driver and a second power driver configured to supply power to the display panel, wherein the first power driver and the second power driver may respectively include a first power IC and a second power IC, and the first power IC and the second power IC may each generate switching signals having the same phase width, an inverted shape, and the same absolute value of amplitude.

[0009] The timing controller may supply a first data enable signal to the first power IC, and the timing controller may supply a second data enable signal to the second power IC.

[0010] The display device may further include a delay unit configured to receive a first data enable signal from a timing controller and output a second data enable signal. The timing controller may supply the first data enable signal to a first power IC, and the delay unit may supply the second data enable signal to a second power IC.

[0011] The delay unit may include a resistor and a capacitor. The resistor is serially connected to a signal line through which the first data enable signal is transmitted, and the capacitor is connected between a signal line through which the second data enable signal is transmitted and the ground.

[0012] The display device may further include a frequency generator configured to generate a clock signal and an inverted clock signal. The frequency generator may supply the clock signal to a first power IC, and the frequency generator may supply the inverted clock signal to a second power IC.

[0013] The display device may further include: a frequency generator configured to generate a clock signal; and an inverter configured to receive the clock signal from the frequency generator and output an inverted clock signal. The frequency generator may supply the clock signal to a first power IC, and the inverter may supply the inverted clock signal to a second power IC.

[0014] The display device may further include a frequency generator configured to generate a clock signal. The frequency generator may supply the clock signal to a first power IC. The first power IC may generate an inverted clock signal based on the clock signal and supply the inverted clock signal to a second power IC.

[0015] The display device may further include a phase detector configured to receive switching signals from a first power IC and a second power IC.

[0016] The phase detector may include: an edge detector configured to detect edges of the switching signals; and an integrator configured to accumulate the detected edge signals and supply the accumulated signals to the first power IC.

[0017] A method of driving a display device according to another embodiment may include: outputting a data enable signal by a timing controller; and generating switching signals having the same phase width, opposite shapes, and the same absolute value of amplitude by each of a first power IC and a second power IC included in a first power driver and a second power driver configured to supply power to a display panel, respectively.

[0018] The method may further include: supplying, by a timing controller, a first data enable signal to a first power IC; and supplying, by the timing controller, a second data enable signal to a second power IC.

[0019] The method may further include: supplying, by a timing controller, a first data enable signal to a first power IC, and supplying, by a delay unit, a second data enable signal to a second power IC, where the delay unit may receive the first data enable signal from the timing controller and output the second data enable signal.

[0020] The method may further include: supplying, by a frequency generator, a clock signal to a first power IC, and supplying, by the frequency generator, an inverted clock signal to a second power IC, where the frequency generator may generate the clock signal and the inverted clock signal.

[0021] The method may further include: supplying, by a frequency generator, a clock signal to a first power IC, and supplying, by an inverter, an inverted clock signal to a second power IC, where the frequency generator may generate the clock signal, and the inverter may receive the clock signal from the frequency generator and output the inverted clock signal.

[0022] The method may further include: supplying, by a frequency generator, the clock signal to the first power IC, and generating, by the first power IC, an inverted clock signal based on the clock signal and supplying the inverted clock signal to the second power IC.

[0023] The method may further include: receiving, by a phase detector, the switching signals from the first power IC and the second power IC, detecting, by the phase detector, edges of the switching signals, and accumulating, by the phase detector, the detected edge signals and supplying the accumulated signals to the first power IC. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a block diagram showing a display device according to a comparative example of the present disclosure.

[0025] Figure 2 is a diagram showing pixels and sub-pixels according to various embodiments of the present disclosure.

[0026] Figure 3 is a circuit diagram showing a circuit of a sub-pixel according to various embodiments of the present disclosure.

[0027] Figure 4 is a circuit diagram showing the inside of a power driver according to a comparative example of the present disclosure.

[0028] Figure 5 is a block diagram showing a display device according to a first embodiment of the present disclosure.

[0029] Figure 6 is a circuit diagram showing the inside of a first power driver according to a first embodiment of the present disclosure and a switching signal output from a first power IC.

[0030] Figure 7 is a circuit diagram showing the inside of a second power driver according to a first embodiment of the present disclosure and a switching signal output from a second power IC.

[0031] Figure 8 is a timing diagram showing switching signals output from a first power IC and a second power IC according to a first embodiment of the present disclosure.

[0032] Figure 9 is a circuit diagram showing a second data enable signal being supplied from a delay unit to a second power IC according to a second embodiment of the present disclosure.

[0033] Figure 10 is a circuit diagram showing the inside of a delay unit according to a second embodiment of the present disclosure.

[0034] Figure 11 is a timing diagram showing switching signals output from a first power IC and a second power IC according to a third embodiment of the present disclosure.

[0035] Figure 12 is a circuit diagram showing an inverted clock signal being supplied from an inverter unit to a second power IC according to a fourth embodiment of the present disclosure.

[0036] Figure 13 is a timing diagram showing switching signals output from a first power IC and a second power IC according to a fifth embodiment of the present disclosure.

[0037] Figure 14 is a circuit diagram showing switching signals being supplied from a first power IC and a second power IC to a phase detector according to a fifth embodiment of the present disclosure.

[0038] Figure 15 is a circuit diagram showing a DC output voltage being generated using the inside of a phase detector and switching signals output from a first power IC and a second power IC according to a fifth embodiment of the present disclosure.

[0039] Figure 16 is a timing diagram showing switching signals detected by an edge detector being eliminated according to a fifth embodiment of the present disclosure.

[0040] Figure 17 is a diagram showing noise introduced by a coupler according to the present disclosure.

[0041] Figure 18 This is a diagram showing the effects according to the present disclosure. Detailed implementation

[0042] The advantages and features of the present disclosure and the methods for achieving them will become clear with reference to the following embodiments described in detail in conjunction with the accompanying drawings. The present disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms. These embodiments are provided only to make the disclosure of the present disclosure complete and to fully inform those skilled in the art of the scope of the present disclosure, and the present disclosure is limited only by the scope of the appended claims.

[0043] Since the shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present disclosure are illustrative, the present disclosure is not limited to the items shown. Throughout the specification, the same reference numerals indicate the same components. In addition, when determining that a detailed description of related known technologies may unnecessarily obscure the gist of the present disclosure, the detailed description thereof will be omitted.

[0044] When using the terms "comprising", "including", "having", and "consisting of" described in this specification, unless "only" is used, other parts can be added. When a component is expressed in the singular, it can be interpreted as multiple components unless otherwise specifically stated.

[0045] When interpreting a component, even without a separate explicit statement, the component is interpreted as including an error range.

[0046] When describing a positional relationship, for example, when using terms such as "on", "above", "below", "next to", etc. to describe the positional relationship between two components, unless the terms "immediately" or "directly" are used, one or more other components can be positioned between the described components.

[0047] Although terms such as "first" and "second" can be used to distinguish components, the functions or structures of the components are not limited by the serial numbers or component names added in front of the components.

[0048] The following embodiments can be partially or fully coupled or combined, and various technical interconnections and drivings are possible. The embodiments can be implemented independently of each other and can be implemented together in a related relationship.

[0049] The driving circuit of a display device can write the pixel data of an input image into the pixels. The driving circuit of a flat panel display device can include a data driver for supplying a data signal to a data line and a gate driver for supplying a gate signal to a gate line.

[0050] In a display device according to the present disclosure, each of the pixel circuit and the gate driver may include a plurality of transistors and may be directly formed on a substrate of the display panel. The transistors may be implemented as thin film transistors (TFTs) having a metal oxide semiconductor field effect transistor (MOSFET) structure and may be oxide TFTs including an oxide semiconductor or LTPS TFTs including low temperature polycrystalline silicon (LTPS).

[0051] A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode for supplying carriers to the transistor. Carriers flow starting from the source in the transistor. The drain is an electrode through which carriers move out of the transistor to the outside. In the transistor, the flow of carriers is from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor, the direction of the current is from the drain to the source. In the case of a p-channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain may change according to the applied voltage. Therefore, the present disclosure is not limited to the source and drain of the transistor. In the following description, the source and drain of the transistor are referred to as "the first electrode and the second electrode".

[0052] The gate signal may swing between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor. The gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0053] The transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage VGH or VEH, and the gate-off voltage may be a gate low voltage VGL or VEL. In the case of a p-channel transistor, the gate-on voltage may be a gate low voltage VGL or VEL, and the gate-off voltage may be a gate high voltage VGH or VEH. In the following embodiments, although an example in which the transistors of the pixel circuit are implemented as p-channel transistors will be mainly described, it should be noted that the present disclosure is not limited thereto.

[0054] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, although the display device is an OLED display device in the examples, the present disclosure is not limited thereto.

[0055] Figure 1is a block diagram showing a display device according to various embodiments of the present disclosure.

[0056] Referring Figure 1 , a display device according to various embodiments of the present disclosure may include a display panel 100, a timing controller 200, a gate driver 300, a data driver 400, and a power driver 500.

[0057] The display panel 100 includes a pixel array in which an input image is displayed on a screen. The pixel array includes a plurality of data lines DL, a plurality of gate lines GL intersecting the data lines DL, and sub-pixels SP arranged in a matrix form.

[0058] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The display panel 100 may be manufactured as a flexible display panel. The flexible display panel may be implemented as an OLED panel using a plastic substrate.

[0059] The timing controller 200 receives digital video data Data of an input image and timing signals Vsync, Hsync, and Clk synchronized with the digital video data Data from a setting system (or a host system). The digital video data is a differential data signal and may be serial data. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal Clk. The setting system or the host system may include: a TV, a monitor, a set-top box, a navigation system, a personal computer, a home theater system, a mobile device, a wearable device, a vehicle system, etc.

[0060] The timing controller 200 may control the operation timing of the display panel 100 according to an input frequency (or a driving frequency). In the National Television Standards Committee (NTSC) format, the input frequency may be 60 Hz. Recently, display devices driven at a higher frequency of 120 Hz have become popular. Additionally, in some cases, a display device driven at 120 Hz may be controlled to be temporarily driven at 60 Hz. Additionally, recently, display devices supporting variable refresh rate (VRR) have been developed, and under the variable refresh rate, the display device is operated by: in a low-speed driving mode, reducing the frame frequency to a frequency between 1 Hz and 30 Hz, and in the case of a high-resolution image (e.g., game mode), increasing the frame frequency to 144 Hz.

[0061] The timing controller 200 may output serial image data Sdata provided to the data driver 400, command data CMD for controlling the data driver 400, and a gate control signal GCS for controlling the gate driver 300 based on the received timing signals Vsync, Hsync, and Clk.

[0062] The gate driver 300 can be implemented as an in-panel gate (GIP) circuit, which is formed directly on the display panel 100 together with the TFT array and lines in the pixel array. The gate driver 300 can sequentially output gate signals to the gate lines GL under the control of the timing controller 200. The gate driver 300 can shift the gate signals by using a shift register unit (not shown) and sequentially output the signals to a plurality of gate lines GL.

[0063] The data driver 400 can use a digital-to-analog converter (not shown) to convert the pixel data of the input image received from the timing controller 200 as a digital signal into a gamma-compensated voltage in each frame period and output a data voltage. The data driver 400 can be implemented as a plurality of source driver integrated circuits. The data driver 400 can be electrically connected to the data lines DL of the display panel 100 by a chip-on-glass (COG) process or a tape automated bonding (TAB) process.

[0064] The power driver 500 can use a DC-DC converter to output the DC power required to drive the pixel array of the display panel 100 and the drivers 300 and 400. The power driver 500 can receive a DC input voltage Vin and can output DC voltages, such as a gate high voltage VGH, a gate low voltage VGL, a high potential power supply voltage ELVDD, a low potential power supply voltage ELVSS, a high potential reference voltage (not shown), and an initialization voltage (not shown).

[0065] Specifically, the gate high voltage VGH is a voltage set to be equal to or higher than the threshold voltage of the transistors formed in the array of sub-pixels SP. The gate high voltage VGH can be output to the gate driver 300 and supplied to the level shifter in the gate driver 300.

[0066] The gate low voltage VGL is a voltage lower than the threshold voltage of the transistors formed in the array of sub-pixels SP. The gate low voltage VGL can be supplied to a level shifter (not shown) in the gate driver 300.

[0067] The high potential power supply voltage ELVDD is a voltage supplied to the anode of the light-emitting element and is a positive voltage for driving the light-emitting element. The high potential power supply voltage ELVDD can be supplied to the high potential power supply voltage lines connected to each sub-pixel SP in the display panel 100. The low potential power supply voltage ELVSS is a voltage supplied to the cathode of the light-emitting element and is a negative voltage for driving the light-emitting element. The low potential power supply voltage ELVSS can be supplied to the low potential power supply voltage lines connected to each sub-pixel SP in the display panel 100.

[0068] Figure 2It is a diagram showing pixels and sub-pixels according to various embodiments of the present disclosure.

[0069] A pixel may have Figure 2 the arrangement shown. Referring to Figure 2 , each pixel P may include a plurality of sub-pixels SP. The sub-pixels SP may include a red sub-pixel SP(R), a green sub-pixel SP(G), and a blue sub-pixel SP(B). In some cases, the pixel P may also include a white sub-pixel (not shown).

[0070] Each of data lines DL1 to DL6 may transmit a data voltage Vdata for displaying an image to the sub-pixel SP. For example, gate signals of scan signals SC1 and SC2 for turning on and off transistors and emission signals EM1 and EM2 for controlling light emission may be applied to gate lines GL1 and GL2, respectively.

[0071] The gate signal may be in the form of a pulse that swings between a gate-on voltage and a gate-off voltage. The scan signals SC1 and SC2 may select the pixels of the gate lines into which data is written synchronously with the data voltage Vdata. The emission signals EM1 and EM2 may define the emission time of the pixels.

[0072] Figure 3 It is a circuit diagram showing the circuit of a sub-pixel according to various embodiments of the present disclosure. Figure 3 It shows an example in which a pixel PX ij is connected to the i-th gate line GL i and the j-th data line DL j .

[0073] Referring to Figure 3 , the pixel PX ij may include a switching transistor ST, a driving transistor DT, a sensing transistor SST, a storage capacitor Cst, and a light-emitting element LD.

[0074] The first electrode (e.g., source electrode) of the switching transistor ST may be electrically connected to the j-th data line DL j , and the second electrode (e.g., drain electrode) of the switching transistor ST may be electrically connected to the first node N1. The gate electrode of the switching transistor ST may be electrically connected to the i-th first gate line GL1 i . When a gate signal at a gate-on level is applied to the i-th first gate line GL1 i , the switching transistor ST may be turned on to transmit the data signal applied to the j-th data line DL j to the first node N1.

[0075] The first electrode of the storage capacitor Cst may be electrically connected to the first node N1, and the second electrode of the storage capacitor Cst may be connected to the second node N2. The first electrode of the light-emitting element LD may be electrically connected to the second node N2. The storage capacitor Cst may be charged to a voltage corresponding to the difference between the voltage applied to the first node N1 and the voltage applied to the second node N2.

[0076] The first electrode (e.g., source electrode) of the driving transistor DT may be configured to receive a high-potential power supply voltage ELVDD, the second electrode (e.g., drain electrode) of the driving transistor DT may be electrically connected to the second node N2, and the gate electrode of the driving transistor DT may be electrically connected to the first node N1. When a voltage at a gate-conducting level is applied through the first node N1, the driving transistor DT may be turned on, and the driving transistor DT may control the amount of driving current flowing through the light-emitting element LD in response to the voltage supplied to the gate electrode.

[0077] The first electrode (e.g., source electrode) of the sensing transistor SST may be electrically connected to the j-th sensing line SL j , the second electrode (e.g., drain electrode) of the sensing transistor SST may be electrically connected to the second node N2, and the gate electrode of the sensing transistor SST may be electrically connected to the i-th second gate line GL2 i . When a sensing signal at a gate-conducting level is applied to the i-th second gate line GL2 i , the sensing transistor SST may be turned on to transmit a reference voltage applied to the j-th sensing line SL j to the first electrode of the light-emitting element LD.

[0078] The light-emitting element LD may emit light corresponding to the driving current. The light-emitting element LD may output light corresponding to any one of red, green, blue, and white. The light-emitting element LD may be an OLED or an ultra-small inorganic light-emitting element having a size range from the micron scale to the nanometer scale, but the present embodiment is not limited thereto. Hereinafter, the technical spirit of the present embodiment will be described with reference to an embodiment in which the light-emitting element LD is configured as an OLED.

[0079] In the present embodiment, the structure of the pixel PX ij is not limited to Figure 3 the structure shown. According to an embodiment, the pixel PX ij may further include at least one element for compensating the threshold voltage of the driving transistor DT or initializing the voltage of the gate electrode of the driving transistor DT and / or the voltage of the first electrode of the light-emitting element LD. In this case, the sensing transistor SST may be omitted from the pixel PX ij .

[0080] Figure 3 FIG. Figure 3 shows an example in which the switching transistor ST, the driving transistor DT, and the sensing transistor SST are NMOS transistors, but the present disclosure is not limited thereto. For example, at least some or all of the transistors forming each pixel PX may be formed as PMOS transistors. In various embodiments, the switching transistor ST, the driving transistor DT, and the sensing transistor SST may each be implemented as an LTPS TFT, an oxide TFT, or a low-temperature polycrystalline oxide (LTPO) TFT.

[0081] Figure 4 is a circuit diagram showing the inside of a power driver according to one or more embodiments of the present disclosure.

[0082] Referring to Figure 4 , the power driver 500 may receive a DC input voltage Vin and generate a DC output voltage Vout. The DC output voltage Vout may be a gate high voltage VGH, a gate low voltage VGL, a high potential power supply voltage ELVDD, or a low potential power supply voltage ELVSS.

[0083] The power IC 501 may output a switching signal SW. The switching signal SW may be input to the gate electrode of the switching MOSFET Ms to generate the DC output voltage Vout using a pulse width modulation (PWM) method. In this case, in order to stably output the DC output voltage Vout, the power driver 501 may further include a switching diode Ds, a switching inductor Ls, and a switching capacitor Cs.

[0084] Figure 5 is a block diagram showing a display device according to a first embodiment of the present disclosure.

[0085] Referring to Figure 5 , a display device according to a first embodiment of the present disclosure may include: a first display panel 110, a second display panel 120, a timing controller 200, a first gate driver 310, a second gate driver 320, a first data driver 410, a second data driver 420, a first power driver 510, and a second power driver 520.

[0086] Referring to Figure 1 and Figure 5 , the display panel 100 may be separately driven as the first display panel 110 and the second display panel 120.

[0087] The timing controller 200 receives digital video data Data of an input image and timing signals Vsync, Hsync, and Clk synchronized with the digital video data Data from a setting system (or a host system). The digital video data Data is a differential data signal and is serial data. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal Clk. The timing controller 200 may control the operation timings of the first display panel 110 and the second display panel 120 according to an input frequency (or a driving frequency).

[0088] The timing controller 200 may output each of the following: serial image data Sdata1, Sdata2 provided to the first data driver 410 and the second data driver 420; command data CMD1 and CMD2 for controlling the first data driver 410 and the second data driver 420; and gate control signals GCS1 and GCS2 for controlling the first gate driver 310 and the second gate driver 320 based on the received timing signals Vsync, Hsync, and Clk.

[0089] The first power driver 510 and the second power driver 520 may output a gate high voltage VGH1 and VGH2, a gate low voltage VGL1 and VGL2, a high-potential power supply voltage ELVDD1 and ELVDD2, and a low-potential power supply voltage ELVSS1 and ELVSS2. The timing controller 200 may supply a first data enable signal DE1 and a second data enable signal DE2 to the first power driver 510 and the second power driver 520, respectively. The first data enable signal DE1 and the second data enable signal DE2 are signals having a period of one horizontal period 1H. The first power driver 510 may supply the gate high voltage VGH1 and the gate low voltage VGL1 to the first gate driver circuit 310. The second power driver 520 may supply the gate high voltage VGH2 and the gate low voltage VGL2 to the second gate driver circuit 320.

[0090] Figure 6 is a circuit diagram showing the inside of the first power driver according to the first embodiment of the present disclosure and switching signals output from the first power IC Figure 7 is a circuit diagram showing the inside of the second power driver according to the first embodiment of the present disclosure and switching signals output from the second power IC.

[0091] Referring to Figure 6 and Figure 7 , the first power IC 511 and the second power IC 521 may output a first switching signal SW1 and a second switching signal SW2, respectively. The phase widths of the first switching signal SW1 and the second switching signal SW2 may be one period (1T).

[0092] Referring to Figure 6 , the first switching signal SW1 can be input to the gate electrode of the first switching MOSFET M1s to generate a first DC output voltage Vout1 using the PWM method. In this case, in order to stably output the first DC output voltage Vout1, the first power driver 510 may further include a first switching diode D1s, a first switching inductor L1s, and a first switching capacitor C1s.

[0093] Referring to Figure 7 , the second switching signal SW2 can be input to the gate electrode of the second switching MOSFET M2s to generate a second DC output voltage Vout2 using the PWM method. In this case, in order to stably output the second DC output voltage Vout2, the second power driver 520 may further include a second switching diode D2s, a second switching inductor L2s, and a second switching capacitor C2s.

[0094] Referring to Figure 6 and Figure 7 , the second data enable signal DE2 can be a signal that is one cycle (1T) later than the first data enable signal DE1. Therefore, the second switching signal SW2 generated based on the second data enable signal DE2 can be a signal that is one cycle (1T) later than the first switching signal SW1 generated based on the first data enable signal DE1.

[0095] Figure 8 is a timing diagram showing switching signals output from the first power IC and the second power IC according to the first embodiment of the present disclosure.

[0096] Referring to Figure 8 , the timing controller 200 can supply the first data enable signal DE1 to the first power IC 511, and the first power IC 511 can output the first switching signal SW1. In addition, the timing controller 200 can supply the second data enable signal DE2 to the second power IC 521, and the second power IC 521 can output the second switching signal SW2.

[0097] The second data enable signal DE2 output from the timing controller 200 can be a signal that is one cycle (1T) later than the first data enable signal DE1. Since the phase widths of the first switching signal SW1 and the second switching signal SW2 are one cycle (1T), the second switching signal SW2 and the first switching signal SW1 can have the same phase width, shapes that are opposite to each other, and the same absolute value of amplitude (anti-phase signals). Therefore, the first switching signal SW1 can have a first phase, the second switching signal SW2 can have a second phase, and the first phase can be opposite to the second phase.

[0098] Figure 9 This is a circuit diagram showing the supply of a second data enable signal from a delay unit to a second power IC according to a second embodiment of the present disclosure.

[0099] Referring to Figure 9 , the timing controller 200 can supply a first data enable signal DE1 to the first power IC 511, and the first power IC 511 can output a first switch signal SW1. Additionally, the timing controller 200 can supply the first data enable signal DE1 to the delay unit 610, the delay unit 610 can supply a second data enable signal DE2 to the second power IC 521, and the second power IC 521 can output a second switch signal SW2.

[0100] The second data enable signal DE2 output from the delay unit 610 can be a signal that is one cycle (1T) later than the first data enable signal DE1. Since the phase widths of the first switch signal SW1 and the second switch signal SW2 are 1 cycle (1T), the second switch signal SW2 and the first switch signal SW1 can have the same phase width, shapes that are inverted with respect to each other, and the same absolute value of amplitude (inverted signals).

[0101] Figure 10 This is a circuit diagram showing the inside of a delay unit according to a second embodiment of the present disclosure.

[0102] The delay unit 610 can include: a resistor R that is serially connected to the signal line through which the first data enable signal DE1 is transmitted; and a capacitor C that is connected between the signal line through which the second data enable signal DE2 is transmitted and the ground.

[0103] By adjusting the size of the resistor and the capacitance of the capacitor, the second data enable signal DE2 can be generated by delaying the first data enable signal DE1. In this case, when the second data enable signal DE2 is delayed by one cycle (1T) compared to the first data enable signal DE1, the second switch signal SW2 and the first switch signal SW1 can have the same phase width, shapes that are inverted with respect to each other, and the same absolute value of amplitude (inverted signals).

[0104] Figure 11 This is a timing diagram showing the switch signals output from the first power IC and the second power IC according to a third embodiment of the present disclosure.

[0105] Referring to Figure 11, the frequency generator 700 can supply a clock signal CLK to the first power IC 511, and the first power IC 511 can output a first switching signal SW1. Additionally, the frequency generator 700 can supply an inverted clock signal CLKB to the second power IC 521, and the second power IC 521 can output a second switching signal SW2. In one or more embodiments, the frequency generator 700 is part of the timing controller 200.

[0106] The clock signal CLK output from the frequency generator 700 can be a signal that is one cycle (1T) later than the inverted clock signal CLKB. Since the phase widths of the first switching signal SW1 and the second switching signal SW2 are one cycle (1T), the second switching signal SW2 and the first switching signal SW1 can have the same phase width, shapes that are inverted with respect to each other, and the same absolute value of amplitude (inverted signals).

[0107] Figure 12 is a circuit diagram showing the supply of an inverted clock signal from an inverter unit to a second power IC according to a fourth embodiment of the present disclosure.

[0108] Refer to Figure 12 , the frequency generator 700 can supply a clock signal CLK to the first power IC 511, and the first power IC 511 can output a first switching signal SW1. Additionally, the frequency generator 700 can supply a clock signal CLK to the inverter 620, the inverter 620 can supply an inverted clock signal CLKB to the second power IC 521, and the second power IC 521 can output a second switching signal SW2.

[0109] The inverted clock signal CLKB output from the inverter 620 can be a signal that is one cycle (1T) later than the clock signal CLK. Since the phase widths of the first switching signal SW1 and the second switching signal SW2 are one cycle (1T), the second switching signal SW2 and the first switching signal SW1 can have the same phase width, shapes that are inverted with respect to each other, and the same absolute value of amplitude (inverted signals).

[0110] Figure 13 is a timing diagram showing the switching signals output from the first power IC and the second power IC according to a fifth embodiment of the present disclosure.

[0111] Refer to Figure 13 , the frequency generator 700 can supply a clock signal CLK to the first power IC 511, and the first power IC 511 can output a first switching signal SW1. The first power IC 511 can supply an inverted clock signal CLKB to the second power IC 521, and the second power IC 521 can output a second switching signal SW2.

[0112] The first power IC 521 can generate an inverted clock signal CLKB based on the clock signal CLK. By generating the inverted clock signal CLKB from the first power IC 511 and supplying the inverted clock signal CLKB to the second power IC 521, the phase difference between the clock signal CLK and the inverted clock signal CLKB can be reduced.

[0113] The inverted clock signal CLKB output from the first power IC 521 can be a signal that is one cycle (1T) later than the clock signal CLK. Since the phase widths of the first switch signal SW1 and the second switch signal SW2 are one cycle (1T), the second switch signal SW2 and the first switch signal SW1 can have the same phase width, shapes that are inverted with respect to each other, and the same absolute value of amplitude (inverted signals).

[0114] Figure 14 is a circuit diagram showing the supply of switch signals from a first power IC and a second power IC to a phase detector according to a fifth embodiment of the present disclosure.

[0115] Referring to Figure 14 , the phase detector 630 can receive the switch signals SW1 and SW2 and determine whether the first switch signal SW1 and the second switch signal SW2 have the same phase width, shapes that are inverted with respect to each other, the same absolute value of amplitude, etc.

[0116] Figure 15 is a circuit diagram showing the inside of a phase detector according to a fifth embodiment of the present disclosure.

[0117] Referring to Figure 15 , the phase detector 630 can include: an edge detector 631 for detecting the edges of the switch signals SW1 and SW2; and an integrator 632 for accumulating the detected edge signals and supplying the accumulated signals to the first power IC 511. The first power IC 511 can receive the accumulated signals from the integrator 632 and adjust the phase of the inverted clock signal CLKB based on the accumulated signals, and the inverted clock signal CLKB is then output to the second power IC 521. By adjusting the phase of the inverted clock signal CLKB, the output of the edge detector 631 can be held at the ground voltage (0V), which corresponds to the switch signals SW1 and SW2 having opposite phases to each other.

[0118] The edge detector 631 may have a first input terminal connected to the output terminal of the first power IC 511 and a second input terminal connected to the output terminal of the second power IC 521. The output terminal of the edge detector 631 may be connected to the inverting terminal (“-” terminal) of the integrator 632. A resistor may also be connected between the output terminal of the edge detector 631 and the inverting terminal (“-” terminal) of the integrator 632.

[0119] The inverting terminal (“-” terminal) of the integrator 632 may be connected to the output terminal of the edge detector 631, and the non-inverting terminal (“+” terminal) of the integrator 632 may be connected to ground. The output terminal of the integrator 632 may be connected to the first power IC 511, and a capacitor may also be connected between the output terminal of the integrator 632 and the inverting terminal (“-” terminal).

[0120] Referring to Figure 15 , the first switching signal SW1 output from the first power IC 511 may be input to the gate electrode of the first switching MOSFET M1s to generate a first DC output voltage Vout1 using the PWM method. In this case, in order to stably output the first DC output voltage Vout1, the phase detector 630 may further include a first switching diode D1s, a first switching inductor L1s, a first switching capacitor C1s, and a first variable resistor R1s.

[0121] The second switching signal SW2 output from the second power IC 521 may be input to the gate electrode of the second switching MOSFET M2s to generate a second DC output voltage Vout2 using the PWM method. In this case, in order to stably output the second DC output voltage Vout2, the phase detector 630 may further include a second switching diode D2s, a second switching inductor L2s, a second switching capacitor C2s, and a second variable resistor R2s.

[0122] Figure 16 is a timing diagram showing that the switching signal detected by the edge detector according to the fifth embodiment of the present disclosure is eliminated.

[0123] Referring to Figure 15 and Figure 16 , the output terminal of the edge detector 631 outputs the sum of the accumulated values of the high-potential voltage +Vdd output from the first switching signal SW1 and the low-potential voltage -Vdd output from the second switching signal SW2.

[0124] When the output of the edge detector 631 remains at the ground voltage (0 V), it can be seen that the second switch signal SW2 and the first switch signal SW1 have the same phase width, shapes that are inverted with respect to each other, and the same absolute value of amplitude. When the output of the edge detector 631 is not the ground voltage (0 V), the voltage accumulated at the output terminal of the integrator 632 is input to the first power IC. The first power IC can determine the input accumulated voltage and compensate the phases of the first switch signal SW1 and the second switch signal SW2 to be the same through the first variable resistor R1s and the second variable resistor R2s.

[0125] Figure 17 FIG. is a diagram showing noise introduced by a coupler according to one or more embodiments of the present disclosure.

[0126] Referring to Figure 17 , the coupler may have a long hexagonal shape and the coupler has an input port. The DC output voltage Vout may be connected to the input port PORT of the coupler.

[0127] Referring to FIG. 171, FIG. 171 shows that when non-inverted switch signals are not used, noise is generated throughout the coupler.

[0128] Referring to FIG. 172, FIG. 172 shows that when inverted switch signals are used, the noise is reduced throughout the coupler.

[0129] Figure 18 FIG. is a diagram showing the effect of inverted switch signals when driving a display device according to one or more embodiments of the present disclosure.

[0130] Figure 18 In FIGS. 181 to 182, the horizontal axis indicates the frequency in megahertz (MHz), and the vertical axis indicates the noise in decibels (dB).

[0131] Referring to FIG. 181, when the power driver 500 is used as the first power driver 510 and the second power driver 520, FIG. 181 shows that the noise increases by 5.58 dB.

[0132] Referring to FIG. 182, when the first power driver 510 and the second power driver 520 use inverted switch signals, the noise is reduced by 23.59 dB.

[0133] A method of driving the above-described display device according to an embodiment of the present disclosure will be schematically described below. However, only the description related to the driving method is schematically described to assist understanding, and the description related to the driving method should not be construed as the entire content of the specific embodiments of the present disclosure.

[0134] First, the timing controller 200 outputs a first data enable signal DE1 and a second data enable signal DE2. The first data enable signal DE1 is received at a first power IC 511 inside a first power driver 510 that supplies a first power to the display panel 110. The second data enable signal DE2 is received at a second power IC 521 inside a second power driver 520 that supplies a second power to the display panel 120. Next, the first power IC 511 and the second power IC 521 each generate switching signals having the same phase width, shapes that are inverted with respect to each other, and the same absolute value of amplitude, based on the first data enable signal DE1 and the second data enable signal DE2.

[0135] The first power IC 511 and the second power IC 521 may receive a clock signal CLK and an inverted clock signal CLKB from a frequency generator 700 instead of the timing controller 200.

[0136] In addition, the second power IC 521 may receive the second data enable signal DE2 and the inverted clock signal CLKB from a delay unit 610 and an inverter 620, respectively, instead of receiving the second data enable signal DE2 and the inverted clock signal CLKB from the timing controller 200 and the frequency generator 700, respectively.

[0137] Based on the display device according to an embodiment of the present disclosure, noise characteristics can be improved by outputting inverted switching signals from the first power IC and the second power IC.

[0138] The above description and the drawings only illustrate the technical spirit of the present disclosure, and those skilled in the art to which the present disclosure pertains can make various changes or modifications without departing from the basic characteristics of the present disclosure, such as coupling, separating, replacing, and changing components. Therefore, the embodiments disclosed herein are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The scope of the present disclosure should be interpreted according to the appended claims, and all technical spirits within the equivalent scope should be interpreted as being included within the scope of the present disclosure.

Claims

1. A display device, comprising: a timing controller configured to output image data, a command signal, and a data enable signal; A display panel, on which a plurality of pixels connected to the data lines are arranged; as well as a first power driver and a second power driver, the first power driver and the second power driver being configured to supply power to the display panel, The first power driver and the second power driver include a first power IC and a second power IC, respectively, and The first power IC and the second power IC each generate a switching signal having the same phase width, an inverted shape, and the same absolute value of amplitude.

2. The display device according to claim 1, wherein: The timing controller supplies a first data enable signal to the first power IC, and The timing controller supplies a second data enable signal to the second power IC.

3. The display device according to claim 1 , further comprising a delay unit configured to: receive a first data enable signal from the timing controller and output a second data enable signal, in, The timing controller supplies the first data enable signal to the first power IC, and The delay unit supplies the second data enable signal to the second power IC.

4. The display device according to claim 3, wherein: The delay unit includes: a resistor connected in series to a signal line through which the first data enable signal is transmitted; and a capacitor connected between the signal line through which the second data enable signal is transmitted and a ground line.

5. The display device according to claim 1 , further comprising a frequency generator configured to generate a clock signal and an inverted clock signal, in, The frequency generator supplies the clock signal to the first power IC, and The frequency generator supplies the inverted clock signal to the second power IC.

6. The display device according to claim 1, further comprising: a frequency generator configured to generate a clock signal; as well as an inverter configured to receive the clock signal from the frequency generator and output an inverted clock signal, wherein the frequency generator supplies the clock signal to the first power IC, and The inverter supplies the inverted clock signal to the second power IC.

7. The display device according to claim 1, further comprising: a frequency generator configured to generate a clock signal, wherein the frequency generator supplies the clock signal to the first power IC, The first power IC generates an inverted clock signal based on the clock signal, and The first power IC supplies the inverted clock signal to the second power IC. 8 . The display device of claim 7 , further comprising a phase detector configured to receive the switching signal from the first power IC and the second power IC.

9. The display device according to claim 8, wherein: The phase detector comprises: an edge detector configured to detect an edge of the switching signal; and An integrator is configured to accumulate the detected edge signal and supply the accumulated signal to the first power IC.

10. A method for driving a display device, comprising: The timing controller outputs a data enable signal; as well as A switching signal having the same phase width, inverted shape, and the same absolute amplitude value is generated by each of the first power IC and the second power IC, wherein the first power IC and the second power IC are respectively included in the first power driver and the second power driver configured to supply power to the display panel.

11. The method according to claim 10, further comprising: The timing controller supplies a first data enable signal to the first power IC; as well as The timing controller supplies a second data enable signal to the second power IC.

12. The method according to claim 10, further comprising: The timing controller supplies a first data enable signal to the first power IC; as well as supplying a second data enable signal to the second power IC through the delay unit, The delay unit receives the first data enable signal from the timing controller and outputs the second data enable signal.

13. The method according to claim 10, further comprising: Supplying a clock signal to the first power IC from a frequency generator; as well as The frequency generator supplies an inverted clock signal to the second power IC. Wherein, the frequency generator generates the clock signal and the inverted clock signal.

14. The method according to claim 10, further comprising: Supplying a clock signal to the first power IC from a frequency generator; as well as The inverter supplies an inverted clock signal to the second power IC. The frequency generator generates the clock signal, and the inverter receives the clock signal from the frequency generator and outputs the inverted clock signal.

15. The method according to claim 10, further comprising: A frequency generator supplies a clock signal to the first power IC, and An inverted clock signal is generated by the first power IC based on the clock signal, and the inverted clock signal is supplied to the second power IC.

16. The method according to claim 15, further comprising: receiving the switching signal from the first power IC and the second power IC by a phase detector, The edge of the switching signal is detected by a phase detector, and The detected edge signal is accumulated by the phase detector and the accumulated signal is supplied to the first power IC.

17. A display device, comprising: a timing controller configured to generate one or more data enable signals; a first display panel having a first plurality of pixels; a second display panel having a second plurality of pixels; a first power driver configured to: generate a first switching signal having a first phase based on the one or more data enable signals, and supply one or more first output voltages generated based on the first switching signal to the first display panel; as well as A second power driver is configured to generate a second switching signal having a second phase different from the first phase based on the one or more data enable signals, and supply one or more second output voltages generated based on the second switching signal to the second display panel.

18. The display device according to claim 17, wherein: The first phase is opposite to the second phase, and the first switching signal and the second switching signal have the same cycle of one horizontal period and the same absolute value of amplitude.

19. The display device according to claim 17, wherein: The one or more data enable signals include a first data enable signal; The display device further includes a delay unit configured to: receive the first data enable signal, and generate a second data enable signal by delaying the first data enable signal; The first power driver is further configured to: generate a first switching signal having the first phase based on the first data enable signal; and The second power driver is further configured to generate a second switching signal having the second phase based on the second data enable signal.

20. The display device according to claim 17, wherein: The one or more data enable signals include a clock signal; The timing controller includes a frequency generator configured to generate the clock signal; The display device further includes an inverter configured to receive the clock signal and output an inverted clock signal; The first power driver is further configured to: generate a first switching signal having the first phase based on the clock signal; as well as The second power driver is further configured to generate a second switching signal having the second phase based on the inverted clock signal.

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