Level shifter and display device including same

Abstract

A level shifter according to an embodiment and a display device including the same are disclosed. A level shifter includes: a first logic circuit configured to receive, from a timing controller, a mode selection signal of a first voltage level for selectively driving a first light emitting element and a second light emitting element emitting light at different viewing angles of a pixel circuit, and transmit the mode selection signal; and a second logic circuit configured to convert the mode selection signal of the first voltage level to a mode selection signal of a second voltage level higher than the first voltage level, and output the converted mode selection signal of the second voltage level to the pixel circuit.

Description

[0001] Cross - reference to related applications

[0002] This patent application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0193929, filed on December 28, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a level shifter and a display device including the level shifter. Background art

[0004] Variable viewing angle technology is being applied to display devices. The variable viewing angle technology can present video content or visual information reproduced on the display device only to users within a narrow viewing angle range or to multiple users within a wide viewing angle range.

[0005] As the market for future vehicles such as electric vehicles and autonomous driving vehicles expands, the demand for vehicle display devices has increased rapidly. Research is being conducted on methods for dividing the screen of a vehicle display device and controlling a part of the screen to have a narrow viewing angle while another part has a wide viewing angle. This technology can drive pixels with a narrow viewing angle arranged in one area of the screen to display personal content or information that can be viewed only by a specific user, and at the same time drive pixels with a wide viewing angle arranged in another area of the screen to display shared content that can be viewed by multiple users together.

[0006] In a vehicle display device, a display panel for an organic light - emitting display device has drawn attention. The organic light - emitting display device includes organic light - emitting diodes (hereinafter referred to as "OLEDs") that emit light by themselves, and has advantages such as a fast response speed, good luminous efficiency and brightness, and a wide viewing angle. The organic light - emitting display device has a fast response speed, is excellent in terms of luminous efficiency, brightness, and viewing angle, and provides excellent contrast and color reproducibility because it can represent black grayscale with all - black. Since the display panel of the organic light - emitting display device can be flexibly bent, a curved surface can be easily realized. Due to these advantages, the market share of the organic light - emitting display device in the vehicle display device market is increasing rapidly. Summary of the invention

[0007] In a display device to which variable viewing angle technology is applied, the entire screen can be controlled to a specific viewing angle, or the viewing angle can be controlled for each screen area having a preset size. Various methods are required to apply a mode selection signal for such viewing angle control.

[0008] The present disclosure aims to solve all of the above - mentioned needs and problems.

[0009] The present disclosure provides a level shifter and a display device including the level shifter.

[0010] It should be noted that the purpose of the present disclosure is not limited to the above purpose, and according to the following description, other purposes of the present disclosure will be obvious to those skilled in the art.

[0011] The level shifter according to an embodiment of the present disclosure is set forth in the appended claims.

[0012] The display device according to an embodiment of the present disclosure is set forth in the appended claims.

[0013] According to the present disclosure, a mode selection signal for selectively driving two light-emitting elements can be output by using a level shifter, and the output mode selection signal can be applied to a pixel circuit through a mode line, so as to apply the mode selection signal with a simple structure.

[0014] The effects of this specification are not limited to the above effects, and those skilled in the art will clearly understand other effects not mentioned according to the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] By referring to the accompanying drawings and describing in detail the exemplary embodiments of the present disclosure, the above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art, wherein:

[0016] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure;

[0017] Figure 2 is a circuit diagram showing a pixel circuit according to an embodiment of the present disclosure;

[0018] Figure 3 is shown as being provided on Figure 2 the first and second light-emitting elements shown;

[0019] Figure 4 is shown as Figure 2 a diagram showing the driving waveforms of each mode of the pixel circuit shown;

[0020] Figures 5A to 5C is shown as being based on Figure 4 the driving waveform of the operation principle of the pixel circuit;

[0021] Figure 6 is a diagram showing the switching process between the first mode and the second mode;

[0022] Figure 7 is a diagram showing the transmission path of the mode selection signal according to the first embodiment;

[0023] Figure 8 is a diagram showing a transmission path of a mode selection signal according to a second embodiment;

[0024] Figures 9A to 9C is a diagram showing an operating principle of a level shifter according to an embodiment; and

[0025] Figures 10 to 12 is a diagram showing an arrangement position of a level shifter according to an embodiment. DETAILED DESCRIPTION

[0026] Advantages and features of this specification and methods for achieving them will become apparent with reference to preferred embodiments described in detail in conjunction with the accompanying drawings. However, this specification is not limited to the embodiments to be described below and can be implemented in different forms. The embodiments are provided only to fully disclose the present disclosure and fully convey the scope of the present disclosure to those skilled in the art. This specification is defined by the disclosed claims.

[0027] Since shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings for describing embodiments of the present disclosure are merely exemplary, the present disclosure is not limited to the items shown. Throughout the specification, the same reference numerals denote the same components. In addition, when determining that a detailed description of related known technologies may unnecessarily obscure the gist of the present disclosure, its detailed description will be omitted.

[0028] When using "comprising", "having", "consisting of", etc. mentioned in this specification, other parts may be added unless "only" is used. Unless otherwise clearly stated, the case of denoting a component in the singular form includes the plural form.

[0029] When interpreting a component, it should be understood that an error range is included even if there is no separate explicit description.

[0030] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described as "on", "in the upper part", "in the lower part", "adjacent", etc., unless "immediately" or "directly" is used, one or more other parts may be located between the two parts.

[0031] Although various components are described using first, second, etc., these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present disclosure.

[0032] Throughout the present disclosure, the same reference numerals may refer to substantially the same elements.

[0033] The following embodiments can be partially or fully combined or combined with each other, and can be connected and operated in various technical ways. The embodiments can be executed independently or in association with each other.

[0034] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] In the display device of the present disclosure, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistors can be implemented as oxide thin film transistors (oxide TFTs) including oxide semiconductors, low temperature polysilicon (LTPS) TFTs including low temperature polysilicon, and the like.

[0036] A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In a transistor, carriers start to flow from the source. The drain is an electrode through which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, so that electrons can flow from the source to the drain. The n-channel transistor has a current direction from the drain to the source. In the case of a p-channel transistor (p-channel metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change according to the applied voltage. Therefore, the present disclosure is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor are referred to as the first electrode and the second electrode.

[0037] The gate signal swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0038] The transistor conducts in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage can be a gate-high voltage, and the gate-off voltage can be a gate-low voltage. In the case of a p-channel transistor, the gate-on voltage can be a gate-low voltage, and the gate-off voltage can be a gate-high voltage.

[0039] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure.

[0040] Reference Figure 1, a display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driving circuit for writing pixel data into pixels of the display panel 100, and a power supply 150 for generating power required to drive the pixels and the display panel driving circuit.

[0041] The display panel 100 includes a pixel array AA for displaying an input image. The pixel array AA includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix form.

[0042] The pixel array AA includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of pixels arranged along the row direction X in the pixel array AA of the display panel 100. The pixels arranged in one pixel row share the gate line 103. Sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period 1H is a time obtained by dividing one frame period by the total number of the pixel rows L1 to Ln.

[0043] A touch sensor may be disposed on the display panel 100. Touch input may be sensed using a separate touch sensor, or may be sensed through pixels. The touch sensor may be set as an on-cell type or an add-on type on the screen of the display panel or implemented as an in-cell type touch sensor embedded in the pixel array AA.

[0044] The display panel 100 may be implemented as a flexible or curved display panel. The flexible or curved display panel may be made of a plastic OLED panel. An organic film may be disposed on the backplane of the plastic OLED panel, and the pixel array AA may be formed on the organic film.

[0045] The backplane of the plastic OLED may be a polyethylene terephthalate (PET) substrate. The organic film is formed on the backplane. The pixel array AA and the touch sensor array may be formed on the organic film. The backplane blocks moisture penetration so that the pixel array AA is not exposed to moisture. The organic film may be a thin polyimide (PI) film substrate. A multi-layer buffer film may be formed of an insulating material (not shown) on the organic film. Lines may be formed on the organic film to provide power or signals applied to the pixel array AA and the touch sensor array.

[0046] To achieve colors, each pixel may be divided into a red sub-pixel (hereinafter referred to as "R sub-pixel"), a green sub-pixel (hereinafter referred to as "G sub-pixel"), and a blue sub-pixel (hereinafter referred to as "B sub-pixel"). Each pixel may also include a white sub-pixel. Each sub-pixel 101 includes a pixel circuit. The pixel circuit is connected to the data line 102 and the gate line 103.

[0047] The power supply 150 generates the DC power required to drive the pixel array AA of the display panel 100 and the display panel driving circuit by using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 150 may adjust the DC input voltage from a host system (not shown) to generate a constant voltage, such as a gamma reference voltage VGMA, a gate-on voltage VGH and VEH, a gate-off voltage VGL and VEL, a pixel driving voltage EVDD, a pixel low-potential power supply voltage EVSS, an initialization voltage VINIT, and a reference voltage VREF. The gamma reference voltage VGMA is supplied to the data driver 110. The gate-on voltage VGH and VEH and the gate-off voltage VGL and VEL are supplied to the gate driver 120. Constant voltages such as the pixel driving voltage EVDD, the pixel low-potential power supply voltage EVSS, the initialization voltage VINIT, and the reference voltage VREF may be supplied to the pixel 101 through a power line commonly connected to the pixel 101.

[0048] The display panel driving circuit writes the pixel data of the input image to the pixels of the display panel 100 under the control of the timing controller (TCON) 130.

[0049] The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0050] A demultiplexer (DEMUX) array may be provided between the data driver 110 and the data lines 102. The demultiplexer array sequentially connects one channel of the data driver 110 to a plurality of data lines 102 and distributes the data voltage output from one channel of the data driver 110 to the data lines 102 in a time-division manner, thereby reducing the number of channels of the data driver 110. The demultiplexer array may be omitted. In this case, the output buffer AMP of the data driver 110 is directly connected to the data lines 102.

[0051] The display panel driving circuit may further include a touch sensor driver for driving a touch sensor. Figure 1 The touch sensor driver is omitted. In a mobile device, the timing controller 130, the power supply 150, the data driver 110, etc. may be integrated into one driving integrated circuit (IC).

[0052] The data driver 110 generates a data voltage Vdata by converting pixel data of an input image received from the timing controller 130 with a gamma compensation voltage every frame period using a digital-to-analog converter (DAC). The gamma reference voltage VGMA is divided for each gray level by a voltage divider circuit. The gamma compensation voltage divided from the gamma reference voltage VGMA is provided to the DAC of the data driver 110. The data voltage Vdata is output through an output buffer AMP in each channel of the data driver 110.

[0053] In the data driver 110, the output buffer included in one channel may be connected to an adjacent data line 102 through a demultiplexer array (not shown). The demultiplexer array may be directly formed on the substrate of the display panel 100, or integrated with the data driver 110 into one driving IC.

[0054] The gate driver 120 may be implemented as a gate-in-panel (GIP) circuit directly formed on the border area of the display panel 100 together with the TFT array of the pixel array AA. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 may sequentially provide the gate signals to the gate lines 103 by shifting the gate signals using a shift register.

[0055] The timing controller 130 receives digital video data DATA of an input image and a timing signal synchronized with the digital video data from a host system. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal CLK, a data enable signal DE, etc. Since the vertical period and the horizontal period can be obtained by a method of counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The data enable signal DE has a period of one horizontal period 1H.

[0056] The timing controller 130 may control the display panel driving circuit by generating a data timing control signal for controlling the operation timing of the data driver 110 and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, DE received from the host system 200. The timing controller 130 may synchronize the data driver 110 and the gate driver 120 by controlling the operation timing of the display panel driving circuit.

[0057] The gate timing control signal output from the timing controller 130 may be input to the shift register of the gate driver 120 through the level shifter 140. The mode selection signal output from the timing controller 130 may be input to the mode selection circuit through the level shifter 140. Here, the mode selection signal may include a first mode selection signal S_sel for the first mode and a second mode selection signal P_sel for the second mode.

[0058] The level shifter 140 may convert the voltage of the signal received from the timing controller 130 into a swing width between the gate high voltage and the gate low voltage and output it. The level shifter 140 may decode the gate timing signal to output a start pulse and a clock signal for driving the gate driver 120, and may decode the mode selection signal to output the mode selection signal. Each of the start pulse, the clock signal, and the mode selection signal may be an AC signal that swings between the gate high voltage and the gate low voltage.

[0059] The host system 200 may include a main board of one of a television system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a vehicle system, and a mobile device system. In this case, the data driver 110, the gate driver 120, the timing controller 130, etc. may be integrated into one driving IC (DIC) in a mobile device or a wearable device.

[0060] Figure 2 is a circuit diagram showing a pixel circuit according to an embodiment of the present disclosure. Figure 3 is shown in Figure 2 a diagram showing lenses disposed on the first and second light-emitting elements shown.

[0061] Reference Figure 2 and Figure 3 , the pixel circuit includes a first light-emitting element EL1 configured to emit light in a first mode SMODE, a second light-emitting element EL2 configured to emit light in a second mode PMODE, a driving element DT configured to drive the first light-emitting element EL1 and the second light-emitting element EL2, a plurality of switching elements T1 to T6, a first mode switching element T7, a second mode switching element T8, and a capacitor Cst. The driving element DT, the switching elements T1 to T6, and the first mode switching element T7 and the second mode switching element T8 may be implemented as p-channel transistors, but the present disclosure is not limited thereto.

[0062] The pixel circuit is connected to power supply lines to which a DC voltage (or a constant voltage) is applied, such as a pixel driving voltage line to which a pixel driving voltage VDD is applied, or a first power supply line PL1, a pixel reference voltage line to which a pixel reference voltage VSS is applied, or a second power supply line PL2, and a reference voltage line to which a reference voltage Vref is applied, or a third power supply line PL3. The power supply lines may be commonly connected to all the pixels on the display panel 100.

[0063] The pixel driving voltage VDD is set to a voltage higher than the maximum voltage of the data voltage Vdata, and the driving element DT is allowed to operate in the saturation region. The pixel driving voltage VDD is a voltage higher than the pixel reference voltage VSS. The reference voltage Vref may be set to a voltage lower than the pixel driving voltage VDD and higher than the pixel reference voltage VSS. The gate-on voltage VGL may be set to a voltage higher than the pixel driving voltage VDD, and the gate-off voltage VGH may be set to a voltage lower than the pixel reference voltage VSS.

[0064] The driving element DT drives the first light-emitting element EL1 and the second light-emitting element EL2 by generating a current according to the gate-source voltage Vgs. The driving element DT includes a first electrode connected to the first power supply line PL1 to which the pixel driving voltage VDD is applied, a gate electrode connected to the second node n2, and a second electrode connected to the third node n3.

[0065] The first light-emitting element EL1 and the second light-emitting element EL2 may be implemented as organic light-emitting diodes (OLEDs). Each of the light-emitting elements EL1 and EL2 includes an anode, a cathode, and an organic compound layer formed between the anode and the cathode. The anode of the first light-emitting element EL1 is connected to the fifth node n5, and its cathode is connected to the second power supply line PL2 to which the pixel reference voltage VSS is applied. The anode of the second light-emitting element EL2 is connected to the sixth node n6, and its cathode is connected to the second power supply line PL2. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, and an electron injection layer EIL, but the present disclosure is not limited thereto. Each of the light-emitting elements EL1 and EL2 may be implemented in a series structure in which a plurality of light-emitting layers are stacked. The light-emitting elements EL1 and EL2 in the series structure may improve the brightness and lifetime of the pixels.

[0066] The first switching element T1 is connected between the data line DL and the first node n1. The first switching element T1 is turned on according to the gate-on voltage VGL of the first gate signal SCAN1 to apply the data voltage Vdata of the pixel data to the first node n1. The first switching element T1 includes a first electrode connected to the data line DL, a gate electrode to which the first gate signal SCAN1 is applied, and a second electrode connected to the first node n1.

[0067] The second switching element T2 is connected between the second node n2 and the third node n3. The second switching element T2 is turned on according to the gate conduction voltage VGL of the second gate signal SCAN2 to connect the gate electrode and the second electrode of the driving element DT. The second switching element T2 includes a first electrode connected to the second node n2, a gate electrode to which the second gate signal SCAN2 is applied, and a second electrode connected to the third node n3.

[0068] The fifth switching element T5 is connected between the first node n1 and the third power supply line PL3. The fifth switching element T5 is turned on according to the gate conduction voltage VGL of the third gate signal EM to connect the first node n1 to the third power supply line PL3. The fifth switching element T5 includes a first electrode connected to the first node n1, a gate electrode to which the third gate signal EM is applied, and a second electrode connected to the third power supply line PL3.

[0069] The sixth switching element T6 is connected between the third node n3 and the fourth node n4. The sixth switching element T6 is turned on according to the gate conduction voltage VGL of the third gate signal EM to connect the third node n3 to the fourth node n4. The sixth switching element T6 includes a first electrode connected to the third node n3, a gate electrode to which the third gate signal EM is applied, and a second electrode connected to the fourth node n4.

[0070] The third switching element T3 is connected between the fifth node n5 and the third power supply line PL3. The third switching element T3 is turned on according to the gate conduction voltage VGL of the second gate signal SCAN2 to connect the fifth node n5 to the third power supply line PL3. The third switching element T3 includes a first electrode connected to the third power supply line PL3, a gate electrode to which the second gate signal SCAN2 is applied, and a second electrode connected to the fifth node n5.

[0071] The fourth switching element T4 is connected between the sixth node n6 and the third power supply line PL3. The fourth switching element T4 is turned on according to the gate conduction voltage VGL of the second gate signal SCAN2 to connect the sixth node n6 to the third power supply line PL3 to which the reference voltage Vref is applied. The fourth switching element T4 includes a first electrode connected to the third power supply line PL3, a gate electrode to which the second gate signal SCAN2 is applied, and a second electrode connected to the sixth node n6.

[0072] The first mode switching element T7 is connected between the fourth node n4 and the fifth node n5. The first mode switching element T7 is turned on according to the gate conduction voltage VGL of the first mode selection signal S_sel to connect the fourth node n4 to the fifth node n5. The first mode switching element T7 includes a first electrode connected to the fourth node n4, a gate electrode to which the first mode selection signal S_sel is applied, and a second electrode connected to the fifth node n5.

[0073] The second mode switching element T8 is connected between the fourth node n4 and the sixth node n6. The second mode switching element T8 is turned on according to the gate conduction voltage VGL of the second mode selection signal P_sel to connect the fourth node n4 to the sixth node n6. The second mode switching element T8 includes a first electrode connected to the fourth node n4, a gate electrode to which the second mode selection signal P_sel is applied, and a second electrode connected to the sixth node n6.

[0074] The capacitor Cst is connected between the first node n1 and the second node n2. The capacitor Cst holds the gate-source voltage Vgs of the driving element DT during light emission.

[0075] Reference Figure 3 , Figure 3 The first lens LENS1 shown can be disposed on the first light-emitting element EL1. The first lens LENS1 can be a semi-cylindrical lens so as to limit the vertical viewing angle and widen the horizontal viewing angle. The first lens LENS1 is long in the horizontal direction (or X-axis direction) of the display panel 100 and narrow in its vertical direction. The first lens LENS1 can have a hemispherical cross-section. The first lens converges the light traveling in the vertical direction among the light emitted by the first light-emitting element EL1 in the first mode, so as to narrow the vertical viewing angle and widen the horizontal viewing angle. Through the first lens LENS1, the vertical viewing angle of the first light-emitting element EL1 is comparable to the vertical viewing angle of the second light-emitting element EL2, and the horizontal viewing angle of the first light-emitting element EL1 is greater than the horizontal viewing angle of the second light-emitting element EL2. In Figure 3 ,“R” indicates the red sub-pixel that emits light, “G” indicates the green sub-pixel that emits light, and “B” indicates the blue sub-pixel that emits light. In Figure 3 The sub-pixels represented by dark black are non-driven sub-pixels that do not emit light.

[0076] The light emitted from the screen of the vehicle display disposed on the dashboard of the vehicle can travel to the forward camera in front of the upper end of the space in the vehicle, and the screen of the vehicle display can be seen in the image captured by the forward camera. The first lens LENS1 limits the vertical viewing angle of the first light-emitting element EL1 that emits light in the first mode to prevent a ghost image of the screen of the vehicle display captured by the forward camera.

[0077] Figure 3 The second lens LENS2 shown can be disposed on the second light-emitting element EL2. The second lens LENS2 can be a hemispherical lens having a greater thickness at the center and a smaller thickness toward its edge. The second lens LENS2 can converge the light of the second light-emitting element EL2 emitted in the second mode, thereby narrowing the vertical viewing angle and the horizontal viewing angle of the second light-emitting element EL2.

[0078] The first lens and the second lens LENS1 and LENS2 can be implemented as a transparent medium or a transparent insulating layer pattern disposed in the display panel 100, but the present disclosure is not limited thereto.

[0079] The first light-emitting element EL1 emits light at a first viewing angle through the first lens LENS1, and the second light-emitting element EL2 emits light at a second viewing angle smaller than the first viewing angle through the second lens LENS2.

[0080] The pixel circuit can be driven in a first mode (e.g., a first display viewing angle mode) in which the first light-emitting device EL1 emits light at a narrow viewing angle or a second mode (e.g., a second display viewing angle mode) in which the second light-emitting device EL2 emits light at a wide viewing angle.

[0081] Figure 4 is a diagram showing Figure 2 the driving waveforms of each mode of the pixel circuit shown. Figures 5A to 5C is a diagram showing Figure 4 the operating principle of the pixel circuit based on the driving waveform. Figure 6 is a diagram showing the switching process between the first mode and the second mode.

[0082] Referring to Figure 4 , in the first mode and the second mode, the pixel circuit is driven in the order of an initialization period Tini, a data writing and sensing period Tw / s, and an emission period Tem. The time for executing the initialization period Tini, the data writing and sensing period Tw / s, and the emission period Tem can be controlled by the waveforms of the gate signals SCAN1, SCAN2, and EM.

[0083] Referring to Figure 5A , during the initialization period Tini, the first switching element T1 is turned off, and the second switching element T2 to the sixth switching element T6 are turned on, so that the reference voltage Vref can be applied to the first node n1.

[0084] In this case, when the first mode switching element T7 is turned on in the first mode, the reference voltage Vref is applied to the second node n2 through the first mode switching element T7, and when the second mode switching element T8 is turned on in the second mode, the reference voltage Vref is applied to the second node n2 through the second mode switching element T8.

[0085] Reference Figure 5B During the data write and sense period Tw / s, the third switching element T3 and the fourth switching element T4, as well as the first switching element T1 and the second switching element T2, are turned on, and the fifth switching element T5 and the sixth switching element T6 are turned off, so that the data voltage Vdata of the pixel data is applied to the first node n1, and the pixel driving voltage VDD is applied to the driving element to sense the threshold voltage Vth of the driving element, resulting in the voltage at the second node n2 being VDD + Vth.

[0086] Reference Figure 5C During the emission period Tem, the first switching element T1 and the second switching element T2, as well as the third switching element T3 and the fourth switching element T4, are turned off, and the fifth switching element T5 and the sixth switching element T6 are turned on, so that the current generated based on the gate-source voltage of the driving element DT is supplied to the first light-emitting element EL1 or the second light-emitting element EL2 to make them emit light.

[0087] In this case, when the first mode switching element T7 is turned on in the first mode, the current generated based on the gate-source voltage of the driving element DT is supplied to the first light-emitting element EL1 through the first mode switching element T7, and when the second mode switching element T8 is turned on in the second mode, the current generated based on the gate-source voltage of the driving element DT is supplied to the second light-emitting element EL2 through the second mode switching element T8.

[0088] In the pixel circuit according to the embodiment, the mode selection signals can be applied in a non-overlapping manner, so that when switching from the first mode to the second mode or from the second mode to the first mode, both the first light-emitting element and the second light-emitting element experience an off state in a very short time, as Figure 6 shown.

[0089] For example, it can be designed to have a predetermined time interval between the rising time point of the first mode selection signal S_sel and the falling time point of the second mode selection signal P_sel.

[0090] Since the first mode selection signal S_sel and the second mode selection signal P_sel are generated by the timing controller rather than the gate signal, they are applied to the pixel circuit through the level shifter.

[0091] Figure 7 is a diagram showing the transmission path of the mode selection signal according to the first embodiment. Figure 8 is a diagram showing the transmission path of the mode selection signal according to the second embodiment.

[0092] Reference Figure 7, the display panel 100 according to the first embodiment may further include a plurality of horizontal mode lines 105 for transmitting mode selection signals S_sel and P_sel. The horizontal mode lines 105 are arranged parallel to the gate lines and connected to the pixel circuits of each pixel.

[0093] The horizontal mode lines 105 may be arranged side by side in the non-display areas on the left and right sides of the display panel, and may be arranged parallel to the gate lines in the display area.

[0094] In this case, since the horizontal mode lines 105 are set to bypass the non-display area where the gate driver circuit is provided, some of the horizontal mode lines 105 may overlap with the gate driver circuit with an insulating layer therebetween.

[0095] Reference Figure 8 , the display panel 100 according to the second embodiment may further include a plurality of vertical mode lines 104 for transmitting mode selection signals S_sel and P_sel. The vertical mode lines 104 are arranged parallel to the data lines and connected to the pixel circuits of each pixel.

[0096] The display device may include a circuit board PCB and a chip on film (COF) electrically connected to the display panel 100. A source driver IC (DIC) integrated with the circuit of the data driver 110 may be mounted on the flexible film of the COF. The circuit board PCB includes a timing controller 130, a level shifter 140, a power supply 150, etc. The circuit board PCB may be electrically connected to the COF.

[0097] The COF may be disposed between the circuit board PCB and the display panel 100 to electrically connect the circuit board PCB to the display panel 100, and may supply the data voltage output from the source driver IC (DIC) to the data lines on the display panel 100.

[0098] The gate timing control signal and the mode selection signal output from the timing controller 130 may be provided to the level shifter 140. The level shifter 140 receives the signal from the timing controller 130, the gate high voltage VGH, and the gate low voltage VGL. The level shifter 140 decodes the gate timing control signal to output a start pulse and a clock signal that swings between the gate high voltage VGH and the gate low voltage VGL. The start pulse and the clock signal are provided to the gate driver 120. When the start pulse and the clock signal are input, the gate driver 120 may output pulses of the gate signal.

[0099] The level shifter 140 decodes the mode selection signal to output the mode selection signals S_sel and P_sel that swing between the gate high voltage VGH and the gate low voltage VGL.

[0100] The mode selection signals S_sel and P_sel can be provided to the pixel circuit P of a pixel through corresponding vertical mode lines 104 and horizontal mode lines 105. Each pixel can be driven individually in a viewing angle mode indicated by the mode selection signals S_sel and P_sel.

[0101] Figures 9A to 9C It is a diagram showing the operating principle of a level shifter according to an embodiment.

[0102] Reference Figure 9A , the level shifter 140 can receive a mode selection signal of a first voltage level, a start signal VST0, and a clock signal CLK0 from the timing controller 130. For example, the start signal and the clock signal can include a start signal SCAN1_VST0 and SCAN2_VST0 for a scan driver, clock signals SCAN1_CLK0 and SCAN2_CLK0, and a start signal EM_VST0 and a clock signal EM_CLK0 for an EM driver. The mode selection signal can include a first mode selection signal S_sel0 and a second mode selection signal P_sel0.

[0103] The level shifter 140 can include a logic circuit 141 for converting a voltage level. The logic circuit can be implemented as a plurality of logic circuits that convert the voltage levels of signals SCAN1_VST0, SCAN1_CLK0, SCAN2_VST0, SCAN2_CLK0, EM_VST0, EM_CLK0, S_sel0, and P_sel0.

[0104] In one example, the logic circuit 141 can convert the start signals SCAN1_VST0, SCAN2_VST0, and EM_VST0 of a first voltage level and the clock signals SCAN1_CLK0, SCAN2_CLK0, and EM_CLK0 into a start signal VST and a clock signal CLK of a second voltage level, and apply them to the gate driver. The gate driver can generate gate signals SCAN1, SCAN2, and EM based on the start signal VST and the clock signal CLK, and apply them to the pixel circuit through gate lines.

[0105] In another example, the logic circuit 141 can receive the first mode selection signal S_sel0 and the second mode selection signal P_sel0 of a first voltage level VCC, and output the first mode selection signal S_sel and the second mode selection signal P_sel of a second voltage level.

[0106] The first mode selection signal S_sel and the second mode selection signal P_sel output from the logic circuit 141 can be applied to the pixel circuit through the vertical mode line 104 or the horizontal mode line 105.

[0107] Reference Figure 9B and Figure 9C According to an embodiment, the logic circuit 141 may include a first logic circuit 141a and a second logic circuit 141b. The first logic circuit 141a may receive the first mode selection signal S_sel0 and the second mode selection signal P_sel0 of a first voltage level from the timing controller and transmit them to the second logic circuit 141b. For example, the first logic circuit 141a may be implemented as a buffer BUF, but the present invention is not limited thereto.

[0108] The second logic circuit 141b may convert the first mode selection signal S_sel0 and the second mode selection signal P_sel0 of the first voltage level into the first mode selection signal S_sel and the second mode selection signal P_sel of a second voltage level that swings between the gate high voltage VGH and the gate low voltage VGL and output them. For example, the second logic circuit 141b may be implemented as a pull-up transistor Tu and a pull-down transistor Td, but the present disclosure is not limited thereto. The pull-up transistor Tu may convert the high voltage level of the first mode selection signal S_sel0 and the second mode selection signal P_sel0 into the gate high voltage VGH of the first mode selection signal S_sel and the second mode selection signal P_sel, and the pull-down transistor Td may convert the low voltage level of the first mode selection signal S_sel0 and the second mode selection signal P_sel0 into the gate low voltage VGL of the first mode selection signal S_sel and the second mode selection signal P_sel.

[0109] Figures 10 to 12 is a diagram showing the arrangement position of the level shifter according to an embodiment.

[0110] Reference Figures 10 to 12 According to an embodiment, the level shifter may be provided in the control PCB (CPCB), the source PCB (SPCB), or the DIC. The level shifter is preferably provided in the CPCB because it has the same number of input and output signals and only changes the voltage level of the signal.

[0111] As Figure 10 shown, the level shifter may be provided in the CPCB. The logic circuit of the level shifter may convert the voltage level of the mode selection signal and output it. The mode selection signal output from the logic circuit passes through the flexible printed circuit (FPC), the SPCB, and the chip on film (COF), and then is provided to the pixel circuit through the non-display area in the display panel.

[0112] Accordingly, a mode line including a horizontal and a vertical mode line is connected to a level shifter 140 provided in the CPCB, passes through the FPC, the SPCB, and the COF, and also passes through a non-display area in the display panel and is connected to the pixel circuit.

[0113] As Figure 11 shown, the level shifter may be provided in the SPCB. A mode selection signal output from the logic circuit passes through the COF and then is provided to the pixel circuit through a non-display area in the display panel.

[0114] Accordingly, a mode line including a horizontal and a vertical mode line is connected to a level shifter 140 provided in the SPCB, passes through the COF, and also passes through a non-display area in the display panel and is connected to the pixel circuit.

[0115] As Figure 12 shown, the level shifter may be provided in the DIC. A mode selection signal output from the logic circuit passes through the COF and then is provided to the pixel circuit through a non-display area in the display panel.

[0116] Accordingly, a mode line including a horizontal and a vertical mode line is connected to a level shifter 140 provided in the DIC and also passes through a non-display area in the display panel and is connected to the pixel circuit.

[0117] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Accordingly, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure.

[0118] In addition, the present disclosure includes configurations according to the following clauses.

[0119] Clause 1, a level shifter, comprising: a first logic circuit configured to receive a mode selection signal of a first voltage level for selectively driving a first light-emitting element and a second light-emitting element that emit light from different viewing angles of a pixel circuit from a timing controller and transmit the mode selection signal; and a second logic circuit configured to convert the mode selection signal of the first voltage level into a mode selection signal of a second voltage level higher than the first voltage level and output the converted mode selection signal of the second voltage level to the pixel circuit.

[0120] Clause 2. The level shifter according to Clause 1, wherein the second logic circuit converts the mode selection signal of the first voltage level into the mode selection signal of the second voltage level capable of switching between a gate high voltage and a gate low voltage.

[0121] Clause 3. The level shifter according to Clause 2, wherein the second logic circuit receives the gate high voltage and the gate low voltage from a power supply.

[0122] Clause 4. A display device, comprising: a display panel in which a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixel circuits are provided, each pixel circuit including a first light-emitting element and a second light-emitting element that emit light at different viewing angles; a data driver configured to provide a data voltage of pixel data to the data lines; a level shifter configured to output a gate timing control signal and a mode selection signal; and a gate driver configured to generate a gate signal based on the gate timing control signal and provide the generated gate signal to the gate lines, wherein the level shifter includes: a first logic circuit configured to receive a mode selection signal of a first voltage level for selectively driving the first light-emitting element and the second light-emitting element of the pixel circuit from a timing controller and transmit the mode selection signal; and a second logic circuit configured to convert the mode selection signal of the first voltage level into the mode selection signal of a second voltage level higher than the first voltage level and output the converted mode selection signal of the second voltage level to the pixel circuit.

[0123] Clause 5. The display device according to Clause 4, wherein the level shifter and the pixel circuit are electrically connected through a mode line, and the mode selection signal of the second voltage level output from the level shifter is applied to the pixel circuit through the mode line.

[0124] Clause 6. The display device according to Clause 5, wherein the level shifter is provided in a control printed circuit board (CPCB), and the mode line passes through a flexible printed circuit (FPC), a source printed circuit board (SPCB), and a chip on film (COF), and then passes through a non-display area of the display panel to be connected to the pixel circuit.

[0125] Clause 7. The display device according to Clause 6, wherein the mode lines are arranged side by side in the non-display area of the display panel and are arranged in parallel with the gate lines in the display area of the display panel.

[0126] Clause 8. The display device according to Clause 6, wherein the mode lines are arranged side by side in the non-display area of the display panel and are arranged in parallel with the data lines in the display area of the display panel.

[0127] Clause 9. The display device according to Clause 4, wherein the second logic circuit converts the mode selection signal of the first voltage level into the mode selection signal of the second voltage level that can be switched between the gate high voltage and the gate low voltage.

[0128] Clause 10. The display device according to Clause 9, wherein the second logic circuit receives the gate high voltage and the gate low voltage from a power supply.

[0129] Clause 11. The display device according to Clause 4, wherein the level shifter is provided in any one of a control PCB (CPCB), a source PCB (SPCB), and a driver IC (DIC).

Claims

1. A level shifter for a display panel driving circuit, the level shifter comprising a logic circuit, the logic circuit being configured to receive a mode selection signal, convert the mode selection signal into a mode selection gate signal, and output the mode selection gate signal, wherein: The mode selection signal has a first voltage, and the mode selection gate signal has a second voltage different from the first voltage.

2. The level shifter according to claim 1, wherein: Based on the mode selection signal, the second voltage is one of a gate-on voltage or a gate-off voltage.

3. The level shifter according to claim 1 or 2, wherein: The logic circuit comprises a first logic circuit and a second logic circuit, wherein: The first logic circuit receives the mode selection signal and transmits the mode selection signal to the second logic circuit, and The second logic circuit converts the mode selection signal into the mode selection gate signal and outputs the mode selection gate signal.

4. The level shifter according to claim 3, wherein: The second logic circuit receives a gate high voltage and a gate low voltage from a power supply.

5. A level shifter according to any one of the preceding claims, wherein: The mode selection signal includes a first mode selection signal for controlling a first display viewing angle mode and a second mode selection signal for controlling a second display viewing angle mode.

6. The level shifter according to claim 5, wherein: The mode selection gate signal includes a first mode selection gate signal for controlling a first mode switch element in the pixel circuit and a second mode selection gate signal for controlling a second mode switch element in the pixel circuit.

7. The level shifter according to claim 6, wherein: The first mode selection gate signal and the second mode selection gate signal are mutually exclusive in a switch on state.

8. A level shifter according to any one of the preceding claims, wherein: The level shifter is also configured to receive a gate timing control signal, decode the gate timing control signal, and output a start pulse and a clock signal.

9. A display device, comprising: A display panel having a plurality of pixels in a display area; as well as A display panel driving circuit for controlling the plurality of pixels, the display panel driving circuit comprising: A level shifter according to any one of claims 1 to 8; and A pixel circuit for each pixel of the display panel, wherein each pixel circuit includes a light-emitting element connected to a mode switch element, the mode switch element being arranged to receive a mode selection gate signal from the level shifter, wherein the mode switch element is configured to open or close based on a voltage level of the received mode selection gate signal.

10. The display device according to claim 9, wherein: The pixel circuit comprises: a first light emitting element connected to the first mode switching element, and a second light emitting element connected to the second mode switching element; wherein each of the first mode switch element and the second mode switch element is arranged to receive a corresponding mode selection gate signal from the level shifter, and The first light emitting element has a first viewing angle, and the second light emitting element has a second viewing angle, and the second viewing angle is smaller than the first viewing angle.

11. The display device according to claim 9 or 10, wherein: The level shifter and the pixel circuit are electrically connected through a mode line, and The mode selection gate signal output from the level shifter is applied to the pixel circuit through the mode line.

12. The display device according to claim 11, wherein: The level shifter is provided in a control PCB (CPCB), and The mode line passes through a flexible printed circuit (FPC), a source PCB (SPCB), and a chip on film (COF), and is then connected to the pixel circuit through a non-display area of ​​the display panel.

13. The display device according to claim 12, wherein: The mode lines are arranged side by side in a non-display area of ​​the display panel.

14. The display device according to claim 13, wherein: The mode lines are arranged as: parallel to the gate lines in the display area of ​​the display panel, or The display panel is parallel to the data lines in the display area.

15. The display device according to any one of claims 9 to 14, wherein: The level shifter is provided in any one of a control PCB (CPCB), a source PCB (SPCB), and a chip on film (COF).

16. The display device according to any one of claims 9 to 15, wherein: The display panel driving circuit further comprises a gate control circuit arranged to receive a start pulse and a clock signal from the level shifter.

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