Pixel circuit and display device including same

Abstract

A pixel circuit according to an embodiment and a display device including the same are disclosed. The pixel circuit includes: a first light emitting element; a second light emitting element; a driving element transistor configured to drive the first and second light emitting elements; a compensation voltage line for applying a compensation voltage; a first switching element including a first electrode and connected between the driving element transistor and the first light emitting element, and driven by a first mode selection signal; a second switching element including a first electrode and connected between the driving element transistor and the second light emitting element, and driven by a second mode selection signal; and a third switching element configured to apply a predetermined compensation voltage to at least one of the anode electrodes of the first and second light emitting elements, in which a first electrode of the third switching element is connected to a first electrode of the first switching element and a first electrode of the second switching element, and a second electrode of the third switching element is connected to a second electrode of the second switching element. And a second electrode of the third switching element is connected to the compensation voltage line.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0193956, filed on December 28, 2023, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a pixel circuit and a display device including the pixel circuit. Background art

[0004] Variable viewing angle technology is being applied to display devices. The variable viewing angle technology can present video content or visual information reproduced on the display device only to users within a narrow viewing angle range, or to multiple users within a wide viewing angle range.

[0005] With the expansion of future vehicle markets such as electric vehicles and autonomous driving vehicles, the demand for in - vehicle display devices is increasing rapidly. Methods of dividing the screen of an in - vehicle display device and controlling a part of the screen to have a narrow viewing angle and another part to have a wide viewing angle are being studied. This technology can drive pixels with a narrow viewing angle arranged in one area of the screen to display personal content or information that can only be viewed by specific users, while driving pixels with a wide viewing angle arranged in another area of the screen to display shared content that can be viewed by multiple users together.

[0006] In in - vehicle display devices, display panels for organic light - emitting display devices are attracting attention. The organic light - emitting display device includes self - emitting organic light - emitting diodes (hereinafter referred to as "OLEDs"), and has the advantages of fast response speed, good luminous efficiency and brightness, and wide viewing angle. The organic light - emitting display device has a fast response speed, excellent luminous efficiency, brightness and viewing angle, and has excellent contrast and color reproducibility because it can represent black grayscale with all - black. Since the display panel of the organic light - emitting display device can be flexibly bent, a curved surface can be easily achieved. Due to these advantages, the market share of organic light - emitting display devices in the in - vehicle display device market is increasing rapidly. Summary of the invention

[0007] However, due to deviations in the panel manufacturing process, the capacitance of parasitic capacitors formed in the light - emitting elements varies at each planar position. This results in different charging times between the anode voltage of the first light - emitting element and the anode voltage of the second light - emitting element at low gray levels with a small current amount, thereby causing a deviation in brightness uniformity at low gray levels.

[0008] The present disclosure aims to solve all the above - mentioned necessities and problems.

[0009] The present disclosure provides a pixel circuit and a display device including the pixel circuit.

[0010] It should be noted that the objectives of the present disclosure are not limited to the above objectives, and those skilled in the art will clearly understand other objectives of the present disclosure from the following description.

[0011] The pixel circuit according to an embodiment of the present disclosure may include: a first light-emitting element; a second light-emitting element; a driving element transistor configured to drive the first and second light-emitting elements; a compensation voltage line for applying a compensation voltage; a first switching element including a first electrode and connected between the driving element transistor and the first light-emitting element, and driven by a first mode selection signal; a second switching element including a first electrode and connected between the driving element transistor and the second light-emitting element, and driven by a second mode selection signal; and a third switching element configured to apply a predetermined compensation voltage to at least one of the anode electrodes of the first light-emitting element and the second light-emitting element, wherein a first electrode of the third switching element is connected to the first electrode of the first switching element and the first electrode of the second switching element, and a second electrode of the third switching element is connected to the compensation voltage line.

[0012] The display device according to an embodiment of the present disclosure may include: the above pixel circuit; a data driver; a gate driver; and a power supply configured to provide a pixel base voltage and a compensation voltage.

[0013] According to the present disclosure, by initializing the anode electrode of the light-emitting element to a reference voltage and then applying a compensation voltage of a predetermined voltage level before the emission period, the initial voltage of the anode electrode can be increased, thereby compensating for the brightness deviation in the low gray-scale region with a small amount of current.

[0014] According to the present disclosure, low-power driving can be achieved by compensating for the brightness deviation in the low gray-scale region.

[0015] The effects of this specification are not limited to the above effects, and those skilled in the art will clearly understand other effects not mentioned based on the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] By describing the exemplary embodiments of the present disclosure in detail with reference to the drawings, the above and other objectives, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art. In the drawings:

[0017] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure;

[0018] Figure 2 is a circuit diagram showing a pixel circuit according to an embodiment of the present disclosure;

[0019] Figure 3 is a diagram showing lenses provided on the first and second light-emitting elements shown in Figure 2 ;

[0020] Figure 4 is a diagram showing waveforms of a pixel circuit shown in Figure 2 when driven in a first mode;

[0021] Figures 5A to 5F is a diagram showing operations of the pixel circuit in the first-mode driving;

[0022] Figure 6 is a diagram showing different waveforms of the pixel circuit shown in Figure 2 when driven in the first mode;

[0023] Figure 7A and Figure 7B is a diagram comparing the luminance deviation between a comparative example and an embodiment;

[0024] Figure 8 is a diagram showing waveforms of the pixel circuit shown in Figure 2 when driven in a second mode;

[0025] Figures 9A to 9F is a diagram showing operations of the pixel circuit in the second-mode driving;

[0026] Figure 10 is a diagram showing different waveforms of the pixel circuit shown in Figure 2 when driven in the second mode;

[0027] Figure 11 is a diagram showing waveforms of the pixel circuit shown in Figure 2 when simultaneously driven in the first and second modes; and

[0028] Figures 12A to 12E is a diagram showing operations of the pixel circuit driven by the waveform of Figure 11 . DETAILED DESCRIPTION

[0029] Advantages and features of this specification and methods for achieving them will become apparent with reference to the preferred embodiments described in detail below in conjunction with the accompanying drawings. However, this specification is not limited to the embodiments to be described below and can be implemented in different forms. The embodiments are provided only to completely disclose the present disclosure and fully convey the scope of the present disclosure to those skilled in the art, and this specification is defined by the disclosed claims.

[0030] Since the shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings used to describe the embodiments of the present disclosure are merely exemplary, the present disclosure is not limited to the items shown. Throughout the specification, the same reference numerals indicate the same components. In addition, when determining that a detailed description of related known technologies may unnecessarily obscure the gist of the present disclosure, the detailed description thereof will be omitted.

[0031] When using terms such as "comprising", "having", "consisting of", etc. mentioned in this specification, other parts can be added unless "only" is used. Unless otherwise clearly stated, the case of expressing components in the singular form includes the plural form.

[0032] When interpreting components, it should be understood that an error range is included even if there is no separate and explicit description.

[0033] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described as "on", "in the upper part", "in the lower part", "next to", etc., one or more other parts can be located between these two parts unless "immediately" or "directly" is used.

[0034] Although various components are described using the first, second, etc., these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below can also be the second component within the technical spirit of the present disclosure.

[0035] The same reference numerals can refer to substantially the same elements throughout the present disclosure.

[0036] The following embodiments can be partially or wholly combined or combined with each other, and can be linked and operated in various ways technically. The embodiments can be executed independently or in relation to each other.

[0037] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the drawings.

[0038] In the display device of the present disclosure, the pixel circuit and the gate driving circuit can include a plurality of transistors. The transistors can be implemented as oxide thin film transistors (oxide TFTs) including oxide semiconductors, low temperature polysilicon (LTPS) TFTs including low temperature polysilicon, etc.

[0039] A transistor is a three - electrode device including a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. In a transistor, carriers start to flow from the source. The drain is the electrode from which carriers flow out of the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n - channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, enabling electrons to flow from the source to the drain. An n - channel transistor has a current direction from the drain to the source. In the case of a p - channel transistor (p - channel metal - oxide - semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, enabling holes to flow from the source to the drain. In a p - channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change according to the applied voltage. Therefore, the present disclosure is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0040] The gate signal swings between a gate - on voltage and a gate - off voltage. The gate - on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate - off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0041] The transistor conducts in response to the gate - on voltage and turns off in response to the gate - off voltage. In the case of an n - channel transistor, the gate - on voltage can be a gate - high voltage, and the gate - off voltage can be a gate - low voltage. In the case of a p - channel transistor, the gate - on voltage can be a gate - low voltage, and the gate - off voltage can be a gate - high voltage.

[0042] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure.

[0043] Refer to Figure 1 , a display device according to an embodiment of the present disclosure includes a display panel 100, and a display - panel driving circuit for writing pixel data to the pixels of the display panel 100. In addition, the display device includes a power supply 150.

[0044] The display panel 100 can be, but is not limited to, a panel having a rectangular structure, having a length in the X - axis direction, a width in the Y - axis direction, and a thickness in the Z - axis direction. For example, the display panel 100 can be a heterogeneous panel with at least a part being curved or elliptical.

[0045] The display area AA of the display panel 100 includes a pixel array to display an input image. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix form. The display panel 100 may also include a power supply line commonly connected to the pixels. The power supply line may be commonly connected to the pixel circuit to supply the voltage required to drive the pixel 101 to the pixel 101.

[0046] Each pixel 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to achieve color. Each pixel may also include a white sub-pixel. Each sub-pixel includes a pixel circuit for driving a light-emitting element. The light-emitting element may include an OLED or an inorganic light-emitting diode (LED). Each pixel circuit is connected to a data line, a gate line, and a power supply line. In the following description, a pixel may be interpreted as a sub-pixel.

[0047] Pixels may be arranged as true-color pixels and pentile pixels. Pentile pixels can achieve a higher resolution than true-color pixels by driving two different-color sub-pixels as one pixel 101 and using a preset pixel rendering algorithm. The pixel rendering algorithm can compensate for the insufficient color performance in each pixel with the color of the light emitted from adjacent pixels.

[0048] Each pixel may include at least one first light-emitting element that emits light in a first mode, and a second light-emitting element that emits light in a second mode. Each pixel 101 emits light from the first light-emitting element with a wide viewing angle in the first mode, and emits light from the second light-emitting element with a narrow viewing angle in the second mode.

[0049] The display area AA includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes a line of pixels arranged along the line direction (X-axis direction) in the pixel array of the display panel 100. Those pixels arranged in one pixel line share the gate line 103. Sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. A horizontal time period is the time obtained by dividing one frame time period by the total number of the pixel lines L1 to Ln.

[0050] The display panel 100 may be implemented using a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device that displays an image on the screen and the real object in the background is visible. The display panel 100 may be made of a flexible display panel.

[0051] The power supply 150 receives an input voltage applied from the host system 200 and outputs voltages required to drive the pixels 101 of the display panel 100 and the display panel driving circuit. To this end, the power supply 150 may include a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 150 may output a constant voltage (or DC voltage) through the DC-DC converter, such as a gate-on voltage, a gate-off voltage, a pixel driving voltage, a cathode voltage, a reference voltage, and an IC driving voltage for the display panel driving circuit. The gate-on voltage and the gate-off voltage may be supplied to the level shifter 140 and the gate driver 120. Voltages such as the pixel driving voltage, the cathode voltage, and the reference voltage may be supplied to the pixels 101 through power lines commonly connected to the pixels 101.

[0052] The power supply 150 may further include a gamma voltage generator. The gamma voltage generator receives a high-potential reference voltage and a low-potential reference voltage and outputs a plurality of gamma reference voltages divided at specific intervals on a preset gamma curve (e.g., a 2.2 gamma curve). The gamma reference voltages are supplied to the data driver 110. In the data driver 110, the gamma reference voltages are subdivided into gray-scale voltages by a voltage dividing circuit. The gamma voltage generator may be implemented using a programmable gamma circuit, which may adjust the voltage of each gamma reference voltage according to digital data. The timing controller 130, the host system 200, or a separate external device may update the digital data stored in the register of the programmable gamma circuit through a communication interface.

[0053] The display panel driving circuit writes the pixel data of the input image to the pixels 101 of the display panel 100 under the control of the timing controller 130. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0054] The display panel driving circuit may further include a touch sensor driver for driving a touch sensor. The touch sensor driver is not shown in Figure 1 The data driver 110 and the touch sensor driver may be integrated into one source driver IC.

[0055] The data driver 110 receives the pixel data of the input image as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 may receive gamma reference voltages and generate gamma compensation voltages for each gray scale through a voltage dividing circuit. The gamma compensation voltages for each gray scale are supplied to digital-to-analog converters (hereinafter referred to as "DACs") provided in each channel of the data driver 110.

[0056] The data driver 110 samples and latches the digital data received from the timing controller 130, and then inputs the digital data into the DAC. Here, the digital data includes pixel data of the input image. In addition, the digital data may include mode selection data for selecting the first mode and the second mode. The DAC converts the pixel data into a gamma-compensated voltage and outputs the data voltage of the pixel data.

[0057] The gate driver 120 may be formed on the display panel 100 together with the circuit elements and wirings of the display area AA. The gate driver 120 may be disposed in at least one of the left and right non-display areas NA outside the display area AA in the display panel 100, or at least a part thereof may be disposed within the display area AA.

[0058] The gate driver 120 may be disposed in the non-display areas NA on both sides of the display panel 100, with the display area AA of the display panel therebetween, so as to supply gate pulses on both sides of the gate line 103 in a dual-feed manner. In another embodiment, the gate driver 120 may be disposed in at least one of the left and right non-display areas NA of the display panel 100, so as to supply a gate signal to the gate line 103 in a single-feed manner. Under the control of the timing controller 130, the gate driver 120 sequentially outputs pulses of the gate signal to the gate line 103. The gate driver 120 may shift the pulses of the gate signal by using a shift register and sequentially supply the gate signal to the gate line 103. When a plurality of gate signals are applied to each pixel, the gate driver 120 may include a plurality of shift registers. The gate signal may include a scan signal input to the pixel circuit through a plurality of gate lines and an emission signal (or EM signal).

[0059] The timing controller 130 receives the digital video data of the input image and the timing signal synchronized with the data from the host system 200. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The periods of the horizontal synchronization signal Hsync and the data enable signal DE are one horizontal period (1H).

[0060] The timing controller 130 may control the display panel driving circuit by generating a data timing control signal for controlling the operation timing of the data driver 110 and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system 200. The timing controller 130 may synchronize the data driver 110 and the gate driver 120 by controlling the operation timing of the display panel driving circuit.

[0061] The gate timing control signal output by the timing controller 130 may be input to the shift register of the gate driver 120 through the level shifter 140. The level shifter 140 may convert the voltage of the gate timing control signal received from the timing controller 130 into a swing width between the gate-on voltage and the gate-off voltage and supply it to the gate driver 120.

[0062] The timing controller 130 may supply the first and second mode selection signals S_sel and P_sel to the pixel circuit. For example, the timing controller 130 may generate the first and second mode selection signals S_sel and P_sel of a first voltage level, supply them to the level shifter, and the level shifter may convert the first and second mode selection signals S_sel and P_sel of the first voltage level into the first and second mode selection signals S_sel and P_sel of a second voltage level and supply them to the pixel circuit.

[0063] The host system 200 may include a main board of one of a television system, a set-top box, a navigation system, a personal computer (PC), an in-vehicle system, a mobile terminal, and a wearable terminal. The host system 200 may scale an image signal from a video source according to the resolution of the display panel 100 and transmit it to the timing controller 130 together with a timing signal.

[0064] The host system 200 may transmit a mode signal having different logic values in the first mode and the second mode to the timing controller 130 together with the image signal at least once per frame.

[0065] Figure 2 It is a circuit diagram showing a pixel circuit according to an embodiment of the present disclosure. Figure 3 It shows Figure 2 a diagram of lenses provided on the first light-emitting element and the second light-emitting element shown in

[0066] Referring to Figure 2 and Figure 3 , the pixel circuit according to the embodiment includes a first light-emitting element EL1 that emits light in a first mode SMODE, a second light-emitting element EL2 that emits light in a second mode PMODE, a driving element DT that drives the first light-emitting element EL1 and the second light-emitting element EL2, a compensation circuit 10 connected to the driving element, a first switching element T1, a second switching element T2, and a third switching element T3. The compensation circuit includes a plurality of switching elements T4 to T9 and a capacitor Cst. The driving element DT and the switching elements T1 to T9 may be implemented as p-channel transistors, but are not limited thereto.

[0067] The pixel circuit is connected to a power supply line to which a DC voltage or a constant voltage is applied, such as a pixel driving voltage line (or a first power supply line) PL1 for applying a pixel driving voltage VDD, a pixel base voltage line (or a second power supply line) PL2 for applying a pixel base voltage VSS, a reference voltage line (or a third power supply line) PL3 for applying a reference voltage Vref, and a compensation voltage line (or a fourth power supply line) PL4 for applying a compensation voltage Vdc. The power supply lines on the display panel 100 may be commonly connected to all pixels.

[0068] The pixel driving voltage VDD is set to a voltage higher than the maximum voltage of the data voltage Vdata and allows the driving element DT to operate in the saturation region. The pixel driving voltage VDD is a voltage higher than the pixel base voltage VSS. The reference voltage Vref may be set to a voltage lower than the pixel driving voltage VDD and higher than the pixel base voltage VSS. The gate-on voltage VGL may be set to a voltage higher than the pixel driving voltage VDD, and the gate-off voltage VGH may be set to a voltage lower than the pixel base voltage VSS.

[0069] The driving element DT drives the first and second light emitting elements EL1 and EL2 by generating a current according to the gate-source voltage Vgs. The driving element DT includes a first electrode connected to the first power supply line PL1 to which the pixel driving voltage VDD is applied, a gate electrode connected to the second node n2, and a second electrode connected to the third node n3.

[0070] The first and second light emitting elements EL1 and EL2 may be implemented as organic light emitting diodes (OLEDs). Each of the light emitting elements EL1 and EL2 includes an anode, a cathode, and an organic compound layer formed between the anode (or the first electrode) and the cathode (or the second electrode). The anode of the first light emitting element EL1 is connected to the fifth node n5, and its cathode is connected to the second power supply line PL2 to which the pixel base voltage VSS is applied. The anode of the second light emitting element EL2 is connected to the sixth node n6, and its cathode is connected to the second power supply line PL2. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, an electron injection layer EIL, but the present disclosure is not limited thereto. Each of the light emitting elements EL1 and EL2 may be implemented in a series structure in which a plurality of light emitting layers are stacked. The light emitting elements EL1 and EL2 having a series structure may improve the brightness and lifetime of the pixel.

[0071] The first switching element T1 is connected between the fourth node n4 and the fifth node n5. The first switching element T1 is turned on in response to the gate conduction voltage VGL of the first mode selection signal S_sel to connect the fourth node n4 to the fifth node n5. The first switching element T1 includes a first electrode connected to the fourth node n4, a gate electrode to which the first mode selection signal S_sel is applied, and a second electrode connected to the fifth node n5.

[0072] The second switching element T2 is connected between the fourth node n4 and the sixth node n6. The second switching element T2 is turned on in response to the gate conduction voltage VGL of the second mode selection signal P_sel to connect the fourth node n4 to the sixth node n6. The second switching element T2 includes a first electrode connected to the fourth node n4, a gate electrode to which the second mode selection signal P_sel is applied, and a second electrode connected to the sixth node n6.

[0073] The third switching element T3 is connected between the fourth node n4 and the fourth power supply line PL4. The third switching element T3 is turned on in response to the gate conduction voltage VGL of the third gate signal SCAN3 to connect the fourth node n4 to the fourth power supply line PL4 through which the compensation voltage Vdc is applied. The third switching element T3 includes a first electrode connected to the fourth node n4, a gate electrode to which the third gate signal SCAN3 is applied, and a second electrode connected to the fourth power supply line PL4.

[0074] The compensation circuit 10 can initialize the pixel circuit and compensate the data voltage Vdata input through the data line DL with the threshold voltage Vth of the driving element DT.

[0075] The capacitor Cst is connected between the first node n1 and the second node n2. During the sensing period Tsen, the data voltage Vdata compensated with the threshold voltage Vth of the driving element DT is stored in the capacitor Cst. The capacitor Cst maintains the gate-source voltage Vgs of the driving element DT during the emission period Tem.

[0076] The fourth switching element T4 is connected between the data line DL and the first node n1. The fourth switching element T4 is turned on in response to the gate conduction voltage VGL of the first gate signal SCAN1 to apply the data voltage Vdata of the pixel data to the capacitor Cst. The fourth switching element T4 includes a first electrode connected to the data line DL, a gate electrode to which the first gate signal SCAN1 is applied, and a second electrode connected to the first node n1.

[0077] The fifth switching element T5 is connected between the second node n2 and the third node n3. The fifth switching element T5 is turned on in response to the gate conduction voltage VGL of the second gate signal SCAN2 to connect the gate electrode of the driving element DT to its second electrode. The fifth switching element T5 includes a first electrode connected to the second node n2, a gate electrode to which the second gate signal SCAN2 is applied, and a second electrode connected to the third node n3.

[0078] The sixth switching element T6 is connected between the first node n1 and the third power supply line PL3. The sixth switching element T6 is turned on in response to the gate conduction voltage VGL of the fourth gate signal EM to connect the first node n1 to the third power supply line PL3. The sixth switching element T6 includes a first electrode connected to the first node n1, a gate electrode to which the fourth gate signal EM is applied, and a second electrode connected to the third power supply line PL3.

[0079] The seventh switching element T7 is connected between the third node n3 and the fourth node n4. The seventh switching element T7 is turned on in response to the gate conduction voltage VGL of the fourth gate signal EM to connect the third node n3 to the fourth node n4. The seventh switching element T7 includes a first electrode connected to the third node n3, a gate electrode to which the fourth gate signal EM is applied, and a second electrode connected to the fourth node n4.

[0080] The eighth switching element T8 is connected between the fifth node n5 and the third power supply line PL3. The eighth switching element T8 is turned on in response to the gate conduction voltage VGL of the second gate signal SCAN2 to connect the fifth node n5 to the third power supply line PL3 through which the reference voltage Vref is applied. The eighth switching element T8 includes a first electrode connected to the third power supply line PL3, a gate electrode to which the second gate signal SCAN2 is applied, and a second electrode connected to the fifth node n5.

[0081] The ninth switching element T9 is connected between the sixth node n6 and the third power supply line PL3. The ninth switching element T9 is turned on in response to the gate conduction voltage VGL of the second gate signal SCAN2 to connect the sixth node n6 to the third power supply line PL3 through which the reference voltage Vref is applied. The ninth switching element T9 includes a first electrode connected to the third power supply line PL3, a gate electrode to which the second gate signal SCAN2 is applied, and a second electrode connected to the sixth node n6.

[0082] Reference Figure 3 As Figure 3The first lens LENS1 shown can be disposed on the first light-emitting element EL1. The first lens LENS1 can be a semi-cylindrical lens to limit the vertical viewing angle and expand the horizontal viewing angle. The first lens LENS1 is longer in the horizontal direction (or X-axis direction) of the display panel 100 and narrower in its vertical direction. The first lens LENS1 can have a hemispherical cross-section. The first lens compresses the light traveling in the vertical direction among the light emitted by the first light-emitting element EL1 in the first mode, so as to narrow the vertical viewing angle and expand the horizontal viewing angle. Through the first lens LENS1, the vertical viewing angle of the first light-emitting element EL1 is comparable to that of the second light-emitting element EL2, while its horizontal viewing angle is larger than that of the second light-emitting element EL2. In Figure 3 "R" indicates the light-emitting red sub-pixel, "G" indicates the light-emitting green sub-pixel, and "B" indicates the light-emitting blue sub-pixel. Figure 3 The sub-pixels shown in dark colors in

[0083] are non-driven sub-pixels that do not emit light. The light emitted from the screen of the in-vehicle display disposed on the vehicle dashboard can travel to the front camera disposed in front of the upper end of the vehicle interior, and the screen of the in-vehicle display can be seen in the image captured by the front camera. The first lens LENS1 limits the vertical viewing angle of the first light-emitting element EL1 that emits light in the first mode, so as to prevent ghosting of the screen of the in-vehicle display captured by the front camera.

[0084] Figure 3 The second lens LENS2 shown can be disposed on the second light-emitting element EL2. The second lens LENS2 can be a hemispherical lens with a larger thickness at the center and a smaller thickness towards its edge. The second lens LENS2 can compress the light emitted by the second light-emitting element EL2 in the second mode, so as to narrow the upper-lower and left-right viewing angles of the second light-emitting element EL2.

[0085] The first lens LENS1 and the second lens LENS2 can be implemented as a transparent medium or a transparent insulating layer pattern disposed in the display panel 100, but the present disclosure is not limited thereto.

[0086] The first light-emitting element EL1 emits light at a first viewing angle through the first lens LENS1, and the second light-emitting element EL2 emits light at a second viewing angle smaller than the first viewing angle through the second lens LENS2.

[0087] The pixel circuit can be driven in a first mode in which the first light-emitting device EL1 with a narrow viewing angle emits light, or in a second mode in which the second light-emitting device EL2 with a wide viewing angle emits light.

[0088] Figure 4 is a diagram showing the waveform of the pixel circuit shown in Figure 2 when driven in the first mode.Figures 5A to 5F This is a diagram showing the operation of a pixel circuit driven in a first mode.

[0089] Reference Figure 4 , in the first mode, the pixel circuit is driven in the order of an initialization period Tini_s, a sensing period Tsen_s, a data writing period Tw_s, a pre-charge period Tp_s, a charge sharing period Tc_s, and an emission period Tem_s.

[0090] Reference Figure 5A , during the initialization period Tini_s, the second to fourth switching elements T2 to T4 are turned off, while the first switching element T1 and the fifth to ninth switching elements T5 to T9 are turned on, thereby applying a reference voltage Vref to both ends of the capacitor Cst (i.e., the first node n1 and the second node n2), and the anode electrodes of the first and second light-emitting elements (i.e., the fifth node n5 and the sixth node n6) to initialize them.

[0091] Reference Figure 5B , during the sensing period Tsen_s, the first to fourth switching elements T1 to T4 and the sixth and seventh switching elements T6 and T7 are turned off, while the fifth, eighth, and ninth switching elements T5, T8, and T9 are turned on, thereby applying a pixel driving voltage to the second node n2 to sense the threshold voltage Vth of the driving element DT. As a result, the voltage at the second node n2 becomes VDD + Vth.

[0092] Reference Figure 5C , during the data writing period Tw_s, the first to third switching elements T1 to T3 and the sixth and seventh switching elements T6 and T7 are turned off, while the fourth, fifth, eighth, and ninth switching elements T4, T5, T8, and T9 are turned on, thereby applying a data voltage Vdata to the first node n1. As a result, the voltage of the first node n1 becomes Vdata, and the voltage of the second node n2 becomes VDD + Vth.

[0093] Reference Figure 5D , during the pre-charge period Tp_s, the first switching element T1 and the fourth to ninth switching elements T4 to T9 are turned off, while the second and third switching elements T2 and T3 are turned on to pre-charge the sixth node n6 with a compensation voltage Vdc. As a result, the voltage of the sixth node n6 becomes Vref + Vdc, and the second parasitic capacitor C EL2 is charged with a charge +Q.

[0094] In this case, the compensation voltage Vdc can be higher than the reference voltage Vref to pre-charge the sixth node n6 that has been initialized to the reference voltage Vref, and can satisfy Vref < Vdc < V EL1 、VEL2 , to prevent the light-emitting element from emitting light before the emission period. Among them, V EL1 represents the voltage across the first light-emitting element EL1, and V EL2 represents the voltage across the second light-emitting element EL2.

[0095] Reference Figure 5E , during the charge sharing period Tc_s, the third to ninth switching elements T3 to T9 are turned off, while the first and second switching elements T1 and T2 are turned on, so as to short-circuit them by connecting the anode electrode of the first light-emitting element (i.e., the fifth node n5) and the anode electrode of the second light-emitting element (i.e., the sixth node n6) to each other. As a result, the voltages at the fifth node n5 and the sixth node n6 are charge-shared and are both (Vref + Vdc) / 2, and the second parasitic capacitor C EL2 discharges with the charge +Q / 2, while the first parasitic capacitor C EL1 is charged with an equal amount of charge +Q / 2.

[0096] Reference Figure 5F , during the emission period Tem_s, the second to fifth switching elements T2 to T5 and the eighth and ninth switching elements T8 and T9 are turned off, while the first, sixth and seventh switching elements T1, T6 and T7 are turned on, so that current flows through the driving element DT, thereby causing the first light-emitting element EL1 to emit light.

[0097] In this case, since the voltage at the fifth node n5 is (Vref + Vdc) / 2 instead of the reference voltage Vref, the time to rise to the threshold voltage of the first light-emitting element can be reduced, thereby reducing the luminance deviation.

[0098] Figure 6 is a diagram showing different waveforms of the pixel circuit driven in the first mode Figure 2 shown in

[0099] Reference Figure 6 , in the first mode, the pixel circuit is driven in the order of the initialization period Tini_s, the sensing period Tsen_s, the data writing period Tw_s, the pre-charge period Tp_s, and the emission period Tem_s.

[0100] Here, different from Figure 4 , since the compensation voltage is directly applied to the anode electrode of the first light-emitting element, the charge sharing period can be omitted, and a voltage lower than the compensation voltage Vdc can be used.

[0101] Figure 7A and Figure 7B are diagrams comparing the luminance deviation between the comparative example and the embodiment.

[0102] Reference Figure 7A , different from the embodiment shown in Figure 2 , the pixel circuit according to the comparative example is a circuit to which no separate compensation voltage is applied. In this case, due to variations in the panel manufacturing process, the capacitance of parasitic capacitors formed in the light-emitting elements varies at each in-plane position. This causes differences in the charging time of the anode voltage of the light-emitting elements at low gray levels with small current amounts, resulting in variations in brightness uniformity at low gray levels.

[0103] For example, when the capacitance of the parasitic capacitor is large, the charging time of the anode voltage of the light-emitting element is short, so the brightness becomes relatively high, and when the capacitance of the parasitic capacitor is small, the charging time of the anode voltage of the light-emitting element is long, so the brightness is relatively low.

[0104] Reference Figure 7B , the pixel circuit according to the embodiment is a circuit to which the compensation voltage shown in Figure 2 is applied. In this case, even if the capacitance of the parasitic capacitors formed in the light-emitting elements varies at each in-plane position due to variations in the panel manufacturing process, the deviation in brightness uniformity can be compensated by pre-charging the anode voltage of the light-emitting element with a separate compensation voltage higher than the reference voltage during the driving process and driving the pre-charged voltage to perform charge sharing between two adjacent light-emitting elements to increase the initial anode voltage of the light-emitting element.

[0105] For example, when the capacitance of the parasitic capacitor is small, the initial anode voltage of the light-emitting element increases, so the charging time is shortened, resulting in higher brightness. The brightness deviation is compensated by this charge sharing between the anode voltages of the light-emitting elements.

[0106] Figure 8 is a diagram showing the waveform of driving the pixel circuit shown in Figure 2 in the second mode. Figures 9A to 9F is a diagram showing the operation of the pixel circuit driven in the second mode.

[0107] Reference Figure 8 , in the second mode, the pixel circuit is driven in the order of an initialization period Tini_p, a sensing period Tsen_p, a data writing period Tw_p, a pre-charging period Tp_p, a charge sharing period Tc_p, and an emission period Tem_p.

[0108] Reference Figure 9A, during the initialization period Tini_p, the first, third, and fourth switching elements T1, T3, and T4 are turned off, while the second switching element T2 and the fifth to ninth switching elements T5 to T9 are turned on, thereby applying the reference voltage Vref across the capacitor Cst (i.e., the first node n1 and the second node n2), as well as the anode electrodes of the first and second light-emitting elements (i.e., the fifth node n5 and the sixth node n6), to initialize them.

[0109] Reference Figure 9B , during the sensing period Tsen_p, the first to fourth switching elements T1 to T4 and the sixth and seventh switching elements T6 and T7 are turned off, while the fifth, eighth, and ninth switching elements T5, T8, and T9 are turned on, thereby applying the pixel driving voltage to the second node n2 to sense the threshold voltage Vth of the driving element DT. As a result, the voltage at the second node n2 becomes VDD + Vth.

[0110] Reference Figure 9C , during the data writing period Tw_p, the first to third switching elements T1 to T3 and the sixth and seventh switching elements T6 and T7 are turned off, while the fourth, fifth, eighth, and ninth switching elements T4, T5, T8, and T9 are turned on, thereby applying the data voltage Vdata to the first node n1. As a result, the voltage at the first node n1 becomes Vdata, and the voltage at the second node n2 becomes VDD + Vth.

[0111] Reference Figure 9D , during the pre-charge period Tp_p, the second switching element T2 and the fourth to ninth switching elements T4 to T9 are turned off, while the first and third switching elements T1 and T3 are turned on to pre-charge the fifth node n5 with the compensation voltage Vdc. As a result, the voltage at the fifth node n5 becomes Vref + Vdc, and the first parasitic capacitor C EL1 is charged with a charge of +Q.

[0112] At this time, the compensation voltage Vdc can be higher than the reference voltage Vref to pre-charge the fifth node n5 that has been initialized to the reference voltage Vref, and it can satisfy Vref < Vdc < V EL1 、V EL2 , to prevent the light-emitting element from emitting light before the emission period. Wherein, V EL1 represents the voltage across the first light-emitting element EL1, and V EL2 represents the voltage across the second light-emitting element EL2.

[0113] Reference Figure 9E, during the charge sharing period Tc_p, the third to ninth switching elements T3 to T9 are turned off, while the first and second switching elements T1 and T2 are turned on to short-circuit them by connecting the anode electrode of the first light-emitting element (i.e., the fifth node n5) and the anode electrode of the second light-emitting element (i.e., the sixth node n6) to each other. As a result, the voltages at the fifth node n5 and the sixth node n6 are charge-shared and both are (Vref + Vdc) / 2, and the first parasitic capacitor C EL1 discharges with a charge of +Q / 2, while the second parasitic capacitor C EL2 is charged with a charge of +Q / 2.

[0114] Refer to Figure 9F , during the emission period Tem_p, the first switching element T1, the third to fifth switching elements T3 to T5, and the eighth and ninth switching elements T8 and T9 are turned off, while the second, sixth, and seventh switching elements T2, T6, and T7 are turned on, so that current flows through the driving element DT, causing the second light-emitting element EL2 to emit light.

[0115] At this time, since the voltage at the sixth node n6 is (Vref + Vdc) / 2 instead of the reference voltage Vref, the time to rise to the threshold voltage of the second light-emitting element can be reduced, thereby reducing the luminance deviation.

[0116] Figure 10 is a diagram showing different waveforms of the pixel circuit driven in the second mode Figure 2 shown in

[0117] Refer to Figure 10 , in the second mode, the pixel circuit is driven in the order of the initialization period Tini_p, the sensing period Tsen_p, the data writing period Tw_p, the pre-charge period Tp_p, and the emission period Tem_p.

[0118] Here, different from Figure 8 , since the compensation voltage is directly applied to the anode electrode of the second light-emitting element, the charge sharing period can be omitted, and a voltage lower than the compensation voltage Vdc can be used.

[0119] The pixel circuit according to the embodiment can allow the first light-emitting element or the second light-emitting element to selectively emit light, but is not limited thereto. That is, in the pixel circuit according to the embodiment, both the first light-emitting element and the second light-emitting element can emit light. When both the first and second light-emitting elements emit light, a high dynamic range (HDR) image with high luminance and high contrast can be reproduced.

[0120] Figure 11 is a diagram showing the waveforms of the pixel circuit driven in the first and second modes simultaneously Figure 2 shown inFigures 12A to 12E shows the operation of a pixel circuit driven by the waveform of Figure 11 .

[0121] Referring to Figure 11 , in the simultaneous operation of the first mode and the second mode, the pixel circuit is driven in the order of an initialization period Tini_sp, a sensing period Tsen_sp, a data writing period Tw_sp, a pre-charge period Tp_sp, and a transmission period Tem_sp.

[0122] Referring to Figure 12A , during the initialization period Tini_sp, the third and fourth switching elements T3 and T4 are turned off, while the first and second switching elements T1 and T2 and the fifth to ninth switching elements T5 to T9 are turned on, so that a reference voltage Vref is applied to both ends of the capacitor Cst (i.e., the first node n1 and the second node n2), and the anode electrodes of the first and second light-emitting elements (i.e., the fifth node n5 and the sixth node n6) to initialize them.

[0123] Referring to Figure 12B , during the sensing period Tsen_sp, the first to fourth switching elements T1 to T4 and the sixth and seventh switching elements T6 and T7 are turned off, while the fifth, eighth, and ninth switching elements T5, T8, and T9 are turned on, so that a pixel driving voltage is applied to the second node n2 to sense the threshold voltage Vth of the driving element DT. As a result, the voltage at the second node n2 becomes VDD + Vth.

[0124] Referring to Figure 12C , during the data writing period Tw_sp, the first to third switching elements T1 to T3 and the sixth and seventh switching elements T6 and T7 are turned off, while the fourth, fifth, eighth, and ninth switching elements T4, T5, T8, and T9 are turned on to apply a data voltage Vdata to the first node n1. As a result, the voltage at the first node n1 becomes Vdata, and the voltage at the second node n2 becomes VDD + Vth.

[0125] Referring to Figure 12D , during the pre-charge period Tp_sp, the fourth to ninth switching elements T4 to T9 are turned off, while the first to third switching elements T1 to T3 are turned on to apply a compensation voltage Vdc' to the fifth and sixth nodes n5 and n6. As a result, the voltages at the fifth node n5 and the sixth node n6 both become Vref + Vdc', and the first parasitic capacitor C EL1 and the second parasitic capacitor C EL2 are both charged with a charge +Q.

[0126] At this time, the compensation voltage Vdc' can be lower than the voltage in the first mode or the second mode operation, satisfying Vref < Vdc' < V EL1 and V EL2 . Among them, V EL1 represents the voltage across the first light-emitting element EL1, and V EL2 represents the voltage across the second light-emitting element EL2.

[0127] When the first mode and the second mode are simultaneously operated, since the compensation voltage Vdc' is simultaneously applied to the fifth node n5 and the sixth node n6, a separate charge sharing period is not required.

[0128] Refer to Figure 12E , in the emission period Tem_sp, the third to fifth switching elements T3 to T5 and the eighth and ninth switching elements T8 and T9 are turned off, while the first, second, sixth, and seventh switching elements T1, T2, T6, and T7 are turned on, so that current flows through the driving element DT, thereby causing both the first light-emitting element EL1 and the second light-emitting element EL2 to emit light.

[0129] At this time, since the voltages at the fifth and sixth nodes are the compensation voltage Vdc' instead of the reference voltage Vref, the time to rise to the threshold voltage of the light-emitting element can be reduced, thereby reducing the luminance deviation.

[0130] Although the embodiments of the present disclosure have been described in more detail with reference to the drawings, the present disclosure is not limited thereto, and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are only for illustrative purposes and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all aspects and do not limit the present disclosure.

[0131] The following numbered clauses are also disclosed:

[0132] 1. A pixel circuit, comprising: a first light-emitting element; a second light-emitting element; a driving element configured to drive the first light-emitting element and the second light-emitting element; a first switching element connected between the driving element and the first light-emitting element and driven by a first mode selection signal; a second switching element connected between the driving element and the second light-emitting element and driven by a second mode selection signal; and a third switching element configured to apply a predetermined compensation voltage to at least one of an anode electrode of the first light-emitting element and an anode electrode of the second light-emitting element.

[0133] 2. The pixel circuit according to Clause 1, wherein the pixel circuit is driven in the order of an initialization period, a sensing period, a data writing period, a pre-charging period, and a light emitting period. During the initialization period, a reference voltage is applied to the anode electrodes of the first light emitting element and the second light emitting element to initialize them. During the pre-charging period, the compensation voltage is applied to the anode electrode of the first light emitting element and the anode electrode of the second light emitting element that has been initialized to the reference voltage.

[0134] 3. The pixel circuit according to Clause 2, wherein the compensation voltage is set to be greater than the reference voltage and less than the voltage across each of the first light emitting element and the second light emitting element.

[0135] 4. The pixel circuit according to Clause 2, wherein the pixel circuit is driven in a charge sharing period after the pre-charging period. During the charge sharing period, the anode electrodes of the first light emitting element and the second light emitting element are connected to each other to share the applied compensation voltage.

[0136] 5. The pixel circuit according to Clause 4, further comprising a compensation circuit. The compensation circuit includes: a capacitor connected between a first node and a second node to which the gate electrode of the driving element is connected; a fourth switching element including a first electrode connected to a data line, a second electrode connected to the first node, and a gate electrode to which a first gate signal is applied; a fifth switching element including a first electrode connected to the second node, a second electrode connected to a third node to which the source electrode of the driving element is connected, and a gate electrode to which a second gate signal is applied; a sixth switching element including a first electrode connected to the first node, a second electrode connected to a reference voltage line, and a gate electrode to which a fourth gate signal is applied; a seventh switching element including a first electrode connected to the third node, a second electrode connected to a fourth node, and a gate electrode to which the fourth gate signal is applied; an eighth switching element including a first electrode connected to the reference voltage line, a second electrode connected to a fifth node to which the anode electrode of the first light emitting element is connected, and a gate electrode to which the second gate signal is applied; and a ninth switching element including a first electrode connected to the reference voltage line, a second electrode connected to a sixth node to which the anode electrode of the second light emitting element is connected, and a gate electrode to which the second gate signal is applied.

[0137] 6. The pixel circuit according to Clause 5, wherein the first switching element includes a first electrode connected to the fourth node, a second electrode connected to the fifth node, and a gate electrode to which the first mode selection signal is applied, the second switching element includes a first electrode connected to the fourth node, a second electrode connected to the sixth node, and a gate electrode to which the second mode selection signal is applied, and the third switching element includes a first electrode connected to the fourth node, a second electrode connected to the power supply line to which the compensation voltage is applied, and a gate electrode to which a third gate signal is applied.

[0138] 7. The pixel circuit according to Clause 6, wherein during the pre-charge period, at least one of the first switching element and the second switching element and the third switching element is turned on, while all other switching elements are turned off.

[0139] 8. The pixel circuit according to Clause 7, wherein during the charge sharing period, the first switching element and the second switching element are turned on, while all other switching elements are turned off.

[0140] 9. A display device, comprising: a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are provided; a data driver configured to output data voltages to the plurality of data lines; and a gate driver configured to output gate signals to the plurality of gate lines, wherein each of the pixel circuits includes: a first light-emitting element; a second light-emitting element; a driving element configured to drive the first light-emitting element and the second light-emitting element; a first switching element connected between the driving element and the first light-emitting element and driven by a first mode selection signal; a second switching element connected between the driving element and the second light-emitting element and driven by a second mode selection signal; and a third switching element configured to apply a predetermined compensation voltage to at least one of an anode electrode of the first light-emitting element and an anode electrode of the second light-emitting element.

[0141] 10. The display device according to Clause 9, wherein the pixel circuit is driven in the order of an initialization period, a sensing period, a data writing period, a pre-charge period, and an emission period, wherein during the initialization period, a reference voltage is applied to the anode electrode of the first light-emitting element and the anode electrode of the second light-emitting element to initialize them, and during the pre-charge period, the compensation voltage is applied to the anode electrode that has been initialized to the reference voltage among the anode electrode of the first light-emitting element and the anode electrode of the second light-emitting element.

[0142] 11. The display device according to Clause 10, wherein the pixel circuit is driven during a charge sharing period after the pre-charge period, and during the charge sharing period, an anode electrode of the first light-emitting element and an anode electrode of the second light-emitting element are connected to each other to share the applied compensation voltage.

[0143] 12. The display device according to Clause 11, further comprising a compensation circuit, the compensation circuit including: a capacitor connected between a first node and a second node to which a gate electrode of the driving element is connected; a fourth switching element including a first electrode connected to a data line, a second electrode connected to the first node, and a gate electrode to which a first gate signal is applied; a fifth switching element including a first electrode connected to the second node, a second electrode connected to a third node to which a source electrode of the driving element is connected, and a gate electrode to which a second gate signal is applied; a sixth switching element including a first electrode connected to the first node, a second electrode connected to a reference voltage line, and a gate electrode to which a fourth gate signal is applied; a seventh switching element including a first electrode connected to the third node, a second electrode connected to a fourth node, and a gate electrode to which the fourth gate signal is applied; an eighth switching element including a first electrode connected to the reference voltage line, a second electrode connected to a fifth node to which the anode electrode of the first light-emitting element is connected, and a gate electrode to which the second gate signal is applied; and a ninth switching element including a first electrode connected to the reference voltage line, a second electrode connected to a sixth node to which the anode electrode of the second light-emitting element is connected, and a gate electrode to which the second gate signal is applied.

[0144] 13. The display device according to Clause 12, wherein the first switching element includes a first electrode connected to the fourth node, a second electrode connected to the fifth node, and a gate electrode to which the first mode selection signal is applied, the second switching element includes a first electrode connected to the fourth node, a second electrode connected to the sixth node, and a gate electrode to which the second mode selection signal is applied, and the third switching element includes a first electrode connected to the fourth node, a second electrode connected to a power supply line to which the compensation voltage is applied, and a gate electrode to which a third gate signal is applied.

[0145] 14. The display device according to Clause 9, wherein the first mode selection signal and the second mode selection signal are received from a timing controller.

Claims

1. A pixel circuit, comprising: a first light emitting element; a second light emitting element; a driving element transistor configured to drive the first light emitting element and the second light emitting element; A compensation voltage line, wherein the compensation voltage line is used to apply a compensation voltage; a first switching element including a first electrode and connected between the driving element transistor and the first light emitting element, and driven by a first mode selection signal; a second switching element including a first electrode and connected between the driving element transistor and the second light emitting element and driven by a second mode selection signal; as well as a third switching element configured to apply a predetermined compensation voltage to at least one of the anode electrode of the first light emitting element and the anode electrode of the second light emitting element, The first electrode of the third switching element is connected to the first electrode of the first switching element and the first electrode of the second switching element, and the second electrode of the third switching element is connected to the compensation voltage line.

2. The pixel circuit according to claim 1, wherein: The third switch element is used for receiving a scan signal.

3. The pixel circuit according to claim 1 or 2, further comprising: Pixel drive voltage line; as well as A pixel basic voltage line, wherein the pixel basic voltage line is used to apply a pixel basic voltage; The driving element transistor is configured to connect the pixel driving voltage line to the first electrode of the first switching element and the first electrode of the second switching element.

4. The pixel circuit according to claim 3, wherein: The first electrode of the first light emitting element is connected to the second electrode of the first switching element, and the second electrode of the first light emitting element is connected to the pixel basic voltage line; and The first electrode of the second light emitting element is connected to the second electrode of the second switching element, and the second electrode of the second light emitting element is connected to the pixel basic voltage line.

5. A pixel circuit according to any preceding claim, wherein: The pixel circuit will be driven in the order of an initialization period, a sensing period, a data writing period, a pre-charging period and an emission period. wherein during the initialization period, a reference voltage is applied to the first electrode of the first light emitting element and the first electrode of the second light emitting element to initialize them, and During the precharge period, the compensation voltage is applied to a first electrode of the first electrode of the first light emitting element and the first electrode of the second light emitting element that has been initialized to the reference voltage.

6. The pixel circuit according to claim 5, wherein: The compensation voltage is set to be greater than the reference voltage and less than a voltage across each of the first light emitting element and the second light emitting element.

7. The pixel circuit according to claim 5 or 6, wherein: The pixel circuit is to be driven in a charge sharing period after the pre-charging period, and During the charge sharing period, the first electrode of the first light emitting element and the first electrode of the second light emitting element are connected to each other to share an applied compensation voltage.

8. The pixel circuit according to any one of claims 5 to 7, further comprising a compensation circuit, wherein the compensation circuit comprises: a capacitor connected between the first node and a second node to which the gate electrode of the driving element transistor is connected; a fourth switching element, comprising a first electrode connected to the data line, a second electrode connected to the first node, and a gate electrode for receiving a first gate signal; a fifth switching element including a first electrode connected to the second node, a second electrode connected to a third node to which the source electrode of the driving element transistor is connected, and a gate electrode for receiving a second gate signal; a sixth switching element, comprising a first electrode connected to the first node, a second electrode connected to a reference voltage line, and a gate electrode for receiving a fourth gate signal; a seventh switching element, comprising a first electrode connected to the third node, a second electrode connected to a fourth node, and a gate electrode for receiving the fourth gate signal; an eighth switching element, comprising a first electrode connected to the reference voltage line, a second electrode connected to a fifth node to which the first electrode of the first light emitting element is connected, and a gate electrode for receiving the second gate signal; as well as A ninth switching element includes a first electrode connected to the reference voltage line, a second electrode connected to a sixth node to which the first electrode of the second light emitting element is connected, and a gate electrode for receiving the second gate signal.

9. The pixel circuit according to claim 8, wherein The first electrode of the first switching element is connected to the fourth node, the second electrode of the first switching element is connected to the fifth node, and the gate electrode of the first switching element is used to receive the first mode selection signal, The first electrode of the second switching element is connected to the fourth node, the second electrode of the second switching element is connected to the sixth node, and the gate electrode of the second switching element is used to receive the second mode selection signal, and The first electrode of the third switching element is connected to the fourth node, and a gate electrode of the third switching element is used to receive a third gate signal.

10. The pixel circuit according to claim 9, wherein: During the pre-charging period, at least one of the first switching element and the second switching element and the third switching element are turned on, and all other switching elements are turned off.

11. The pixel circuit according to claim 10, wherein: During the charge sharing period, the first switching element and the second switching element are turned on, and all other switching elements are turned off.

12. A pixel circuit according to any preceding claim, wherein: The first light emitting element and the second light emitting element are organic light emitting diodes.

13. A pixel circuit according to any preceding claim, wherein: The viewing angle of the first light emitting element is greater than the viewing angle of the second light emitting element.

14. A display device, comprising: The pixel circuit according to claim 1; Data drives; Gate driver; as well as A power supply is configured to provide the pixel base voltage and the compensation voltage.

15. The display device according to claim 14, wherein: The pixel circuit is configured to be driven in the order of an initialization period, a sensing period, a data writing period, a pre-charging period, and an emission period, wherein, during the initialization period, a reference voltage is applied to the first electrode of the first light emitting element and the first electrode of the second light emitting element to initialize them, and During the precharge period, the compensation voltage is applied to a first electrode of the first electrode of the first light emitting element and the first electrode of the second light emitting element that has been initialized to the reference voltage, Wherein, the power supply is configured to provide the reference voltage.

16. The display device according to claim 15, wherein: The pixel circuit is configured to be driven in a charge sharing period after the pre-charging period, and During the charge sharing period, the first electrode of the first light emitting element and the first electrode of the second light emitting element are connected to each other to share an applied compensation voltage.

17. The display device according to claim 16, wherein: The compensation circuit comprises: a capacitor connected between the first node and a second node to which the gate electrode of the driving element transistor is connected; a fourth switching element including a first electrode connected to the data line, a second electrode connected to the first node, and a gate electrode to which a first gate signal is applied; a fifth switching element including a first electrode connected to the second node, a second electrode connected to a third node to which the source electrode of the driving element transistor is connected, and a gate electrode to which a second gate signal is applied; a sixth switching element, comprising a first electrode connected to the first node, a second electrode connected to a reference voltage line, and a gate electrode to which a fourth gate signal is applied; a seventh switching element, comprising a first electrode connected to the third node, a second electrode connected to a fourth node, and a gate electrode to which the fourth gate signal is applied; an eighth switching element including a first electrode connected to the reference voltage line, a second electrode connected to a fifth node to which the first electrode of the first light emitting element is connected, and a gate electrode to which the second gate signal is applied; and a ninth switching element including a first electrode connected to the reference voltage line, a second electrode connected to a sixth node to which the first electrode of the second light emitting element is connected, and a gate electrode to which the second gate signal is applied, The data driver is connected to the data line and the gate driver is configured to provide the gate signal.

18. The display device according to claim 17, wherein the first electrode of the first switching element is connected to the fourth node, the second electrode of the first switching element is connected to the fifth node, and the first mode selection signal is applied to the gate electrode of the first switching element, The first electrode of the second switching element is connected to the fourth node, the second electrode of the second switching element is connected to the sixth node, and the second mode selection signal is applied to the gate electrode of the second switching element, and The first electrode of the third switching element is connected to the fourth node, and a third gate signal is applied to a gate electrode of the third switching element.

19. The display device according to any one of claims 14 to 18, wherein: The display device further includes a timing controller, and the first mode selection signal and the second mode selection signal are received from the timing controller.

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