Pixel circuit and display device including same

Abstract

An embodiment discloses a pixel circuit and a display device including the same, the pixel circuit including: a driving element including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a light emitting element connected to the second electrode of the driving element; a first capacitor connected to the first node and the fourth node; a second capacitor connected to the fourth node and the second node; a first switching element connected to the first node and the third node; a second switching element connected to the fourth node and a reference voltage supply line; and a third switching element connected to the first node and the initialization voltage supply line.

Description

Technical Field

[0001] Embodiments relate to a pixel circuit and a display device including the same. Background Art

[0002] In an information society, various technologies have been developed in the field of display devices for displaying visual information in the form of images or videos. Among various display devices, organic light emitting display devices are regarded as next-generation displays because: organic light emitting display devices use organic light emitting diodes, which are self-luminous elements that emit light from their light emitting layers through the recombination of electrons and holes, and thus have a fast response time, high brightness, and low driving voltage, can be made ultrathin, and can be implemented in various shapes.

[0003] An organic light emitting display device generally reduces brightness non-uniformity by compensating the characteristics of driving transistors (thin film transistors) configured to control the driving current flowing to the organic light emitting diodes.

[0004] The description provided in this background art section should not be assumed to be prior art merely because it is mentioned in or related to the background art section. The background art section may include information that describes one or more aspects of the subject technology. Summary of the Invention

[0005] However, the inventors of the present application newly recognized that: in the trend of high resolution and high speed driving of organic light emitting display devices, conventional compensation methods cannot sufficiently compensate for differences in driving characteristics of pixels. For example, as the resolution and / or driving frequency increase, the horizontal period H for writing data to the pixels in one row in the display panel decreases. The horizontal period H is the time for writing data to the pixels in one horizontal row provided on the screen.

[0006] The driving circuit of an organic light emitting display device samples the threshold voltage (Vth) of the driving transistor within one horizontal period (H), compensates the data voltage according to the threshold voltage (Vth), and writes the data to the pixel. Therefore, when the horizontal period (H) decreases, the time required to sample the threshold voltage (Vth) of the driving transistor decreases.

[0007] When the time required to sample the threshold voltage (Vth) of the driving transistor is insufficient, the threshold voltage (Vth) of the driving transistor may be inaccurately sensed, resulting in differences in driving characteristics between pixels.

[0008] One aspect of the present disclosure is to provide a pixel circuit and a display device including the same that substantially eliminate one or more problems caused by the limitations and disadvantages of the related art.

[0009] Another aspect of the present disclosure is to provide a pixel circuit and a display device including the same that can ensure sufficient sampling time even during high-speed driving.

[0010] Another aspect of the present disclosure is to provide a display device that can prevent or reduce a short circuit between a pixel driving voltage and an initialization voltage during an initialization period.

[0011] It should be noted that the aspects of the present disclosure are not limited to the above aspects, and other aspects of the present disclosure will be apparent to those skilled in the art from the following description.

[0012] According to one aspect of the present disclosure, there is provided a pixel circuit including: a driving element including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a light-emitting element connected to the second electrode of the driving element; a first capacitor connected to the first node and a fourth node; a second capacitor connected to the fourth node and the second node; a first switching element connected to the first node and the third node; a second switching element connected to the fourth node and a reference voltage supply line; and a third switching element connected to the first node and an initialization voltage supply line.

[0013] The reference voltage applied from the reference voltage supply line may be greater than the initialization voltage applied from the initialization voltage supply line.

[0014] The first capacitor can be initialized by applying a reference voltage and an initialization voltage to both ends of the first capacitor, respectively.

[0015] The second capacitor can be initialized by applying a reference voltage and a pixel driving voltage to both ends of the second capacitor, respectively.

[0016] The pixel circuit may include: a fifth switching element configured to connect the initialization voltage supply line and the anode of the light-emitting element; and a first gate line connected to the gate electrodes of the third switching element and the fifth switching element.

[0017] The pixel circuit may include a fourth switching element provided between the fourth node and the data voltage supply line.

[0018] The pixel circuit may include: the first gate line that applies a first gate voltage to the gate electrode of the third switching element; a second gate line that applies a second gate voltage to the gate electrode of the second switching element; a third gate line that applies a third gate voltage to the gate electrode of the first switching element; and a fourth gate line that applies a fourth gate voltage to the gate electrode of the fourth switching element.

[0019] The pixel circuit can be driven in an initialization period, a sampling period, a programming period, and a light-emitting period. During the initialization period, the second switching element, the third switching element, and the driving element are turned on, and the first switching element and the fourth switching element are turned off; during the sampling period, the first switching element and the second switching element are turned on, so that the level of the fourth node is fixed at the reference voltage, and the level of the first node changes from the initialization voltage to the difference between the pixel driving voltage and the threshold voltage of the driving element; during the programming period, the fourth switching element is turned on, and the first to third switching elements are turned off, so that the level of the first node is changed to the difference between the pixel driving voltage and the threshold voltage of the driving element; and during the light-emitting period, the current flowing through the driving element is independent of the pixel driving voltage or the threshold voltage of the driving element.

[0020] The reference voltage can be greater than the data voltage applied from the data voltage supply line.

[0021] The initialization voltage supply line can be electrically isolated from the second electrode of the driving element.

[0022] According to another aspect of the present disclosure, a display device is provided, which includes: a data driving circuit; a gate driving circuit; and a pixel circuit, which includes: a driving element, which includes a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a light-emitting element, which is connected to the second electrode of the driving element; a first capacitor, which is disposed between the first node and a fourth node; a second capacitor, which is disposed between the fourth node and the second node; a first switching element, which is disposed between the first node and the third node; a second switching element, which is disposed between the fourth node and a reference voltage supply line; and a third switching element, which is disposed between the first node and an initialization voltage supply line.

[0023] The pixel circuit can be driven in an initialization period, a sampling period, a programming period, and a light-emitting period. In the initialization period, a reference voltage and an initialization voltage are applied to both ends of the capacitor. In the sampling period, the threshold voltage of the driving element is sampled using the reference voltage and the pixel driving voltage. And in the programming period, a data voltage is applied to the pixel circuit to store the data voltage in the capacitor.

[0024] According to the present disclosure, it is possible to ensure a sampling time longer than one horizontal period, so that accurate sampling can be performed even during high-speed driving. Therefore, it has the advantage of achieving uniform driving characteristics even during high-speed driving.

[0025] According to the present disclosure, by ensuring that the pixel driving voltage and the initialization voltage do not short-circuit during initialization, damage to the pixel circuit can be minimized or reduced and low-power control can be achieved.

[0026] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the inventive concept claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings may be included to provide a further understanding of the present disclosure and may be incorporated into and constitute a part of the present disclosure. The drawings illustrate embodiments of the present disclosure and, together with the description, are used to explain the various principles of the present disclosure.

[0028] By describing in detail exemplary embodiments of the present disclosure with reference to the drawings, the above and other aspects, features, and effects of the present disclosure will become clearer to those of ordinary skill in the art. In the drawings:

[0029] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure;

[0030] Figure 2 is illustrative of Figure 1 an example of a cross-sectional view showing a cross-sectional structure of the display panel shown;

[0031] Figure 3 is a diagram schematically illustrating a display device according to an exemplary embodiment of the present disclosure;

[0032] Figure 4 is a circuit diagram illustrating a pixel circuit according to an exemplary embodiment of the present disclosure;

[0033] Figure 5A is a circuit diagram illustrating an example operation of the pixel circuit during an initialization period;

[0034] Figure 5B is an example of a waveform diagram illustrating the operation of the pixel circuit during an initialization period;

[0035] Figure 6A is a circuit diagram illustrating an example operation of the pixel circuit during a sampling period;

[0036] Figure 6B is an example of a waveform diagram illustrating the operation of the pixel circuit during a sampling period;

[0037] Figure 7 is an example of a waveform diagram illustrating a state in which the sampling period is controlled to be longer than one horizontal period;

[0038] Figure 8A is a circuit diagram illustrating an example operation of the pixel circuit during a programming period;

[0039] Figure 8B is an example of a waveform diagram illustrating the operation of the pixel circuit during a programming period;

[0040] Figure 9A is a circuit diagram illustrating an example operation of the pixel circuit during a light emission period;

[0041] Figure 9B is an example of a waveform diagram illustrating the operation of the pixel circuit during a light emission period;

[0042] Figure 10 is a diagram schematically illustrating a pixel circuit according to an exemplary embodiment of the present disclosure;

[0043] Figure 11 is a diagram illustrating an example of a pixel circuit that performs sampling using a data voltage;

[0044] Figure 12 is Figure 11 a waveform diagram of the circuit;

[0045] Figure 13 is a circuit diagram illustrating a pixel circuit according to another exemplary embodiment of the present disclosure; and

[0046] Figure 14 is a waveform diagram of a pixel circuit according to another exemplary embodiment of the present disclosure.

[0047] Throughout the drawings and the detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the dimensions, lengths, and thicknesses of layers, regions, and elements, and their illustrations, may be exaggerated. Detailed Description

[0048] Now, embodiments of the present disclosure will be described in detail, examples of which may be shown in the drawings. In the following description, when a detailed description of well-known functions or configurations related to this document is determined to unnecessarily obscure the gist of the inventive concept, its detailed description will be omitted or briefly provided. The progress of the described processing steps and / or operations is an example; however, the order of the steps and / or operations is not limited to the order set forth herein and may be changed as known in the art, except for steps and / or operations that must occur in a specific order. Similar reference numerals designate similar elements throughout. The names of the corresponding elements used in the following description may be selected only for the convenience of writing the specification and may therefore be different from the names used in actual products.

[0049] The advantages and features of the present disclosure and the method of implementing the same will be clarified by the following exemplary embodiments described with reference to the accompanying drawings. The present disclosure is not limited to the following exemplary embodiments, but may be implemented in various different forms. The exemplary embodiments are provided only to make the present disclosure complete and to fully convey the scope of the present disclosure to those of ordinary skill in the art to which the present disclosure pertains, and the present disclosure will be defined by the appended claims.

[0050] The numbers, dimensions, ratios, angles, quantities, etc. disclosed in the drawings used to describe the exemplary embodiments of the present disclosure are merely exemplary, and thus the present disclosure is not limited to the matters illustrated in the drawings. Throughout the specification, like reference numerals refer to substantially like components. In addition, when determining that a detailed description of well-known technologies may unnecessarily obscure the gist of the present disclosure, the detailed description of these well-known technologies will be omitted. Any implementation described herein as an "example" need not be construed as being preferred or advantageous compared to other implementations.

[0051] Unless used together with the term "only", terms such as "comprising", "having", and "consisting of" used herein are intended to allow the addition of other elements. When a component is expressed in the singular form, it may be construed in the plural form unless otherwise expressly stated.

[0052] Even if not expressly mentioned, components are construed to include a conventional error range.

[0053] When using terms such as "on", "above", "below", "over", "under", "beneath", "near", "close to", "adjacent to", "next to", "connected or coupled", "crossed or intersected", etc. to describe the positional or interconnection relationship between two components, unless a more restrictive term such as "immediately", "closely", or "directly" is used, one or more other components may be interposed between the two components. In addition, terms such as "left", "right", "top", "bottom", "down", "up", "upper", "lower", etc. refer to an arbitrary reference system.

[0054] When using terms such as "after", "subsequently", "next", "before", etc. to describe a chronological relationship, unless a more restrictive term such as "only", "immediately", or "directly" is used, discontinuous cases may be included.

[0055] Although ordinal numbers such as first, second, "A", "B", "(a)", "(b)", etc. are used to distinguish between components, the functions or structures of these components are not limited by the ordinal numbers or component names before the components. In addition, when an element or layer is described as "connected", "coupled" or "adhered" to another element or layer, the element or layer can not only be directly connected or adhered to the other element or layer, but also be indirectly connected or adhered to the other element or layer, and one or more intermediate elements or layers are disposed between the element or layer, unless otherwise specified.

[0056] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of the first element, the second element, and the third element" covers the combination of all three listed elements, the combination of any two of the three elements, and each individual element, the first element, the second element, or the third element.

[0057] The following embodiments can be coupled or combined with each other locally or globally, and can interoperate and execute in various ways technically. Each embodiment can be operable independently of each other, and can be implemented together in a related relationship.

[0058] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of this specification have the same meaning as those commonly understood by those skilled in the art to which this specification pertains, unless specifically defined and described explicitly, and the meanings of common terms (such as terms defined in a dictionary) can be interpreted in consideration of the context meanings of the relevant fields, and should not be interpreted in an idealized or overly formal meaning, unless explicitly defined as such herein. For example, the term "component" or "unit" can be applied, for example, to a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described functions, as should be understood by those of ordinary skill in the art.

[0059] In the display device of the present disclosure, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistors may be oxide thin film transistors (TFTs) including an oxide semiconductor, or LTPS TFTs including low temperature polycrystalline silicon (LTPS).

[0060] A transistor is a three - electrode device including a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. Carriers in the transistor start to flow out from the source. The drain is the electrode through which carriers are drained out of the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n - channel transistor, the carriers are electrons, so the source voltage is lower than the drain voltage, causing electrons to flow from the source to the drain. In an n - channel transistor, current flows from the drain to the source. In the case of a p - channel transistor, the carriers are holes, so the source voltage is higher than the drain voltage, causing holes to flow from the source to the drain. In a p - channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the positions of the source and drain of a transistor are not fixed. For example, depending on the applied voltage, the source and drain can be interchanged. Therefore, the present disclosure is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0061] The strobe signal can swing between a gate - on voltage and a gate - off voltage. The transistor turns on in response to the gate - on voltage and turns off in response to the gate - off voltage. In the case of an n - channel transistor, the gate - on voltage can be the gate - high voltage VGH, and the gate - off voltage can be the gate - low voltage VGL. In the case of a p - channel transistor, the gate - on voltage can be the gate - low voltage VGL, and the gate - off voltage can be the gate - high voltage VGH.

[0062] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0063] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure. Figure 2 is illustrative of Figure 1 a cross - sectional view of the cross - sectional structure of the display panel shown. Figure 3 is a diagram schematically illustrating a display device.

[0064] Referring to Figures 1 to 3 , a display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driving circuit configured to write pixel data to pixels of the display panel 100, and a power supply 140 configured to generate power required to drive the pixels and the display panel driving circuit.

[0065] The display panel 100 can be made of a plastic substrate, a thin glass substrate, or a metal substrate. Pixels 101 are implemented on the display panel 100.

[0066] The display panel 100 may be a panel having a rectangular structure with a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction, but the present disclosure is not limited thereto. The display area AA of the display panel 100 includes a pixel array configured to display an input image. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels 101 arranged in a matrix form. The display panel 100 may further include power lines commonly connected to the pixels 101. The power lines are connected to the constant voltage nodes of the pixel circuits and supply a constant voltage required for driving the pixels 101 to the pixels 101.

[0067] Each pixel 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for realizing color. Each pixel may further include a white sub-pixel. Each sub-pixel includes a pixel circuit for driving a light-emitting element. Each pixel circuit is connected to a data line, a gate line, and a power line. Hereinafter, a "pixel" may be interpreted as a "sub-pixel".

[0068] The pixels may be set as true color pixels or pentile pixels. In pentile pixels, two sub-pixels of different colors are driven as one pixel 101 using a predetermined pixel rendering algorithm to achieve a higher resolution than that of true color pixels. The pixel rendering algorithm may use the colors of light emitted from adjacent pixels to compensate for the insufficient color reproduction of each pixel.

[0069] The pixel array includes a plurality of pixel rows L1 to Ln. Each row of the pixel rows L1 to Ln includes a row of pixels arranged in the row direction (X-axis direction) in the pixel array of the display panel 100. The pixels provided in one pixel row share the gate line 103. The sub-pixels arranged in the column direction (Y-axis direction) along the data line share the same data line 102. One horizontal period is a time obtained by dividing one frame period by the total number of the pixel rows L1 to Ln.

[0070] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel is applicable to a transparent display device in which an image is displayed on a screen and real background objects are visible. The display panel 100 may be manufactured as a flexible display panel.

[0071] The cross-sectional structure of the display panel 100 may include a circuit layer CIR, a light-emitting element layer EMIL, and a packaging layer ENC laminated on a substrate SUBS, as Figure 2 shown.

[0072] The circuit layer CIR may include: a thin film transistor (TFT) array of pixel circuits including lines connected to lines such as data lines, gate lines, power lines, etc., a demultiplexer array, a gate driver 120, etc. The circuit layer CIR includes a plurality of metal layers and semiconductor material layers, and the plurality of metal layers are insulated from each other by an insulating layer interposed therebetween.

[0073] The light-emitting element layer EMIL may include a light-emitting element EL driven by a pixel circuit. The light-emitting element may include a light-emitting element for a red sub-pixel, a light-emitting element for a green sub-pixel, and a light-emitting element for a blue sub-pixel. The light-emitting element layer EMIL may also include a light-emitting element for a white sub-pixel. The light-emitting element layer EMIL in each sub-pixel may have a structure in which a light-emitting element and a color filter are stacked. The light-emitting element EL of the light-emitting element layer EMIL may be covered with a multi-layer protective layer including an organic film and an inorganic film.

[0074] The encapsulation layer ENC covers the light-emitting element layer EMIL to seal the circuit layer CIR and the light-emitting element layer EMIL. The encapsulation layer ENC may have a multi-insulating film structure in which an organic film and an inorganic film are alternately stacked. The inorganic film blocks the infiltration of moisture or oxygen. The organic film planarizes the surface of the inorganic film. When the organic film and the inorganic film are stacked in multiple layers, the moving path of moisture or oxygen becomes longer compared to a single layer, so the infiltration of moisture and oxygen affecting the light-emitting element layer EMIL can be effectively blocked.

[0075] The touch sensor layer omitted in the figure may be formed on the encapsulation layer ENC, and a polarizing plate or a color filter layer may be provided on the touch sensor layer. The touch sensor layer may include a capacitive touch sensor that senses a touch input based on a change in capacitance before and after the touch input. The touch sensor layer may include a metal wiring pattern and an insulating film that form the capacitance of the touch sensor. The insulating film may insulate the crossing portions of the metal wiring pattern and planarize the surface of the touch sensor layer. The polarizing plate can improve visibility and contrast by converting the polarization of external light reflected from the metal of the touch sensor layer and the circuit layer. The polarizing plate may be implemented as a polarizing plate in which a linear polarizing plate and a phase retardation film are joined, or a circular polarizing plate. A cover glass may be adhered to the polarizing plate. The color filter layer may include a red color filter, a green color filter, and a blue color filter. The color filter layer may also include a black matrix pattern. The color filter layer can absorb a part of the wavelength of the light reflected from the circuit layer and the touch sensor layer to replace the function of the polarizing plate, and can improve the color purity of the image reproduced on the pixel array.

[0076] Power supply 140 generates a constant voltage (or direct current (DC) voltage) required to drive the pixel array and the display panel driving circuit of display panel 100 by using a DC-DC converter. The DC-DC converter may include a charge pump, a rectifier, a buck converter, a boost converter, etc. Power supply 140 may adjust the level of the DC input voltage applied from host system 200 to generate constant voltages such as a gamma reference voltage, a gate high voltage, a gate low voltage, a pixel driving voltage, a cathode voltage, an initialization voltage, etc. The gamma reference voltage is supplied to data driver 110. The dynamic range of the data voltage output from data driver 110 is determined by the voltage range of the gamma reference voltage. The dynamic range of the data voltage is the voltage range between the highest grayscale voltage and the lowest grayscale voltage.

[0077] The gate high voltage and the gate low voltage are supplied to level shifter 150 and gate driver 120. Constant voltages such as the pixel driving voltage, the cathode voltage, and the initialization voltage are supplied to pixel 101 via power lines commonly connected to pixel 101.

[0078] The pixel driving voltage may be output from the main power supply of host system 200 and supplied to display panel 100. In this case, there is no need to output the pixel driving voltage from power supply 140.

[0079] The display panel driving circuit writes the pixel data of the input image to the pixels of display panel 100 under the control of timing controller 130. The display panel driving circuit includes data driver 110 and gate driver 120.

[0080] The display panel driving circuit may further include a touch sensor driver for driving a touch sensor. The touch sensor driver is omitted from Figure 1 Data driver 110 and the touch sensor driver may be integrated in one driver integrated circuit (IC). In a mobile terminal or a wearable terminal, timing controller 130, power supply 140, level shifter 150, data driver 110, the touch sensor driver, etc. may be integrated into one driver IC DIC, as shown in Figure 3 shown.

[0081] The data driver 110 receives pixel data of an input image received as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 outputs a data voltage by converting the pixel data of the input image into a gamma-compensated voltage using a digital-to-analog converter (DAC). The gamma reference voltage VGMA is divided into gamma-compensated voltages for each gray level by a voltage divider circuit of the data driver 110 and supplied to the DAC. The DAC generates a data voltage using the gamma-compensated voltage corresponding to the gray level value of the pixel data. The data voltage output from the DAC may be output to the data line 102 through an output buffer in each channel of the data driver 110, or may be output to the data line 102 via a demultiplexer array.

[0082] The gate driver 120 may be formed together with the TFT array and lines of the pixel array in a circuit layer CIR on the display panel 100. The gate driver 120 may be disposed in a non-display area BZ outside the display area AA of the display panel 100, or at least partially disposed in the display area AA.

[0083] The gate driver 120 may include a plurality of shift registers for sequentially shifting pulses of a gate signal. The gate driver 120 is disposed on the left non-display area BZ or the right non-display area BZ outside the display area AA in the display panel 100 to supply a gate signal to the gate line 103 by a single-feed method. In the single-feed method, the gate signal is applied from one side end of the gate line 103. The gate driver 120 may be disposed in each of the left non-display area BZ and the right non-display area BZ of the display panel 100, and may apply a gate signal to the gate line 103 by a double-feed method. In the double-feed method, the gate signal is applied simultaneously from both side ends of the gate line 103. At least some circuits of the gate driver 120 may be disposed in the display area AA.

[0084] The gate driver 120 sequentially outputs pulses of a gate signal to the gate line under the control of the timing controller 130. The gate driver 120 may sequentially supply a gate signal to the gate line 103 by shifting pulses of the gate signal using a shift register. The gate driver 120 may output a plurality of gate signals having different phases and pulse widths using a plurality of shift registers. The gate signal may be divided into a scan signal and a light emission control signal (hereinafter referred to as an "EM signal").

[0085] The timing controller 130 receives the digital video data of the input image and the timing signal synchronized with the digital video data from the host system 200. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, etc. Since the vertical period and the horizontal period can be obtained by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of one horizontal period 1H.

[0086] The timing controller 130 can generate a data timing control signal for controlling the operation timing of the data driver 110, a multiplexer (MUX) control signal for controlling the operation timing of the demultiplexer array, and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system 200. The timing controller 130 controls the operation timing of the display panel driving circuit so that the data driver 110, the demultiplexer array, the touch sensor driver, and the gate driver 120 are synchronized therewith.

[0087] The gate timing control signal generated by the timing controller 130 can be input to the shift register of the gate driver 120 through the level shifter 150. The level shifter 150 can receive the gate timing control signal and generate a start pulse and a shift clock and provide the start pulse and the shift clock to the gate driver 120 through the clock line CLK. The level shifter 150 can provide the MUX control signal to the demultiplexer array. The input signal of the level shifter 150 can be a digital voltage level signal, and the output signal of the level shifter 150 can be an analog voltage signal that swings between the gate high voltage VGH and the gate low voltage VGL.

[0088] The host system 200 may include the main board of any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a vehicle system, a mobile terminal, and a wearable terminal. The host system can scale the image signal from the video source to match the resolution of the display panel 100 and send the obtained image signal and timing signal to the timing controller 130.

[0089] In a mobile system, the host system 200 can be implemented as an application processor (AP). The host system 200 can send the pixel data of the input image to the driver IC DIC through the Mobile Industry Processor Interface (MIPI). As Figure 3As shown, the host system 200 can be connected to the driver IC DIC through a flexible printed circuit (e.g., flexible printed circuit (FPC)). The driver IC can be attached to the display panel 100 by a COG (chip on glass) process. The driver IC can be mounted on a flexible circuit film and electrically connected to the lines on the display panel 100.

[0090] Each sub-pixel includes a pixel circuit, and the pixel circuit includes a driving element for driving a light-emitting element and a capacitor connected to the driving element. The pixel circuit of each sub-pixel may include an internal compensation circuit to compensate for the data voltage according to the threshold voltage of the driving element.

[0091] Figure 4 is a circuit diagram illustrating a pixel circuit according to an exemplary embodiment of the present disclosure.

[0092] Referring to Figure 4 , the pixel circuit according to an embodiment includes a light-emitting element EL, a driving element DT configured to drive the light-emitting element EL, a plurality of switching elements T1 to T6, and capacitors C1 and C2. The driving element DT and the switching elements T1 to T6 can be implemented as transistors. The driving element DT and the switching elements T1 to T6 can all be p-channel transistors, but the present disclosure is not necessarily limited thereto.

[0093] The driving element DT generates a current for driving the light-emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate electrode G connected to the first node n1, a first electrode S connected to the second node n2, and a second electrode D connected to the third node n3. The pixel driving voltage ELVDD is applied to the second node n2 and can also be referred to as a high-potential power supply voltage.

[0094] The light-emitting element EL can be implemented as an organic light-emitting diode (OLED) or an inorganic LED. The OLED includes an anode, a cathode, and an organic compound layer interposed therebetween. In the light-emitting element EL, the anode is electrically connected to the fifth node n5, and the cathode voltage ELVSS is applied to the cathode and can also be referred to as a low-potential power supply voltage or a ground voltage.

[0095] The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, a light-emitting layer EML, an electron transport layer ETL, and an electron injection layer EIL, but the present disclosure is not limited thereto. When a voltage is applied to the anode and cathode of the light-emitting element EL, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the light-emitting layer EML to create excitons. At this time, visible light is emitted from the light-emitting layer EML. The OLED can be implemented as an OLED having a cascade structure in which a plurality of light-emitting layers are stacked. The OLED with a cascade structure can improve the brightness and lifespan of the pixel.

[0096] The first switching element T1 may have a first electrode connected to the first node n1 and a second electrode connected to the third node n3. The gate electrode of the first switching element T1 may be connected to the third gate line GL3 through which the third scan signal Scan3 is applied. One side (e.g., the first electrode) of the first switching element T1 may be connected to the gate electrode of the driving element DT, while the other side (e.g., the second electrode) of the first switching element T1 may be connected to the second electrode of the driving element DT and the sixth switching element T6.

[0097] The first switching element T1 may be turned on or off in response to the third scan signal Scan3 applied through the third gate line GL3, and may connect the first node n1 to the third node n3 when turned on.

[0098] The second switching element T2 may have a first electrode connected to the fourth node n4 and a second electrode connected to the reference voltage supply line PL4. The gate electrode of the second switching element T2 is connected to the second gate line GL2 through which the second scan signal Scan2 is provided.

[0099] The second switching element T2 may be turned on or off in response to the second scan signal Scan2 provided through the second gate line GL2, and may supply the reference voltage Vref to the fourth node n4 when turned on.

[0100] The third switching element T3 may have a first electrode connected to the first node n1 and a second electrode connected to the initialization voltage supply line PL3. The gate electrode of the third switching element T3 is connected to the first gate line GL1 through which the first scan signal Scan1 is provided.

[0101] The third switching element T3 may be turned on or off in response to the first scan signal Scan1 provided through the first gate line GL1, and may supply the initialization voltage Vinit to the first node n1 when turned on.

[0102] The fourth switching element T4 may have a first electrode connected to the data voltage supply line PL5 and a second electrode connected to the fourth node n4. The gate electrode of the fourth switching element T4 is connected to the fourth gate line GL4 through which the fourth scan signal Scan4 is provided.

[0103] The fourth switching element T4 may be turned on or off in response to the fourth scan signal Scan4 provided through the fourth gate line GL4, and may supply the data voltage Vdata to the fourth node n4 when turned on.

[0104] The fifth switching element T5 may have a first electrode connected to the initialization voltage supply line PL3 and a second electrode connected to the fifth node n5. The gate electrode of the fifth switching element T5 is connected to the first gate line GL1 through which the first scan signal Scan1 is provided.

[0105] The fifth switching element T5 may be turned on or off in response to the first scan signal Scan1 provided through the first gate line GL1, and may supply the initialization voltage Vinit to the anode of the light-emitting element EL when turned on.

[0106] The sixth switching element T6 may have a first electrode connected to the third node n3 and a second electrode connected to the fifth node n5. The gate electrode of the sixth switching element T6 is connected to the fifth gate line GL5. The sixth switching element T6 may be turned on or off in response to the signal EM(n) applied through the fifth gate line GL5, and may connect the third node n3 to the fifth node n5 when turned on.

[0107] The first capacitor C1 and the second capacitor C2 may keep the gate-source voltage Vgs of the driving element DT constant within one frame. The first capacitor C1 may store the threshold voltage Vth of the driving element DT, and the second capacitor C2 may store the data voltage Vdata.

[0108] The first terminal of the first capacitor C1 may be connected to the first node n1, and its second terminal may be connected to the fourth node n4. The first terminal of the first capacitor C1 may be connected to the gate electrode of the driving element DT, the first electrode of the first switching element T1, and the first electrode of the third switching element T3.

[0109] The first terminal of the second capacitor C2 may be connected to the fourth node n4, and its second terminal may be connected to the second node n2. The fourth node n4 may be provided between the first capacitor C1 and the second capacitor C2 and connected to the second switching element T2 and the fourth switching element T4. The other side (e.g., its second terminal) of the second capacitor C2 may be connected to the driving voltage supply line PL1.

[0110] The first capacitor C1 and the second capacitor C2 may be configured as parasitic capacitors of an internal capacitor, but are not limited thereto, and may be external capacitors intentionally designed outside the driving element DT.

[0111] Figures 5A to 9B It is a diagram illustrating the operation of the pixel circuit.

[0112] The refresh frame may include an initialization period INI, a sampling period SAM, a programming period PRO, and an emission period EMI. The initialization period INI is a period during which a capacitor and a gate electrode of a driving element DT are initialized. The sampling period SAM is a period during which a threshold voltage of the driving element DT is sensed. The programming period PRO is a period during which a data voltage Vdata is stored. And the emission period EMI is a period during which a light-emitting element EL is turned on.

[0113] Referring to Figure 5A and Figure 5B , in the initialization period INI, a first scan signal Scan1 and a second scan signal Scan2 respectively output from a first gate line GL1 and a second gate line GL2 may have a gate-on voltage VGL or VEL, and scan signals respectively output from a third gate line GL3, a fourth gate line GL4, and a fifth gate line GL5 may have a gate-off voltage VGH or VEH. Since the driving element DT and the plurality of switching elements T1 to T6 according to an embodiment are p-channel transistors, they may be turned off when a high gate voltage is applied and turned on when a low gate voltage is applied.

[0114] Specifically, the third switching element T3 may be turned on by the gate-on voltage VGL or VEL output from the first gate line GL1 to apply an initialization voltage Vinit to a first node n1. Accordingly, the initialization voltage Vinit may be applied to one end of a first capacitor C1 connected to the first node n1 and a gate electrode G of the driving element DT.

[0115] The initialization voltage Vinit may be a sufficiently low voltage to saturate the driving element DT. Accordingly, when the initialization voltage Vinit is applied to the gate electrode G of the driving element DT, the driving element DT may be turned on in advance before the sampling period, which allows a source-drain channel to be formed. Accordingly, a pixel driving voltage ELVDD may be applied to a third node n3. Accordingly, when sampling starts, the voltage applied to the third node n3 is quickly applied to the gate electrode of the driving element DT, which allows the threshold voltage to be quickly sampled.

[0116] In the initialization period INI, a fifth switching element T5 connected to the first gate line GL1 is turned on so that the initialization voltage Vinit may be applied to a fifth node n5. The initialization voltage Vinit may be set to a sufficiently low voltage such that the light-emitting element EL does not emit light during the initialization period INI.

[0117] As an example, when the pixel driving voltage ELVDD is set to 4.6V and the cathode voltage ELVSS is set to -6.0V, the initialization voltage Vinit can be set to -3.5V to fully saturate the driving element DT during initialization. However, this is exemplary and can be appropriately adjusted according to the characteristics of each element and the pixel circuit.

[0118] According to an embodiment, when the initialization voltage Vinit is applied to the first node n1, the initialization voltage Vinit does not short-circuit with the pixel driving voltage ELVDD applied to the second electrode D of the driving element DT. Therefore, the gate-source voltage Vgs of the driving element just becomes Vinit - ELVDD, making the conduction bias voltage larger, which can improve the on-bias stress (OBS) effect. OBS is an abbreviation for "on-bias stress", which refers to the operation of applying stress to a transistor to prevent or reduce the threshold voltage fluctuation of the transistor.

[0119] Due to the time required to change the hysteresis characteristic of the driving element DT when the gray value of the pixel data changes significantly, the response time can increase during the first frame period of starting to reproduce the input image. As a result, the first frame response (FFR) may deteriorate. However, according to an embodiment, the hysteresis of the driving element DT is reduced by the high OBS voltage during the initialization period INI, which can improve the FFR.

[0120] Since the gate conduction voltage is applied to the second gate line GL2, the second switching element T2 can be driven, and the reference voltage Vref can be applied to the fourth node n4. Therefore, the first capacitor C1 can be initialized to Vinit - Vref, and the second capacitor C2 can be initialized to Vref - ELVDD.

[0121] During the light emission period EMI, the driving element DT needs to be in a saturated state to apply current to the light emitting element EL. To saturate the driving element DT, the source-gate voltage Vsg needs to be greater than the threshold voltage Vth. For example, the reference voltage Vref needs to be greater than the data voltage Vdata (see Equation 1 below). When the reference voltage Vref and the initialization voltage Vinit use negative polarity voltages together, the driving element DT may not become saturated.

[0122] The reference voltage Vref can be set to a predetermined voltage level to perform the function of fixing the fourth node n4 from being affected by the previous data voltage during the initialization period, and to perform the function of keeping the voltage of the fourth node n4 constant regardless of how the gate voltage of the driving element DT changes due to diode connection during the sampling period. The initialization voltage Vinit can be set low so that the driving element is fully saturated during initialization. Therefore, the reference voltage Vref and the initialization voltage Vinit have different functions and can thus have different voltage levels.

[0123] As an example, the reference voltage Vref can be set to 2V or higher so that the data voltage Vdata can vary from 0V (white) to 2V (black). However, the range of each voltage does not have to be limited to this, and various modifications can be made. The reference voltage Vref can be appropriately set within a range greater than the initialization voltage Vinit and the data voltage Vdata and less than the pixel driving voltage ELVDD.

[0124] Referring to Figure 6A and Figure 6B and, during the sampling period SAM, the gate cutoff voltage VGH or VEH can be applied to the first gate line GL1, the fourth gate line GL4, and the fifth gate line GL5, and the gate conduction voltage VGL or VEL can be applied to the second gate line GL2 and the third gate line GL3.

[0125] Therefore, when the first switching element T1 is turned on by the gate conduction voltage VGL or VEL applied to the third gate line GL3, the voltage charged into the third node n3 is charged into the first node n1.

[0126] Due to the gate conduction voltage VGL or VEL applied to the second gate line GL2, even during the sampling period, the second switching element T2 can be turned on to apply the reference voltage Vref to the fourth node n4. Therefore, even when the voltage of the gate electrode of the driving element DT changes from the initialization voltage Vinit to ELVDD - Vth during the transition from the initialization period INI to the sampling period SAM, the voltage of the fourth node n4 can be kept constant.

[0127] During the sampling period SAM, ELVDD - |Vth| can be applied to the first node n1 connected to one end of the first capacitor C1, and the reference voltage Vref can be applied to the fourth node n4 connected to the other end of the first capacitor C1. Therefore, the voltage charged into the first capacitor C1 can be the difference between ELVDD - Vth and Vref. For example, the voltage charged into the first capacitor C1 can be Vref - (ELVDD - Vth).

[0128] A reference voltage Vref may be applied to a fourth node n4 connected to one end of a second capacitor C2, and a pixel driving voltage ELVDD may be applied to the other end of the second capacitor C2. The voltage charged into the second capacitor C2 may be the difference between ELVDD and Vref. For example, the voltage charged into the second capacitor C2 may be ELVDD - Vref. Thus, when the voltages stored in the first capacitor C1 and the second capacitor C2 are added together, the pixel driving voltage ELVDD and the reference voltage Vref may cancel out, leaving only the threshold voltage Vth. During a sampling period SAM, the threshold voltage Vth of a driving element DT may be stored in the first capacitor C1.

[0129] According to an embodiment, since sampling is performed using the reference voltage Vref instead of the data voltage Vdata, the sampling period SAM may be set to be longer than or shorter than one horizontal period 1H. Thus, advantageously, even during high-speed driving, it is possible to accurately sense the threshold voltage by ensuring sufficient sampling time without being limited by one horizontal period. Referring to Figure 7 , by controlling a second scan signal Scan2 and a third scan signal Scan3, the sampling time may be set to be longer than one horizontal period 1H.

[0130] Furthermore, since the pixel driving voltage ELVDD is used to sense the threshold voltage, the voltage of the gate electrode is quickly charged by the driving element DT that has been saturated during an initialization period INI, enabling the sampling time to be faster. Thus, fast sampling is feasible, which would be advantageous for high-speed driving. In this case, the sampling time may be set to be shorter than one horizontal period.

[0131] Referring to Figure 8A and Figure 8B , during a programming period PRO, a gate cut-off voltage VGH or VEH may be applied to a first gate line GL1 to a third gate line GL3 and a fifth gate line GL5, and a gate on-voltage VGL or VEL may be applied to a fourth gate line GL4. Thus, only a fourth switching element T4 to which a fourth scan signal Scan4 is applied conducts to apply a data voltage Vdata to the fourth node n4.

[0132] At this time, a first switching element T1 is cut off, so a first node n1 is floated, such that the voltage of the first node n1 may become Vdata - Vref + ELVDD - Vth due to capacitor coupling.

[0133] The first capacitor C1 can be charged with a voltage corresponding to the difference between Vdata - Vref + ELVDD - Vth and Vdata. For example, the voltage charged into the first capacitor C1 can be Vdata - (Vdata - Vref + ELVDD - Vth).

[0134] The second capacitor C2 can be charged with a voltage corresponding to the difference between Vdata and ELVDD. For example, the voltage charged into the second capacitor C2 can be ELVDD - Vdata. Therefore, when the voltages stored in the first capacitor C1 and the second capacitor C2 are added together, the pixel driving voltage ELVDD can be canceled out, leaving Vref - Vdata + Vth. The data voltage Vdata can be charged into the second capacitor C2 during the programming period PRO. The voltages stored in the first capacitor C1 and the second capacitor C2 can be the source-gate voltage Vsg.

[0135] At this time, the first capacitor C1 and the second capacitor C2 are connected in parallel so that the data voltage Vdata is not distributed. Therefore, the data voltage Vdata can be applied across each of the first capacitor C1 and the second capacitor C2. When the first capacitor C1 and the second capacitor C2 are connected in series and the data voltage is distributed, a wider data voltage range is required, and the ratio of the distributed voltages can be affected by the capacitor sizes that are difficult to accurately control.

[0136] Referring to Figure 9A and Figure 9B , during the light emitting period EMI, the gate cut-off voltage VGH or VEH can be applied to all of the first gate lines GL1 to the fourth gate lines GL4, and the gate on-voltage VGL or VEL can be applied only to the fifth gate line GL5. Therefore, all the switching elements except the sixth switching element T6 can be turned off.

[0137] At this time, the current IOLED flowing through the light emitting element EL, the source-gate voltage Vsg of the driving element, and the threshold voltage Vth of the driving element can satisfy Equation 1 below.

[0138]

Equation 1

[0139] I OLED = k(Vsg - |Vth|) 2

[0140] = k{ELVDD - (Vdata - Vref + ELVDD - |Vth|) - |Vth|} 2

[0141] = k(Vref - Vdata) 2

[0142] Therefore, the current flowing into the light-emitting element EL is determined by the difference between the reference voltage Vref and the data voltage Vdata, and is not affected by the threshold voltage of the driving element DT, such that the driving elements DT of each pixel can have uniform characteristics. In addition, the influence on the pixel driving voltage ELVDD can be eliminated, which can also reduce the influence on the IR drop.

[0143] In addition, even when the pixel driving voltage ELVDD changes during the light-emitting period EMI, the gate voltage of the driving element DT can change in accordance with α. Therefore, as the pixel driving voltage ELVDD changes in accordance with α, the gate voltage of the driving element DT can also change in accordance with α.

[0144] Substituting this into the above formula 1, it can be seen that formula 1 becomes k{(ELVDD + α) - (Vdata - Vref + ELVDD - |Vth| + α) - |Vth|} 2 , from which it is confirmed that the formula is k(Vref - Vdata) 2 . Therefore, it is possible to prevent or reduce the brightness change caused by the current - resistance (IR) drop (voltage drop) of the pixel driving voltage ELVDD.

[0145] It should be noted that although Figures 4 to 9B shows the specific structure and detailed operation of the pixel circuit, the present disclosure is not limited thereto. For example, more or fewer transistors or capacitors may be included in the pixel circuit of the present disclosure, and the selection communication function can be changed in various ways by those skilled in the art as needed.

[0146] Figure 10 is a diagram schematically illustrating a pixel circuit according to an exemplary embodiment of the present disclosure.

[0147] Referring to Figure 10 , the pixel circuit according to the exemplary embodiment may include a light-emitting element EL, a driving element DT configured to drive the light-emitting element EL, a plurality of switching elements T1 to T4, and capacitors C1 and C2.

[0148] In the initialization period, the second switching element T2 and the third switching element T3 are turned on, such that the reference voltage Vref and the initialization voltage Vinit are respectively applied to both ends of the first capacitor C1. At this time, the initialization voltage Vinit may be applied to the gate electrode of the driving element DT to saturate the driving element DT.

[0149] Thereafter, in the sampling period, the reference voltage Vref is applied to the fourth node n4, and the first switching element T1 is turned on, such that the voltage of the first node n1 becomes ELVDD - Vth. Therefore, the threshold voltage Vth of the driving element DT can be stored in the first capacitor C1.

[0150] Thereafter, during the programming period, when the fourth switching element T4 is turned on and the data voltage Vdata is applied to the first node n1, due to capacitor coupling, the voltage of the fourth node n4 becomes Vdata - Vref + ELVDD - |Vth|. At this time, the data voltage Vdata can be stored in the second capacitor C2.

[0151] Therefore, during the light emission period, current can flow to the light emitting element EL in proportion to Vref - Vdata, without being affected by the threshold voltage of the driving element.

[0152] According to the embodiment, different voltages, namely the reference voltage Vref and the initialization voltage Vinit, are used to initialize the capacitor. The initialization voltage Vinit is advantageously set low to enable the driving element to saturate quickly and increase the OBS effect. The reference voltage Vref needs to be greater than the data voltage Vdata to satisfy the condition for saturating the driving element. For example, in order to saturate the driving element, the source-gate voltage Vsg needs to be greater than the threshold voltage Vth, such that according to Equation 1, the reference voltage Vref needs to be greater than the data voltage Vdata.

[0153] Figure 11 is a diagram illustrating an example of a pixel circuit that performs sampling using a data voltage. Figure 12 is Figure 11 a waveform diagram of the circuit of.

[0154] Referring to Figure 11 and Figure 12 In the 6T1C (6 thin film transistors, 1 capacitor) pixel circuit, during the initialization period INI, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 can be turned on by applying the gate conduction voltage VGL or VEL thereto.

[0155] The reference voltage Vref can be applied to each of the nodes A and B at both ends of the capacitor Cst. Therefore, the capacitor Cst can be initialized by applying the same reference voltage Vref to its both ends. At this time, the reference voltage Vref can be applied to the node B through the third transistor M3, the fourth transistor M4, and the first transistor M1.

[0156] When the reference voltage Vref is an initialization voltage that is low enough, the driving element DT can saturate and the source-drain channel can be opened. Therefore, there is a problem that the reference voltage Vref and the pixel driving voltage ELVDD are short-circuited at the node C, which causes continuous damage to the pixel circuit. However, according to the embodiment, the initialization voltage does not pass through the node connected to the drain electrode of the driving element, so that a short circuit between the initialization voltage and the pixel driving voltage can be prevented or reduced.

[0157] In addition, in the 6T1C pixel circuit, during the sampling period SAM, the fifth transistor M5 is turned on, and the data voltage Vdata is applied to node A. In addition, the first transistor M1 may be turned on, and the voltage at node B may become ELVDD - Vth.

[0158] At this time, since the input and sampling of the data voltage Vdata are driven simultaneously, the sampling period SAM is limited to a horizontal period 1H during which the data voltage Vdata is applied. Therefore, during high-speed driving, a horizontal period becomes shorter, making it impossible to ensure sufficient sampling time. As a result, it is difficult to accurately sense the threshold voltage.

[0159] However, according to the embodiment, since sampling is performed using the reference voltage Vref instead of the data voltage Vdata, there is an advantage that sufficient sampling time can be ensured without being limited to a horizontal period.

[0160] Figure 13 is a schematic diagram illustrating a pixel circuit according to another embodiment of the present disclosure. Figure 14 is a waveform diagram of the pixel circuit.

[0161] The pixel circuit according to the embodiment includes a light-emitting element EL, a driving element DT configured to drive the light-emitting element EL, a plurality of switching elements, and a capacitor. The driving element DT and the switching elements may be implemented as transistors. The driving element DT and the switching elements may all be p-channel transistors, but the present disclosure is not necessarily limited thereto.

[0162] The driving element DT generates a current for driving the light-emitting element EL based on the gate-source voltage. The driving element DT includes a gate electrode connected to the first node n1, a first electrode connected to the second node n2, and a second electrode connected to the third node n3. The pixel driving voltage ELVDD is applied to the second node n2.

[0163] According to the embodiment, the first scan signal Scan1(N + 1) of the (N + 1)-th row may be applied to the third gate line GL3, and the first scan signal Scan1(N + 2) of the (N + 2)-th row may be applied to the fourth gate line GL4. With this configuration, the number of sub-stages for outputting the scan signal to one pixel can be reduced, thereby reducing the size of the gate driver.

[0164] In this case, when the width of the first scan signal Scan1(N + 1) of the (N + 1)-th row is changed to ensure sufficient sampling time on the N-th row, the initialization period INI of the (N + 1)-th pixel may also be changed to the same period. For example, the initial time and the sampling time may be equivalently adjusted to be longer or shorter than a horizontal period.

[0165] The first switching element T1 may have a first electrode connected to the first node n1 and a second electrode connected to the third node n3. The gate electrode of the first switching element T1 may be connected to the third gate line GL3, and the first scan signal Scan1(N + 1) of the (N + 1)-th row is applied through the third gate line GL3. One side of the first switching element T1 may be connected to the gate electrode of the driving element DT, and the other side of the first switching element T1 may be connected to the second electrode of the driving element DT and the sixth switching element T6.

[0166] The first switching element T1 may be turned on or off in response to the first scan signal Scan1(N + 1) of the (N + 1)-th row applied through the third gate line GL3, and when turned on, may connect the first node n1 to the third node n3.

[0167] The second switching element T2 may have a first electrode connected to the fourth node n4 and a second electrode connected to the reference voltage supply line PL4. The gate electrode of the second switching element T2 is connected to the second gate line GL2, and the second scan signal Scan2(N) is provided through the second gate line GL2.

[0168] The second switching element T2 may be turned on or off in response to the second scan signal Scan2(N) provided through the second gate line GL2, and when turned on, may supply the reference voltage Vref to the fourth node n4.

[0169] The third switching element T3 may have a first electrode connected to the first node n1 and a second electrode connected to the initialization voltage supply line PL3. The gate electrode of the third switching element T3 is connected to the first gate line GL1, and the first scan signal Scan1(N) is provided through the first gate line GL1.

[0170] The third switching element T3 may be turned on or off in response to the first scan signal Scan1(N) provided through the first gate line GL1, and when turned on, may supply the initialization voltage Vinit to the first node n1.

[0171] The fourth switching element T4 may have a first electrode connected to the data voltage supply line PL5 and a second electrode connected to the fourth node n4. The gate electrode of the fourth switching element T4 is connected to the fourth gate line GL4, and the first scan signal Scan1(N + 2) of the (N + 2)-th row is provided through the fourth gate line GL4.

[0172] The fourth switching element T4 may be turned on or off in response to the first scan signal Scan1(N + 2) of the (N + 2)-th row provided through the fourth gate line GL4, and when turned on, may supply the data voltage Vdata to the fourth node n4.

[0173] The fifth switching element T5 may have a first electrode connected to the initialization voltage supply line PL3 and a second electrode connected to the fifth node n5. The gate electrode of the fifth switching element T5 is connected to the first gate line GL1, and a first scan signal Scan1(N) is provided through the first gate line GL1.

[0174] The fifth switching element T5 may be turned on or off in response to the first scan signal Scan1(N) provided through the first gate line GL1, and may supply the initialization voltage Vinit to the anode of the light-emitting element EL when turned on.

[0175] The sixth switching element T6 may have a first electrode connected to the third node n3 and a second electrode connected to the fifth node n5. The gate electrode of the sixth switching element T6 is connected to the fifth gate line GL5. The sixth switching element T6 may be turned on or off in response to a signal applied through the fifth gate line GL5, and may connect the third node n3 to the fifth node n5 when turned on.

[0176] The first capacitor C1 and the second capacitor C2 may keep the gate-source voltage Vgs of the driving element DT constant within one frame. The first capacitor C1 may store the threshold voltage Vth of the driving element DT, and the second capacitor C2 may store the data voltage Vdata.

[0177] The first terminal of the first capacitor C1 may be connected to the first node n1, and its second terminal may be connected to the fourth node n4. The first terminal of the first capacitor C1 may be connected to the gate electrode of the driving element DT, the first electrode of the first switching element T1, and the first electrode of the third switching element T3.

[0178] The first terminal of the second capacitor C2 may be connected to the fourth node n4, and its second terminal may be connected to the second node n2. The fourth node n4 may be provided between the first capacitor C1 and the second capacitor C2 and connected to the second switching element T2 and the fourth switching element T4. The other side of the second capacitor C2 may be connected to the driving voltage supply line PL1.

[0179] Since the content of the present disclosure described in the problem to be solved, the means for solving the problem, and the effects is not an essential feature of the specified claims, the scope of the claims is not limited to the matters described in the present disclosure.

[0180] According to the embodiment, it is possible to ensure that the sampling time is longer than one horizontal period, so that accurate sampling can be performed even during high-speed driving. Therefore, there is an advantage that uniform driving characteristics between pixels are achieved even during high-speed driving.

[0181] In addition, by ensuring that the pixel driving voltage and the initialization voltage do not short-circuit during initialization, damage to the pixel circuit can be minimized or reduced, and low-power control can be achieved.

[0182] The effects of the present disclosure will not be limited to the above effects, and those skilled in the art will clearly understand other unmentioned effects from the following claims.

[0183] Although the embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the present disclosure is not necessarily limited to these embodiments, and various modifications and variations can be made without departing from the technical spirit of the present disclosure. Therefore, the embodiments disclosed herein should be regarded as descriptive rather than limiting the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. Therefore, the above embodiments should be understood as exemplary and not restrictive in any way. The scope of the present disclosure should be interpreted by the appended claims, and all technical spirits within the scope of their equivalents should be interpreted as being included within the scope of the present disclosure.

[0184] Cross-reference to related applications

[0185] This application claims the priority and benefits of Korean Patent Application No. 10-2023-0196275, filed in Korea on December 29, 2023, the entire disclosure of which is incorporated herein by reference for all purposes.

Claims

1. A pixel circuit, comprising: a driving element including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a light emitting element connected to the second electrode of the driving element; a first capacitor connected to the first node and a fourth node; a second capacitor connected to the fourth node and the second node; a first switching element connected to the first node and the third node; a second switching element connected to the fourth node and a reference voltage supply line; as well as A third switching element is connected to the first node and an initialization voltage supply line.

2. The pixel circuit according to claim 1, wherein: The reference voltage applied from the reference voltage supply line is greater than the initialization voltage applied from the initialization voltage supply line.

3. The pixel circuit according to claim 2, wherein: The first capacitor is initialized by respectively applying the reference voltage and the initialization voltage to both ends of the first capacitor, and wherein the second capacitor is initialized by respectively applying the reference voltage and the pixel driving voltage to both ends of the second capacitor.

4. The pixel circuit according to claim 2, further comprising: a fourth switching element connected to the fourth node and a data voltage supply line; a fifth switching element, the fifth switching element being configured to connect the initialization voltage supply line and the anode of the light emitting element; as well as A first gate line is connected to a gate electrode of the third switching element and a gate electrode of the fifth switching element.

5. The pixel circuit according to claim 4, further comprising: the first gate line applying a first gate voltage to a gate electrode of the third switching element; a second gate line applying a second gate voltage to a gate electrode of the second switching element; a third gate line for applying a third gate voltage to a gate electrode of the first switching element; as well as A fourth gate line that applies a fourth gate voltage to a gate electrode of the fourth switching element.

6. The pixel circuit according to claim 4, wherein: The pixel circuit is driven in an initialization period, a sampling period, a programming period and a light emitting period, wherein, during the initialization period, the second switch element, the third switch element and the drive element are turned on, and the first switch element and the fourth switch element are turned off, wherein, during the sampling period, the first switching element and the second switching element are turned on, so that the level of the fourth node is fixed to the reference voltage, and the level of the first node is changed from the initialization voltage to the difference between the pixel driving voltage and the threshold voltage of the driving element, wherein, during the programming period, the fourth switch element is turned on, and the first to third switch elements are turned off, so that the level of the first node is changed to the difference between the pixel driving voltage and the threshold voltage of the driving element, and During the light emitting period, the current flowing through the driving element is independent of the pixel driving voltage or the threshold voltage of the driving element.

7. The pixel circuit according to claim 4, wherein: The reference voltage is greater than a data voltage applied from the data voltage supply line, and The driving element and the first to fourth switching elements are all p-channel transistors.

8. A display device, comprising: Data driving circuit; Strobe drive circuit; as well as A pixel circuit according to any one of claims 1 to 7.

9. The display device according to claim 8, in, The pixel circuit is driven in an initialization period, a sampling period, a programming period and a light emitting period, In the initialization period, the first capacitor is initialized by respectively applying a reference voltage from the reference voltage supply line and an initialization voltage from the initialization voltage supply line to both ends of the first capacitor, In the sampling period, the threshold voltage of the driving element is sampled using the reference voltage and the pixel driving voltage, In the programming period, a data voltage is applied to the pixel circuit to store the data voltage in the second capacitor.

10. The display device according to claim 9, wherein: The sampling period is longer or shorter than a horizontal period, and The initialization period and the sampling period have the same time length.

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