Display panel and display device including the same

Abstract

The embodiment of the invention relates to a display panel and a display device including the same. The display panel includes: a mode selection circuit configured to output a light emitting signal to a first node in response to a first mode selection signal and to output the light emitting signal to a second node in response to a second mode selection signal; a pixel circuit; and a first light emitting element and a second light emitting element, where the first light emitting element is configured to be driven by the pixel circuit in a first mode according to a voltage of a first node, and the second light emitting element is configured to be driven by the pixel circuit in a second mode according to a voltage of a second node.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority and the benefit of Korean Patent Application No. 10 - 2023 - 0193983, filed on December 28, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a display panel having a variable viewing angle based on pixels and a display device including the display panel. Background Art

[0004] Variable viewing angle technology can be applied to display devices. The variable viewing angle technology can display video content or visual information reproduced on the display device only to users within a relatively narrow viewing angle range, or display video content or visual information reproduced on the display device to multiple users existing within a relatively wide viewing angle range.

[0005] As the future vehicle market such as electric trains and autonomous vehicles expands, the demand for vehicle display devices has increased rapidly. Research is being conducted on a method of dividing the screen of a vehicle display device and controlling a part of the screen with a narrow viewing angle and another part of the screen with a wide viewing angle. This technology can display personal content or information that can only be viewed by specific users by driving pixels with a narrow viewing angle arranged in a partial area of the screen; meanwhile, by driving pixels with a wide viewing angle arranged in other areas of the screen, shared content that can be seen by multiple users can be displayed.

[0006] The display panel of an organic light - emitting display device has drawn attention in vehicle display devices. The organic light - emitting display device includes an organic light - emitting diode that emits light by itself (hereinafter, referred to as "OLED"), and has the advantages of a fast response speed, high luminous efficiency, high brightness, and a wide viewing angle. The organic light - emitting display device has a fast response speed, excellent luminous efficiency, brightness, viewing angle, etc., and has excellent contrast and color reproduction rate because it can represent black gray levels in full black. Since the display panel of the organic light - emitting display device can be flexibly bent, it is easy to implement a curved surface. Due to these advantages, the market share of organic light - emitting display devices in the vehicle display device market has increased rapidly.

[0007] To implement variable viewing angle technology, wires, circuit elements, optical elements, etc. can be added to transmit signals for selecting a viewing angle for pixels in the display panel. Adding a large number of wires and circuit elements to the display panel not only makes the design of the display panel more difficult but also increases the cost of the display device. Summary of the Invention

[0008] The present invention is made to address the above-mentioned needs and / or drawbacks.

[0009] The present invention provides a display panel capable of changing the viewing angle of pixels and having a simplified circuit configuration of a pixel circuit, and a display device including the display panel.

[0010] The problems or limitations to be addressed or solved by the present invention are not limited to those mentioned above, and other problems or limitations not mentioned will be clearly understood by those of ordinary skill in the art from the following description.

[0011] A display panel according to an embodiment of the present invention includes: a mode selection circuit configured to output a light emission signal to a first node in response to a first mode selection signal and output the light emission signal to a second node in response to a second mode selection signal; a pixel circuit; and a first light emitting element and a second light emitting element, wherein the first light emitting element is configured to be driven by the pixel circuit according to a voltage of the first node in a first mode, and the second light emitting element is configured to be driven by the pixel circuit according to a voltage of the second node in a second mode.

[0012] The pixel circuit may include: a driving element including a first electrode to which a pixel driving voltage is applied, a gate to which a data voltage of pixel data is applied, and a second electrode connected to a third node; a first switching element including a first electrode connected to the third node, a gate electrically connected to the first node, and a second electrode electrically connected to an anode of the first light emitting element; and a second switching element including a first electrode connected to the third node, a gate electrically connected to the second node, and a second electrode connected to an anode of the second light emitting element.

[0013] The light-emitting signal may swing between a gate-on voltage and a gate-off voltage. Each of the first switching element and the second switching element may conduct in response to the gate-on voltage and cut off in response to the gate-off voltage. The mode selection circuit may include: a first mode switching element including a first electrode to which the light-emitting signal is applied, a gate to which the first mode selection signal is applied, and a second electrode electrically connected to the first node; a second mode switching element including a first electrode to which a separate gate-off voltage is applied, a gate to which the second mode selection signal is applied, and a second electrode electrically connected to the first node; a third mode switching element including a first electrode to which the light-emitting signal is applied, a gate to which the second mode selection signal is applied, and a second electrode electrically connected to the second node; and a fourth mode switching element including a first electrode to which the separate gate-off voltage is applied, a gate to which the first mode selection signal is applied, and a second electrode electrically connected to the second node.

[0014] The pixel circuit may further include: a capacitor connected between a fourth node and a fifth node; a third switching element including a first electrode to which the data voltage is applied, a gate to which a first scan signal is applied, and a second electrode electrically connected to the fifth node; a fourth switching element including a first electrode electrically connected to the third node, a gate to which a second scan signal is applied, and a second electrode connected to the fourth node; a fifth switching element including a first electrode electrically connected to a sixth node to which a reference voltage is applied, a gate to which the second scan signal is applied, and a second electrode connected to a seventh node; a sixth switching element including a first electrode connected to the sixth node, a gate to which the second scan signal is applied, and a second electrode electrically connected to an eighth node; and a seventh switching element including a first electrode connected to the fifth node, a gate to which the light-emitting signal is applied, and a second electrode connected to the sixth node. The gate of the driving element may be electrically connected to the fourth node. The first light-emitting element may include an anode connected to the seventh node and a cathode to which a cathode voltage is applied. The second light-emitting element may include an anode connected to the eighth node and a cathode to which the cathode voltage is applied.

[0015] The light-emitting signal may swing between a gate-on voltage and a gate-off voltage. Each of the first switching element, the second switching element, the third switching element, the fourth switching element, the fifth switching element, the sixth switching element, and the seventh switching element may conduct in response to the gate-on voltage and cut off in response to the gate-off voltage. The voltage of the first scan signal in each of the first mode and the second mode may be the gate-off voltage during a first period, may be the gate-on voltage during a second period after the first period, and may be the gate-off voltage during a third period after the second period. The voltage of the second scan signal in each of the first mode and the second mode may be the gate-on voltage during the first period and the second period, and may be the gate-off voltage during the third period. The voltage of the light-emitting signal in each of the first mode and the second mode may be the gate-on voltage during the first period, may be the gate-off voltage during the second period, and may be the gate-on voltage during the third period. The voltage of the first mode selection signal may be the gate-on voltage in the first period, the second period, and the third period of the first mode, and may be the gate-off voltage in the first period, the second period, and the third period of the second mode. The voltage of the second mode selection signal may be the gate-on voltage in the first period, the second period, and the third period of the second mode, and may be the gate-off voltage in the first period, the second period, and the third period of the first mode. In the first mode, the voltage of the first mode signal applied to the first node may be the voltage of the light-emitting signal, and the voltage of the second mode signal applied to the second node may be the gate-off voltage. In the second mode, the voltage of the first mode signal applied to the first node may be the gate-off voltage, and the voltage of the second mode signal applied to the second node may be the voltage of the light-emitting signal.

[0016] The pixel circuit may further include: a capacitor connected between a fourth node and a fifth node; a third switching element including a first electrode to which the data voltage is applied, a gate to which a first scan signal is applied, and a second electrode electrically connected to the fifth node; a fourth switching element including a first electrode electrically connected to the third node, a gate to which a second scan signal is applied, and a second electrode connected to the fourth node; a fifth switching element including a first electrode electrically connected to a sixth node to which a reference voltage is applied, a gate to which the second scan signal is applied, and a second electrode connected to a seventh node; a sixth switching element including a first electrode connected to the sixth node, a gate to which the second scan signal is applied, and a second electrode electrically connected to an eighth node; a 7-1 switching element including a first electrode connected to the fifth node, a gate connected to the first node, and a second electrode connected to the sixth node; and a 7-2 switching element including a first electrode connected to the fifth node, a gate connected to the second node, and a second electrode connected to the sixth node. The gate of the driving element may be electrically connected to the fourth node. The first light-emitting element may include an anode connected to the seventh node and a cathode to which a cathode voltage is applied. The second light-emitting element may include an anode connected to the eighth node and a cathode to which the cathode voltage is applied.

[0017] The light-emitting signal may swing between a gate-on voltage and a gate-off voltage. Each of the first switching element, the second switching element, the third switching element, the fourth switching element, the fifth switching element, the sixth switching element, the 7-1 switching element, and the 7-2 switching element may conduct in response to the gate-on voltage and may turn off in response to the gate-off voltage. The voltage of the first scan signal in each of the first mode and the second mode may be the gate-off voltage during a first period, may be the gate-on voltage during a second period after the first period, and may be the gate-off voltage during a third period after the second period. The voltage of the second scan signal in each of the first mode and the second mode may be the gate-on voltage during the first period and the second period, and may be the gate-off voltage during the third period. The voltage of the light-emitting signal in each of the first mode and the second mode may be the gate-on voltage during the first period, may be the gate-off voltage during the second period, and may be the gate-on voltage during the third period. The voltage of the first mode selection signal may be the gate-on voltage in the first period, the second period, and the third period of the first mode, and may be the gate-off voltage in the first period, the second period, and the third period of the second mode. The voltage of the second mode selection signal may be the gate-on voltage in the first period, the second period, and the third period of the second mode, and may be the gate-off voltage in the first period, the second period, and the third period of the first mode. In the first mode, the voltage of the first mode signal applied to the first node may be the voltage of the light-emitting signal, and the voltage of the second mode signal applied to the second node may be the gate-off voltage. In the second mode, the voltage of the first mode signal applied to the first node may be the gate-off voltage, and the voltage of the second mode signal applied to the second node may be the voltage of the light-emitting signal.

[0018] The mode selection circuit may include: a first mode switching element including a first electrode to which the light emission signal is applied, a gate to which the first mode selection signal is applied, and a second electrode electrically connected to the first node; a second mode switching element including a first electrode to which a high gate voltage is applied, a gate to which the second mode selection signal is applied, and a second electrode electrically connected to the first node; a third mode switching element including a first electrode to which the light emission signal is applied, a gate to which the second mode selection signal is applied, and a second electrode electrically connected to the second node; and a fourth mode switching element including a first electrode to which the high gate voltage is applied, a gate to which the first mode selection signal is applied, and a second electrode electrically connected to the second node. The light emission signal may swing between the high gate voltage and the low gate voltage. The first switching element may be turned on in response to the low gate voltage applied to the first node and turned off in response to the high gate voltage applied to the first node. The second switching element may be turned on in response to the low gate voltage applied to the second node and turned off in response to the high gate voltage applied to the second node.

[0019] The pixel circuit may further include: a capacitor connected between a VDD node to which the pixel driving voltage is applied and a fourth node; a third switching element including a first electrode to which the data voltage is applied, a gate to which a second scanning signal is applied, and a second electrode electrically connected to a fifth node; a fourth switching element including a first electrode electrically connected to the third node, a gate to which a first scanning signal is applied, and a second electrode connected to the fourth node; a fifth switching element including a first electrode to which a second compensation voltage is applied, a gate to which a third scanning signal is applied, and a second electrode connected to a sixth node; a sixth switching element including a first electrode to which the second compensation voltage is applied, a gate to which the third scanning signal is applied, and a second electrode connected to a seventh node; a seventh switching element including a first electrode connected to an INI node to which an initialization voltage is applied, a gate to which a fourth scanning signal is applied, and a second electrode connected to the fourth node; an eighth switching element including a first electrode to which a first compensation voltage is applied, a gate to which the third scanning signal is applied, and a second electrode connected to the fifth node; and a ninth switching element including a first electrode connected to the VDD node, a gate to which the light emission signal is applied, and a second electrode connected to the fifth node. The gate of the driving element may be electrically connected to the fourth node. The first light emitting element may include an anode connected to the sixth node and a cathode to which a cathode voltage is applied. The second light emitting element may include an anode connected to the seventh node and a cathode to which the cathode voltage is applied. Each of the first mode switching element, the second mode switching element, the third mode switching element, the fourth mode switching element, the first switching element, the second switching element, the third switching element, the fifth switching element, the sixth switching element, the eighth switching element, and the ninth switching element may be turned on in response to a low gate voltage applied to the corresponding gate and turned off in response to a high gate voltage applied to the corresponding gate. Each of the fourth switching element and the seventh switching element may be turned on in response to a high gate voltage applied to the corresponding gate and turned off in response to a low gate voltage applied to the corresponding gate.

[0020] The pixel circuit may further include: a capacitor connected between the VDD node to which the pixel driving voltage is applied and the fourth node; a third switching element including a first electrode to which the data voltage is applied, a gate to which a second scan signal is applied, and a second electrode electrically connected to the fifth node; a fourth switching element including a first electrode electrically connected to the third node, a gate to which a first scan signal is applied, and a second electrode connected to the fourth node; a fifth switching element including a first electrode to which a second compensation voltage is applied, a gate to which a third scan signal is applied, and a second electrode connected to the sixth node; a sixth switching element including a first electrode to which the second compensation voltage is applied, a gate to which the third scan signal is applied, and a second electrode connected to the seventh node; a seventh switching element including a first electrode connected to the INI node to which an initialization voltage is applied, a gate to which a fourth scan signal is applied, and a second electrode connected to the fourth node; an eighth switching element including a first electrode to which a first compensation voltage is applied, a gate to which the third scan signal is applied, and a second electrode connected to the fifth node; a 9-1 switching element including a first electrode connected to the VDD node, a gate connected to the first node, and a second electrode connected to the fifth node; and a 9-2 switching element including a first electrode connected to the VDD node, a gate connected to the second node, and a second electrode connected to the fifth node. The gate of the driving element may be electrically connected to the fourth node. The first light-emitting element may include an anode connected to the sixth node and a cathode to which a cathode voltage is applied. The second light-emitting element may include an anode connected to the seventh node and a cathode to which the cathode voltage is applied. Each of the first mode switching element, the second mode switching element, the third mode switching element, the fourth mode switching element, the first switching element, the second switching element, the third switching element, the fifth switching element, the sixth switching element, the eighth switching element, the 9-1 switching element, and the 9-2 switching element may be turned on in response to a low gate voltage applied to the corresponding gate and turned off in response to a high gate voltage applied to the corresponding gate. Each of the fourth switching element and the seventh switching element may be turned on in response to a high gate voltage applied to the corresponding gate and turned off in response to a low gate voltage applied to the corresponding gate.

[0021] The voltage of the first scan signal in each of the first mode and the second mode may be the gate low voltage during a first period, the gate high voltage during a second period after the first period, the gate high voltage during a third period after the second period, the gate low voltage during a fourth period after the third period, and the gate low voltage during a fifth period after the fourth period. The voltage of the second scan signal in each of the first mode and the second mode may be the gate high voltage during the first period, the second period, the fourth period, and the fifth period, and the gate low voltage during the third period. The voltage of the third scan signal in each of the first mode and the second mode may be the gate low voltage during the first period and the fourth period, and the gate high voltage during the second period, the third period, and the fifth period. The voltage of the fourth scan signal in each of the first mode and the second mode may be the gate low voltage during the first period, the third period, the fourth period, and the fifth period, and the gate high voltage during the second period. The voltage of the light emission signal in each of the first mode and the second mode may be the gate high voltage during the first period, the second period, the third period, and the fourth period, and the gate low voltage during the fifth period. The voltage of the first mode selection signal may be the gate low voltage during the first period, the second period, the third period, the fourth period, and the fifth period of the first mode, and the gate high voltage during the first period, the second period, the third period, the fourth period, and the fifth period of the second mode. The voltage of the second mode selection signal may be the gate low voltage during the first period, the second period, the third period, the fourth period, and the fifth period of the second mode, and the gate high voltage during the first period, the second period, the third period, the fourth period, and the fifth period of the first mode. In the first mode, the voltage of the first mode signal applied to the first node may be the voltage of the light emission signal, and the voltage of the second mode signal applied to the second node may be the gate high voltage. In the second mode, the voltage of the first mode signal applied to the first node may be the gate high voltage, and the voltage of the second mode signal applied to the second node may be the voltage of the light emission signal.

[0022] The pixel circuit may further include: a capacitor connected between a VDD node to which the pixel driving voltage is applied and a fourth node; a third switching element including a first electrode to which the data voltage is applied, a gate to which an Nth scan signal (where N is a natural number) is applied, and a second electrode electrically connected to a fifth node; a fourth switching element including a first electrode electrically connected to the third node, a gate to which the Nth scan signal is applied, and a second electrode connected to the fourth node; a fifth switching element including a first electrode connected to an INI node to which an initialization voltage is applied, a gate to which an (N-1)th scan signal is applied, and a second electrode connected to a sixth node; a sixth switching element including a first electrode connected to the INI node, a gate to which the (N-1)th scan signal is applied, and a second electrode electrically connected to a seventh node; a seventh switching element including a first electrode connected to the INI node, a gate to which the (N-1)th scan signal is applied, and a second electrode connected to the fourth node; and an eighth switching element including a first electrode connected to the VDD node, a gate to which the light emission signal is applied, and a second electrode connected to the fifth node. A gate of the driving element may be electrically connected to the fourth node. The first light emitting element may include an anode connected to the sixth node and a cathode to which a cathode voltage is applied. The second light emitting element may include an anode connected to the seventh node and a cathode to which the cathode voltage is applied.

[0023] The pixel circuit may further include: a capacitor connected between a VDD node to which the pixel driving voltage is applied and a fourth node; a third switching element including a first electrode to which the data voltage is applied, a gate to which the Nth scan signal (where N is a natural number) is applied, and a second electrode electrically connected to a fifth node; a fourth switching element including a first electrode electrically connected to the third node, a gate to which the Nth scan signal is applied, and a second electrode connected to the fourth node; a fifth switching element including a first electrode connected to an INI node to which an initialization voltage is applied, a gate to which the (N-1)th scan signal is applied, and a second electrode connected to a sixth node; a sixth switching element including a first electrode connected to the INI node, a gate to which the (N-1)th scan signal is applied, and a second electrode electrically connected to a seventh node; a seventh switching element including a first electrode connected to the INI node, a gate to which the (N-1)th scan signal is applied, and a second electrode connected to the fourth node; an 8-1 switching element including a first electrode connected to the VDD node, a gate connected to the first node, and a second electrode connected to the fifth node; and an 8-2 switching element including a first electrode connected to the VDD node, a gate connected to the second node, and a second electrode connected to the fifth node. The gate of the driving element may be electrically connected to the fourth node. The first light-emitting element may include an anode connected to the sixth node and a cathode to which a cathode voltage is applied. The second light-emitting element may include an anode connected to the seventh node and a cathode to which the cathode voltage is applied.

[0024] The pixel circuit may further include: a capacitor connected between a fourth node and an eighth node; a third switching element including a first electrode to which the data voltage is applied, a gate to which an N-th scan signal (where N is a natural number) is applied, and a second electrode electrically connected to a fifth node; a fourth switching element including a first electrode electrically connected to the third node, a gate to which the N-th scan signal is applied, and a second electrode connected to the fourth node; a fifth switching element including a first electrode connected to an INI node to which an initialization voltage is applied, a gate to which an (N-1)-th scan signal is applied, and a second electrode connected to a sixth node; a sixth switching element including a first electrode connected to the INI node, a gate to which the (N-1)-th scan signal is applied, and a second electrode electrically connected to a seventh node; a seventh switching element including a first electrode connected to the INI node, a gate to which the (N-1)-th scan signal is applied, and a second electrode connected to the fourth node; an eighth switching element including a first electrode connected to a VDD node to which the pixel driving voltage is applied, a gate to which the light emission signal is applied, and a second electrode connected to the eighth node; a ninth switching element including a first electrode connected to the fifth node, a gate to which the light emission signal is applied, and a second electrode connected to the eighth node; a tenth switching element including a first electrode connected to a REF node to which a reference voltage is applied, a gate to which the (N-1)-th scan signal is applied, and a second electrode connected to the eighth node; and an eleventh switching element including a first electrode connected to the REF node, a gate to which the N-th scan signal is applied, and a second electrode connected to the eighth node. The gate of the driving element may be electrically connected to the fourth node. The first light-emitting element may include an anode connected to the sixth node and a cathode to which a cathode voltage is applied. The second light-emitting element may include an anode connected to the seventh node and a cathode to which the cathode voltage is applied.

[0025] The pixel circuit may further include: a capacitor connected between a fourth node and an eighth node; a third switching element including a first electrode to which the data voltage is applied, a gate to which an Nth scan signal (where N is a natural number) is applied, and a second electrode electrically connected to a fifth node; a fourth switching element including a first electrode electrically connected to the third node, a gate to which the Nth scan signal is applied, and a second electrode connected to the fourth node; a fifth switching element including a first electrode connected to an INI node to which an initialization voltage is applied, a gate to which an (N-1)th scan signal is applied, and a second electrode connected to a sixth node; a sixth switching element including a first electrode connected to the INI node, a gate to which the (N-1)th scan signal is applied, and a second electrode electrically connected to a seventh node; a seventh switching element including a first electrode connected to the INI node, a gate to which the (N-1)th scan signal is applied, and a second electrode connected to the fourth node; an 8-1 switching element including a first electrode connected to a VDD node to which a pixel driving voltage is applied, a gate connected to the first node, and a second electrode connected to the eighth node; an 8-2 switching element including a first electrode connected to the VDD node, a gate connected to the second node, and a second electrode connected to the eighth node; a 9-1 switching element including a first electrode connected to the fifth node, a gate connected to the first node, and a second electrode connected to the eighth node; a 9-2 switching element including a first electrode connected to the fifth node, a gate connected to the second node, and a second electrode connected to the eighth node; a tenth switching element including a first electrode connected to a REF node to which a reference voltage is applied, a gate to which the (N-1)th scan signal is applied, and a second electrode connected to the eighth node; and an eleventh switching element including a first electrode connected to the REF node, a gate to which the Nth scan signal is applied, and a second electrode connected to the eighth node. The gate of the driving element may be electrically connected to the fourth node. The first light-emitting element may include an anode connected to the sixth node and a cathode to which a cathode voltage is applied. The second light-emitting element may include an anode connected to the seventh node and a cathode to which the cathode voltage is applied.

[0026] In each of the first mode and the second mode, the voltage of the (N-1)-th scan signal may be the gate-on voltage during a first period, may be the gate-off voltage during a second period after the first period, and may be the gate-off voltage during a third period after the second period. In each of the first mode and the second mode, the voltage of the N-th scan signal may be the gate-off voltage during the first period and the third period, and may be the gate-on voltage during the second period. In each of the first mode and the second mode, the voltage of the light-emitting signal may be the gate-off voltage during the first period and the second period, and may be the gate-on voltage during the third period. The voltage of the first mode selection signal may be the gate-on voltage during the first period, the second period, and the third period of the first mode, and may be the gate-off voltage during the first period, the second period, and the third period of the second mode. The voltage of the second mode selection signal may be the gate-off voltage during the first period, the second period, and the third period of the first mode, and may be the gate-on voltage during the first period, the second period, and the third period of the second mode. In the first mode, the voltage of the first mode signal applied to the first node may be the voltage of the light-emitting signal, and the voltage of the second mode signal applied to the second node may be the gate-off voltage. In the second mode, the voltage of the first mode signal applied to the first node may be the gate-off voltage, and the voltage of the second mode signal applied to the second node may be the voltage of the light-emitting signal.

[0027] A display device according to an embodiment of the present invention includes: a display panel in which a plurality of data lines, a plurality of gate lines, a plurality of power supply lines, and a plurality of pixel circuits are provided; a data driver configured to provide a data voltage to the data lines; a gate driver configured to receive a gate timing signal and provide a scan signal and a light-emitting signal to the gate lines; a level shifter configured to output a first mode selection signal, a second mode selection signal, and the gate timing signal; and a mode selection circuit configured to output the light-emitting signal to a first node in response to the first mode selection signal and output the light-emitting signal to a second node in response to the second mode selection signal. Each sub-pixel may be configured to drive a first light-emitting element in response to the voltage of the first node in a first mode and drive a second light-emitting element in response to the voltage of the second node in a second mode. Each sub-pixel may include the pixel circuit.

[0028] A display device according to an embodiment of the present invention includes: the above-mentioned display panel, in which a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of the above-mentioned pixel circuits are provided; a data driver configured to provide a data voltage to the data lines; a gate driver configured to receive a gate timing signal and provide a scan signal and a light emission signal to the gate lines; a level shifter configured to output a first mode selection signal, a second mode selection signal, and the gate timing signal.

[0029] The present invention can achieve low power and process optimization, and use the mode selection signal to change the viewing angle of the pixel.

[0030] The present invention can reduce the number of switching elements for changing the viewing angle of each pixel, and can simplify the structure of the pixel circuit capable of changing the viewing angle by reducing the number of wires connected between the pixel and the gate driver. In addition, the present invention can reduce the number of wires in the display panel, which can optimize the process of the display panel and improve the yield.

[0031] The effects of the present invention are not limited to the above effects, and other effects not mentioned will be clearly understood by those of ordinary skill in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other objects, features, and advantages of the present invention will become more apparent to those of ordinary skill in the art by referring to the exemplary embodiments described in detail with reference to the accompanying drawings, in which:

[0033] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present invention;

[0034] Figure 2 is a circuit diagram schematically illustrating a pixel circuit and a mode selection circuit according to an embodiment of the present invention;

[0035] Figure 3 is a detailed illustration Figure 2 of the circuit diagram of the mode selection circuit shown;

[0036] Figure 4 is an illustration Figure 2 of an example of the input / output signals of the mode selection circuit shown;

[0037] Figure 5 is a diagram illustrating an example of a lens provided above the light-emitting element;

[0038] Figure 6 is a diagram illustrating one frame period and one horizontal period of the display device;

[0039] Figure 7is a block diagram schematically illustrating a gate driver;

[0040] Figure 8 is a block diagram illustrating a plurality of gate drivers and a mode selector;

[0041] Figure 9 is a diagram illustrating a transmission path of a mode selection signal;

[0042] Figure 10 is a waveform diagram illustrating an example of driving a pixel in a first mode during an n-th frame period and driving a pixel in a second mode during an (n + 1)-th frame period;

[0043] Figure 11 is Figure 10 an enlarged waveform diagram of the portion marked as A in;

[0044] Figures 12A to 17B is a diagram illustrating the operation of a pixel circuit and a mode selection circuit in a stage according to an embodiment of the present invention;

[0045] Figures 18A to 23B is a diagram illustrating the operation of a pixel circuit and a mode selection circuit in a stage according to another embodiment of the present invention;

[0046] Figures 24A to 29B is a diagram illustrating the operation of a pixel circuit and a mode selection circuit in a stage according to another embodiment of the present invention;

[0047] Figure 30A and 30B is a diagram illustrating a pixel circuit and a mode selection circuit according to another embodiment of the present invention and signals applied to these circuits;

[0048] Figures 31A to 34B is a diagram illustrating the operation of a pixel circuit and a mode selection circuit in a stage according to another embodiment of the present invention;

[0049] Figure 35A and 35B is a diagram illustrating a pixel circuit and a mode selection circuit according to another embodiment of the present invention and signals applied to these circuits;

[0050] Figures 36A to 39B is a diagram illustrating the operation of a pixel circuit and a mode selection circuit in a stage according to another embodiment of the present invention;

[0051] Figure 40A and 40B is a diagram illustrating a pixel circuit and a mode selection circuit according to another embodiment of the present invention and signals applied to these circuits. Detailed Description

[0052] The advantages and features of the present invention and their implementation methods will be more clearly understood through the following embodiments described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments below, but can be implemented in various different forms. Rather, the embodiments of the present invention will make the disclosure of the present invention complete and allow those of ordinary skill in the art to fully understand the scope of the present invention. The present invention is defined only within the scope of the appended claims.

[0053] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings used to describe the embodiments of the present invention are merely examples, and the present invention is not limited thereto. Throughout this specification, similar reference numerals generally refer to similar elements. In addition, when describing the present invention, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present invention.

[0054] Terms such as "comprising", "having", "including", "constituting", etc. used herein generally intend to allow the addition of other components, unless these terms are used together with the term "only". Any reference to the singular may include the plural, unless specifically stated otherwise.

[0055] Even if not explicitly specified, elements should be interpreted as including the usual error ranges.

[0056] When using terms such as "on", "above", "below", "after", "connected or joined", "crossed" or "intersected" to describe the positional or interconnection relationship between two components, one or more other components may be interposed between these two components, unless the terms "immediately" or "directly" are used.

[0057] When using terms such as "after", "subsequently", "next" or "before" to describe time-related relationships, they may be discontinuous in the time coordinate, unless the terms "immediately" or "directly" are used.

[0058] Terms such as "first", "second", etc. may be used to distinguish elements from each other, but the functions or structures of the elements are not limited by the ordinal numbers or element names in front of the elements.

[0059] The following embodiments may be combined or combined with each other partially or wholly, and may be connected and operated in various ways technically. The embodiments may be implemented independently of each other, or implemented in association with each other.

[0060] The pixel circuit of the display device may include a plurality of transistors. The transistors may be implemented as thin film transistors (TFTs). The transistors may be implemented as oxide thin film transistors (TFTs) including oxide semiconductors, low temperature polycrystalline silicon TFTs (LTPS TFTs) including low temperature polycrystalline silicon, etc.

[0061] A transistor is a three - electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In a transistor, carriers flow starting from the source. The drain is an electrode for allowing carriers to flow out of the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n - channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, so that electrons can flow from the source to the drain. The n - channel transistor has a current direction from the drain to the source. In the case of a p - channel transistor (p - channel metal - oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p - channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed according to the applied voltage. Therefore, the present invention does not limit the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0062] The gate signal swings between a gate - on voltage and a gate - off voltage. The transistor turns on in response to the gate - on voltage and turns off in response to the gate - off voltage. In the case of an n - channel transistor, the gate - on voltage can be a gate - high voltage VGH, and the gate - off voltage can be a gate - low voltage VGL. In the case of a p - channel transistor, the gate - on voltage can be a gate - low voltage VGL, and the gate - off voltage can be a gate - high voltage VGH.

[0063] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0064] Refer to Figure 1 , a display device according to an embodiment of the present invention includes a display panel 100 and a display panel driving circuit for writing pixel data to pixels of the display panel 100. The display device further includes a power supply 150.

[0065] The display panel 100 may be a rectangular panel having a length in the X - axis direction (or the first direction), a width in the Y - axis direction (or the second direction), and a thickness in the Z - axis direction (or the third direction), but is not limited thereto. For example, the display panel 100 may be a deformed panel that is at least partially curved or elliptical.

[0066] The display area AA of the display panel 100 includes a pixel array for displaying an input image thereon. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix form. The display panel 100 may further include a power supply line commonly connected to the pixels. The power supply line may be commonly connected to a pixel circuit and supply a voltage required to drive the pixel 101 to the pixel 101.

[0067] Each pixel 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for implementing colors. Each pixel may further include a white sub-pixel. Each sub-pixel includes a pixel circuit for driving a light-emitting element. The light-emitting element may be implemented as an organic light-emitting element such as an OLED or an inorganic light-emitting element such as a micro light-emitting diode (LED). Each pixel circuit may be connected to a data line, a gate line, and a power supply line. Hereinafter, a pixel may be interpreted to have the same meaning as a sub-pixel.

[0068] Each pixel 101 may include a first light-emitting element that emits light in a first mode and a second light-emitting element that emits light in a second mode. Each pixel 101 emits light from the first light-emitting element at a wide viewing angle in the first mode, while emitting light from the second light-emitting element at a narrow viewing angle in the second mode.

[0069] The display array or the display area AA includes a plurality of pixel rows L1 to Ln. Each of the plurality of pixel rows L1 to Ln includes a row of pixels arranged in the row direction (X-axis direction) in the pixel array of the display panel 100. The pixels arranged in one pixel row may share the gate line 103. The sub-pixels arranged in the column direction (Y-axis direction) may share the same data line 102. One horizontal period is a time obtained by dividing one frame period by the total number of the pixel rows L1 to Ln.

[0070] The display panel 100 may be implemented using a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device, where an image is displayed on the screen and an actual object is visible outside the display panel. The display panel 100 may be manufactured as a flexible display panel capable of being flexibly bent.

[0071] The power supply 150 receives an input voltage from the host system 200 and outputs voltages required to drive the pixels 101 of the display panel 100 and the display panel driving circuit. To this end, the power supply 150 may include a DC-DC converter. The DC-DC converter may include a charge pump, a rectifier, a buck converter, a boost converter, etc. The power supply 150 may output a constant voltage (or a DC voltage) via the DC-DC converter, such as a gate high voltage, a gate low voltage, a pixel driving voltage, a cathode voltage, a reference voltage, an initialization voltage, and an IC driving voltage for the display panel driving circuit. The gate high voltage and the gate low voltage may be supplied to the level shifter 140 and the gate driver 120. Constant voltages such as the pixel driving voltage, the cathode voltage, the reference voltage, and the initialization voltage are supplied to the pixels 101 via power lines commonly connected to the pixels 101.

[0072] The power supply 150 may further include a gamma voltage generator. The gamma voltage generator may receive a high-potential reference voltage and a low-potential reference voltage and output a plurality of gamma reference voltages divided by a predetermined voltage difference interval on a preset gamma curve, such as a 2.2 gamma curve. The gamma reference voltages are supplied to the data driver 110. The gamma reference voltages are divided by a voltage dividing circuit and are further divided into a plurality of gray-level voltages in the data driver 110. The gamma voltage generator may be implemented as a programmable gamma circuit capable of adjusting the level of each gamma reference voltage according to digital data. The timing controller 130, or the host system 200, or a separate external device may update the digital data stored in the register of the programmable gamma circuit via a communication interface.

[0073] The display panel driving circuit writes pixel data of an input image to the pixels 101 of the display panel 100 under the control of the timing controller 130. The display panel driving circuit includes a data driver 110, a gate driver 120, a mode selector 160, and a timing controller 130.

[0074] The display panel driving circuit may further include a touch sensor driver for driving a touch sensor. The touch sensor driver is Figure 1 omitted herein. The data driver 110 and the touch sensor driver may be integrated into a source driver integrated circuit (IC).

[0075] The data driver 110 receives pixel data of an input image received as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 may receive a gamma reference voltage and generate a gamma-compensated voltage for each gray level via a voltage dividing circuit. The gamma-compensated voltage is supplied to a digital-to-analog converter (DAC) provided on each channel of the data driver 110.

[0076] The data driver 110 samples and latches the digital data received from the timing controller 130, and then inputs the digital data to the DAC. Here, the digital data includes pixel data of the input image. The DAC converts the pixel data into a gamma-compensated voltage and outputs the data voltage of the pixel data.

[0077] The gate driver 120 may be formed on the display panel 100 together with circuit elements and wires in the display area AA. The gate driver 120 may be provided in at least one of the left and right non-display areas NA of the display panel 100 located outside the display area AA, or at least a part thereof may be provided inside the display area AA.

[0078] The gate driver 120 may be provided in the non-display areas NA on both sides of the display panel 100 with the display area AA of the display panel interposed therebetween, and may supply gate pulses from both sides of the gate line 103 in a double feeding method. In another embodiment, the gate driver 120 may be provided in at least one of the left and right non-display areas NA of the display panel 100 to supply a gate signal to the gate line 103 in a single feeding method. The gate driver 120 sequentially outputs pulses of the gate signal to the gate line 103 under the control of the timing controller 130. The gate driver 120 may sequentially supply the gate signal to the gate line 103 by shifting the pulses of the gate signal by using a shift register and an edge trigger.

[0079] The gate signal may include a scan signal input to the pixel circuit via a plurality of gate lines and a light emission signal (hereinafter, referred to as an “EM” signal). In this case, the gate driver may include a gate driver that outputs a scan signal and a gate driver that outputs an EM signal. The mode selector 160 is connected to an output terminal of the gate driver for outputting an EM signal. Each of the scan signal and the EM signal may swing between a gate high voltage and a gate low voltage. The mode selector 160 may include a plurality of Figure 2 The mode selection circuits shown. One mode selection circuit may be provided for each row of pixels.

[0080] The timing controller 130 receives digital video data of an input image and a timing signal synchronized with this data from the host system 200. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a period of one horizontal period (1H).

[0081] The timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a gate timing control signal for controlling the operation timing of the gate driver 120, and a mode selection signal based on the timing signals Vsync, Hsync, and DE received from the host system 200, thereby controlling the display panel driving circuit. The timing controller 130 synchronizes the data driver 110 and the gate driver 120 by controlling the operation timing of the display panel driving circuit.

[0082] The mode selection signal is a signal that selects either the first mode or the second mode as the operation mode of the pixel 101 according to its logic value. The mode selection signal can be separately output from the level shifter 140 as a first mode selection signal and a second mode selection signal.

[0083] The timing control signal output from the timing controller 130 can be input to the shift register of the gate driver 120 via the level shifter 140. The mode selection signal output from the timing controller 130 can be input to the mode selection circuit via the level shifter 140.

[0084] The level shifter 140 can convert the voltage level of the signal received from the timing controller 130 into a swing width between a gate high voltage and a gate low voltage and output it. The level shifter 140 can decode the gate timing signal to output a start pulse and a clock to drive the gate driver 120, and can decode the mode selection signal to output a first and a second mode selection signal. Each of the start pulse, the clock, and the mode selection signal is an AC signal that swings between a gate on voltage and a gate off voltage.

[0085] The host system 200 can scale the image signal from the video source to match the resolution of the display panel 100, and can transmit it to the timing controller 130 together with the timing signal. The host system 200 can transmit a viewing angle mode signal having different logic values in the first mode and the second mode to the timing controller 130 together with the image signal at least once per frame. The timing controller 130 can output a mode selection signal in response to the viewing angle mode signal.

[0086] Figure 2 and 3 is a diagram showing a pixel circuit and a mode selection circuit according to an embodiment of the present invention. Figure 4 is a diagram showing Figure 2 an example of waveforms of input / output signals of the mode selection circuit shown. In Figure 4 , the S mode is a first mode in which the pixel emits light with a wide viewing angle. The P mode is a second mode in which the pixel emits light with a narrow viewing angle.

[0087] Referring to Figures 2 to 4 , the pixel circuit drives the first light-emitting element EL1 in response to the voltage of the first node n01 in the first mode, and drives the second light-emitting element EL2 in response to the voltage of the second node n02 in the second mode.

[0088] The pixel circuit includes: a first light-emitting element EL1; a second light-emitting element EL2; a driving element DT for driving the first light-emitting element EL1 and the second light-emitting element EL2; a compensation circuit 10 connected to the driving element DT; a first switching element M01 connected between the driving element DT and the first light-emitting element EL1; and a second switching element M02 connected between the driving element DT and the second light-emitting element EL2. The driving element DT and the switching elements M01 and M02 may be implemented as p-channel transistors, but are not limited thereto.

[0089] The first light-emitting element EL1 can be driven by a current from the driving element DT via the first switching element M01 to emit light in the first mode. The first light-emitting element EL1 includes an anode connected to the second electrode of the first switching element M01 and a cathode connected to a VSS node to which a cathode voltage VSS is applied.

[0090] The second light-emitting element EL2 can be driven by a current from the driving element DT via the second switching element M02 to emit light in the second mode. The second light-emitting element EL2 includes an anode connected to the second electrode of the second switching element M02 and a cathode connected to a VSS node to which a cathode voltage VSS is applied.

[0091] The driving element DT generates a current according to the gate-source voltage to drive the first light-emitting element EL1 and the second light-emitting element EL2. The driving element DT includes a first electrode to which a driving voltage VDD is applied, a gate, and a second electrode connected to a third node n03. The pixel driving voltage VDD can be applied to the first electrode of the driving element DT. The data voltage Vdata of the pixel data can be provided to the gate of the driving element DT. The second electrode of the driving element DT can be electrically connected to the first electrode of the first switching element M01 and the first electrode of the second switching element M02 via the third node n03.

[0092] The compensation circuit 10 can be connected to the driving element DT, but is not limited thereto. The compensation circuit 10 can use two or more switching elements and capacitors to initialize the pixel circuit, sample the threshold voltage of the driving element DT, and apply a data voltage Vdata compensated by the amount of the threshold voltage to the gate of the driving element DT.

[0093] The first switching element M01 is connected between the third node n03 and the anode of the first light-emitting element EL1, and is turned on in response to the gate conduction voltage VGL of the first mode signal S. When the first switching element M01 is turned on, the third node n03 is electrically connected to the first light-emitting element EL1, so that the first light-emitting element EL1 can emit light. The first switching element M01 includes: a first electrode electrically connected to the third node n03; a gate electrically connected to the first node n01 to which the first mode signal S is applied; and a second electrode electrically connected to the anode of the first light-emitting element EL1.

[0094] The second switching element M02 is connected between the third node n03 and the anode of the second light-emitting element EL2, and is turned on in response to the gate conduction voltage VGL of the second mode signal P. When the second switching element M02 is turned on, the third node n03 is electrically connected to the second light-emitting element EL2, so that the second light-emitting element EL2 can emit light. The second switching element M02 includes: a first electrode connected to the third node n03; a gate electrically connected to the second node n02 to which the second mode signal P is applied; and a second electrode electrically connected to the anode of the second light-emitting element EL2.

[0095] Each of the first switching element M01 and the second switching element M02 switches the current path flowing through the light-emitting elements EL1 and EL2 in response to the voltages of the corresponding mode signals S and P.

[0096] The mode selection circuit SPM receives the Nth (N is a natural number) EM signal EM(N), the first mode selection signal S_SEL, the second mode selection signal P_SEL, and a separate gate cut-off voltage VGH via a constant voltage node. Wires 161 and 162 for supplying the first mode selection signal S_SEL and the second mode selection signal P_SEL to a plurality of mode selection circuits SPM can be provided in the non-display area NA of the display panel 100. The mode selection circuit SPM can output the EM signal EM(N) to the first node n01 in the first mode and output the EM signal EM(N) to the second node n02 in the second mode.

[0097] The mode selection circuit SPM transmits a pulse of the Nth EM signal EM(N) as an activation mode signal S or P to the pixel circuit PXL in response to the gate conduction voltage VGL of the first mode selection signal S_SEL and the second mode selection signal P_SEL. Meanwhile, the mode selection circuit SPM transmits other mode signals as a deactivation mode signal P or S to the pixel circuit PXL in response to the gate cut-off voltage VGH.

[0098] The mode selection circuit SPM includes a first mode switching element T01, a second mode switching element T02, a third mode switching element T03, and a fourth mode switching element T04. The first mode switching element T01, the second mode switching element T02, the third mode switching element T03, and the fourth mode switching element T04 can be implemented as p-channel transistors, but are not limited thereto. Each of the first mode switching element T01, the second mode switching element T02, the third mode switching element T03, and the fourth mode switching element T04 can be turned on in response to the gate conduction voltage VGL and turned off in response to the gate cut-off voltage VGH.

[0099] The first mode switching element T01 is connected between the node to which the Nth EM signal EM(N) is applied and the first node n01, and is turned on in response to the gate conduction voltage VGL of the first mode selection signal S_SEL. The node to which the Nth EM signal EM(N) is applied can be connected to the output terminal of the gate driver 120 that outputs the Nth EM signal EM(N). When the first mode switching element T01 is turned on, the Nth EM signal EM(N) is transmitted to the pixel circuit PXL as the first mode signal S. The first mode signal S controls the on / off timing of the first switching element M01 of the pixel circuit PXL. The first mode switching element T01 includes a first electrode to which the Nth EM signal EM(N) is applied, a gate to which the first mode selection signal S_SEL is applied, and a second electrode electrically connected to the first node n01.

[0100] The second mode switching element T02 is connected between the VGH node to which the gate cut-off voltage VGH is applied and the first node n01, and is turned on in response to the gate conduction voltage VGL of the second mode selection signal P_SEL. When the second mode switching element T02 is turned on, the gate cut-off voltage VGH is applied to the first node n01 to turn off the first switching element M01 of the pixel circuit PXL. The second mode switching element T02 includes a first electrode to which a separate gate cut-off voltage VGH is applied, a gate to which the second mode selection signal P_SEL is applied, and a second electrode electrically connected to the first node n01.

[0101] The third mode switching element T03 is connected between the node to which the N-th EM signal EM(N) is applied and the second node n02, and is turned on in response to the gate conduction voltage VGL of the second mode selection signal P_SEL. When the third mode switching element T03 is turned on, the N-th EM signal EM(N) is transmitted as the second mode signal P to the pixel circuit PXL. The second mode signal P controls the on / off timing of the second switching element M02 of the pixel circuit PXL. The third mode switching element T03 includes a first electrode to which the N-th EM signal EM(N) is applied, a gate to which the second mode selection signal P_SEL is applied, and a second electrode electrically connected to the second node n02.

[0102] The fourth mode switching element T04 is connected between the VGH node to which the gate cutoff voltage VGH is applied and the second node n02, and is turned on in response to the gate conduction voltage VGL of the first mode selection signal S_SEL. When the fourth mode switching element T04 is turned on, the gate cutoff voltage VGH is applied to the second node n02 to turn off the second switching element M02 of the pixel circuit PXL. The fourth mode switching element T04 includes a first electrode to which a separate gate cutoff voltage VGH is applied, a gate to which the first mode selection signal S_SEL is applied, and a second electrode electrically connected to the second node n02.

[0103] Figure 5 FIG. is an example diagram showing a lens provided above the light-emitting element.

[0104] Referring to Figure 5 , the first lens 32 may be provided above the first light-emitting element EL1. The first lens 32 may be implemented as a semi-cylindrical lens to limit the vertical viewing angle while increasing the horizontal viewing angle. The first lens 32 may be elongated in the X-axis direction parallel to the gate line 103 of the display panel 100, and may have a narrow and convex center in the Y-axis direction parallel to the data line 102. The first lens 32 diffuses the light of the first light-emitting element EL1 emitted in the first mode (S mode) in the left and right viewing angles.

[0105] The second lens 34 may be provided above the second light-emitting element EL2. The second lens 34 may be a hemispherical lens that bulges at the center and narrows toward the edge. The second lens 34 may converge the light of the second light-emitting element EL2 emitted in the second mode (P mode) to narrow the vertical and horizontal viewing angles of the second light-emitting element EL2.

[0106] The first lens 32 and the second lens 34 may be implemented as a transparent medium or a transparent insulating layer pattern provided inside the display panel 100, but are not limited thereto.

[0107] Figure 6 It is a diagram showing one frame period and one horizontal period of the graphic display device.

[0108] Refer to Figure 6 , one cycle of the vertical synchronization signal Vsync defines one frame period. One cycle of the horizontal synchronization signal Hsync defines one horizontal period (1H). The clock of the data enable signal DE represents valid data, which includes pixel data of pixels to be written into a pixel row of the display panel 100. One cycle of the data enable signal DE is one horizontal period (1H).

[0109] The interval of one frame (1 frame) is divided into: an active interval AT, in which the pixel data of the input image is written into the pixels 101; and a vertical blank period VB without pixel data. Within one horizontal period (1H), pixel data is written into the pixels existing in a pixel row of the display panel 100. One horizontal period (1H) includes a horizontal blank period HB without pixel data between pixel rows.

[0110] Figure 7 It is a block diagram schematically illustrating the gate driver 120.

[0111] Refer to Figure 7 , the gate driver 120 includes signal transmission units ST(n - 1) to ST(n + 2) connected in cascade with each other.

[0112] The signal transmission units ST(n - 1) to ST(n + 2) are connected to the clock lines to which the clocks CLK1 and CLK2 are applied. The signal transmission units ST(n - 1) to ST(n + 2) are connected in cascade via the carry signal lines to which the carry pulses CAR(n - 1) to CAR(n + 2) are applied. The clocks CLK1 and CLK2 can be shown as 2 - phase clocks in Figure 6 , but it is not limited thereto. For example, an i - phase clock whose phases are shifted in sequence can be input to the shift register or edge trigger in the gate driver, where i is a natural number greater than or equal to 2.

[0113] Each of the signal transmission units ST(n-1) to ST(n+2) may include: a VST node to which a start pulse VST is input; a CLK node to which shift clocks CLK1 and CLK2 are input; a first output node from which pulses of gate signals Gout(n-1) to Gout(n+2) are output; and a second output node from which carry pulses CAR(n-1) to CAR(n+2) are output. The first output node from which the gate pulses are output is connected to the gate lines of the display panel 100. The gate pulses Gout(n-1) to Gout(n+2) and the carry pulses CAR(n-1) to CAR(n+2) may be output via a common output node. In this case, the second output node and the first output node may be connected to a common output node.

[0114] The start pulse VST is generally input to the first signal transmission unit. In Figure 7 the example, the (n-1)th signal transmission unit ST(n-1) may be the first signal transmission unit. The signal transmission units ST(n) to ST(n+2) connected to the (n-1)th signal transmission unit ST(n-1) in a cascaded manner start driving when they receive the carry pulses CAR(n-1) to CAR(n+1) from their respective preceding signal transmission units. When a start pulse or a carry signal is input and a clock is input, each of the signal transmission units ST(n-1) to ST(n+2) outputs a pulse of the corresponding gate signal Gout(n-1) to Gout(n+2). Accordingly, the signal transmission units ST(n-1) to ST(n+2) may sequentially output pulses of the gate signals Gout(n-1) to Gout(n+2) while shifting the pulses. The gate signal may be a scan signal or an EM signal, but is not limited thereto.

[0115] Each of the signal transmission units ST(n-1) to ST(n+2) includes a first control node Q, a second control ground QB, and a buffer circuit. Each of the signal transmission units ST(n-1) to ST(n+2) may charge and discharge the first control node Q and the second control node QB using a plurality of transistors. A reset pulse from a next signal transmission unit may be input to the reset nodes of the signal transmission units ST(n-1) to ST(n+2). The signal transmission units ST(n-1) to ST(n+2) may discharge the first control node Q in response to a reset pulse from a next signal transmission unit.

[0116] The buffer circuit outputs a pulse of the gate signal to the gate lines connected to the pixel circuits via the first output node or the common output node via a pull-up transistor Tu and a pull-down transistor Td.

[0117] While the first control node Q is being charged while the input clocks CLK1 and CLK2 are input, the buffer circuit can supply the gate conduction voltage of the clocks CLK1 and CLK2 or the gate conduction voltage applied as a constant voltage via the power supply line to the first output node or the common output node, thereby outputting the voltage of the gate signal that is the gate conduction voltage. When the second control node QB is charged to output the voltage of the gate signal that is the gate cut-off voltage, the buffer circuit can discharge the first output node or the common output node.

[0118] The pull-up transistor Tu includes a gate connected to the first control node Q, a first electrode to which the clocks CLK1 and CLK2 are applied or the gate conduction voltage is input, and a second electrode connected to the first output node or the common output node. The pull-down transistor Td includes a gate connected to the second control node QB, a first electrode connected to the first output node or the common output node, and a second electrode to which the gate cut-off voltage is applied.

[0119] An inverter circuit (not shown) can be connected between the first control node Q and the second control node QB. The inverter circuit controls the voltages of the first control node Q and the second control node QB using voltages that are inverted with respect to each other.

[0120] Figure 8 is a block diagram illustrating a plurality of gate drivers and a mode selector.

[0121] Referring to Figure 8 , pulses of gate signals such as pulses of the first scan signal, pulses of the second scan signal, and pulses of the EM signal can be applied to each sub-pixel of the display panel 100. In this case, the gate driver 120 can include: a first gate driver 121 that sequentially outputs pulses of the first scan signal SCAN1(1) to (n); a second gate driver 122 that sequentially outputs pulses of the second scan signal SCAN2(1) to (n); and a third gate driver 123 that sequentially outputs pulses of the EM signal EM(1) to (n). The gate drivers 121, 122, and 123 can independently receive S1VST, S2VST, and EVST corresponding to the output waveforms and the clocks S1CLK1, S1CLK2, S2CLK1, S2CLK2, ECLK1, and ECLK2.

[0122] Pixels in the first pixel row can receive the first gate signals SCAN1(1), SCAN(2), and EM(1) output from the gate drivers 121, 122, and 123. Pixels in the nth pixel row can receive the nth gate signals SCAN1(n), SCAN2(n), and EM(n) output from the gate drivers 121, 122, and 123.

[0123] The mode selector 160 is connected to the output terminal of the third gate driver 123 and receives the EM signals EM(1) to (n), and also receives the first mode selection signal S_SEL and the second mode selection signal P_SEL. The mode selector 160 also receives the gate cut-off voltage VGH. The mode selector 160 provides the EM signals EM(1) to (n) as active mode signals to the pixels in response to the mode selection signal S_SEL or P_SEL of the gate-on voltage, or provides the EM signals EM(1) to (n) as de-active mode signals to the pixels in response to the mode selection signal S_SEL or P_SEL of the gate cut-off voltage. The pixels of the first pixel row can be driven at a wide viewing angle or a narrow viewing angle in response to the active mode signal among the first mode signal S(1) and the second mode signal P(1) input from the mode selector 160. The pixels in the nth pixel row can be driven at a wide viewing angle or a narrow viewing angle in response to the active mode signal among the first mode signal S(n) and the second mode signal P(n) input from the mode selector 160.

[0124] Figure 9 FIG. is a diagram illustrating a transmission path of the mode selection signal.

[0125] Refer to Figure 9 , the display device may include a control board CPCB, a source board SPCB, and a chip on film COF that are electrically connected to the display panel 100. The source driver IC DIC having a circuit integrated with the data driver 110 may be mounted on the flexible film of the COF.

[0126] The control board CPCB includes a timing controller 130, a level shifter 140, a power supply 150, etc. The control board CPCB may be electrically connected to the source board SPCB via flexible circuits such as a flexible flat cable (FFC) and a flexible printed circuit board (FPCB) and connectors.

[0127] The COF is connected between the source board SPCB and the display panel 100 to electrically connect the source board SPCB to the display panel 100 and supply the data voltage output from the source driver IC DIC to the data lines in the display panel 100.

[0128] The gate timing control signal, mode selection signals S_SEL and P_SEL output from the timing controller 130 can be converted in the level shifter 140 into signals that swing between a gate-on voltage and a gate-off voltage. The timing controller 130 can encode the timing information of the gate timing control signal and the mode selection signals to transmit it to the level shifter 140; the level shifter 140 can decode the signals received from the timing controller 130 to output the mode selection signals S_SEL and P_SEL and the gate timing control signal that swing between the gate-on voltage and the gate-off voltage. The gate timing control signal includes a start pulse and a clock. The gate timing control signal and the mode selection signals S_SEL and P_SEL output from the level shifter 140 can be transmitted to the display panel 100 via the source printed circuit board (SPCB) and wires on the chip on film (COF), and then can be transmitted to the gate driver 120 and the mode selector 160 via wires provided in the non-display area (NA) of the display panel 100.

[0129] Figure 10 is a waveform diagram illustrating an example of driving pixels in a first mode during an n-th frame period and driving pixels in a second mode during an (n + 1)-th frame period.

[0130] Referring to Figure 10 , under the control of the timing controller 130, the viewing angle modes S and P can be selected in each frame period. For example, pixels can be driven in a first mode (S mode) during an n-th frame period FR(n) and in a second mode (P mode) during an (n + 1)-th frame period FR(n + 1).

[0131] During each frame, the waveforms of the gate signals SCAN1, SCAN2, and EM applied to the pixels in one horizontal period (1H) can be the same. In contrast, the mode selection signals S_SEL and P_SEL and the mode signals S and P can have different waveforms according to the selected mode. For example, when the voltage of the first mode selection signal S_SEL generated during one horizontal period (1H) of the n-th frame period FR(n) is the gate-on voltage VGL and the voltage of the second mode selection signal P_SEL is the gate-off voltage VGH, the pixels in the corresponding pixel row can be driven in the first mode (S mode) in response to the gate-on voltage VGL of the first mode signal S. Subsequently, when the voltage of the first mode selection signal S_SEL is the gate-off voltage VGH and the voltage of the second mode selection signal P_SEL is the gate-on voltage VGL during one horizontal period (1H) of the (n + 1)-th frame period FR(n + 1), the pixels in the corresponding pixel row can be driven in the second mode (P mode) in response to the gate-on voltage VGL of the second mode signal P.

[0132] When the viewing angle mode changes, the brightness of the pixels may fluctuate, causing the screen on the display panel 100 to look abnormal. The pixels can be controlled by waveforms in the portions marked as A in Figure 10 and 11 during the vertical blanking period VB and / or the horizontal blanking period HB, so that the abnormal-looking screen is not visible when the viewing angle mode is switched.

[0133] Referring to Figure 2 、 3 、10, and 11, when the viewing angle mode of the pixel is switched from the first mode (S mode) to the second mode (P mode), the voltage of the first mode selection signal S_SEL may be inverted to the gate cut-off voltage VGH during the vertical blanking period VB and / or the horizontal blanking period HB, and then the second mode selection signal P_SEL may be inverted to the gate conduction voltage VGL. As a result, an interval tf occurs in which both the first mode selection signal S_SEL and the second mode selection signal P_SEL are the gate cut-off voltage VGH, so that the first node n01 and the second node n02 float. Subsequently, when the second mode selection signal P_SEL is inverted to the gate conduction voltage VGL, the first node n01 may be charged to the gate cut-off voltage VGH, and the second node n01 may be charged to the gate conduction voltage VGL.

[0134] Figures 12A to 17B is a diagram illustrating the operation of a pixel circuit and a mode selection circuit in stages according to an embodiment of the present invention. In this embodiment, the pixel circuit includes a compensation circuit. Figures 12A to 14B An example of the operation of the pixel circuit and the mode selection circuit in the first mode (S mode) is illustrated. Figures 15A to 17B An example of the operation of the pixel circuit and the mode selection circuit in the second mode (P mode) is illustrated. In Figures 12A to 17B the detailed description of components that are substantially the same as those in the embodiment shown in Figure 2 and 3 may be omitted.

[0135] Referring to Figures 12A to 17B , the pixel circuit includes: a first light-emitting element EL1; a second light-emitting element EL2; a driving element DT for driving the first light-emitting element EL1 and the second light-emitting element EL2; a plurality of switching elements M1 to M7; and a capacitor Cst. The driving element DT and the switching elements M1 to M7 may be implemented as p-channel transistors, but are not limited thereto.

[0136] The pixel circuit is connected to a VDD node to which a pixel driving voltage VDD is applied, a VSS node to which a cathode voltage VSS is applied, and a REF node to which a reference voltage Vref is applied. The VDD node, the VSS node, and the REF node are connected to corresponding power supply lines and thus commonly connected to all pixels. The pixel circuit can be connected to a mode selection circuit SPM via a data line to which a data voltage Vdata is applied, gate lines to which gate signals SCAN1, SCAN2, and EM are applied, and a first node n1 and a second node n2.

[0137] The pixel driving voltage VDD can be set to a voltage that is higher than the maximum voltage of the data voltage Vdata and enables the driving element DT to operate in the saturation region. The pixel driving voltage VDD is higher than the cathode voltage VSS. The reference voltage Vref can be set to a voltage that is lower than the minimum voltage of the data voltage Vdata and higher than the cathode voltage VSS. For example, the reference voltage Vref can be set to a voltage that is 1 to 2 volts higher than the cathode voltage VSS, but is not limited thereto. The gate cutoff voltage VGH can be set to a voltage higher than the pixel driving voltage VDD, and the gate conduction voltage VGL can be set to a voltage lower than the cathode voltage VSS. For example, the following settings can be made: VDD = 15 [V], VSS = 3 [V], Vref = 3 [V], VGH = 16 [V], VGL = -9 [V], but are not limited thereto. The data voltage Vdata of the pixel data can have a dynamic range between 2V and 7V. The higher the gray level value of the pixel data, the lower the voltage level of the data voltage Vdata that can be selected. The higher the gray level value of the pixel data, the higher the brightness of the light emitting elements EL1 and EL2.

[0138] The first light emitting element EL1 includes an anode connected to a seventh node n7 and a cathode to which a cathode voltage VSS is applied. The second light emitting element EL2 includes an anode connected to an eighth node n8 and a cathode to which a cathode voltage VSS is applied. The first light emitting element EL1 can be driven by a current from the driving element DT to emit light in a first mode (S mode). The second light emitting element EL2 can be driven by a current from the driving element DT to emit light in a second mode (P mode).

[0139] The driving element DT includes a first electrode to which a pixel driving voltage VDD is applied, a gate connected to a fourth node n4, and a second electrode connected to a third node n3. The driving element DT generates a current according to the gate-source voltage, such that the first light emitting element EL1 is driven in the first mode (S mode) and the second light emitting element EL2 is driven in the second mode (P mode). A capacitor Cst is connected between the fourth node n4 and the fifth node n5.

[0140] The first switching element M1 is connected between the third node n03 and the seventh node n7, and is turned on in response to the gate conduction voltage VGL of the first mode signal S applied via the first node n1. When the first switching element M1 is turned on, the third node n3 can be electrically connected to the seventh node n7. The first switching element M1 includes: a first electrode connected to the third node n3; a gate connected to the first node n1 to which the first mode signal S is applied; and a second electrode connected to the seventh node n7.

[0141] The second switching element M2 is connected between the third node n3 and the eighth node n8, and is turned on in response to the gate conduction voltage VGL of the second mode signal P applied via the second node n2. When the second switching element M2 is turned on, the third node n3 can be electrically connected to the eighth node n8. The second switching element M2 includes: a first electrode connected to the third node n3; a gate connected to the second node n2 to which the second mode signal P is applied; and a second electrode connected to the eighth node n8.

[0142] The third switching element M3 is connected between the data line to which the data voltage Vdata of the pixel data is applied and the fifth node n5, and is turned on in response to the gate conduction voltage VGL of the first scan signal SCAN1. When the third switching element M3 is turned on, the data voltage Vdata can be applied to the fifth node n5. The third switching element M3 includes a first electrode to which the data voltage Vdata is applied, a gate to which the first scan signal SCAN1 is applied, and a second electrode connected to the fifth node n5.

[0143] The fourth switching element M4 is connected between the third node n3 and the fourth node n4, and is turned on in response to the gate conduction voltage VGL of the second scan signal SCAN2. When the fourth switching element M4 is turned on, the third node n3 can be electrically connected to the fourth node n4. The fourth switching element M4 includes a first electrode connected to the third node n3, a gate to which the second scan signal SCAN2 is applied, and a second electrode connected to the fourth node n4.

[0144] The fifth switching element M5 is connected between the sixth node n6 to which the reference voltage Vref is applied and the seventh node n7, and is turned on in response to the gate conduction voltage VGL of the second scan signal SCAN2. When the fifth switching element M5 is turned on, the sixth node n6 can be electrically connected to the seventh node n7. The fifth switching element M5 includes a first electrode connected to the sixth node n6, a gate to which the second scan signal SCAN2 is applied, and a second electrode connected to the seventh node n7.

[0145] The sixth switching element M6 is connected between a sixth node n6 and an eighth node n8, and is turned on in response to the gate-on voltage VGL of a second scan signal SCAN2. When the sixth switching element M6 is turned on, the sixth node n6 can be electrically connected to the eighth node n8. The sixth switching element M6 includes a first electrode connected to the sixth node n6, a gate to which the second scan signal SCAN2 is applied, and a second electrode connected to the eighth node n8.

[0146] The seventh switching element M7 is connected between a fifth node n5 and the sixth node n6, and is turned on in response to the gate-on voltage VGL of an EM signal EM. When the seventh switching element M7 is turned on, the fifth node n5 can be electrically connected to the sixth node n6. The seventh switching element M7 includes a first electrode connected to the fifth node, a gate to which the EM signal EM is applied, and a second electrode connected to the sixth node n6.

[0147] The mode selection circuit SPM includes a first mode switching element T1, a second mode switching element T2, a third mode switching element T3, and a fourth mode switching element T4. The first mode switching element T1, the second mode switching element T2, the third mode switching element T3, and the fourth mode switching element T4 can be implemented as p-channel transistors, but are not limited thereto.

[0148] The first mode switching element T1 is connected between a node to which the EM signal is applied and a first node n1, and is turned on in response to the gate-on voltage VGL of a first mode selection signal S_SEL. The node to which the EM signal EM is applied can be connected to an output terminal of a third gate driver 123. When the first mode switching element T1 is turned on, the EM signal EM is applied to the first node n1 as a first mode signal S. The first mode switching element T1 includes a first electrode to which the EM signal EM is applied, a gate to which the first mode selection signal S_SEL is applied, and a second electrode connected to the first node n1.

[0149] The second mode switching element T2 is connected between a VGH node to which a gate cutoff voltage VGH is applied and the first node n1, and is turned on in response to the gate-on voltage VGL of a second mode selection signal P_SEL. When the second mode switching element T2 is turned on, the gate cutoff voltage VGH is applied to the first node n1. The second mode switching element T2 includes a first electrode to which the gate cutoff voltage VGH is applied, a gate to which the second mode selection signal P_SEL is applied, and a second electrode connected to the first node n1.

[0150] The third mode switching element T3 is connected between the node to which the EM signal is applied and the second node n2, and conducts in response to the gate conduction voltage VGL of the second mode selection signal P_SEL. When the third mode switching element T3 conducts, the EM signal EM is applied as the second mode signal P to the second node n2. The third mode switching element T3 includes a first electrode to which the EM signal EM is applied, a gate to which the second mode selection signal P_SEL is applied, and a second electrode connected to the second node n2.

[0151] The fourth mode switching element T4 is connected between the VGH node to which the gate cutoff voltage VGH is applied and the second node n2, and conducts in response to the gate conduction voltage VGL of the first mode selection signal S_SEL. When the fourth mode switching element T4 conducts, the gate cutoff voltage VGH is applied to the second node n2. The fourth mode switching element T4 includes a first electrode to which the gate cutoff voltage VGH is applied, a gate to which the first mode selection signal S_SEL is applied, and a second electrode connected to the second node n2.

[0152] The pixel circuit can be driven in an initialization stage, a data writing and threshold voltage sampling stage, and a light emitting stage. Figures 12A to 14B is a diagram showing the initialization stage, the data writing and threshold voltage sampling stage, and the light emitting stage of the pixel circuit in the stage of the first mode (S mode).

[0153] In the first mode (S mode), the voltage of the first mode selection signal S_SEL is the gate conduction voltage VGL, and the voltage of the second mode selection signal P_SEL is the gate cutoff voltage VGH. Therefore, in the first mode (S mode), the first mode switching element T1 and the fourth mode switching element T4 conduct, while the second mode switching element T2 and the third mode switching element T3 are cutoff. As a result, in the first mode (S mode), the voltage of the EM signal EM is transmitted to the first node n1, and the second node n2 is maintained at the gate cutoff voltage VGH. The first mode signal S is the EM signal EM transmitted to the first node n1 in the first mode (S mode). The second mode signal P is the gate cutoff voltage VGH applied to the second node n2 in the first mode (S mode).

[0154] Figure 12A and 12B are a waveform and a circuit diagram, respectively, showing the initialization stage of the pixel circuit in the first mode (S mode). In the first mode (S mode), the initialization stage of the pixel circuit is executed during the first time period S1.

[0155] Referring to Figure 12A and 12B, during the first period S1 of the first mode (S mode), the voltage of the first scan signal SCAN1 is the gate cut-off voltage VGH, and the voltages of the second scan signal SCAN2 and the EM signal EM are the gate conduction voltage VGL. During the first period S1 of the first mode (S mode), the fourth switching element M4, the fifth switching element M5, the sixth switching element M6, and the seventh switching element M7 of the pixel circuit PXL are turned on. During the first period S1 of the first mode (S mode), the third switching element M3 is turned off. In the first period S1 of the first mode (S mode), the driving element DT is turned on.

[0156] During the first period S1 of the first mode (S mode), the first switching element M1 of the pixel circuit PXL is turned on in response to the gate conduction voltage VGL of the first mode signal S, and the second switching element M2 is turned off in response to the gate cut-off voltage VGH of the second mode signal P.

[0157] At the end of the first period S1 of the first mode (S mode), the reference voltage Vref is applied to the fourth to eighth nodes n4, n5, n6, n7, and n8 to initialize the capacitor Cst and the light-emitting elements EL1 and EL2. During the first period S1 of the first mode (S mode), the light-emitting elements EL1 and EL2 are in the off state of not emitting light.

[0158] Figure 13A and 13B are a waveform and a circuit diagram, respectively, which show the data writing and threshold voltage sampling phases of the pixel circuit in the first mode (S mode). In the first mode (S mode), the data writing and threshold voltage sampling phases of the pixel circuit are performed during the second period S2. In the first mode (S mode), the first mode switching element T1 and the fourth mode switching element T4 are turned on, while the second mode switching element T2 and the third mode switching element T3 are turned off. As a result, in the first mode (S mode), the voltage of the EM signal EM is transmitted to the first node n1, and the second node n2 is maintained at the gate cut-off voltage VGH.

[0159] Refer to Figure 13A and 13B, during the second period S2 of the first mode (S mode), the voltages of the first scan signal SCAN1 and the second scan signal SCAN2 are the gate-on voltage VGL, and the voltage of the EM signal EM is the gate-off voltage VGH. During the second period S2 of the first mode (S mode), the third switching element M3, the fourth switching element M4, the fifth switching element M5, and the sixth switching element M6 of the pixel circuit PXL are turned on, and the seventh switching element M7 is turned off. In the second period S2 of the first mode (S mode), the data voltage Vdata of the pixel data is applied to the fifth node n5. At the end of the second period S2 of the first mode (S mode), the voltage of the fifth node n5 is the data voltage Vdata, and the voltage of the fourth node n4 is the voltage VDD + Vth. Here, Vth is the threshold voltage of the driving element DT.

[0160] During the second period S2 of the first mode (S mode), the first switching element M1 of the pixel circuit PXL is turned off in response to the gate-off voltage VGH of the first mode signal S, and the second switching element M2 is in the off state according to the gate-off voltage VGH of the second mode signal P. During the second period S2 of the first mode (S mode), the light-emitting elements EL1 and EL2 are in the off state.

[0161] Figure 14A and 14B are a waveform and a circuit diagram, respectively, which show the light-emitting stage of the pixel circuit in the first mode (S mode). In the first mode (S mode), the light-emitting stage of the pixel circuit is executed during the third period S3. In the first mode (S mode), the first mode switching element T1 and the fourth mode switching element T4 are turned on, while the second mode switching element T2 and the third mode switching element T3 are turned off. As a result, in the first mode (S mode), the voltage of the EM signal EM is transmitted to the first node n1, and the second node n2 is maintained at the gate-off voltage VGH.

[0162] Refer to Figure 14A and 14B , during the third period S3 of the first mode (S mode), the voltages of the first scan signal SCAN1 and the second scan signal SCAN2 are the gate-off voltage VGH, and the voltage of the EM signal EM is the gate-on voltage VGL. During the third period S3 of the first mode (S mode), the seventh switching element M7 of the pixel circuit PXL is turned on, while the third switching element M3, the fourth switching element M4, the fifth switching element M5, and the sixth switching element M6 are turned off. At the end of the third period S3 of the first mode (S mode), the voltage of the fifth node n5 is the reference voltage Vref, and the voltage of the fourth node n4 is the voltage Vref - Vdata + VDD + Vth.

[0163] During the third period S3 of the first mode (S mode), the first switching element M1 of the pixel circuit PXL is turned on in response to the gate conduction voltage VGL of the first mode signal S, and the second switching element M2 is turned off according to the gate cut-off voltage VGH of the second mode signal P. During the third period S3 of the first mode (S mode), the current generated according to the gate-source voltage of the driving element DT is supplied to the first light-emitting element EL1 via the first switching element M1. Therefore, during the third period S3 of the first mode (S mode), the first light-emitting element EL1 can be lit by emitting light. During the third period S3 of the first mode (S mode), the second light-emitting element EL2 is in the off state.

[0164] Figures 15A to 17B FIG. is a diagram illustrating an initialization stage, a data writing and threshold voltage sampling stage, and a light-emitting stage of a pixel circuit in a second mode (P mode). In the second mode (P mode), the voltage of the first mode selection signal S_SEL is the gate cut-off voltage VGH, and the voltage of the second mode selection signal P_SEL is the gate conduction voltage VGL. Therefore, in the second mode (P mode), the first mode switching element T1 and the fourth mode switching element T4 are turned off, and the second mode switching element T2 and the third mode switching element T3 are turned on. As a result, in the second mode (P mode), the voltage of the EM signal EM is transmitted to the second node n2, and the first node n1 is maintained at the gate cut-off voltage VGH.

[0165] Figure 15A and 15B are a waveform and a circuit diagram, respectively, showing the initialization stage of the pixel circuit in the second mode (P mode). In the second mode (P mode), the initialization stage of the pixel circuit is performed during the first period P1.

[0166] Referring to Figure 15A and Figure 15B , during the first period P1 of the second mode (P mode), the voltage of the first scan signal SCAN1 is the gate cut-off voltage VGH, and the voltages of the second scan signal SCAN2 and the EM signal EM are the gate conduction voltage VGL. During the first period P1 of the second mode (P mode), the fourth switching element M4, the fifth switching element M5, the sixth switching element M6, and the seventh switching element M7 of the pixel circuit PXL are turned on. During the first period P1 of the second mode (P mode), the third switching element M3 is turned off. In the first period P1 of the second mode (P mode), the driving element DT is turned on.

[0167] During a first period P1 of the second mode (P mode), a second switching element M2 of the pixel circuit PXL is turned on in response to a gate conduction voltage VGL of the second mode signal P, and a first switching element M1 is turned off in response to a gate cut-off voltage VGH of the first mode signal S. Accordingly, at the end of the first period P1 of the second mode (P mode), a reference voltage Vref is applied to fourth to eighth nodes n4, n5, n6, n7, and n8 to initialize the capacitor Cst and light-emitting elements EL1 and EL2. During the first period P1 of the second mode (P mode), the light-emitting elements EL1 and EL2 are in a turned-off state where they do not emit light.

[0168] Figure 16A and 16B are a waveform and a circuit diagram, respectively, which illustrate a data writing and threshold voltage sampling phase of the pixel circuit in the second mode (P mode). In the second mode (P mode), the data writing and threshold voltage sampling phase of the pixel circuit is performed during a second period P2. In the second mode (P mode), a first mode switching element T1 and a fourth mode switching element T4 are turned off, while a second mode switching element T2 and a third mode switching element T3 are turned on. As a result, in the second mode (P mode), a voltage of the EM signal EM is transmitted to a second node n2, and a first node n1 is maintained at the gate cut-off voltage VGH.

[0169] Referring Figure 16A and 16B , during the second period P2 of the second mode (P mode), voltages of a first scan signal SCAN1 and a second scan signal SCAN2 are the gate conduction voltage VGL, and a voltage of the EM signal EM is the gate cut-off voltage VGH. During the second period P2 of the second mode (P mode), third, fourth, fifth, and sixth switching elements M3, M4, M5, and M6 of the pixel circuit PXL are turned on, and a seventh switching element M7 is turned off. In the second period P2 of the second mode (P mode), a data voltage Vdata of pixel data is applied to a fifth node n5. At the end of the second period P2 of the second mode (P mode), a voltage of the fifth node n5 is the data voltage Vdata, and a voltage of a fourth node n4 is a voltage VDD + Vth. Here, Vth is a threshold voltage of a driving element DT.

[0170] During the second period P2 of the second mode (P mode), a first switching element M1 of the pixel circuit PXL is turned off in response to the gate cut-off voltage VGH of the first mode signal S, and a second switching element M2 is in a turned-off state according to the gate cut-off voltage VGH of the second mode signal P. During the second period P2 of the second mode (P mode), the light-emitting elements EL1 and EL2 are in a turned-off state.

[0171] Figure 17A and17B They are a waveform diagram and a circuit diagram, which show the light-emitting stage of the pixel circuit in the second mode (P mode). In the second mode (P mode), the light-emitting stage of the pixel circuit is executed during the third time period P3. In the second mode (P mode), the first-mode switching element T1 and the fourth-mode switching element T4 are turned off, while the second-mode switching element T2 and the third-mode switching element T3 are turned on. As a result, in the second mode (P mode), the voltage of the EM signal EM is transmitted to the second node n2, and the first node n1 is maintained at the gate cut-off voltage VGH.

[0172] Referring to Figure 17A and 17B , during the third time period P3 of the second mode (P mode), the voltages of the first scan signal SCAN1 and the second scan signal SCAN2 are the gate cut-off voltage VGH, and the voltage of the EM signal EM is the gate conduction voltage VGL. During the third time period P3 of the second mode (P mode), the seventh switching element M7 of the pixel circuit PXL is turned on, while the third switching element M3, the fourth switching element M4, the fifth switching element M5, and the sixth switching element M6 are turned off. At the end of the third time period P3 of the second mode (P mode), the voltage of the fifth node n5 is the reference voltage Vref, and the voltage of the fourth node n4 is the voltage Vref - Vdata + VDD + Vth.

[0173] During the third time period P3 of the second mode (P mode), the second switching element M2 of the pixel circuit PXL is turned on in response to the gate conduction voltage VGL of the second mode signal P, and the first switching element M1 is turned off according to the gate cut-off voltage VGH of the first mode signal S. During the third time period P3 of the second mode (P mode), the current generated according to the gate-source voltage of the driving element DT is supplied to the second light-emitting element EL2 via the second switching element M2. Therefore, during the third time period P3 of the second mode (P mode), the second light-emitting element EL2 emits light and is turned on, while the first light-emitting element EL1 is in the off state.

[0174] Figures 18A to 23B is a diagram illustrating the operation of the pixel circuit and the mode selection circuit in a stage according to another embodiment of the present invention. Figures 18A to 20B An example of the operation of the pixel circuit and the mode selection circuit in the first mode (S mode) is illustrated. Figures 21A to 23B An example of the operation of the pixel circuit and the mode selection circuit in the second mode (P mode) is illustrated. In Figures 18A to 23B , a detailed description of components that are substantially the same as those in the above embodiment may be omitted.

[0175] Referring to Figures 18A to 23B, the pixel circuit includes: a first light-emitting element EL1; a second light-emitting element EL2; a driving element DT; a capacitor Cst; and a plurality of switching elements M1 to M72. The driving element DT and the switching elements M1 to M72 can be implemented as p-channel transistors, but are not limited thereto.

[0176] The first light-emitting element EL1 includes an anode connected to the seventh node n7 and a cathode to which a cathode voltage VSS is applied. The second light-emitting element EL2 includes an anode connected to the eighth node n8 and a cathode to which a cathode voltage VSS is applied. The first light-emitting element EL1 can be driven by a current from the driving element DT to emit light in a first mode (S mode). The second light-emitting element EL2 can be driven by a current from the driving element DT to emit light in a second mode (P mode). The driving element DT includes a first electrode to which a pixel driving voltage VDD is applied, a gate connected to the fourth node n4, and a second electrode connected to the third node n3.

[0177] The first switching element M1 includes: a first electrode connected to the third node n3; a gate connected to the first node n1 to which a first mode signal S is applied; and a second electrode connected to the seventh node n7. The second switching element M2 includes: a first electrode connected to the third node n3; a gate connected to the second node n2 to which a second mode signal P is applied; and a second electrode connected to the eighth node n8.

[0178] The third switching element M3 includes a first electrode to which a data voltage Vdata is applied, a gate to which a first scan signal SCAN1 is applied, and a second electrode connected to the fifth node n5. The fourth switching element M4 includes a first electrode connected to the third node n3, a gate to which a second scan signal SCAN2 is applied, and a second electrode connected to the fourth node n4.

[0179] The fifth switching element M5 includes a first electrode connected to the sixth node n6, a gate to which a second scan signal SCAN2 is applied, and a second electrode connected to the seventh node n7. The sixth switching element M6 includes a first electrode connected to the sixth node n6, a gate to which a second scan signal SCAN2 is applied, and a second electrode connected to the eighth node n8.

[0180] The 7-1 switching element M71 is connected between the fifth node n5 and the sixth node n6 and is turned on in response to a gate conduction voltage VGL of the first mode signal S. When the 7-1 switching element M71 is turned on, the fifth node n5 can be electrically connected to the sixth node n6. The 7-1 switching element M71 includes a first electrode electrically connected to the fifth node n5, a gate electrically connected to the first node n1 to which a first mode signal S is applied, and a second electrode electrically connected to the sixth node n6.

[0181] The 7-2nd switching element M72 is connected between the fifth node n5 and the sixth node n6 and is turned on in response to the gate-on voltage VGL of the second mode signal P. When the 7-2nd switching element M72 is turned on, the fifth node n5 can be electrically connected to the sixth node n6. The 7-2nd switching element M72 includes a first electrode electrically connected to the fifth node n5, a gate electrically connected to the second node n2 to which the second mode signal P is applied, and a second electrode electrically connected to the sixth node n6.

[0182] The mode selection circuit SPM includes a first mode switching element T1, a second mode switching element T2, a third mode switching element T3, and a fourth mode switching element T4. The first mode switching element T1, the second mode switching element T2, the third mode switching element T3, and the fourth mode switching element T4 can be implemented as p-channel transistors, but are not limited thereto.

[0183] The first mode switching element T1 includes a first electrode to which the EM signal EM is applied, a gate to which the first mode selection signal S_SEL is applied, and a second electrode connected to the first node n1. The second mode switching element T2 includes a first electrode to which the gate cut-off voltage VGH is applied, a gate to which the second mode selection signal P_SEL is applied, and a second electrode connected to the first node n1.

[0184] The third mode switching element T3 includes a first electrode to which the EM signal EM is applied, a gate to which the second mode selection signal P_SEL is applied, and a second electrode connected to the second node n2. The fourth mode switching element T4 includes a first electrode to which the gate cut-off voltage VGH is applied, a gate to which the first mode selection signal S_SEL is applied, and a second electrode connected to the second node n2.

[0185] The pixel circuit can be driven in an initialization stage, a data writing and threshold voltage sampling stage, and a light emitting stage. Figures 18A to 20B is a diagram showing the initialization stage, the data writing and threshold voltage sampling stage, and the light emitting stage of the pixel circuit in the stage of the first mode (S mode).

[0186] In the first mode (S mode), the voltage of the first mode selection signal S_SEL is the gate-on voltage VGL, and the voltage of the second mode selection signal P_SEL is the gate-off voltage VGH. Therefore, in the first mode (S mode), the first mode switching element T1 and the fourth mode switching element T4 are turned on, while the second mode switching element T2 and the third mode switching element T3 are turned off. As a result, in the first mode (S mode), the voltage of the EM signal EM is transmitted to the first node n1, and the second node n2 is maintained at the gate-off voltage VGH. The first mode signal S is the EM signal EM transmitted to the first node n1 in the first mode (S mode). The second mode signal P is the gate-off voltage VGH applied to the second node n2 in the first mode (S mode).

[0187] Figure 18A and 18B are a waveform and a circuit diagram, respectively, which show the initialization phase of the pixel circuit in the first mode (S mode). In the first mode (S mode), the initialization phase of the pixel circuit is executed during the first time period S1.

[0188] Referring to Figure 18A and 18B , during the first time period S1 of the first mode (S mode), the voltage of the first scan signal SCAN1 is the gate-off voltage VGH, and the voltages of the second scan signal SCAN2 and the EM signal EM are the gate-on voltage VGL. During the first time period S1 of the first mode (S mode), the fourth switching element M4, the fifth switching element M5, the sixth switching element M6, and the 7-1 switching element M71 of the pixel circuit PXL are turned on. During the first time period S1 of the first mode (S mode), the 7-1 switching element M71 is turned on in response to the gate-on voltage VGL of the first mode signal S. During the first time period S1 of the first mode (S mode), the third switching element M3 and the 7-2 switching element M72 are turned off. The 7-2 switching element M72 is turned off in response to the gate-off voltage VGH of the second mode signal P during the first time period S1 of the first mode (S mode). In the first time period S1 of the first mode (S mode), the driving element DT is turned on.

[0189] During the first time period S1 of the first mode (S mode), the first switching element M1 of the pixel circuit PXL is turned on in response to the gate-on voltage VGL of the first mode signal S, and the second switching element M2 is turned off in response to the gate-off voltage VGH of the second mode signal P.

[0190] At the end of the first period S1 of the first mode (S mode), a reference voltage Vref is applied to the fourth to eighth nodes n4, n5, n6, n7, and n8 to initialize the capacitor Cst and the light-emitting elements EL1 and EL2. During the first period S1 of the first mode (S mode), the light-emitting elements EL1 and EL2 are in an off state where they do not emit light.

[0191] Figure 19A and 19B are a waveform and a circuit diagram, respectively, which show the data writing and threshold voltage sampling phases of the pixel circuit in the first mode (S mode). In the first mode (S mode), the data writing and threshold voltage sampling phases of the pixel circuit are performed during the second period S2. In the first mode (S mode), the first mode switching element T1 and the fourth mode switching element T4 are turned on, while the second mode switching element T2 and the third mode switching element T3 are turned off. As a result, in the first mode (S mode), the voltage of the EM signal EM is transmitted to the first node n1, and the second node n2 is maintained at the gate cut-off voltage VGH.

[0192] Refer to Figure 19A and 19B . During the second period S2 of the first mode (S mode), the voltages of the first scan signal SCAN1 and the second scan signal SCAN2 are the gate conduction voltage VGL, and the voltage of the EM signal EM is the gate cut-off voltage VGH. During the second period S2 of the first mode (S mode), the third switching element M3, the fourth switching element M4, the fifth switching element M5, and the sixth switching element M6 of the pixel circuit PXL are turned on, and the 7-1 switching element M71 and the 7-2 switching element M72 are turned off. The 7-1 switching element M71 is turned off in response to the gate cut-off voltage VGH of the first mode signal S during the second period S2 of the first mode (S mode). The 7-2 switching element M72 is turned off in response to the gate cut-off voltage VGH of the second mode signal P during the second period S2 of the first mode (S mode).

[0193] In the second period S2 of the first mode (S mode), the data voltage Vdata of the pixel data is applied to the fifth node n5. At the end of the second period S2 of the first mode (S mode), the voltage of the fifth node n5 is the data voltage Vdata, and the voltage of the fourth node n4 is the voltage VDD + Vth. Here, Vth is the threshold voltage of the driving element DT.

[0194] During the second period S2 of the first mode (S mode), the first switching element M1 of the pixel circuit PXL is turned off in response to the gate cut-off voltage VGH of the first mode signal S, and the second switching element M2 is in the off state according to the gate cut-off voltage VGH of the second mode signal P. During the second period S2 of the first mode (S mode), the light-emitting elements EL1 and EL2 are in the off state.

[0195] Figure 20A and 20B are a waveform and a circuit diagram, respectively, which show the light-emitting stage of the pixel circuit in the first mode (S mode). In the first mode (S mode), the light-emitting stage of the pixel circuit is performed during the third period S3. In the first mode (S mode), the first mode switching element T1 and the fourth mode switching element T4 are turned on, while the second mode switching element T2 and the third mode switching element T3 are turned off. As a result, in the first mode (S mode), the voltage of the EM signal EM is transmitted to the first node n1, and the second node n2 is maintained at the gate cut-off voltage VGH.

[0196] Refer to Figure 20A and 20B . During the third period S3 of the first mode (S mode), the voltages of the first scan signal SCAN1 and the second scan signal SCAN2 are the gate cut-off voltage VGH, and the voltage of the EM signal EM is the gate conduction voltage VGL. During the third period S3 of the first mode (S mode), the 7-1 switching element M71 of the pixel circuit PXL is turned on in response to the gate conduction voltage VGL of the first mode signal S, while the third switching element M3, the fourth switching element M4, the fifth switching element M5, and the sixth switching element M6 are turned off. The 7-2 switching element M72 is turned off during the third period S3 of the first mode (S mode) in response to the gate cut-off voltage VGH of the second mode signal P. At the end of the third period S3 of the first mode (S mode), the voltage of the fifth node n5 is the reference voltage Vref, and the voltage of the fourth node n4 is the voltage Vref - Vdata + VDD + Vth.

[0197] During the third period S3 of the first mode (S mode), the first switching element M1 of the pixel circuit PXL is turned on in response to the gate conduction voltage VGL of the first mode signal S, and the second switching element M2 is in the off state according to the gate cut-off voltage VGH of the second mode signal P. During the third period S3 of the first mode (S mode), the current generated according to the gate-source voltage of the driving element DT is supplied to the first light-emitting element EL1 via the first switching element M1. Therefore, during the third period S3 of the first mode (S mode), the first light-emitting element EL1 can be lit by emitting light. During the third period S3 of the first mode (S mode), the second light-emitting element EL2 is in the off state.

[0198] Figures 21A to 23B It is a diagram showing the initialization phase, data writing and threshold voltage sampling phase, and light emission phase of the pixel circuit in the second mode (P mode).

[0199] In the second mode (P mode), the voltage of the first mode selection signal S_SEL is the gate cut-off voltage VGH, and the voltage of the second mode selection signal P_SEL is the gate conduction voltage VGL. Therefore, in the second mode (P mode), the second mode switching element T2 and the third mode switching element T3 are turned on, while the first mode switching element T1 and the fourth mode switching element T4 are turned off. As a result, in the second mode (P mode), the voltage of the EM signal EM is transmitted to the second node n2, and the first node n1 is maintained at the gate cut-off voltage VGH. The second mode signal P is the EM signal EM transmitted to the second node n2 in the second mode (P mode). The first mode signal S is the gate cut-off voltage VGH applied to the first node n1 in the second mode (P mode).

[0200] Figure 21A and 21B are a waveform diagram and a circuit diagram, respectively, showing the initialization phase of the pixel circuit in the second mode (P mode). In the second mode (P mode), the initialization phase of the pixel circuit is executed during the first period P1.

[0201] Referring to Figure 21A and Figure 21B , during the first period P1 of the second mode (P mode), the voltage of the first scan signal SCAN1 is the gate cut-off voltage VGH, and the voltages of the second scan signal SCAN2 and the EM signal EM are the gate conduction voltage VGL. During the first period P1 of the second mode (P mode), the fourth switching element M4, the fifth switching element M5, the sixth switching element M6, and the 7-2 switching element M72 of the pixel circuit PXL are turned on. The 7-2 switching element M72 is turned on in response to the gate conduction voltage VGL of the second mode signal P during the first period P1 of the second mode (P mode). During the first period P1 of the second mode (P mode), the third switching element M3 and the 7-1 switching element M71 are turned off. The 7-1 switching element M71 is turned off in response to the gate cut-off voltage VGH of the first mode signal S during the first period P1 of the second mode (P mode). In the first period P1 of the second mode (P mode), the driving element DT is turned on.

[0202] During the first period P1 of the second mode (P mode), the second switching element M2 of the pixel circuit PXL is turned on in response to the gate conduction voltage VGL of the second mode signal P, and the first switching element M1 is turned off in response to the gate cut-off voltage VGH of the first mode signal S.

[0203] At the end of the first period P1 of the second mode (P mode), a reference voltage Vref is applied to the fourth to eighth nodes n4, n5, n6, n7, and n8 to initialize the capacitor Cst and the light-emitting elements EL1 and EL2. During the first period P1 of the second mode (P mode), the light-emitting elements EL1 and EL2 are in an off state where they do not emit light.

[0204] Figure 22A and 22B are a waveform and a circuit diagram, respectively, which illustrate the data writing and threshold voltage sampling phases of the pixel circuit in the second mode (P mode). In the second mode (P mode), the data writing and threshold voltage sampling phases of the pixel circuit are performed during the second period P2. In the second mode (P mode), the second mode switching element T2 and the third mode switching element T3 are turned on, while the first mode switching element T1 and the fourth mode switching element T4 are turned off. As a result, in the second mode (P mode), the voltage of the EM signal EM is transmitted to the second node n2, and the first node n1 is maintained at the gate cut-off voltage VGH.

[0205] Referring to Figure 22A and 22B , during the second period P2 of the second mode (P mode), the voltages of the first scan signal SCAN1 and the second scan signal SCAN2 are the gate conduction voltage VGL, and the voltage of the EM signal EM is the gate cut-off voltage VGH. During the second period P2 of the second mode (P mode), the third switching element M3, the fourth switching element M4, the fifth switching element M5, and the sixth switching element M6 of the pixel circuit PXL are turned on, and the 7-1 switching element M71 and the 7-2 switching element M72 are turned off. The 7-1 switching element M71 is turned off in response to the gate cut-off voltage VGH of the first mode signal S during the second period P2 of the second mode (P mode). The 7-2 switching element M72 is turned off in response to the gate cut-off voltage VGH of the second mode signal P during the second period P2 of the second mode (P mode).

[0206] In the second period P2 of the second mode (P mode), the data voltage Vdata of the pixel data is applied to the fifth node n5. At the end of the second period P2 of the second mode (P mode), the voltage of the fifth node n5 is the data voltage Vdata, and the voltage of the fourth node n4 is the voltage VDD + Vth. Here, Vth is the threshold voltage of the driving element DT.

[0207] During a second period P2 of the second mode (P mode), a first switching element M1 of a pixel circuit PXL is turned off in response to a gate cut-off voltage VGH of a first mode signal S, and a second switching element M2 is in a cut-off state according to the gate cut-off voltage VGH of a second mode signal P. During the second period P2 of the second mode (P mode), light-emitting elements EL1 and EL2 are in an off state.

[0208] Figure 23A and 23B are a waveform and a circuit diagram, respectively, which show a light-emitting stage of a pixel circuit in the second mode (P mode). In the second mode (P mode), the light-emitting stage of the pixel circuit is executed during a third period P3. In the second mode (P mode), a second mode switching element T2 and a third mode switching element T3 are turned on, while a first mode switching element T1 and a fourth mode switching element T4 are turned off. As a result, in the second mode (P mode), a voltage of an EM signal EM is transmitted to a second node n2, and a first node n1 is held at the gate cut-off voltage VGH.

[0209] Refer to Figure 23A and 23B , during a third period P3 of the second mode (P mode), voltages of a first scan signal SCAN1 and a second scan signal SCAN2 are the gate cut-off voltage VGH, and a voltage of the EM signal EM is the gate conduction voltage VGL. During the third period P3 of the second mode (P mode), a 7-2 switching element M72 of the pixel circuit PXL is turned on in response to the gate conduction voltage VGL of the second mode signal P, while a third switching element M3, a fourth switching element M4, a fifth switching element M5, and a sixth switching element M6 are turned off. A 7-1 switching element M71 is turned off according to the gate cut-off voltage VGH of the first mode signal S during the third period P3 of the second mode (P mode). At the end of the third period P3 of the second mode (P mode), a voltage of a fifth node n5 is a reference voltage Vref, and a voltage of a fourth node n4 is a voltage Vref - Vdata + VDD + Vth.

[0210] During the third period P3 of the second mode (P mode), a second switching element M2 of the pixel circuit PXL is turned on in response to the gate conduction voltage VGL of the second mode signal P, and a first switching element M1 is in a cut-off state according to the gate cut-off voltage VGH of the first mode signal S. During the third period P3 of the second mode (P mode), a current generated according to a gate-source voltage of a driving element DT is supplied to a second light-emitting element EL2 via the second switching element M2. Therefore, during the third period P3 of the second mode (P mode), the second light-emitting element EL2 is lit, and the first light-emitting element EL1 is in an off state.

[0211] Figures 24A to 29BIt is a diagram illustrating the operation of a pixel circuit and a mode selection circuit in a stage according to another embodiment of the present invention. Figures 24A to 28B An example of the operation of the pixel circuit and the mode selection circuit in the first mode (S mode) is illustrated. Figures 29A to 29B An example of the operation of the pixel circuit and the mode selection circuit in the light emission stage of the second mode (P mode) is illustrated. The pixel circuit according to the present embodiment can be driven at a variable refresh rate (VRR) under the control of the timing controller 130. The timing controller 130 can reduce the power consumption of the display device by analyzing the input image and reducing the refresh rate when the input image has not changed for a preset amount of time. The timing controller 130 can reduce the refresh rate of the pixels when the display device is in the standby mode or in response to a user command. The refresh rate can be reduced on the always-on display (AOD) screen. The AOD screen is a smaller pixel area in the display area AA where preset information, such as brief information such as remaining battery level, time, etc., is displayed in the standby mode.

[0212] Referring to Figures 24A to 29B , the pixel circuit includes: a first light-emitting element EL1; a second light-emitting element EL2; a driving element DT; a capacitor Cst; and a plurality of switching elements M1, M2, M33 to M39. The driving element DT and the switching elements M1, M2, M33, M35, M36, M38, and M39 can be implemented as p-channel transistors. The switching elements M34 and M37 can be implemented as n-channel transistors. The switching elements M1, M2, M33, M35, M36, M38, and M39 implemented as p-channel transistors can be turned on in response to a low gate voltage VGL and turned off in response to a high gate voltage VGH.

[0213] The switching elements M34 and M37 implemented as n-channel transistors can be turned on in response to a high gate voltage VGH and turned off in response to a low gate voltage VGL. In Figures 24A to 29B , considering the channel type of the transistor, the gate on / off voltage is described as the high / low gate voltage.

[0214] The pixel circuit can be connected to a VDD node to which a pixel driving voltage VDD is applied, a VSS node to which a cathode voltage VSS is applied, an INI node to which an initialization voltage Vini is applied, an OBS node to which a first compensation voltage VOBS is applied, and a VAR node to which a second compensation voltage VAR is applied. The VDD, VSS, INI, OBS, and VAR nodes can be connected to corresponding power lines and can be commonly connected to all pixels. The pixel circuit can be connected to a mode selection circuit SPM via a data line to which a data voltage Vdata is applied, gate lines to which gate signals SCAN1, SCAN2, SCAN3, SCAN4, and EM are applied, and a first node n1 and a second node n2. The compensation voltages VOBS and VAR can prevent brightness fluctuations from occurring when the refresh rate of the pixel changes.

[0215] The first light-emitting element EL1 includes an anode connected to a sixth node n36 and a cathode to which a cathode voltage VSS is applied. The second light-emitting element EL2 includes an anode connected to a seventh node n37 and a cathode to which a cathode voltage VSS is applied. The first light-emitting element EL1 can be driven by a current from a driving element DT to emit light in a first mode (S mode). The second light-emitting element EL2 can be driven by a current from the driving element DT to emit light in a second mode (P mode).

[0216] The driving element DT includes a first electrode connected to a fifth node n35, a second electrode connected to a third node n33, and a gate connected to a fourth node n34. The driving element DT generates a current according to the gate-source voltage such that the first light-emitting element EL1 is driven in the first mode (S mode) and the second light-emitting element EL2 is driven in the second mode (P mode). A capacitor Cst is connected between the VDD node to which the pixel driving voltage VDD is applied and the fourth node n34.

[0217] The first switching element M1 is connected between the third node n33 and the sixth node n36 and conducts in response to a gate low voltage VGL of a first mode signal S applied via the first node n1. When the first switching element M1 conducts, the third node n33 can be electrically connected to the sixth node n36. The first switching element M1 includes: a first electrode connected to the third node n33; a gate connected to the first node n1 to which the first mode signal S is applied; and a second electrode connected to the sixth node n36.

[0218] The second switching element M2 is connected between the third node n33 and the seventh node n37, and is turned on in response to the gate low voltage VGL of the second mode signal P applied via the second node n2. When the second switching element M2 is turned on, the third node n33 can be electrically connected to the seventh node n37. The second switching element M2 includes: a first electrode connected to the third node n33; a gate connected to the second node n2 to which the second mode signal P is applied; and a second electrode connected to the seventh node n37.

[0219] The third switching element M33 is connected between the data line to which the pixel data data voltage Vdata is applied and the fifth node n35, and is turned on in response to the gate low voltage VGL of the second scan signal SCAN2. When the third switching element M33 is turned on, the data voltage Vdata can be applied to the fifth node n35. The third switching element M33 includes a first electrode to which the data voltage Vdata is applied, a gate to which the second scan signal SCAN2 is applied, and a second electrode connected to the fifth node n35.

[0220] The fourth switching element M34 is connected between the third node n33 and the fourth node n34, and is turned on in response to the gate high voltage VGH of the first scan signal SCAN1. When the fourth switching element M34 is turned on, the third node n33 can be electrically connected to the fourth node n34. The fourth switching element M34 includes a first electrode connected to the third node n33, a gate to which the first scan signal SCAN1 is applied, and a second electrode connected to the fourth node n34.

[0221] The fifth switching element M35 is connected between the VAR node to which the second compensation voltage VAR is applied and the sixth node n36, and is turned on in response to the gate low voltage VGL of the third scan signal SCAN3. When the fifth switching element M35 is turned on, the second compensation voltage VAR can be applied to the sixth node n36. The fifth switching element M35 includes a first electrode electrically connected to the VAR node to which the second compensation voltage VAR is applied, a gate to which the third scan signal SCAN3 is applied, and a second electrode connected to the sixth node n36.

[0222] The sixth switching element M36 is connected between the VAR node to which the second compensation voltage VAR is applied and the seventh node n37, and is turned on in response to the gate low voltage VGL of the third scan signal SCAN3. When the sixth switching element M36 is turned on, the second compensation voltage VAR can be applied to the seventh node n37. The sixth switching element M36 includes a first electrode to which the second compensation voltage VAR is applied, a gate to which the third scan signal SCAN3 is applied, and a second electrode connected to the seventh node n37.

[0223] The seventh switching element M37 is connected between the INI node to which the initialization voltage Vini is applied and the fourth node n34, and is turned on in response to the gate high voltage VGH of the fourth scan signal SCAN4. When the seventh switching element M37 is turned on, the initialization voltage Vini can be applied to the fourth node n34. The seventh switching element M37 includes a first electrode to which the initialization voltage Vini is applied, a gate to which the fourth scan signal SCAN4 is applied, and a second electrode connected to the fourth node n34.

[0224] The eighth switching element M38 is connected between the OBS node to which the first compensation voltage VOBS is applied and the fifth node n35, and is turned on in response to the gate low voltage VGL of the third scan signal SCAN3. When the eighth switching element M38 is turned on, the first compensation voltage VOBS can be applied to the fifth node n35. The eighth switching element M38 includes a first electrode to which the first compensation voltage VOBS is applied, a gate to which the third scan signal SCAN3 is applied, and a second electrode connected to the fifth node n35.

[0225] The ninth switching element M39 is connected between the VDD node to which the pixel driving voltage VDD is applied and the fifth node n35, and is turned on in response to the gate low voltage VGL of the EM signal EM. When the ninth switching element M39 is turned on, the pixel driving voltage VDD can be applied to the fifth node n35. The ninth switching element M39 includes a first electrode connected to the VDD node to which the pixel driving voltage VDD is applied, a gate to which the EM signal EM is applied, and a second electrode connected to the fifth node n35.

[0226] The mode selection circuit SPM includes a first mode switching element T1, a second mode switching element T2, a third mode switching element T3, and a fourth mode switching element T4. The first mode switching element T1, the second mode switching element T2, the third mode switching element T3, and the fourth mode switching element T4 can be implemented as p-channel transistors, but are not limited thereto.

[0227] The first mode switching element T1 is connected between the node to which the EM signal is applied and the first node n1, and is turned on in response to the gate low voltage VGL of the first mode selection signal S_SEL. The node to which the EM signal EM is applied can be connected to the output terminal of the third gate driver 123. When the first mode switching element T1 is turned on, the EM signal EM is applied to the first node n1 as the first mode signal S. The first mode switching element T1 includes a first electrode to which the EM signal EM is applied, a gate to which the first mode selection signal S_SEL is applied, and a second electrode connected to the first node n1.

[0228] The second-mode switching element T2 is connected between the VGH node to which a high gate voltage VGH is applied and the first node n1, and is turned on in response to the low gate voltage VGL of the second-mode selection signal P_SEL. When the second-mode switching element T2 is turned on, the high gate voltage VGH can be applied to the first node n1, so that the first switching element M1 is turned off. The second-mode switching element T2 includes a first electrode to which the high gate voltage VGH is applied, a gate to which the second-mode selection signal P_SEL is applied, and a second electrode connected to the first node n1.

[0229] The third-mode switching element T3 is connected between the node to which the EM signal is applied and the second node n2, and is turned on in response to the low gate voltage VGL of the second-mode selection signal P_SEL. When the third-mode switching element T3 is turned on, the EM signal EM is applied to the second node n2 as the second-mode signal P. The third-mode switching element T3 includes a first electrode to which the EM signal EM is applied, a gate to which the second-mode selection signal P_SEL is applied, and a second electrode connected to the second node n2.

[0230] The fourth-mode switching element T4 is connected between the VGH node to which a high gate voltage VGH is applied and the second node n2, and is turned on in response to the low gate voltage VGL of the first-mode selection signal S_SEL. When the fourth-mode switching element T4 is turned on, the high gate voltage VGH can be applied to the second node n2, so that the second switching element M2 is turned off. The fourth-mode switching element T4 includes a first electrode to which the high gate voltage VGH is applied, a gate to which the first-mode selection signal S_SEL is applied, and a second electrode connected to the second node n2.

[0231] Figures 24A to 29B The pixel circuit shown can be driven in a first reset phase, an initialization phase, a data write and threshold voltage sampling phase, a second reset phase, and a light-emitting phase. Figures 24A to 28B is a diagram illustrating the operation of the pixel circuit in the stages of the first mode (S mode). In the light-emitting phase of the first mode (S mode), the first light-emitting element EL1 emits light. Figure 29A and 29B is a diagram illustrating the light-emitting phase of the pixel circuit in the second mode (P mode).

[0232] In the first mode (S mode), the voltage of the first mode selection signal S_SEL is the gate low voltage VGL, and the voltage of the second mode selection signal P_SEL is the gate high voltage VGH. Therefore, in the first mode (S mode), the first mode switching element T1 and the fourth mode switching element T4 are turned on, while the second mode switching element T2 and the third mode switching element T3 are turned off. As a result, in the first mode (S mode), the voltage of the EM signal EM is transmitted to the first node n1, and the second node n2 is maintained at the gate high voltage VGH. The first mode signal S is the EM signal EM transmitted to the first node n1 in the first mode (S mode). The second mode signal P is the gate high voltage VGH applied to the second node n2 in the first mode (S mode).

[0233] Figure 24A and 24B are a waveform and a circuit diagram, respectively, which show the first reset stage of the pixel circuit in the first mode (S mode). The first reset stage of the first mode (S mode) is executed during the first time period S31.

[0234] Referring to Figure 24A and 24B , during the first time period S31 of the first mode (S mode), the voltages of the first scan signal SCAN1, the third scan signal SCAN3, and the fourth scan signal SCAN4 are the gate low voltage VGL, and the voltages of the second scan signal SCAN2 and the EM signal EM are the gate high voltage VGH. During the first time period S31 of the first mode (S mode), the voltages of the first mode signal S and the second mode signal P are the gate high voltage VGH.

[0235] During the first time period S31 of the first mode (S mode), the fifth switching element M35, the sixth switching element M36, and the eighth switching element M38 of the pixel circuit PXL are turned on, and the other switching elements M1, M2, M33, M34, M37, and M39 are turned off. During the first time period S31 of the first mode (S mode), the first compensation voltage VOBS is applied to the fifth node n35 to turn on the driving element DT. During the first time period S31 of the first mode (S mode), the second compensation voltage VAR is applied to the sixth node n36 and the seventh node n37 via the turned-on fifth switching element M35 and sixth switching element M36. During the first time period S31 of the first mode (S mode), the light-emitting elements EL1 and EL2 are in the off state.

[0236] Figure 25A and 25BThey are a waveform and a circuit diagram, respectively, which show the initialization phase of the pixel circuit in the first mode (S mode). The initialization phase of the first mode (S mode) is executed during the second period S32. In the first mode (S mode), the first mode switching element T1 and the fourth mode switching element T4 are turned on, while the second mode switching element T2 and the third mode switching element T3 are turned off. As a result, in the first mode (S mode), the voltage of the EM signal EM is transmitted to the first node n1, while the second node n2 is maintained at the gate high voltage VGH.

[0237] Refer to Figure 25A and 25B , during the second period S32 of the first mode (S mode), the voltages of the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, the fourth scan signal SCAN4, and the EM signal EM are the gate high voltage VGH. During the second period S32 of the first mode (S mode), the voltages of the first mode signal S and the second mode signal P are the gate high voltage VGH.

[0238] During the second period S32 of the first mode (S mode), the fourth switching element M34 and the seventh switching element M37 of the pixel circuit are turned on, and the other switching elements M1, M2, M33, M35, M36, M38, and M39 are turned off. During the second period S32 of the first mode (S mode), the initialization voltage Vini is applied to the fourth node n34 to initialize the capacitor Cst. During the second period S32 of the first mode (S mode), the light-emitting elements EL1 and EL2 are in the off state.

[0239] Figure 26A and 26B They are a waveform and a circuit diagram, respectively, which show the data writing and threshold voltage sampling phases of the pixel circuit in the first mode (S mode). The data writing and threshold voltage sampling phases of the first mode (S mode) are executed during the third period S33. In the first mode (S mode), the first mode switching element T1 and the fourth mode switching element T4 are turned on, while the second mode switching element T2 and the third mode switching element T3 are turned off. As a result, in the first mode (S mode), the voltage of the EM signal EM is transmitted to the first node n1, while the second node n2 is maintained at the gate high voltage VGH.

[0240] Refer to Figure 26A and 26B, during the third period S33 of the first mode (S mode), the voltages of the first scan signal SCAN1 and the third scan signal SCAN3 are the gate high voltage VGH, and the voltages of the second scan signal SCAN2 and the fourth scan signal SCAN4 are the gate low voltage VGL. During the third period S33 of the first mode (S mode), the voltage of the EM signal EM is the gate high voltage VGH. During the third period S33 of the first mode (S mode), the voltages of the first mode signal S and the second mode signal P are the gate high voltage VGH.

[0241] During the third period S33 of the first mode (S mode), the third switching element M33 and the fourth switching element M34 of the pixel circuit PXL are turned on, while the other switching elements M1, M2, M35, M36, M37, M38, and M39 are turned off. At the end of the third period S33 of the first mode (S mode), the voltages of the third node n33 and the fifth node n35 are the data voltage Vdata, and the voltage of the fourth node n34 is the voltage Vdata + Vth. During the third period S33 of the first mode (S mode), the light-emitting elements EL1 and EL2 are turned off.

[0242] Figure 27A and 27B are a waveform and a circuit diagram, respectively, which show the second reset stage of the pixel circuit in the first mode (S mode). The second reset stage of the first mode (S mode) is executed during the fourth period S34.

[0243] Refer to Figure 27A and 27B , during the fourth period S34 of the first mode (S mode), the voltages of the first scan signal SCAN1, the third scan signal SCAN3, and the fourth scan signal SCAN4 are the gate low voltage VGL, and the voltages of the second scan signal SCAN2 and the EM signal EM are the gate high voltage VGH. During the fourth period S34 of the first mode (S mode), the voltages of the first mode signal S and the second mode signal P are the gate high voltage VGH.

[0244] During the fourth period S34 of the first mode (S mode), the fifth switching element M35, the sixth switching element M36, and the eighth switching element M38 of the pixel circuit PXL are turned on, and the other switching elements M1, M2, M33, M34, M37, and M39 are turned off. During the fourth period S34 of the first mode (S mode), the first compensation voltage VOBS is applied to the fifth node n35 to turn on the driving element DT. During the fourth period S34 of the first mode (S mode), the second compensation voltage VAR is applied to the sixth node n36 and the seventh node n37. During the fourth period S34 of the first mode (S mode), the light-emitting elements EL1 and EL2 are in the off state.

[0245] Figure 28A and 28B are a waveform diagram and a circuit diagram, respectively, which show the light emission stage of the pixel circuit in the first mode (S mode). In the first mode (S mode), the light emission stage of the pixel circuit is performed during the fifth period S35. In the first mode (S mode), the first mode switching element T1 and the fourth mode switching element T4 are turned on, while the second mode switching element T2 and the third mode switching element T3 are turned off. As a result, in the first mode (S mode), the voltage of the EM signal EM is transmitted to the first node n1, while the second node n2 is maintained at the gate high voltage VGH.

[0246] Referring to Figure 28A and 28B , during the fifth period S35 of the first mode (S mode), the voltages of the first scan signal SCAN1 and the fourth scan signal SCAN4 are the gate low voltage VGL, and the voltages of the second scan signal SCAN2 and the third scan signal SCAN3 are the gate high voltage VGH. During the fifth period S35, the voltage of the EM signal EM is the gate low voltage VGL.

[0247] During the fifth period S35 of the first mode (S mode), the first switching element M1 and the ninth switching element M39 of the pixel circuit PXL are turned on, while the other switching elements M2, M33, M34, M35, M36, M37, and M38 are turned off. During the fifth period S35 of the first mode (S mode), the voltage of the fourth node n34 is Vdata + Vth. During the fifth period S35 of the first mode (S mode), the first light-emitting element EL1 is lit, and the second light-emitting element EL2 is in the off state.

[0248] In the second mode (P mode), the method of performing internal compensation before the pixel circuit emits light can be the same as that in the first mode (S mode). In the second mode (P mode), as Figure 29A shown, the pixel circuit can be driven in the first reset stage P31, initialization stage P32, data writing and threshold voltage sampling stage P33, and second reset stage P34 before emitting light. In the light emission stage P35 of the second mode (P mode), the second light-emitting element EL2 emits light.

[0249] Figure 29A and 29BThey are a waveform diagram and a circuit diagram, which show the light-emitting stage of the pixel circuit in the second mode (P mode). In the second mode (P mode), the light-emitting stage of the pixel circuit is executed during the fifth time period P35. In the second mode (P mode), the first mode switching element T1 and the fourth mode switching element T4 are turned off, while the second mode switching element T2 and the third mode switching element T3 are turned on. As a result, in the second mode (P mode), the voltage of the EM signal EM is transmitted to the second node n2, and the first node n1 is maintained at the gate high voltage VGH.

[0250] Referring to Figure 29A and 29B , during the fifth time period P35 of the second mode (P mode), the voltages of the first scan signal SCAN1 and the fourth scan signal SCAN4 are the gate low voltage VGL, and the voltages of the second scan signal SCAN2 and the third scan signal SCAN3 are the gate high voltage VGH. During the fifth time period P35, the voltage of the EM signal EM is the gate low voltage VGL.

[0251] During the fifth time period P35 of the second mode (P mode), the second switching element M2 and the ninth switching element M39 of the pixel circuit PXL are turned on, while the other switching elements M1, M33, M34, M35, M36, M37, and M38 are turned off. During the fifth time period P35 of the second mode (P mode), the voltage of the fourth node n34 is Vdata + Vth. During the fifth time period P35 of the second mode (P mode), the second light-emitting element EL2 is lit, and the first light-emitting element EL1 is in the off state.

[0252] Figure 30A and 30B are diagrams illustrating a pixel circuit, a mode selection circuit, and signals applied to these circuits according to another embodiment of the present invention. Similar to the pixel circuit shown in Figures 24A to 29B , the pixel circuit and the mode selection circuit according to this embodiment are driven in each of the first mode and the second mode (S mode and P mode) during the first reset stage S31 and P31, the initialization stage S32 and P32, the data writing and threshold voltage sampling stage S33 and P33, the second reset stage S34 and P34, and the light-emitting stage S35 and P35. In the pixel circuit and the mode selection circuit according to this embodiment, those components that are substantially the same as those in the embodiment shown in Figures 24A to 29B are denoted by the same reference numerals and will not be described in detail.

[0253] Referring to Figure 30A and 30B , the pixel circuit includes a 9-1 switching element M91 and a 9-2 switching element M92 connected between the VDD node and the fifth node n35.

[0254] The 9-1st switching element M91 is turned on in response to the gate low voltage VGL of the first mode signal S to apply the pixel driving voltage VDD to the fifth node n35. The 9-1st switching element M91 includes a first electrode connected to the VDD node to which the pixel driving voltage VDD is applied, a gate connected to the first node n1 to which the first mode signal S is applied, and a second electrode connected to the fifth node n35.

[0255] The 9-2nd switching element M92 is turned on in response to the gate low voltage VGL of the second mode signal P to apply the pixel driving voltage VDD to the fifth node. The 9-2nd switching element M92 includes a first electrode connected to the VDD node to which the pixel driving voltage VDD is applied, a gate connected to the second node n2 to which the second mode signal P is applied, and a second electrode connected to the fifth node n35.

[0256] In the first mode (S mode), the EM signal EM at the first node n1 is transmitted as the first mode signal S to the gate of the 9-1st switching element M91, and the second node n2 is maintained at the gate high voltage VGH. In the second mode (P mode), the EM signal EM at the second node n2 is transmitted as the second mode signal P to the gate of the 9-2nd switching element M92, and the first node n1 is maintained at the gate high voltage VGH. Therefore, the 9-1st switching element M91 and the 9-2nd switching element M92 can form a current path between the VDD node and the driving element DT in response to the gate low voltage VGL of the EM signal EM during the light emission stages S35 and P35.

[0257] Figures 31A to 34B It is a diagram illustrating the operations of a pixel circuit and a mode selection circuit in a stage according to another embodiment of the present invention.

[0258] Referring to Figures 31A to 34B , the pixel circuit includes: a first light emitting element EL1; a second light emitting element EL2; a driving element DT; a capacitor Cst; and a plurality of switching elements M1, M2, M43 to M48. The driving element DT and the switching elements M1, M2, M43 to M48 can be implemented as p-channel transistors, but are not limited thereto.

[0259] The first light emitting element EL1 includes an anode connected to the sixth node n46 and a cathode to which the cathode voltage VSS is applied. The second light emitting element EL2 includes an anode connected to the seventh node n47 and a cathode to which the cathode voltage VSS is applied. The first light emitting element EL1 can be driven by a current from the driving element DT to emit light in the first mode (S mode). The second light emitting element EL2 can be driven by a current from the driving element DT to emit light in the second mode (P mode).

[0260] The driving element DT includes a first electrode connected to the fifth node n45, a second electrode connected to the third node n43, and a gate connected to the fourth node n44. The driving element DT generates a current according to the gate-source voltage, such that the first light-emitting element EL1 is driven in the first mode (S mode), and the second light-emitting element EL2 is driven in the second mode (P mode). The capacitor Cst is connected between the VDD node to which the pixel driving voltage VDD is applied and the fourth node n44.

[0261] The first switching element M1 is connected between the third node n43 and the sixth node n46, and is turned on in response to the gate conduction voltage VGL of the first mode signal S applied via the first node n1. When the first switching element M1 is turned on, the third node n43 can be electrically connected to the sixth node n46. The first switching element M1 includes: a first electrode connected to the third node n43; a gate connected to the first node n1 to which the first mode signal S is applied; and a second electrode connected to the sixth node n46.

[0262] The second switching element M2 is connected between the third node n43 and the seventh node n47, and is turned on in response to the gate conduction voltage VGL of the second mode signal P applied via the second node n2. When the second switching element M2 is turned on, the third node n43 can be electrically connected to the seventh node n47. The second switching element M2 includes: a first electrode connected to the third node n43; a gate connected to the second node n2 to which the second mode signal P is applied; and a second electrode connected to the seventh node n47.

[0263] The third switching element M43 is connected between the data line to which the data voltage Vdata of the pixel data is applied and the fifth node n45, and is turned on in response to the gate conduction voltage VGL of the Nth scan signal SCAN(N). When the third switching element M43 is turned on, the data voltage Vdata can be applied to the fifth node n45. The third switching element M43 includes a first electrode to which the data voltage Vdata is applied, a gate to which the Nth scan signal SCAN(N) is applied, and a second electrode connected to the fifth node n45.

[0264] The fourth switching element M44 is connected between the third node n43 and the fourth node n44, and is turned on in response to the gate conduction voltage VGL of the Nth scan signal SCAN(N). When the fourth switching element M44 is turned on, the third node n43 can be electrically connected to the fourth node n44. The fourth switching element M44 includes: a first electrode connected to the third node n43, a gate to which the Nth scan signal SCAN(N) is applied, and a second electrode connected to the fourth node n44.

[0265] The fifth switching element M45 is connected between the INI node to which the initialization voltage Vini is applied and the sixth node n46, and is turned on in response to the gate conduction voltage VGL of the (N-1)th scan signal SCAN(N-1). When the fifth switching element M45 is turned on, the sixth node n46 can be initialized to the initialization voltage Vini. The fifth switching element M45 includes a first electrode connected to the INI node to which the initialization voltage Vini is applied, a gate to which the (N-1)th scan signal SCAN(N-1) is applied, and a second electrode connected to the sixth node n46.

[0266] The sixth switching element M46 is connected between the INI node to which the initialization voltage Vini is applied and the seventh node n47, and is turned on in response to the gate conduction voltage VGL of the (N-1)th scan signal SCAN(N-1). When the sixth switching element M46 is turned on, the seventh node n47 can be initialized to the initialization voltage Vini. The sixth switching element M46 includes a first electrode connected to the INI node to which the initialization voltage Vini is applied, a gate to which the (N-1)th scan signal SCAN(N-1) is applied, and a second electrode connected to the seventh node n47.

[0267] The seventh switching element M47 is connected between the INI node to which the initialization voltage Vini is applied and the fourth node n44, and is turned on in response to the gate conduction voltage VGL of the (N-1)th scan signal SCAN(N-1). When the seventh switching element M47 is turned on, the capacitor Cst can be initialized. The seventh switching element M47 includes a first electrode connected to the INI node to which the initialization voltage Vini is applied, a gate to which the (N-1)th scan signal SCAN(N-1) is applied, and a second electrode connected to the fourth node n44.

[0268] The eighth switching element M48 is connected between the VDD node to which the pixel driving voltage is applied and the fifth node n45, and is turned on in response to the gate conduction voltage VGL of the EM signal EM. When the eighth switching element M48 is turned on, a current path is formed between the VDD node and the driving element DT. The eighth switching element M48 includes a first electrode connected to the VDD node to which the pixel driving voltage VDD is applied, a gate to which the EM signal EM is applied, and a second electrode connected to the fifth node n45.

[0269] The mode selection circuit SPM includes a first mode switching element T1, a second mode switching element T2, a third mode switching element T3, and a fourth mode switching element T4. The first mode switching element T1, the second mode switching element T2, the third mode switching element T3, and the fourth mode switching element T4 can be implemented as p-channel transistors, but are not limited thereto.

[0270] When the first-mode switching element T1 is turned on, the EM signal EM is applied as the first-mode signal S to the first node n1. The first-mode switching element T1 includes a first electrode to which the EM signal EM is applied, a gate to which the first-mode selection signal S_SEL is applied, and a second electrode connected to the first node n1.

[0271] When the second-mode switching element T2 is turned on, the gate cutoff voltage VGH is applied to the first node n1. The second-mode switching element T2 includes a first electrode to which the gate cutoff voltage VGH is applied, a gate to which the second-mode selection signal P_SEL is applied, and a second electrode connected to the first node n1.

[0272] When the third-mode switching element T3 is turned on, the EM signal EM is applied as the second-mode signal P to the second node n2. The third-mode switching element T3 includes a first electrode to which the EM signal EM is applied, a gate to which the second-mode selection signal P_SEL is applied, and a second electrode connected to the second node n2.

[0273] When the fourth-mode switching element T4 is turned on, the gate cutoff voltage VGH is applied to the second node n2. The fourth-mode switching element T4 includes a first electrode to which the gate cutoff voltage VGH is applied, a gate to which the first-mode selection signal S_SEL is applied, and a second electrode connected to the second node n2.

[0274] The pixel circuit can be driven in an initialization phase, a data writing and threshold voltage sampling phase, and a light emitting phase. Figures 31A to 33B is a diagram showing the initialization phase, the data writing and threshold voltage sampling phase, and the light emitting phase of the pixel circuit in the first mode (S mode). In the first mode (S mode), the first-mode switching element T1 and the fourth-mode switching element T4 are turned on, while the second-mode switching element T2 and the third-mode switching element T3 are turned off. As a result, in the first mode (S mode), the voltage of the EM signal EM is transmitted to the first node n1, while the second node n2 is held at the gate cutoff voltage VGH.

[0275] Figure 31A and 31B are a waveform and a circuit diagram, respectively, showing the initialization phase of the pixel circuit in the first mode (S mode). In the first mode (S mode), the initialization phase of the pixel circuit is performed during the first time period S41.

[0276] Referring to Figure 31A and 31B , during the first time period S41 of the first mode (S mode), the voltage of the (N - 1)-th scan signal SCAN(N - 1) is the gate conduction voltage VGL, and the voltages of the N-th scan signal SCAN(N) and the EM signal EM are the gate cutoff voltage VGH.

[0277] During the first period S41 of the first mode (S mode), the fifth switching element M45, the sixth switching element M46, and the eighth switching element M48 of the pixel circuit PXL are turned on, and the other switching elements M1, M2, M43, M44, and M48 are turned off. During the first period S41 of the first mode (S mode), the driving element DT is turned on.

[0278] During the first period S41 of the first mode (S mode), the first switching element M1 of the pixel circuit PXL is turned off in response to the gate cut-off voltage VGH of the first mode signal S, and the second switching element M2 is turned off in response to the gate cut-off voltage VGH of the second mode signal P.

[0279] At the end of the first period S41 of the first mode (S mode), the capacitor Cst and the light-emitting elements EL1 and EL2 are initialized. During the first period S41 of the first mode (S mode), the light-emitting elements EL1 and EL2 are in the off state where they do not emit light.

[0280] Figure 32A and 32B are a waveform and a circuit diagram, respectively, which show the data writing and threshold voltage sampling phases of the pixel circuit in the first mode (S mode). In the first mode (S mode), the data writing and threshold voltage sampling phases of the pixel circuit are performed during the second period S42. In the first mode (S mode), the first mode switching element T1 and the fourth mode switching element T4 are turned on, while the second mode switching element T2 and the third mode switching element T3 are turned off. As a result, in the first mode (S mode), the voltage of the EM signal EM is transmitted to the first node n1, and the second node n2 is held at the gate cut-off voltage VGH.

[0281] Refer to Figure 32A and 32B . During the second period S42 of the first mode (S mode), the voltage of the Nth scan signal SCAN(N) is the gate conduction voltage VGL, and the voltages of the (N - 1)th scan signal SCAN(N - 1) and the EM signal EM are the gate cut-off voltages VGH. During the second period S42 of the first mode (S mode), the third switching element M43 and the fourth switching element M44 of the pixel circuit PXL are turned on, and the other switching elements M1, M2, M45, M46, M47, and M48 are turned off. In the second period S42 of the first mode (S mode), the data voltage Vdata of the pixel data is applied to the fifth node n45.

[0282] Figure 33A and 33BThey are a waveform and a circuit diagram, which show the light-emitting stage of the pixel circuit in the first mode (S mode). In the first mode (S mode), the light-emitting stage of the pixel circuit is executed during the third period S43. In the first mode (S mode), the first-mode switching element T1 and the fourth-mode switching element T4 are turned on, while the second-mode switching element T2 and the third-mode switching element T3 are turned off. As a result, in the first mode (S mode), the voltage of the EM signal EM is transmitted to the first node n1, while the second node n2 is maintained at the gate cut-off voltage VGH.

[0283] Referring to Figure 33A and 33B , during the third period S43 of the first mode (S mode), the voltages of the scan signals SCAN(N - 1) and SCAN(N) are the gate cut-off voltage VGH, and the voltage of the EM signal EM is the gate conduction voltage VGL. During the third period S43 of the first mode (S mode), the first switching element M1 and the eighth switching element M48 of the pixel circuit PXL are turned on, while the other switching elements M2, M43, M44, M45, M46, and M47 are turned off.

[0284] During the third period S43 of the first mode (S mode), the current generated according to the gate-source voltage of the driving element DT is supplied to the first light-emitting element EL1 via the first switching element M1. Therefore, during the third period S43 of the first mode (S mode), the first light-emitting element EL1 can be lit. During the third period S43 of the first mode (S mode), the second light-emitting element EL2 is in the off state.

[0285] In the second mode (P mode), the method of performing internal compensation before the pixel circuit emits light can be the same as that in the first mode (S mode). In the second mode (P mode), as Figure 34A shown, the pixel circuit can be driven in the initialization stage P41 and the data writing and threshold voltage sampling stage P42 before emitting light. In the light-emitting stage P43 of the second mode (P mode), the second light-emitting element EL2 emits light.

[0286] Figure 34A and 34B They are a waveform and a circuit diagram, which show the light-emitting stage of the pixel circuit in the second mode (P mode). In the second mode (P mode), the light-emitting stage of the pixel circuit is executed during the third period S43. In the second mode (P mode), the first-mode switching element T1 and the fourth-mode switching element T4 are turned off, while the second-mode switching element T2 and the third-mode switching element T3 are turned on. As a result, in the second mode (P mode), the voltage of the EM signal EM is transmitted to the second node n2, while the first node n1 is maintained at the gate cut-off voltage VGH.

[0287] Refer to Figure 34A and 34B During the third period P43 of the second mode (P mode), the voltages of the scan signals SCAN(N - 1) and SCAN(N) are the gate cut-off voltage VGH, and the voltage of the EM signal EM is the gate conduction voltage VGL. During the third period P43 of the second mode (P mode), the second switching element M2 and the eighth switching element M48 of the pixel circuit PXL are turned on, while the other switching elements M1, M43, M44, M45, M46, and M47 are turned off.

[0288] During the third period P43 of the second mode (P mode), the current generated according to the gate-source voltage of the driving element DT is supplied to the second light-emitting element EL2 via the second switching element M2. Therefore, during the third period P43 of the second mode (P mode), the second light-emitting element EL2 can be lit. During the third period P43 of the second mode (P mode), the first light-emitting element EL1 is in the off state.

[0289] Figure 35A and 35B is a diagram showing a pixel circuit, a mode selection circuit, and signals applied to these circuits according to another embodiment of the present invention. Similar to the pixel circuit shown in Figures 31A to 34B The pixel circuit and the mode selection circuit according to the present embodiment are driven in each of the first mode and the second mode (S mode and P mode) during the initialization phases S41 and P41, the data writing and threshold voltage sampling phases S42 and P42, and the light-emitting phases S43 and P43. In the pixel circuit and the mode selection circuit according to the present embodiment, those components that are substantially the same as those in the embodiment shown in Figures 31A to 34B are denoted by the same reference numerals and will not be described in detail.

[0290] Refer to Figure 35A and 35B The pixel circuit includes an 8 - 1 switching element M81 and an 8 - 2 switching element M82 connected between the VDD node and the fifth node n45.

[0291] The 8 - 1 switching element M81 is turned on in response to the gate conduction voltage VGL of the first mode signal S to apply the pixel driving voltage VDD to the fifth node n45. The 8 - 1 switching element M81 includes a first electrode connected to the VDD node to which the pixel driving voltage VDD is applied, a gate connected to the first node n1 to which the first mode signal S is applied, and a second electrode connected to the fifth node n45.

[0292] The 8-2nd switching element M82 is turned on in response to the gate conduction voltage VGL of the second mode signal P to apply the pixel driving voltage VDD to the fifth node n45. The 8-2nd switching element M82 includes a first electrode connected to the VDD node to which the pixel driving voltage VDD is applied, a gate connected to the second node n2 to which the second mode signal P is applied, and a second electrode connected to the fifth node n45.

[0293] In the first mode (S mode), the EM signal EM at the first node n1 is transmitted as the first mode signal S to the gate of the 8-1st switching element M81, and the second node n2 is maintained at the gate cut-off voltage VGH. In the second mode (P mode), the EM signal EM at the second node n2 is transmitted as the second mode signal P to the gate of the 8-2nd switching element M82, and the first node n1 is maintained at the gate cut-off voltage VGH. Therefore, the 8-1st switching element M81 and the 8-2nd switching element M82 can form a current path between the VDD node and the driving element DT in response to the gate conduction voltage VGL of the EM signal EM during the light emission phases S43 and P43.

[0294] Figures 36A to 39B is a diagram illustrating the operations of a pixel circuit and a mode selection circuit in a stage according to another embodiment of the present invention. The gate signals SCAN(N-1), SCAN(N) and EM and the mode selection signals S_SEL and P_PEL input to the pixel circuit and the mode selection circuit are Figures 31A to 35B substantially the same as the signals shown.

[0295] Referring to Figures 36A to 39B , the pixel circuit includes: a first light-emitting element EL1; a second light-emitting element EL2; a driving element DT; a capacitor Cst; and a plurality of switching elements M1, M2, M53 to M61. The driving element DT and the switching elements M1, M2, M53 to M61 can be implemented as p-channel transistors, but are not limited thereto.

[0296] The first light-emitting element EL1 includes an anode connected to the sixth node n56 and a cathode to which the cathode voltage VSS is applied. The second light-emitting element EL2 includes an anode connected to the seventh node n57 and a cathode to which the cathode voltage VSS is applied. The first light-emitting element EL1 can be driven by the current from the driving element DT to emit light in the first mode (S mode). The second light-emitting element EL2 can be driven by the current from the driving element DT to emit light in the second mode (P mode).

[0297] The driving element DT includes a first electrode connected to the fifth node n55, a second electrode connected to the third node n53, and a gate connected to the fourth node n54. The driving element DT generates a current according to the gate-source voltage, such that the first light-emitting element EL1 is driven in a first mode (S mode), and the second light-emitting element EL2 is driven in a second mode (P mode). A capacitor Cst is connected between the fourth node n54 and the eighth node n58.

[0298] The first switching element M1 is connected between the third node n53 and the sixth node n56, and is turned on in response to the gate conduction voltage VGL of the first mode signal S applied via the first node n1. When the first switching element M1 is turned on, the third node n53 can be electrically connected to the sixth node n56. The first switching element M1 includes: a first electrode connected to the third node n53; a gate connected to the first node n1 to which the first mode signal S is applied; and a second electrode connected to the sixth node n56.

[0299] The second switching element M2 is connected between the third node n53 and the seventh node n57, and is turned on in response to the gate conduction voltage VGL of the second mode signal P applied via the second node n2. When the second switching element M2 is turned on, the third node n53 can be electrically connected to the seventh node n57. The second switching element M2 includes: a first electrode connected to the third node n53; a gate connected to the second node n2 to which the second mode signal P is applied; and a second electrode connected to the seventh node n57.

[0300] The third switching element M53 is connected between the data line to which the data voltage Vdata of the pixel data is applied and the fifth node n55, and is turned on in response to the gate conduction voltage VGL of the Nth scan signal SCAN(N). When the third switching element M53 is turned on, the data voltage Vdata can be applied to the fifth node n55. The third switching element M53 includes a first electrode to which the data voltage Vdata is applied, a gate to which the Nth scan signal SCAN(N) is applied, and a second electrode connected to the fifth node n55.

[0301] The fourth switching element M54 is connected between the third node n53 and the fourth node n54, and is turned on in response to the gate conduction voltage VGL of the Nth scan signal SCAN(N). When the fourth switching element M54 is turned on, the third node n53 can be electrically connected to the fourth node n54. The fourth switching element M54 includes a first electrode connected to the third node n53, a gate to which the Nth scan signal SCAN(N) is applied, and a second electrode connected to the fourth node n54.

[0302] The fifth switching element M55 is connected between the INI node to which the initialization voltage Vini is applied and the sixth node n56, and is turned on in response to the gate conduction voltage VGL of the (N-1)th scan signal SCAN(N-1). When the fifth switching element M55 is turned on, the sixth node n56 can be initialized to the initialization voltage Vini. The fifth switching element M55 includes a first electrode to which the initialization voltage Vini is applied, a gate to which the (N-1)th scan signal SCAN(N-1) is applied, and a second electrode connected to the sixth node n56.

[0303] The sixth switching element M56 is connected between the INI node to which the initialization voltage Vini is applied and the seventh node n57, and is turned on in response to the gate conduction voltage VGL of the (N-1)th scan signal SCAN(N-1). When the sixth switching element M56 is turned on, the seventh node n57 can be initialized to the initialization voltage Vini. The sixth switching element M56 includes a first electrode to which the initialization voltage Vini is applied, a gate to which the (N-1)th scan signal SCAN(N-1) is applied, and a second electrode connected to the seventh node n57.

[0304] The seventh switching element M57 is connected between the INI node to which the initialization voltage Vini is applied and the fourth node n54, and is turned on in response to the gate conduction voltage VGL of the (N-1)th scan signal SCAN(N-1). When the seventh switching element M57 is turned on, the capacitor Cst can be initialized. The seventh switching element M57 includes a first electrode to which the initialization voltage Vini is applied, a gate to which the (N-1)th scan signal SCAN(N-1) is applied, and a second electrode connected to the fourth node n54.

[0305] The eighth switching element M58 is connected between the VDD node to which the pixel driving voltage is applied and the eighth node n58, and is turned on in response to the gate conduction voltage VGL of the EM signal EM. When the eighth switching element M58 is turned on, the VDD node can be electrically connected to the eighth node n58. The eighth switching element M58 includes a first electrode connected to the VDD node to which the pixel driving voltage VDD is applied, a gate to which the EM signal EM is applied, and a second electrode connected to the eighth node n58.

[0306] The ninth switching element M59 is connected between the fifth node n55 and the eighth node n58, and is turned on in response to the gate conduction voltage VGL of the EM signal EM. When the ninth switching element M59 is turned on, the fifth node n55 can be electrically connected to the eighth node n58. The ninth switching element M59 includes a first electrode connected to the fifth node n55, a gate to which the EM signal EM is applied, and a second electrode connected to the eighth node n58.

[0307] The tenth switching element M60 is connected between the REF node to which a reference voltage Vref is applied and the eighth node n58, and is turned on in response to the gate-on voltage VGL of the (N-1)th scan signal SCAN(N-1). When the tenth switching element M60 is turned on, the reference voltage Vref is applied to the eighth node n58. The tenth switching element M60 includes a first electrode connected to the REF node to which the reference voltage Vref is applied, a gate to which the (N-1)th scan signal SCAN(N-1) is applied, and a second electrode connected to the eighth node n58.

[0308] The eleventh switching element M61 is connected between the REF node to which a reference voltage Vref is applied and the eighth node n58, and is turned on in response to the gate-on voltage VGL of the Nth scan signal SCAN(N). When the eleventh switching element M61 is turned on, the reference voltage Vref is applied to the eighth node n58. The eleventh switching element M61 includes a first electrode connected to the REF node to which the reference voltage Vref is applied, a gate to which the Nth scan signal SCAN(N) is applied, and a second electrode connected to the eighth node n58.

[0309] The mode selection circuit SPM includes a first mode switching element T1, a second mode switching element T2, a third mode switching element T3, and a fourth mode switching element T4. The first mode switching element T1, the second mode switching element T2, the third mode switching element T3, and the fourth mode switching element T4 can be implemented as p-channel transistors, but are not limited thereto.

[0310] When the first mode switching element T1 is turned on, the EM signal EM is applied to the first node n1 as a first mode signal S. The first mode switching element T1 includes a first electrode to which the EM signal EM is applied, a gate to which the first mode selection signal S_SEL is applied, and a second electrode connected to the first node n1.

[0311] When the second mode switching element T2 is turned on, the gate-off voltage VGH is applied to the first node n1. The second mode switching element T2 includes a first electrode to which the gate-off voltage VGH is applied, a gate to which the second mode selection signal P_SEL is applied, and a second electrode connected to the first node n1.

[0312] When the third mode switching element T3 is turned on, the EM signal EM is applied to the second node n2 as a second mode signal P. The third mode switching element T3 includes a first electrode to which the EM signal EM is applied, a gate to which the second mode selection signal P_SEL is applied, and a second electrode connected to the second node n2.

[0313] When the fourth-mode switching element T4 is turned on, a gate cut-off voltage VGH is applied to the second node n2. The fourth-mode switching element T4 includes a first electrode to which the gate cut-off voltage VGH is applied, a gate to which a first mode selection signal S_SEL is applied, and a second electrode connected to the second node n2.

[0314] The pixel circuit can be driven in an initialization phase, a data writing and threshold voltage sampling phase, and a light-emitting phase. Figures 36A to 38B is a diagram showing the initialization phase, the data writing and threshold voltage sampling phase, and the light-emitting phase of the pixel circuit in the phase of the first mode (S mode). In the first mode (S mode), the first-mode switching element T1 and the fourth-mode switching element T4 are turned on, while the second-mode switching element T2 and the third-mode switching element T3 are turned off. As a result, in the first mode (S mode), the voltage of the EM signal EM is transmitted to the first node n1, and the second node n2 is maintained at the gate cut-off voltage VGH.

[0315] Figure 36A and 36B are a waveform and a circuit diagram, respectively, showing the initialization phase of the pixel circuit in the first mode (S mode). In the first mode (S mode), the initialization phase of the pixel circuit is executed during the first time period S41.

[0316] Referring to Figure 36A and 36B , during the first time period S41 of the first mode (S mode), the voltage of the (N - 1)-th scan signal SCAN(N - 1) is the gate conduction voltage VGL, and the voltages of the N-th scan signal SCAN(N) and the EM signal EM are the gate cut-off voltage VGH.

[0317] During the first time period S41 of the first mode (S mode), the fifth switching element M55, the sixth switching element M56, the seventh switching element M57, and the tenth switching element M60 of the pixel circuit PXL are turned on, and the other switching elements M1, M2, M53, M54, M58, M59, and M61 are turned off. During the first time period S41 of the first mode (S mode), the driving element DT is turned on. During the first time period S41 of the first mode (S mode), an initialization voltage Vini is applied to the fifth node n55 and the sixth node n56, and a reference voltage Vref is applied to the eighth node n58. At the end of the first time period S41 of the first mode (S mode), the capacitor Cst and the light-emitting elements EL1 and EL2 are initialized. During the first time period S41 of the first mode (S mode), the light-emitting elements EL1 and EL2 are in the off state.

[0318] Figure 37A and 37BWaveform and circuit diagrams, respectively, showing the data writing and threshold voltage sampling phases of the pixel circuit in the first mode (S mode). In the first mode (S mode), the data writing and threshold voltage sampling phases of the pixel circuit are performed during the second period S42. In the first mode (S mode), the first mode switching element T1 and the fourth mode switching element T4 are turned on, while the second mode switching element T2 and the third mode switching element T3 are turned off. As a result, in the first mode (S mode), the voltage of the EM signal EM is transmitted to the first node n1, while the second node n2 is held at the gate cut-off voltage VGH.

[0319] Refer to Figure 37A and 37B , during the second period S42 of the first mode (S mode), the voltage of the Nth scan signal SCAN(N) is the gate conduction voltage VGL, and the voltages of the (N - 1)th scan signal SCAN(N - 1) and the EM signal EM are the gate cut-off voltage VGH. During the second period S42 of the first mode (S mode), the third switching element M53, the fourth switching element M54, and the eleventh switching element M61 of the pixel circuit PXL are turned on, and the other switching elements M1, M2, M55, M56, M57, M58, M59, and M60 are turned off. In the second period S42 of the first mode (S mode), the data voltage Vdata of the pixel data is applied to the fifth node n55. In the second period S42 of the first mode (S mode), the reference voltage Vref is applied to the eighth node n58.

[0320] Figure 38A and 38B Waveform and circuit diagrams, respectively, showing the light emission phase of the pixel circuit in the first mode (S mode). In the first mode (S mode), the light emission phase of the pixel circuit is performed during the third period S43. In the first mode (S mode), the first mode switching element T1 and the fourth mode switching element T4 are turned on, while the second mode switching element T2 and the third mode switching element T3 are turned off. As a result, in the first mode (S mode), the voltage of the EM signal EM is transmitted to the first node n1, while the second node n2 is held at the gate cut-off voltage VGH.

[0321] Refer to Figure 38A and 38B , during the third period S43 of the first mode (S mode), the voltages of the scan signals SCAN(N - 1) and SCAN(N) are the gate cut-off voltage VGH, and the voltage of the EM signal EM is the gate conduction voltage VGL. During the third period S43 of the first mode (S mode), the first switching element M1, the eighth switching element M58, and the ninth switching element M59 of the pixel circuit PXL are turned on, while the other switching elements M2, M53, M54, M55, M56, M57, M60, and M61 are turned off.

[0322] During the third period S43 of the first mode (S mode), the current generated according to the gate-source voltage of the driving element DT is supplied to the first light-emitting element EL1 via the first switching element M1. Therefore, during the third period S43 of the first mode (S mode), the first light-emitting element EL1 can be lit. During the third period S43 of the first mode (S mode), the second light-emitting element EL2 is in the off state.

[0323] In the second mode (P mode), the method of performing internal compensation before the pixel circuit emits light can be the same as that in the first mode (S mode). In the second mode (P mode), as Figure 39A shown, the pixel circuit can be driven in the initialization stage P41 and the data writing and threshold voltage sampling stage P42 before emitting light. In the light-emitting stage P43 of the second mode (P mode), the second light-emitting element EL2 emits light.

[0324] Figure 39A and 39B are a waveform and a circuit diagram, respectively, which show the light-emitting stage of the pixel circuit in the second mode (P mode). In the second mode (P mode), the light-emitting stage of the pixel circuit is executed during the third period P43. In the second mode (P mode), the first-mode switching element T1 and the fourth-mode switching element T4 are cut off, while the second-mode switching element T2 and the third-mode switching element T3 are turned on. As a result, in the second mode (P mode), the voltage of the EM signal EM is transmitted to the second node n2, and the first node n1 is maintained at the gate cut-off voltage VGH.

[0325] Referring to Figure 39A and 39B , during the third period P43 of the second mode (P mode), the voltages of the scan signals SCAN(N - 1) and SCAN(N) are the gate cut-off voltage VGH, and the voltage of the EM signal EM is the gate conduction voltage VGL. During the third period P43 of the second mode (P mode), the second switching element M2, the eighth switching element M58, and the ninth switching element M59 of the pixel circuit PXL are turned on, while the other switching elements M1, M53, M54, M55, M56, M57, M60, and M61 are cut off.

[0326] During the third period P43 of the second mode (P mode), the current generated according to the gate-source voltage of the driving element DT is supplied to the second light-emitting element EL2 via the second switching element M2. Therefore, during the third period P43 of the second mode (P mode), the second light-emitting element EL2 can be lit. During the third period P43 of the second mode (P mode), the first light-emitting element EL1 is in the off state.

[0327] Figure 40A and 40B is a diagram showing a pixel circuit and a mode selection circuit according to another embodiment of the present invention, and signals applied to these circuits. Similar to the pixel circuit shown in Figures 36A to 39B , the pixel circuit and the mode selection circuit according to the present embodiment are driven in each of a first mode and a second mode (S mode and P mode) during an initialization stage S41 and P41, a data writing and threshold voltage sampling stage S42 and P42, and a light emitting stage S43 and P43. In the pixel circuit and the mode selection circuit according to the present embodiment, those components substantially the same as those shown in Figures 36A to 39B are denoted by the same reference numerals and will not be described in detail.

[0328] Referring to Figure 40A and 40B , the pixel circuit includes: an 8-1 switch element M581 and an 8-2 switch element M582 connected between a VDD node and an eighth node n58; and a 9-1 switch element M591 and a 9-2 switch element M592 connected between a fifth node n55 and the eighth node n58.

[0329] The 8-1 switch element M581 is turned on in response to a gate conduction voltage VGL of the first mode signal S to apply a pixel driving voltage VDD to the eighth node n58. The 8-1 switch element M581 includes a first electrode connected to the VDD node to which the pixel driving voltage VDD is applied, a gate connected to a first node n1 to which the first mode signal S is applied, and a second electrode connected to the eighth node n58.

[0330] The 8-2 switch element M582 is turned on in response to a gate conduction voltage VGL of the second mode signal P to apply a pixel driving voltage VDD to the eighth node n58. The 8-2 switch element M582 includes a first electrode connected to the VDD node to which the pixel driving voltage VDD is applied, a gate connected to a second node n2 to which the second mode signal P is applied, and a second electrode connected to the eighth node n58.

[0331] The 9-1 switch element M591 is turned on in response to a gate conduction voltage VGL of the first mode signal S to electrically connect the fifth node n55 to the eighth node n58. The 9-1 switch element M591 includes a first electrode connected to the fifth node n55, a gate connected to the first node n1 to which the first mode signal S is applied, and a second electrode connected to the eighth node n58.

[0332] The 9-2 switch element M592 is turned on in response to the gate turn-on voltage VGL of the second mode signal P to electrically connect the fifth node n55 to the eighth node n58. The 9-2 switch element M592 includes a first electrode connected to the fifth node n55, a gate connected to the second node n2 to which the second mode signal P is applied, and a second electrode connected to the eighth node n58.

[0333] In the first mode (S mode), the EM signal EM at the first node n1 is transmitted as the first mode signal S to the gates of the 8-1 switch element M581 and the 9-1 switch element M591, and the second node n2 is held at the gate cut-off voltage VGH. In the second mode (P mode), the EM signal EM at the second node n2 is transmitted as the second mode signal P to the gates of the 8-2 switch element M582 and the 9-2 switch element M592, and the first node n1 is held at the gate cut-off voltage VGH. Accordingly, the 8-1 switch element M581, the 8-2 switch element M582, the 9-1 switch element M591, and the 9-2 switch element M592 can form a current path between the VDD node and the driving element DT in response to the gate turn-on voltage VGL of the EM signal EM in the light emission stages S43 and P43.

[0334] According to one or more embodiments of the present invention, the display device can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, sliding devices, variable devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation systems, vehicle navigation systems, vehicle display devices, vehicle devices, cinema devices, cinema display devices, televisions, wallpaper devices, sign devices, game devices, notebook computers, displays, cameras, camcorders, and household appliances, etc. In addition, the display device according to one or more embodiments of the present invention can be applied to organic light-emitting lighting devices or inorganic light-emitting lighting devices.

[0335] The objects to be achieved by the present invention, the means for achieving these objects, and the effects of the present invention described above do not specify the essential features of the claims. Therefore, the scope of the claims is not limited to the specific description of the present invention.

[0336] Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not limited thereto, and the present invention can be implemented in many different forms without departing from the technical concept of the present invention. Therefore, the embodiments disclosed in the present invention are provided only for illustrative purposes, and these embodiments are not intended to limit the technical concept of the present invention. The scope of the technical concept of the present invention is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present invention.

Claims

1. A display panel, comprising: a mode selection circuit configured to output a light emitting signal to a first node in response to a first mode selection signal and to output the light emitting signal to a second node in response to a second mode selection signal; Pixel circuit; as well as A first light emitting element and a second light emitting element, wherein the first light emitting element is configured to be driven by the pixel circuit in a first mode according to a voltage of a first node, and the second light emitting element is configured to be driven by the pixel circuit in a second mode according to a voltage of a second node.

2. The display panel according to claim 1, wherein the pixel circuit comprises: a driving element including a first electrode arranged to have a pixel driving voltage applied, a gate arranged to have a data voltage of pixel data applied, and a second electrode connected to a third node; a first switching element including a first electrode connected to the third node, a gate electrically connected to the first node, and a second electrode electrically connected to an anode of the first light emitting element; as well as A second switching element includes a first electrode connected to the third node, a gate electrically connected to the second node, and a second electrode connected to an anode of the second light emitting element.

3. The display panel according to claim 2, wherein: The light emitting signal swings between a gate-on voltage and a gate-off voltage. Each of the first switching element and the second switching element is arranged to be turned on in response to the gate-on voltage and is arranged to be turned off in response to the gate-off voltage, The mode selection circuit comprises: a first mode switching element including a first electrode arranged to have a light emitting signal applied, a gate arranged to have a first mode selection signal applied, and a second electrode electrically connected to the first node; a second mode switch element including a first electrode arranged to have a separate gate-off voltage applied, a gate arranged to have a second mode selection signal applied, and a second electrode electrically connected to the first node; a third mode switching element including a first electrode arranged to have a light emitting signal applied, a gate arranged to have a second mode selection signal applied, and a second electrode electrically connected to the second node; and A fourth mode switching element includes a first electrode arranged to have a separate gate-off voltage applied, a gate arranged to have a first mode selection signal applied, and a second electrode electrically connected to the second node.

4. The display panel according to claim 2, wherein the pixel circuit further comprises: a capacitor connected between the fourth node and the fifth node; a third switching element including a first electrode arranged to have a data voltage applied thereto, a gate arranged to have a first scan signal applied thereto, and a second electrode electrically connected to the fifth node; a fourth switching element including a first electrode electrically connected to the third node, a gate arranged to have a second scan signal applied thereto, and a second electrode connected to the fourth node; a fifth switching element including a first electrode electrically connected to a sixth node arranged to have a reference voltage applied thereto, a gate arranged to have a second scan signal applied thereto, and a second electrode connected to a seventh node; a sixth switching element including a first electrode connected to the sixth node, a gate arranged to have a second scan signal applied thereto, and a second electrode electrically connected to an eighth node; as well as a seventh switching element including a first electrode connected to the fifth node, a gate arranged to have a light emitting signal applied thereto, and a second electrode connected to the sixth node, wherein the gate of the driving element is electrically connected to the fourth node, the first light emitting element includes an anode connected to the seventh node and a cathode arranged to have a cathode voltage applied, The second light emitting element includes an anode connected to the eighth node and a cathode arranged to have a cathode voltage applied.

5. The display panel according to claim 4, wherein: The light emitting signal swings between a gate-on voltage and a gate-off voltage. each of the first switching element, the second switching element, the third switching element, the fourth switching element, the fifth switching element, the sixth switching element and the seventh switching element is arranged to be turned on in response to the gate-on voltage and is arranged to be turned off in response to the gate-off voltage, a voltage of the first scan signal in each of the first mode and the second mode is the gate-off voltage during a first period, is the gate-on voltage during a second period after the first period, and is the gate-off voltage during a third period after the second period, a voltage of the second scan signal in each of the first mode and the second mode is the gate-on voltage during the first period and the second period, and is the gate-off voltage during the third period, a voltage of the light emitting signal in each of the first mode and the second mode is the gate-on voltage during the first period, is the gate-off voltage during the second period, and is the gate-on voltage during the third period, The voltage of the first mode selection signal is the gate-on voltage in the first period, the second period, and the third period of the first mode, and is the gate-off voltage in the first period, the second period, and the third period of the second mode, The voltage of the second mode selection signal is the gate-on voltage in the first period, the second period, and the third period of the second mode, and is the gate-off voltage in the first period, the second period, and the third period of the first mode, In the first mode, the voltage of the first mode signal applied to the first node is the voltage of the light emitting signal, and the voltage of the second mode signal applied to the second node is the gate cut-off voltage. In the second mode, a voltage of a first mode signal applied to the first node is the gate-off voltage, and a voltage of a second mode signal applied to the second node is a voltage of the light emitting signal.

6. The display panel according to claim 2, wherein the pixel circuit further comprises: a capacitor connected between the fourth node and the fifth node; a third switching element including a first electrode arranged to have a data voltage applied thereto, a gate arranged to have a first scan signal applied thereto, and a second electrode electrically connected to the fifth node; a fourth switching element including a first electrode electrically connected to the third node, a gate arranged to have a second scan signal applied thereto, and a second electrode connected to the fourth node; a fifth switching element including a first electrode electrically connected to a sixth node arranged to have a reference voltage applied thereto, a gate arranged to have a second scan signal applied thereto, and a second electrode connected to a seventh node; a sixth switching element including a first electrode connected to the sixth node, a gate arranged to have a second scan signal applied thereto, and a second electrode electrically connected to an eighth node; a 7-1st switching element, the 7-1st switching element including a first electrode connected to the fifth node, a gate connected to the first node, and a second electrode connected to the sixth node; as well as a 7-2nd switching element, the 7-2nd switching element including a first electrode connected to the fifth node, a gate connected to the second node, and a second electrode connected to the sixth node, wherein the gate of the driving element is electrically connected to the fourth node, the first light emitting element includes an anode connected to the seventh node and a cathode arranged to have a cathode voltage applied, The second light emitting element includes an anode connected to the eighth node and a cathode arranged to have a cathode voltage applied.

7. The display panel according to claim 6, wherein: The light emitting signal swings between a gate-on voltage and a gate-off voltage. each of the first switching element, the second switching element, the third switching element, the fourth switching element, the fifth switching element, the sixth switching element, the 7-1st switching element and the 7-2nd switching element is arranged to be turned on in response to the gate-on voltage and is arranged to be turned off in response to the gate-off voltage, a voltage of the first scan signal in each of the first mode and the second mode is the gate-off voltage during a first period, is the gate-on voltage during a second period after the first period, and is the gate-off voltage during a third period after the second period, a voltage of the second scan signal in each of the first mode and the second mode is the gate-on voltage during the first period and the second period, and is the gate-off voltage during the third period, a voltage of the light emitting signal in each of the first mode and the second mode is the gate-on voltage during the first period, is the gate-off voltage during the second period, and is the gate-on voltage during the third period, The voltage of the first mode selection signal is the gate-on voltage in the first period, the second period, and the third period of the first mode, and is the gate-off voltage in the first period, the second period, and the third period of the second mode, The voltage of the second mode selection signal is the gate-on voltage in the first period, the second period, and the third period of the second mode, and is the gate-off voltage in the first period, the second period, and the third period of the first mode, In the first mode, the voltage of the first mode signal applied to the first node is the voltage of the light emitting signal, and the voltage of the second mode signal applied to the second node is the gate cut-off voltage. In the second mode, a voltage of a first mode signal applied to the first node is the gate-off voltage, and a voltage of a second mode signal applied to the second node is a voltage of the light emitting signal.

8. The display panel according to claim 2, wherein the mode selection circuit comprises: a first mode switching element including a first electrode arranged to have a light emitting signal applied, a gate arranged to have a first mode selection signal applied, and a second electrode electrically connected to the first node; a second mode switch element including a first electrode arranged to have a gate high voltage applied, a gate arranged to have a second mode selection signal applied, and a second electrode electrically connected to the first node; a third mode switching element including a first electrode arranged to have a light emitting signal applied, a gate arranged to have a second mode selection signal applied, and a second electrode electrically connected to the second node; as well as a fourth mode switch element including a first electrode arranged to have a gate high voltage applied, a gate arranged to have a first mode selection signal applied, and a second electrode electrically connected to the second node, wherein the light emission signal swings between the gate high voltage and the gate low voltage, the first switching element is arranged to be turned on in response to a gate low voltage applied to the first node and is arranged to be turned off in response to a gate high voltage applied to the first node, The second switching element is arranged to be turned on in response to a gate low voltage applied to the second node and is arranged to be turned off in response to a gate high voltage applied to the second node.

9. The display panel according to claim 8, wherein the pixel circuit further comprises: a capacitor connected between a VDD node arranged to have a pixel driving voltage applied thereto and a fourth node; a third switching element including a first electrode arranged to have the data voltage applied, a gate arranged to have the second scan signal applied, and a second electrode electrically connected to the fifth node; a fourth switching element including a first electrode electrically connected to the third node, a gate arranged to have the first scan signal applied thereto, and a second electrode connected to the fourth node; a fifth switching element including a first electrode arranged to have a second compensation voltage applied thereto, a gate arranged to have a third scan signal applied thereto, and a second electrode connected to a sixth node; a sixth switching element including a first electrode arranged to have a second compensation voltage applied thereto, a gate arranged to have a third scan signal applied thereto, and a second electrode connected to a seventh node; a seventh switching element including a first electrode connected to the INI node and arranged to have an applied initialization voltage, a gate arranged to have an applied fourth scan signal, and a second electrode connected to the fourth node; an eighth switching element including a first electrode arranged to have the first compensation voltage applied, a gate arranged to have the third scan signal applied, and a second electrode connected to the fifth node; as well as a ninth switching element including a first electrode connected to the VDD node, a gate arranged to have a light emitting signal applied thereto, and a second electrode connected to the fifth node, wherein the gate of the driving element is electrically connected to the fourth node, the first light emitting element includes an anode connected to the sixth node and a cathode arranged to have a cathode voltage applied, the second light emitting element includes an anode connected to the seventh node and a cathode arranged to have a cathode voltage applied, each of the first mode switching element, the second mode switching element, the third mode switching element, the fourth mode switching element, the first switching element, the second switching element, the third switching element, the fifth switching element, the sixth switching element, the eighth switching element and the ninth switching element is arranged to be turned on in response to a gate low voltage applied to a corresponding gate, and is arranged to be turned off in response to a gate high voltage applied to a corresponding gate, Each of the fourth switching element and the seventh switching element is arranged to be turned on in response to a gate high voltage applied to the corresponding gate, and is arranged to be turned off in response to a gate low voltage applied to the corresponding gate.

10. The display panel according to claim 8, wherein the pixel circuit further comprises: a capacitor connected between a VDD node arranged to have a pixel driving voltage applied thereto and a fourth node; a third switching element including a first electrode arranged to have the data voltage applied, a gate arranged to have the second scan signal applied, and a second electrode electrically connected to the fifth node; a fourth switching element including a first electrode electrically connected to the third node, a gate arranged to have the first scan signal applied thereto, and a second electrode connected to the fourth node; a fifth switching element including a first electrode arranged to have a second compensation voltage applied thereto, a gate arranged to have a third scan signal applied thereto, and a second electrode connected to a sixth node; a sixth switching element including a first electrode arranged to have a second compensation voltage applied thereto, a gate arranged to have a third scan signal applied thereto, and a second electrode connected to a seventh node; a seventh switching element including a first electrode connected to an INI node arranged to have an applied initialization voltage, a gate arranged to have an applied fourth scan signal, and a second electrode connected to the fourth node; an eighth switching element including a first electrode arranged to have the first compensation voltage applied, a gate arranged to have the third scan signal applied, and a second electrode connected to the fifth node; a 9-1st switching element, the 9-1st switching element including a first electrode connected to the VDD node, a gate connected to the first node, and a second electrode connected to the fifth node; as well as a 9-2nd switching element, the 9-2nd switching element including a first electrode connected to the VDD node, a gate connected to the second node, and a second electrode connected to the fifth node, wherein the gate of the driving element is electrically connected to the fourth node, the first light emitting element includes an anode connected to the sixth node and a cathode arranged to have a cathode voltage applied, the second light emitting element includes an anode connected to the seventh node and a cathode arranged to have a cathode voltage applied, each of the first mode switching element, the second mode switching element, the third mode switching element, the fourth mode switching element, the first switching element, the second switching element, the third switching element, the fifth switching element, the sixth switching element, the eighth switching element, the 9-1st switching element and the 9-2nd switching element is arranged to be turned on in response to a gate low voltage applied to the corresponding gate, and is arranged to be turned off in response to a gate high voltage applied to the corresponding gate, Each of the fourth switching element and the seventh switching element is arranged to be turned on in response to a gate high voltage applied to the corresponding gate, and is arranged to be turned off in response to a gate low voltage applied to the corresponding gate.

11. The display panel according to claim 9 or 10, wherein: a voltage of the first scan signal in each of the first mode and the second mode is the gate low voltage during a first period, is the gate high voltage during a second period after the first period, is the gate high voltage during a third period after the second period, is the gate low voltage during a fourth period after the third period, and is the gate low voltage during a fifth period after the fourth period, a voltage of the second scan signal in each of the first mode and the second mode is the gate high voltage during the first period, the second period, the fourth period, and the fifth period, and is the gate low voltage during the third period, a voltage of the third scan signal in each of the first mode and the second mode is the gate low voltage during the first period and the fourth period, and is the gate high voltage during the second period, the third period, and the fifth period, a voltage of the fourth scan signal in each of the first mode and the second mode is the gate low voltage during the first period, the third period, the fourth period, and the fifth period, and is the gate high voltage during the second period, a voltage of the light emitting signal in each of the first mode and the second mode is the gate high voltage during the first period, the second period, the third period, and the fourth period, and is the gate low voltage during the fifth period, the voltage of the first mode selection signal is the gate low voltage during the first period, the second period, the third period, the fourth period, and the fifth period of the first mode, and is the gate high voltage during the first period, the second period, the third period, the fourth period, and the fifth period of the second mode, The voltage of the second mode selection signal is the gate low voltage during the first period, the second period, the third period, the fourth period, and the fifth period of the second mode, and is the gate high voltage during the first period, the second period, the third period, the fourth period, and the fifth period of the first mode, In the first mode, the voltage of the first mode signal applied to the first node is the voltage of the light emitting signal, and the voltage of the second mode signal applied to the second node is the gate high voltage. In the second mode, a voltage of a first mode signal applied to the first node is the gate high voltage, and a voltage of a second mode signal applied to the second node is a voltage of the light emitting signal.

12. The display panel according to claim 3, wherein the pixel circuit further comprises: a capacitor connected between a VDD node arranged to have a pixel driving voltage applied thereto and a fourth node; a third switching element including a first electrode arranged to have an applied data voltage, a gate arranged to have an applied Nth scan signal (where N is a natural number), and a second electrode electrically connected to the fifth node; a fourth switching element including a first electrode electrically connected to the third node, a gate arranged to have an Nth scan signal applied thereto, and a second electrode connected to the fourth node; a fifth switching element including a first electrode connected to the INI node arranged to have an applied initialization voltage, a gate arranged to have an applied N-1th scan signal, and a second electrode connected to the sixth node; a sixth switching element including a first electrode connected to the INI node, a gate arranged to have an N-1th scan signal applied thereto, and a second electrode electrically connected to a seventh node; a seventh switching element including a first electrode connected to the INI node, a gate arranged to have an N-1th scan signal applied thereto, and a second electrode connected to the fourth node; as well as an eighth switching element including a first electrode connected to the VDD node, a gate arranged to have a light emitting signal applied thereto, and a second electrode connected to the fifth node, wherein the gate of the driving element is electrically connected to the fourth node, the first light emitting element includes an anode connected to the sixth node and a cathode arranged to have a cathode voltage applied, The second light emitting element includes an anode connected to the seventh node and a cathode arranged to have a cathode voltage applied thereto.

13. The display panel according to claim 3, wherein the pixel circuit further comprises: a capacitor connected between a VDD node arranged to have a pixel driving voltage applied thereto and a fourth node; a third switching element including a first electrode arranged to have an applied data voltage, a gate arranged to have an applied Nth scan signal (where N is a natural number), and a second electrode electrically connected to the fifth node; a fourth switching element including a first electrode electrically connected to the third node, a gate arranged to have an Nth scan signal applied thereto, and a second electrode connected to the fourth node; a fifth switching element including a first electrode connected to the INI node arranged to have an applied initialization voltage, a gate arranged to have an applied N-1th scan signal, and a second electrode connected to the sixth node; a sixth switching element including a first electrode connected to the INI node, a gate arranged to have an N-1th scan signal applied thereto, and a second electrode electrically connected to a seventh node; a seventh switching element including a first electrode connected to the INI node, a gate arranged to have an N-1th scan signal applied thereto, and a second electrode connected to the fourth node; an 8-1st switching element, the 8-1st switching element including a first electrode connected to the VDD node, a gate connected to the first node, and a second electrode connected to the fifth node; as well as an 8-2nd switching element, the 8-2nd switching element including a first electrode connected to the VDD node, a gate connected to the second node, and a second electrode connected to the fifth node, wherein the gate of the driving element is electrically connected to the fourth node, the first light emitting element includes an anode connected to the sixth node and a cathode arranged to have a cathode voltage applied, The second light emitting element includes an anode connected to the seventh node and a cathode arranged to have a cathode voltage applied thereto.

14. The display panel according to claim 3, wherein the pixel circuit further comprises: a capacitor connected between the fourth node and the eighth node; a third switching element including a first electrode arranged to have an applied data voltage, a gate arranged to have an applied Nth scan signal (where N is a natural number), and a second electrode electrically connected to the fifth node; a fourth switching element including a first electrode electrically connected to the third node, a gate arranged to have an Nth scan signal applied thereto, and a second electrode connected to the fourth node; a fifth switching element including a first electrode connected to the INI node arranged to have an applied initialization voltage, a gate arranged to have an applied N-1th scan signal, and a second electrode connected to the sixth node; a sixth switching element including a first electrode connected to the INI node, a gate arranged to have an N-1th scan signal applied thereto, and a second electrode electrically connected to a seventh node; a seventh switching element including a first electrode connected to the INI node, a gate arranged to have an N-1th scan signal applied thereto, and a second electrode connected to the fourth node; an eighth switching element including a first electrode connected to the VDD node and arranged to have an applied pixel driving voltage, a gate arranged to have an applied light emitting signal, and a second electrode connected to the eighth node; a ninth switching element including a first electrode connected to the fifth node, a gate arranged to have a light emitting signal applied thereto, and a second electrode connected to the eighth node; a tenth switching element including a first electrode connected to the REF node and arranged to have a reference voltage applied thereto, a gate arranged to have an (N-1)th scan signal applied thereto, and a second electrode connected to the eighth node; as well as an eleventh switching element, the eleventh switching element including a first electrode connected to the REF node, a gate arranged to have an Nth scan signal applied thereto, and a second electrode connected to the eighth node, wherein the gate of the driving element is electrically connected to the fourth node, the first light emitting element includes an anode connected to the sixth node and a cathode arranged to have a cathode voltage applied, The second light emitting element includes an anode connected to the seventh node and a cathode arranged to have a cathode voltage applied thereto.

15. The display panel according to claim 3, wherein the pixel circuit further comprises: a capacitor connected between the fourth node and the eighth node; a third switching element including a first electrode arranged to have an applied data voltage, a gate arranged to have an applied Nth scan signal (where N is a natural number), and a second electrode electrically connected to the fifth node; a fourth switching element including a first electrode electrically connected to the third node, a gate arranged to have an Nth scan signal applied thereto, and a second electrode connected to the fourth node; a fifth switching element including a first electrode connected to the INI node arranged to have an applied initialization voltage, a gate arranged to have an applied N-1th scan signal, and a second electrode connected to the sixth node; a sixth switching element including a first electrode connected to the INI node, a gate arranged to have an N-1th scan signal applied thereto, and a second electrode electrically connected to a seventh node; a seventh switching element including a first electrode connected to the INI node, a gate arranged to have an N-1th scan signal applied thereto, and a second electrode connected to the fourth node; an 8-1st switching element including a first electrode connected to a VDD node arranged to have a pixel driving voltage applied thereto, a gate connected to the first node, and a second electrode connected to the eighth node; an 8-2nd switching element, the 8-2nd switching element including a first electrode connected to the VDD node, a gate connected to the second node, and a second electrode connected to the eighth node; a 9-1st switching element, the 9-1st switching element including a first electrode connected to the fifth node, a gate connected to the first node, and a second electrode connected to the eighth node; a 9-2nd switching element, the 9-2nd switching element comprising a first electrode connected to the fifth node, a gate connected to the second node, and a second electrode connected to the eighth node; a tenth switching element including a first electrode connected to the REF node and arranged to have a reference voltage applied thereto, a gate arranged to have an (N-1)th scan signal applied thereto, and a second electrode connected to the eighth node; as well as an eleventh switching element, the eleventh switching element including a first electrode connected to the REF node, a gate arranged to have an Nth scan signal applied thereto, and a second electrode connected to the eighth node, wherein the gate of the driving element is electrically connected to the fourth node, the first light emitting element includes an anode connected to the sixth node and a cathode arranged to have a cathode voltage applied, The second light emitting element includes an anode connected to the seventh node and a cathode arranged to have a cathode voltage applied thereto.

16. The display panel according to any one of claims 12 to 15, wherein: In each of the first mode and the second mode, the voltage of the N-1th scan signal is the gate-on voltage during a first period, is the gate-off voltage during a second period after the first period, and is the gate-off voltage during a third period after the second period, In each of the first mode and the second mode, the voltage of the Nth scan signal is the gate-off voltage during the first period and the third period, and is the gate-on voltage during the second period, In each of the first mode and the second mode, the voltage of the light emitting signal is the gate-off voltage during the first period and the second period, and is the gate-on voltage during the third period, The voltage of the first mode selection signal is the gate-on voltage during the first period, the second period, and the third period of the first mode, and is the gate-off voltage during the first period, the second period, and the third period of the second mode, The voltage of the second mode selection signal is the gate-off voltage during the first period, the second period, and the third period of the first mode, and is the gate-on voltage during the first period, the second period, and the third period of the second mode, In the first mode, the voltage of the first mode signal applied to the first node is the voltage of the light emitting signal, and the voltage of the second mode signal applied to the second node is the gate cut-off voltage. In the second mode, a voltage of a first mode signal applied to the first node is the gate-off voltage, and a voltage of a second mode signal applied to the second node is a voltage of the light emitting signal.

17. A display panel according to any one of the preceding claims, wherein light is emitted from the first light emitting element at a wide viewing angle when driven in the first mode, and light is emitted from the second light emitting element at a narrow viewing angle when driven in the second mode.

18. A display device comprising: The display panel according to claim 1, wherein a plurality of data lines, a plurality of gate lines, a plurality of power lines and a plurality of pixel circuits are provided in the display panel; a data driver configured to provide a data voltage to the data line; a gate driver configured to receive a gate timing signal and provide a scanning signal and a light emitting signal to the gate line; as well as The level shifter is configured to output a first mode selection signal, a second mode selection signal and the gate timing signal.

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