Gate signal generating circuit and display device including the same

Abstract

The invention relates to a strobe signal generation circuit and a display device including the same. The display device includes: a display panel configured to display an image; and a gate signal generation circuit configured to provide a gate signal to the display panel, the strobe signal generation circuit includes a signal control circuit configured to control a Q node and a signal output circuit configured to operate based on a voltage of the Q node to output the strobe signal, and the signal output circuit includes at least one pull-up transistor and at least one pull-down transistor, at least one pull-up transistor and at least one pull-down transistor each include a gate commonly connected to the Q node.

Description

Technical Field

[0001] The present disclosure relates to a strobe signal generation circuit and a display device including the strobe signal generation circuit, and more particularly, for example but not limited to, a display device including at least two transistors having different threshold voltage characteristics. Background Art

[0002] With the progress of information technology, the market for display devices as a connection medium between users and information is growing. Therefore, the use of display devices such as light-emitting display devices, quantum dot display (QDD) devices, and liquid crystal display (LCD) devices is increasing.

[0003] The above display device includes: a display panel including a plurality of sub-pixels; a driver that outputs a driving signal for driving the display panel; and a power supply that generates a power supply to be provided to the display panel or the driver.

[0004] In such a display device, when a driving signal (e.g., a scan signal and a data signal) is provided to each sub-pixel provided in the display panel, the selected sub-pixel can transmit light or can emit light by itself, and thus an image can be displayed.

[0005] The descriptions provided in this related art section should not be assumed to be prior art merely because they are mentioned in or are associated with the descriptions in the related art section. The descriptions in the related art section may include information that describes one or more aspects of the subject technology, and the descriptions in this section do not limit the present disclosure. Summary of the Invention

[0006] The present disclosure can simplify the circuit for configuring a shift register based on at least two transistors having different threshold voltage characteristics, thereby enabling a narrow bezel of the display panel.

[0007] The object according to the present disclosure is not limited to the above object. Other objects and advantages not mentioned according to the present disclosure can be understood based on the following description, and can be more clearly understood based on the embodiments according to the present disclosure. In addition, it will be readily understood that the objects and advantages according to the present disclosure can be achieved by using the means shown in the claims or combinations thereof.

[0008] To achieve these objects and other advantages, and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, a display device includes: a display panel configured to display an image; and a gate signal generation circuit configured to provide a gate signal to the display panel, wherein the gate signal generation circuit includes a signal control circuit configured to control a Q node and a signal output circuit configured to operate based on a voltage of the Q node to output the gate signal, and the signal output circuit includes at least one pull-up transistor and at least one pull-down transistor, and at least one pull-up transistor and at least one pull-down transistor each include a gate commonly connected to the Q node.

[0009] At least one of the pull-up transistor and the pull-down transistor may include a first gate provided in a lower layer of a semiconductor layer and a second gate provided in an upper layer of the semiconductor layer.

[0010] The at least one pull-up transistor may include a first gate provided in a lower layer of a semiconductor layer and a second gate provided in an upper layer of the semiconductor layer.

[0011] The first gate may be connected to an output terminal of the signal output circuit unit.

[0012] When the pull-up transistor is turned on, a first voltage may be applied to the first gate, and a second voltage lower than the first voltage may be applied to the second gate.

[0013] When the pull-up transistor is turned off, a third voltage lower than the second voltage may be applied to the first gate, and the first voltage may be applied to the second gate.

[0014] In the pull-up transistor or the pull-down transistor, at least one of a shape of the semiconductor layer, a gate insulating layer, and a gate may be different.

[0015] In another aspect of the present disclosure, a gate signal generation circuit includes: a signal control circuit configured to control a Q node; and a signal output circuit configured to operate based on a voltage of the Q node to output a gate signal, wherein the signal output circuit includes at least one pull-up transistor and at least one pull-down transistor, and the at least one pull-up transistor and the at least one pull-down transistor each include a gate commonly connected to the Q node.

[0016] At least one of the pull-up transistor and the pull-down transistor may include a first gate provided in a lower layer of a semiconductor layer and a second gate provided in an upper layer of the semiconductor layer.

[0017] The at least one pull-up transistor may include a first gate disposed in a lower layer of the semiconductor layer and a second gate disposed in an upper layer of the semiconductor layer.

[0018] The first gate may be connected to an output terminal of the signal output circuit unit.

[0019] When the pull-up transistor is turned on, a first voltage may be applied to the first gate, and a second voltage lower than the first voltage may be applied to the second gate. When the pull-up transistor is turned off, a third voltage lower than the second voltage may be applied to the first gate, and the first voltage may be applied to the second gate.

[0020] In the pull-up transistor or the pull-down transistor, at least one of the semiconductor layer, the gate insulating layer, and the gate may have a different shape.

[0021] In another aspect of the present disclosure, a display device includes: a display panel configured to display an image; and a gate signal generation circuit configured to provide a gate signal to the display panel. The gate signal generation circuit includes a signal control circuit configured to control a Q node and a signal output circuit configured to operate based on a voltage of the Q node to output the gate signal. The signal output circuit includes at least one pull-up transistor and at least one pull-down transistor. Each of the at least one pull-up transistor and the at least one pull-down transistor includes a gate commonly connected to the Q node. The pull-up transistor has a negative threshold voltage characteristic, and the pull-down transistor has a positive threshold voltage characteristic.

[0022] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the claimed present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. The above and other objects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings. In the drawings:

[0024] Figure 1 schematically shows a block diagram of a light-emitting display device, and Figure 2 schematically shows Figure 1 the sub-pixels shown in

[0025] Figure 3 and Figure 4is a diagram for describing the configuration of a gate driver of the gate-in-panel (GIP) type, and Figure 5 is a diagram showing an example arrangement of a GIP type gate driver;

[0026] Figure 6 is a block diagram showing a shift register according to a first exemplary embodiment, Figure 7 is a diagram showing Figure 6 a first exemplary diagram of some elements of the Nth stage in the shift register shown; Figure 8 is a diagram for describing the characteristics of transistors included in a signal output circuit unit, and Figure 9 and Figure 10 are diagrams for describing the operation of the signal output circuit unit;

[0027] Figure 11 and Figure 12 are diagrams showing Figure 7 the cross-sectional surface and operating state of each of the pull-up transistor and the pull-down transistor shown, and Figure 13 and Figure 14 are diagrams for describing a comparative example and a first exemplary embodiment by comparison;

[0028] Figure 15 is a diagram showing the cross-sectional surface of each of the pull-up transistor and the pull-down transistor according to a second exemplary embodiment, Figure 16 is a diagram showing the cross-sectional surface of each of the pull-up transistor and the pull-down transistor according to a modified example of the second exemplary embodiment, and Figures 17 to 20 is a diagram for describing parts that can be referred to in the case of implementing the pull-up transistor and the pull-down transistor based on the second exemplary embodiment;

[0029] Figure 21 is a diagram showing the cross-sectional surface of each of the pull-up transistor and the pull-down transistor according to a third exemplary embodiment, and Figure 22 is a diagram for describing parts that can be referred to in the case of implementing the pull-up transistor and the pull-down transistor based on the third exemplary embodiment;

[0030] Figure 23 is a diagram showing the cross-sectional surface of each of the pull-up transistor and the pull-down transistor according to a fourth exemplary embodiment;

[0031] Figures 24 to 26 is a diagram for describing the structure of a transistor according to another exemplary embodiment; and

[0032] Figure 27 and Figure 28 are diagrams showing some elements of the Nth stage according to another exemplary embodiment.

[0033] Throughout the accompanying drawings and the detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. The relative sizes and depictions of these elements may be exaggerated for clarity, illustration, and convenience. Detailed Embodiments

[0034] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. The progression of the described processing steps and / or operations is an example; however, the order of the steps and / or operations is not limited to the order set forth herein and may be changed as is known in the art, except for steps and / or operations that must occur in a specific order. The names of the corresponding elements used in the following description may be selected only for the convenience of writing the specification and may thus be different from the names used in actual products.

[0035] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present disclosure to those skilled in the art.

[0036] The present disclosure can be applied to various display devices. For example, a display device according to the present disclosure can be applied to various display devices such as a television (TV), a video player, a personal computer (PC), a home theater, an electronic device for a vehicle, and a smart phone, but is not limited thereto. A display device according to the present disclosure can be implemented as a light-emitting display device, an electrophoretic display device, a quantum dot display (QDD) device, a liquid crystal display (LCD) device, a micro LED (light-emitting device) display device, or a micro LED display device. Hereinafter, for convenience of description, a light-emitting display device that self-emits light by using, for example, an inorganic light-emitting diode or an organic light-emitting diode will be described.

[0037] Features of various embodiments of the present disclosure can be partially or completely combined with each other and can be technically related to or operable with each other. Embodiments can be implemented independently of each other and can be implemented together in an associated relationship.

[0038] In addition, the transistors described below can be implemented with n-type transistors, p-type transistors, or a combination of n-type transistors and p-type transistors. A transistor can be a three-electrode element including a gate, a source, and a drain. The source can be an electrode that provides carriers to the transistor. In a transistor, carriers can flow starting from the source. The drain can be an electrode through which carriers flow out of the transistor to the outside. That is, in a transistor, carriers flow from the source to the drain.

[0039] In a p-type transistor, since the carriers are holes, the source voltage can be higher than the drain voltage, causing the holes to flow from the source to the drain. In a p-type transistor, since the holes flow from the source to the drain, the current can flow from the source to the drain. On the other hand, in an n-type transistor, since the carriers are electrons, the source voltage can be lower than the drain voltage, causing the electrons to flow from the source to the drain. In an n-type transistor, since the electrons flow from the drain to the source, the current can flow from the drain to the source. However, the source and drain of a transistor can be switched between each other based on the voltage applied thereto. Based on this, in the following description, one of the source and the drain will be described as the first electrode, and the other of the source and the drain will be described as the second electrode.

[0040] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings. For ease of explanation, the scales of the components shown in the drawings have scales different from the actual scales, and thus are not limited to the scales shown in the drawings.

[0041] Figure 1 is a block diagram schematically showing a light-emitting display device, and Figure 2 is schematically showing Figure 1 the sub-pixels shown in

[0042] As Figure 1 and Figure 2 shown, a light-emitting display device according to an embodiment of the present disclosure may include a video supply unit 110, a timing controller 120, a gate driver (gate signal generation circuit) 130, a data driver 140, a display panel 150, a power supply 180, etc.

[0043] The video supply unit 110 (set-top or host system) may output various drive signals and image data signals (video data signals) supplied from the outside or stored in its internal memory. The video supply unit 110 may provide a data signal and various drive signals to the timing controller 120.

[0044] The timing controller 120 may be a device configured to control the operations of the data driver 140 and the gate driver 130. The timing controller 120 may control the driving timings of the plurality of data lines DL1 to DLn and the driving timings of the plurality of gate lines GL1 to GLm. The timing controller 120 may output a gate timing control signal GDC for controlling the operation timing of the gate driver 130, a data timing control signal DDC for controlling the operation timing of the data driver 140, and various synchronization signals (vertical synchronization signal VSYNC and horizontal synchronization signal HSYNC). Here, the horizontal synchronization signal HSYNC is a signal indicating the time taken for one horizontal line of the display screen, and the vertical synchronization signal VSYNC is a signal indicating the time taken for displaying one frame of the screen. The timing controller 120 may provide the data timing control signal DDC and the data signal DATA supplied from the video supply unit 110 to the data driver 140. The timing controller 120 may be implemented as various circuits or electronic components such as an integrated circuit (IC) type and may be mounted on a printed circuit board (PCB), but is not limited thereto. Alternatively, the timing controller 120 may be implemented as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor, but is not limited thereto.

[0045] The gate driver 130 may output a gate signal (or gate voltage) in response to the gate timing control signal GDC supplied from the timing controller 120. The gate driver 130 is a circuit configured to drive the plurality of gate lines GL1 to GLm and may output a gate signal to the plurality of gate lines GL1 to GLm. The gate driver 130 may provide a gate signal to the plurality of sub-pixels included in the display panel 150 through the plurality of gate lines GL1 to GLm. The gate driver 130 may be implemented as an IC type or may be directly disposed on the display panel 150 in a GIP type, but is not limited thereto. Alternatively, the gate driver 130 may be directly disposed on the display panel 150 in a chip on glass (COG) type, a chip on film (COF) type, or the like.

[0046] In response to the data timing control signal DDC provided from the timing controller 120, the data driver 140 may sample and latch the data signal DATA based on the gamma reference voltage, convert the digital data signal into an analog data voltage, and output the analog data voltage. The data driver 140 is a circuit configured to drive the plurality of data lines DL1 to DLn and may output a data signal, such as a data voltage, to the plurality of data lines DL1 to DLn. The data driver 140 may provide a data voltage to the sub-pixels of the display panel 150 through the plurality of data lines DL1 to DLn, respectively. The data driver 140 may be implemented as an IC type or may be mounted on the display panel 150 or the PCB, but is not limited thereto.

[0047] The power supply 180 may generate a high-level voltage and a low-level voltage based on an external input voltage supplied from the outside, and may output the high-level voltage and the low-level voltage through a first power supply line EVDD and a second power supply line EVSS. In addition to the high-level voltage and the low-level voltage, the power supply 180 may also generate and output a voltage required to drive the gate driver 130 (e.g., a gate voltage including a gate high voltage and a gate low voltage) or a voltage required to drive the data driver 140 (a drain voltage including a drain voltage and a semi-drain voltage).

[0048] The display panel 150 may display an image (video) based on a driving voltage including a high-level voltage and a low-level voltage and a driving signal including a gate signal and a data voltage. Sub-pixels of the display panel 150 may each emit light by themselves. The display panel 150 may be manufactured based on a substrate having rigidity or flexibility, such as glass, silicon, or polyimide. Alternatively, the substrate may include a flexible polymer film. For example, the flexible polymer film may be made of any one of the following: polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polyethersulfone (PES), cycloolefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, polyimide (PI) film, and polystyrene (PS), which are only examples and are not necessarily limited thereto. Each of the plurality of sub-pixels may emit light having different wavelengths from each other. The plurality of sub-pixels may include a first sub-pixel to a third sub-pixel that emit different color lights from each other. In addition, the plurality of sub-pixels that emit light may include pixels including red, green, and blue, where the red, green, and blue sub-pixels may be arranged in a repeating manner, or may include pixels including red, green, blue, and white, where the red, green, blue, and white sub-pixels may be arranged in a repeating manner, or the red, green, blue, and white sub-pixels may be arranged in a quaternary type.

[0049] For example, one sub-pixel SP may be connected to a first data line DL1, a first gate line GL1, a first power supply line EVDD, and a second power supply line EVSS, and may include a pixel circuit including a switching transistor, a driving transistor, a capacitor, and an organic light-emitting diode. The sub-pixel SP used in the light-emitting display device may emit light by itself, and may be complex in terms of the configuration of the circuit. In addition, the light-emitting organic light-emitting diodes may be diversified, and the compensation circuits for compensating for the degradation of the driving transistor that provides the driving current required to drive the organic light-emitting diodes may be diversified. Therefore, the sub-pixel SP may be simply shown in a block shape. In the pixel circuit of the present disclosure, various configurations of the compensation circuit are possible.

[0050] In the above description, each of the timing controller 120, the gate driver 130, and the data driver 140 is described as a single element. However, depending on the implementation type of the light-emitting display device, one or more of the timing controller 120, the gate driver 130, and the data driver 140 may be integrated into one IC, but is not limited thereto.

[0051] Figure 3 And Figure 4 is a diagram for describing the configuration of the GIP type gate driver 130, and Figure 5 is a diagram showing an example of the layout of the GIP type gate driver 130.

[0052] As Figure 3 shown, the GIP type gate driver 130 may include a shift register 131 and a level shifter 135. The level shifter 135 may generate a scan clock signal Clks and a start signal Vst based on signals and voltages output from the timing controller 120 and the power supply 180. The shift register 131 may operate based on the clock signal Clks and the start signal Vst output from the level shifter 135, and may output gate signals Gout[1] to Gout[m] through output terminals Out[1] to Out[m].

[0053] As Figure 3 shown, the level shifter 135 may be independently set to a different IC type from the shift register 131, or as Figure 4 shown, the level shifter 135 may be included in the power supply 180. However, this may be merely one implementation, and the embodiments of the present disclosure are not limited thereto.

[0054] As Figure 5 shown, the display panel 150 may include a display area AA and a non-display area NA, and the non-display area NA is provided near, around, or surrounding the display area AA. As Figure 5 shown, in the GIP type gate driver 130, a first shift register 131a and a second shift register 131b for outputting gate signals may be provided in the non-display area NA of the display panel 150. The first shift register 131a and the second shift register 131b may be formed as a thin film type in the display panel 150 based on the GIP type. Examples in which the first shift register 131a and the second shift register 131b are respectively provided in the left non-display area NA and the right non-display area NA of the display panel 150 are shown, but the embodiments of the present disclosure are not limited thereto.

[0055] Figure 6 is a block diagram showing the shift register 131 according to the first exemplary embodiment, Figure 7 is showingFigure 6 A first exemplary diagram of some components of the Nth stage in the shift register 131 shown Figure 8 is a diagram for describing the characteristics of transistors included in the signal output circuit unit, and Figure 9 and Figure 10 is a diagram for describing the operation of the signal output circuit unit.

[0056] As Figure 6 shown, the shift register 131 according to the first exemplary embodiment may include a first stage STG1 to an Mth stage STGm. For example, the shift register 131 according to the first exemplary embodiment may include a first stage STG1 to an Mth stage STGm, which operate based on a clock signal applied through a clock signal line CLKS and output strobe signals Gout[1] to Gout[m] through output terminals Out[1] to Out[m].

[0057] The first stage STG1 to the Mth stage STGm may have a dependent connection relationship to output the strobe signals Gout[1] to Gout[m] in this order or in the reverse order through the output terminals Out[1] to Out[m]. As an example, the output terminal (e.g., carry signal output terminal) of the first stage STG1 may be connected to the input terminal (e.g., start signal input terminal) of the Ith stage (where I may be an integer of 2 or greater). For example, the output terminal (e.g., carry signal output terminal) of the first stage STG1 may be connected to the input terminal (e.g., start signal input terminal) of the second stage STG2. However, this may be merely one embodiment, and the embodiments of the present disclosure are not limited thereto.

[0058] As Figure 6 and Figure 7 shown, the Nth stage STGN according to the first exemplary embodiment may include a signal control circuit unit SC and a signal output circuit unit OC, but is not limited thereto. Here, the Nth stage STGN may correspond to one of the respective stages included in the first stage STG1 to the Mth stage STGm.

[0059] The signal control circuit unit SC can be connected to the clock signal line CLK, the carry signal line CY, the first input line VINH, the second input line VINM, and the third input line VINL. The signal control circuit unit SC can receive the clock signal applied through the clock signal line CLK, the carry signal applied through the carry signal line CRY, the first voltage applied through the first input line VINH, the second voltage applied through the second input line VINM, and the third voltage applied through the third input line VINL. The signal control circuit unit SC can operate and control the Q node QN based on the clock signal applied through the clock signal line CLK, the carry signal (start signal in the case of the first stage) applied through the carry signal line CRY, the first voltage applied through the first input line VINH, the second voltage applied through the second input line VINM, and the third voltage applied through the third input line VINL. The levels of the first voltage to the third voltage can have the relationship of "first voltage > second voltage > third voltage". However, this is merely one embodiment, and the embodiments of the present disclosure are not limited thereto.

[0060] To control the signal output circuit unit OC, the signal control circuit unit SC can operate based on the clock signal, the carry signal, the first voltage, and the second voltage, and can control the internal circuit such that the first voltage or the second voltage is charged in the Q node QN.

[0061] The signal output circuit unit OC can be connected to the Q node QN of the signal control circuit unit SC, the first input line VINH, and the third input line VINL. The signal output circuit unit OC can operate based on the voltage charged in the Q node QN, and can output the first voltage applied through the first input line VINH or the third voltage applied through the third input line VINL as a strobe signal. The strobe signal output based on the first voltage can be defined as a gate high voltage, and the strobe signal output based on the third voltage can be defined as a gate low voltage, but is not limited thereto.

[0062] The signal output circuit unit OC can include a pull-up transistor T6 and a pull-down transistor T7. The pull-up transistor T6 can include a first electrode, a second electrode, and two gates, and the pull-down transistor T7 can include a first electrode, a second electrode, and one gate. Different from the pull-down transistor T7, the pull-up transistor T6 can include two gates respectively provided in the lower layer and the upper layer with respect to the semiconductor layer. The related part can refer to the cross-sectional surface described below. For example, the first electrode of the pull-up transistor T6 can be a source or a drain, and the second electrode of the pull-up transistor T6 can be a drain or a source, but is not limited thereto. Similarly, the first electrode of the pull-down transistor T7 can be a source or a drain, and the second electrode of the pull-down transistor T7 can be a drain or a source, but is not limited thereto.

[0063] The pull-up transistor T6 may include a first gate connected to the Q node QN, a second gate connected to its output terminal OUT[1], a first electrode connected to the first input line VINH, and a second electrode connected to the output terminal OUT[1], but is not limited thereto. The pull-down transistor T7 may include a gate connected to the Q node QN, a first electrode connected to the third input line VINL, and a second electrode connected to the output terminal OUT[1], but is not limited thereto. Alternatively, the pull-down transistor T7 may include a first gate and a second gate. That is, at least one of the pull-up transistor T6 and the pull-down transistor T7 may include a first gate and a second gate.

[0064] As Figures 6 to 8 shown, the pull-up transistor T6 and the pull-down transistor T7 may have different threshold voltage characteristics. Referring to the graph associated with the gate-source voltage Vgs of Figure 8 , the pull-up transistor T6 may have a negative threshold voltage characteristic, and the pull-down transistor T7 may have a positive threshold voltage characteristic, but is not limited thereto.

[0065] The pull-up transistor T6 may have a negative threshold voltage characteristic, and thus may be turned on based on a second voltage Mid lower than the first voltage High. For example, the second voltage Mid may be set to a level close to 0V. However, this may be merely an embodiment and may be changed based on the driving method and implementation type of the light-emitting display device. The pull-down transistor T7 may have a positive threshold voltage characteristic, and thus may be turned on based on the first voltage High higher than the second voltage Mid. For example, the first voltage High may be set to a level close to 10V to 20V. However, this may be merely an embodiment and may be changed based on the driving method and implementation type of the light-emitting display device.

[0066] In addition, in Figures 8 to 10 , examples in which the pull-up transistor T6 has a negative threshold voltage characteristic and the pull-down transistor T7 has a positive threshold voltage characteristic may be described, but it may be the opposite. Alternatively, examples in which the pull-down transistor T7 has a negative threshold voltage characteristic and the pull-up transistor T6 has a positive threshold voltage characteristic are possible.

[0067] Hereinafter, for example, in the case where the pull-up transistor T6 has a negative threshold voltage characteristic and the pull-down transistor T7 has a positive threshold voltage characteristic, the operation will be described as follows.

[0068] The first gate of the pull-up transistor T6 may be connected to the Q node QN. As Figure 9As shown, when charging the second voltage Mid in the Q node QN, the pull-up transistor T6 can be turned on. When the pull-up transistor T6 is turned on, the signal output circuit unit OC can output a gate high voltage strobe signal Out[1](H) through its output terminal OUT[1]. The gate high voltage strobe signal Out[1](H) can be generated based on the first voltage applied through the first input line VINH.

[0069] In addition, the second gate of the pull-up transistor T6 can be connected to the output terminal OUT[1] of the signal output circuit unit OC. Therefore, when charging the second voltage Mid in the Q node QN, the pull-up transistor T6 can be turned on by the second voltage Mid initially applied through the first gate, and then can be turned on by the first voltage High applied through the second gate (the on characteristic is stably maintained / enhanced).

[0070] The gate of the pull-down transistor T7 can be connected to the Q node QN. As Figure 10 shown, when charging the first voltage High in the Q node QN, the pull-down transistor T7 can be turned on. When the pull-down transistor T7 is turned on, the signal output circuit unit OC can output a gate low voltage strobe signal Out[1](L) through the output terminal OUT[1]. The gate low voltage strobe signal Out[1](L) can be generated based on the third voltage L applied through the third input line VINL.

[0071] In addition, the second gate of the pull-up transistor T6 can be connected to the output terminal OUT[1] of the signal output circuit unit OC. Therefore, when charging the first voltage High in the Q node QN, the pull-up transistor T6 can be turned off by the third voltage L output through the output terminal OUT[1] of the signal output circuit unit OC (the off characteristic is stably maintained).

[0072] Referring to the above description, the pull-up transistor T6 can have an on condition because the first voltage High is applied to the second gate, but as the third voltage L lower than the first voltage High is applied to the first gate, the threshold voltage can shift in the positive direction. In addition, when the level of the third voltage L is applied low enough, the pull-up transistor T6 can be turned off. Here, the condition allowing the level of the third voltage L to be low enough can be achieved by adjusting the ratio of the capacitors formed in the first gate or the second gate, or by increasing or decreasing the level of the voltage used as the third voltage L.

[0073] Figure 11 and Figure 12 are diagrams showing Figure 7 the cross-sectional surface and the operating state of each of the pull-up transistor and the pull-down transistor shown, and Figure 13 and Figure 14It is a diagram for describing a comparative example and a first exemplary embodiment by comparison.

[0074] As Figure 11 and Figure 12 shown, according to the first exemplary embodiment, the pull-up transistor T6 and the pull-down transistor T7 can be formed of an insulating material, a metal material, or a semiconductor material on the substrate SUB, and can be formed by a process of patterning the transistors in a process sequence.

[0075] The first gate BG of the pull-up transistor T6 can be provided on the substrate SUB. The first gate BG of the pull-up transistor T6 can be defined as a lower gate. The first insulating layer INS1 covering the first gate BG of the pull-up transistor T6 can be provided on the substrate SUB. The semiconductor layer ACT of each of the pull-up transistor T6 and the pull-down transistor T7 can be provided on the first insulating layer INS1. The semiconductor layer ACT can be selected as an oxide semiconductor, and regions other than the channel regions covered by the second gate TG1 of the pull-up transistor T6 and the gate TG2 of the pull-down transistor T7 can be conductive and can have a metallic property rather than a semiconductor property. As an example, the first gate of at least one of the pull-up transistor T6 and the pull-down transistor T7 can be provided in the lower layer of the semiconductor layer ACT, and the second gate of at least one of the pull-up transistor T6 and the pull-down transistor T7 can be provided in the upper layer of the semiconductor layer ACT, but is not limited thereto. For example, referring to Figure 11 , the first gate of the pull-up transistor T6 can be provided in the lower layer of the semiconductor layer ACT, and the second gate of the pull-up transistor T6 can be provided in the upper layer of the semiconductor layer ACT.

[0076] The gate insulating layer GI of each of the pull-up transistor T6 and the pull-down transistor T7 can be provided on the semiconductor layer ACT. For example, the gate insulating layer GI of each of the pull-up transistor T6 and the pull-down transistor T7 can be provided on a part of the semiconductor layer ACT. The second gate TG1 of the pull-up transistor T6 and the gate TG2 of the pull-down transistor T7 can be provided on the gate insulating layer GI. The second gate TG1 of the pull-up transistor T6 and the gate TG2 of the pull-down transistor T7 can be defined as upper gates.

[0077] The second insulating layer INS2 covering the second gate TG1 of the pull-up transistor T6 and the gate TG2 of the pull-down transistor T7 can be provided on the first insulating layer INS1. For example, the second insulating layer INS2 covering the second gate TG1 of the pull-up transistor T6 and the gate TG2 of the pull-down transistor T7 can be provided on the semiconductor layer ACT. The source-drain electrodes SD1 to SD3 of the pull-up transistor T6 and the pull-down transistor T7 can be provided on the second insulating layer INS2.

[0078] The first input line VINH can be connected to the first electrode of the pull-up transistor T6 through the first source-drain SD1. The output terminal OUT[1] can be connected to the second electrode of the pull-up transistor T6 and the second electrode of the pull-down transistor T7 through the second source-drain SD2. The third input line VINL can be connected to the first electrode of the pull-down transistor T7 through the third source-drain SD3.

[0079] By comparing Figure 13 and Figure 14 it can be seen that the signal output circuit unit OC according to the comparative example and the signal output circuit unit OC according to the first exemplary embodiment can be the same as the signal output circuit unit including the pull-up transistor T6 and the pull-down transistor T7.

[0080] However, the signal output circuit unit OC according to the comparative example may require circuits for controlling each of the Q node QN and the QB node QBN, but the signal output circuit unit OC according to the first exemplary embodiment may only require a circuit for controlling the Q node QN.

[0081] The conditions for driving the pull-up transistor T6 and the pull-down transistor T7 in the comparative example can be the same as the operating state table shown in the circuit diagram of Figure 13 and the conditions for driving the pull-up transistor T6 and the pull-down transistor T7 in the first exemplary embodiment can be the same as the operating state table shown in the circuit diagram of Figure 14 Figure.

[0082] Figure 15 Figure shows a cross-sectional surface of each of the pull-up transistor and the pull-down transistor according to the second exemplary embodiment, Figure 16 Figure shows a cross-sectional surface of each of the pull-up transistor and the pull-down transistor according to a modification example of the second exemplary embodiment, and Figures 17 to 20 Figure is a diagram for describing parts that can be referred to when implementing the pull-up transistor and the pull-down transistor based on the second exemplary embodiment.

[0083] As Figure 15 shown, according to the second exemplary embodiment, the pull-up transistor T6 and the pull-down transistor T7 can have the same layered structure as the first exemplary embodiment, but can have some different structures at the periphery of the semiconductor layer ACT. This will be described below.

[0084] The semiconductor layer ACT of the pull-down transistor T7 may include a region exposing the first insulating layer INS1 disposed therebelow. The gate insulating layer GI of the pull-down transistor T7 may be formed in an island shape similar to the gate TG2, and may include a region covering a part of each of the side surface and the upper surface of the semiconductor layer ACT and a region covering a part of the upper surface of the first insulating layer INS1. The second insulating layer INS2 covering the gate TG2 of the pull-down transistor T7 may be disposed on a part of the first insulating layer INS1. The second insulating layer INS2 covering the second gate TG1 of the pull-up transistor T6 may be disposed on the semiconductor layer ACT.

[0085] As Figure 16 shown, according to a modification example of the second exemplary embodiment, the pull-up transistor T6 and the pull-down transistor T7 may have the same layered structure as the first exemplary embodiment, but may have some different structures at the periphery of the semiconductor layer ACT. This will be described below.

[0086] The semiconductor layer ACT of the pull-down transistor T7 may include a region exposing the first insulating layer INS1 disposed therebelow. The gate insulating layer GI of the pull-down transistor T7 may be formed in an island shape similar to the gate TG2, and may include a region covering a part of the semiconductor layer ACT. That is, as Figure 17 shown, the width of the semiconductor layer ACT located below the gate insulating layer GI of the pull-down transistor T7 may be greater than the width of the gate insulating layer GI of the pull-down transistor T7.

[0087] As Figure 17 and Figure 18 shown, according to the second exemplary embodiment, the first semiconductor layer ACT1 of the pull-up transistor T6 may have a rectangular shape. The second semiconductor layer ACT2 of the pull-down transistor T7 may have a rectangular shape and may have the same size as the first semiconductor layer ACT1 of the pull-up transistor T6, or may have a rectangular shape (striped shape) patterned and divided into four parts in the first direction (horizontal direction). That is, the first semiconductor layer ACT1 of the pull-up transistor T6 and the second semiconductor layer ACT2 of the pull-down transistor T7 may have different shapes.

[0088] As Figure 19 shown, according to a variation of the second exemplary embodiment, the first semiconductor layer ACT1 of the pull-up transistor T6 may have a rectangular shape. The second semiconductor layer ACT2 of the pull-down transistor T7 may have a rectangular shape and may have the same size as the first semiconductor layer ACT1 of the pull-up transistor T6, but a plurality of grooves HH may be provided in a region adjacent to the gate TG2 of the pull-down transistor T7.

[0089] As Figure 20 shown, the threshold voltage Vth of a transistor can be offset based on the width of the channel region of a semiconductor layer. Thus, Figures 17 to 19 the pull-up transistor T6 shown can have a negative threshold voltage characteristic because the width of the channel region of the semiconductor layer is wide, and the pull-down transistor T7 can have a positive threshold voltage characteristic because the width of the channel region of the semiconductor layer is relatively narrow.

[0090] Therefore, the pull-up transistor T6 and the pull-down transistor T7 can be implemented based on the same configuration and structure and can have different threshold voltage characteristics by changing the shape of the semiconductor layer.

[0091] In addition, in Figure 17 and Figure 19 it is shown that the second source / drains SD2-1 and SD2-2 connecting the pull-up transistor T6 and the pull-down transistor T7 to each other are isolated from each other to easily determine the structural difference between the pull-up transistor T6 and the pull-down transistor T7. In addition, in Figure 19 only the boundaries of each of the gates TG1 and TG2 are shown to easily determine the structural difference between the pull-up transistor T6 and the pull-down transistor T7.

[0092] Figure 21 is a diagram showing a cross-sectional surface of each of a pull-up transistor and a pull-down transistor according to a third exemplary embodiment, and Figure 22 is a diagram for describing parts that can be referred to in the case of implementing a pull-up transistor and a pull-down transistor based on the third exemplary embodiment.

[0093] As Figure 21 shown, according to the third exemplary embodiment, the pull-up transistor T6 and the pull-down transistor T7 can have the same layered structure as the first exemplary embodiment, but can have some different structures in the elements provided on the semiconductor layer ACT. This will be described below.

[0094] The gate insulating layer GI and the gate TG2 provided on the semiconductor layer ACT of the pull-down transistor T7 can have a longer length than the gate insulating layer GI and the gate TG1 provided on the semiconductor layer ACT of the pull-up transistor T6. To provide additional description, the pull-down transistor T7 can have a longer channel region than the pull-up transistor T6.

[0095] As Figure 22 shown, the threshold voltage Vth of a transistor can be offset based on the length of the channel region of a semiconductor layer. Thus, Figure 21The pull-up transistor T6 shown may have a negative threshold voltage characteristic because the length of the channel region of the semiconductor layer is short, and the pull-down transistor T7 may have a positive threshold voltage characteristic because the length of the channel region of the semiconductor layer is relatively long.

[0096] Therefore, the pull-up transistor T6 and the pull-down transistor T7 can be implemented based on the same configuration and structure, and can have different threshold voltage characteristics by changing the shape of the elements provided on the semiconductor layer.

[0097] Figure 23 FIG. is a diagram showing a cross-sectional surface of each of a pull-up transistor and a pull-down transistor according to a fourth exemplary embodiment.

[0098] As Figure 23 shown, according to the fourth exemplary embodiment, the pull-up transistor T6 and the pull-down transistor T7 may have the same layered structure as the first exemplary embodiment, but may have some different structures in the elements provided on the second insulating layer INS2. This will be described below. In addition, according to the fourth exemplary embodiment, the pull-up transistor T6 and the pull-down transistor T7 may have some different structures in the elements provided on the semiconductor layer ACT. This will be described below.

[0099] The gate insulating layer GI and the gate TG2 provided on the semiconductor layer ACT of the pull-down transistor T7 may have a length longer than that of the gate insulating layer GI and the gate TG1 provided on the semiconductor layer ACT of the pull-up transistor T6. For additional description, the pull-down transistor T7 may have a longer channel region than the pull-up transistor T6.

[0100] In addition, the third source / drain SD3 provided on the second insulating layer INS2 of the pull-down transistor T7 may extend upward to a region adjacent to the second source / drain SD2 to cover the gate TG2 provided below the second insulating layer INS2.

[0101] The hydrogen component may be on the second insulating layer INS2, and the third source / drain SD3 extending upward to a region adjacent to the second source / drain SD2 may block the hydrogen component. For additional description, in the fourth exemplary embodiment, the pull-down transistor T7 may have a positive threshold voltage characteristic by using a hydrogen-blocking structure for blocking the hydrogen component on the second insulating layer INS2.

[0102] In addition, in the second to fourth exemplary embodiments, for example, the threshold voltage of the pull-up transistor T6 and the threshold voltage of the pull-down transistor T7 may be implemented differently based on the transistor structure described in the first exemplary embodiment. However, the structure of the transistor applicable to the present disclosure is not limited thereto, and examples thereof will be described below.

[0103] Figures 24 to 26 This is a diagram for describing the structure of a transistor according to another exemplary embodiment. Hereinafter, in another exemplary embodiment, the differences from the structure of the transistor described in the first exemplary embodiment will be mainly described.

[0104] As Figure 24 shown, according to the first exemplary embodiment, the gate insulating layer GI may be provided in an island shape based on the positions of the electrodes SD1 to SD3, TG1, and TG2 on the semiconductor layer ACT of each of the pull-up transistor T6 and the pull-down transistor T71. The first source / drain SD1, the second source / drain SD2, and the third source / drain SD3 may be formed of the same material as the material of the gates TG1 and TG2 (e.g., the gate metal layer), and may cover a part of the upper surface of the semiconductor layer ACT and a part of each of the upper surface and the side surface of the gate insulating layer GI provided in an island shape, but is not limited thereto.

[0105] As Figure 25 shown, according to the second exemplary embodiment, based on the positions of the first source / drain SD1, the second source / drain SD2, and the third source / drain SD3 on the semiconductor layer ACT of each of the pull-up transistor T6 and the pull-down transistor T7, the first metal electrode MET1, the second metal electrode MET2, and the third metal electrode MET3 may be provided in an island shape. The gate insulating layer GI may be provided in an island shape based on the positions of the first metal electrode MET1, the second metal electrode MET2, and the third metal electrode MET3. The first source / drain SD1, the second source / drain SD2, and the third source / drain SD3 may be formed of the same material as the material of the gates TG1 and TG2 (e.g., the gate metal layer), and may cover a part of the upper surface of the electrodes MET1 to MET3 and a part of each of the upper surface and the side surface of the gate insulating layer GI provided in an island shape, but is not limited thereto.

[0106] As Figure 26 shown, according to the third exemplary embodiment, based on the positions of the first source / drain SD1, the second source / drain SD2, and the third source / drain SD3 on the semiconductor layer ACT of each of the pull-up transistor T6 and the pull-down transistor T71, the first metal electrode MET1, the second metal electrode MET2, and the third metal electrode MET3 may be provided in an island shape. The second source / drain SD2 may be formed of the same material as the material of the gates TG1 and TG2 (e.g., the gate metal layer), and may cover a part of the upper surface of the second metal electrode MET2 and a part of each of the upper surface and the side surface of the gate insulating layer GI provided in an island shape. The first source / drain SD1 and the third source / drain SD3 may be provided on the second insulating layer INS2, and may be connected to the first metal electrode MET1 and the third metal electrode MET3 through contact holes formed in the second insulating layer INS2. That is, inFigure 24 and Figure 25 In the first and second exemplary embodiments of Figure 25 , the first source-drain SD1, the second source-drain SD2, and the third source-drain SD3 may be disposed under the second insulating layer INS2. However, in Figure 26 In the third exemplary embodiment of Figure 26 , the first source-drain SD1 and the third source-drain SD3 may be disposed on the second insulating layer INS2, and the second source-drain SD2 may be disposed under the second insulating layer INS2.

[0107] Figures 24 to 26 The pull-up transistor T6 and the pull-down transistor T7 shown and described above may be implemented to have different threshold voltages based on the methods described in the first to fourth exemplary embodiments.

[0108] In addition, except for the first exemplary embodiment, the configuration of the signal output circuit unit that can be adopted based on this specification can be diversified. Therefore, this can be described as follows.

[0109] Figure 27 and Figure 28 are diagrams showing some elements of the Nth stage according to another exemplary embodiment.

[0110] As Figure 27 shown, according to the first exemplary embodiment, the signal output circuit unit OC may include a first output terminal SCOUT[1] that outputs a strobe signal and a second output terminal COUT[1] that outputs a carry signal.

[0111] The first pull-up transistor T6a and the first pull-down transistor T7a disposed on the first output terminal SCOUT[1] and the second pull-up transistor T6b and the second pull-down transistor T7b disposed on the second output terminal COUT[1] may each include a gate commonly connected to the Q node QN of the signal control circuit unit SC.

[0112] The first pull-up transistor T6a and the first pull-down transistor T7a disposed on the first output terminal SCOUT[1] may have different threshold voltage characteristics, and the second pull-up transistor T6b and the second pull-down transistor T7b disposed on the second output terminal COUT[1] may have different threshold voltage characteristics.

[0113] The first pull-up transistor T6a can be connected to the 1-1 input line VINH1, the first pull-down transistor T7a can be connected to the 3-1 input line VINL1, the second pull-up transistor T6b can be connected to the 1-2 input line VINH2, and the second pull-down transistor T7b can be connected to the 3-2 input line VINL2. Here, a voltage provided in the form of a clock signal can be applied to some of the input lines VINH1, VINH2, VINL1, and VINL2 (e.g., VINH1 and VINH2).

[0114] As Figure 28 shown, according to the second exemplary embodiment, the signal output circuit unit OC can include a first output terminal SCOUT[1] that outputs a first strobe signal, a second output terminal COUT[1] that outputs a carry signal, and a third output terminal SECOUT[1] that outputs a second strobe signal.

[0115] The first pull-up transistor T6a and the first pull-down transistor T7a provided at the first output terminal SCOUT[1], the second pull-up transistor T6b and the second pull-down transistor T7b provided at the second output terminal COUT[1], and the third pull-up transistor T6c and the third pull-down transistor T7c provided at the third output terminal SECOUT[1] can each include a gate commonly connected to the Q node QN of the signal control circuit unit SC.

[0116] The first pull-up transistor T6a and the first pull-down transistor T7a provided at the first output terminal SCOUT[1] can have different threshold voltage characteristics. In addition, the second pull-up transistor T6b and the second pull-down transistor T7b provided at the second output terminal COUT[1] can have different threshold voltage characteristics. In addition, the third pull-up transistor T6c and the third pull-down transistor T7c provided at the third output terminal SECOUT[1] can have different threshold voltage characteristics.

[0117] The first pull-up transistor T6a can be connected to the 1-1 input line VINH1, the first pull-down transistor T7a can be connected to the 3-1 input line VINL1, the second pull-up transistor T6b can be connected to the 1-2 input line VINH2, the second pull-down transistor T7b can be connected to the 3-2 input line VINL2, the third pull-up transistor T6c can be connected to the 1-3 input line VINH3, and the third pull-down transistor T7c can be connected to the 3-2 input line VINL3. Here, a voltage provided in the form of a clock signal can be applied to some of the input lines VINH1, VINH2, VINH3, VINL1, VINL2, and VINL3 (e.g., VINH1, VINH2, and VINH3).

[0118] The exemplary embodiments of the present disclosure are briefly described below.

[0119] According to an exemplary embodiment of the present disclosure, a display device is provided. The display device includes: a display panel configured to display an image; and a gate signal generation circuit configured to provide a gate signal to the display panel. Wherein, the gate signal generation circuit includes a signal control circuit configured to control a Q node and a signal output circuit configured to operate based on the voltage of the Q node to output the gate signal, and the signal output circuit includes at least one pull-up transistor and at least one pull-down transistor, and at least one pull-up transistor and at least one pull-down transistor each include a gate commonly connected to the Q node.

[0120] According to an exemplary embodiment of the present disclosure, a display device is provided. The display device includes: a display panel configured to display an image; and a gate signal generation circuit configured to provide a gate signal to the display panel. Wherein, the gate signal generation circuit includes a signal control circuit configured to control a Q node and a signal output circuit configured to operate based on the voltage of the Q node to output the gate signal, and the signal output circuit includes at least one pull-up transistor and at least one pull-down transistor, and the pull-down transistor and at least one pull-down transistor each include a gate commonly connected to the Q node, and wherein, the pull-up transistor has a negative threshold voltage characteristic, and the pull-down transistor has a positive threshold voltage characteristic.

[0121] The present disclosure can achieve the effect of implementing a CMOS circuit based on at least two transistors having different threshold voltage characteristics. In addition, the present disclosure can simplify the circuit for configuring a shift register based on at least two transistors having different threshold voltage characteristics. In addition, the present disclosure can simplify the circuit for configuring a shift register to achieve a narrow border of the display panel. In addition, the present disclosure can increase the mobility of current by using gates respectively provided in the upper layer and the lower layer of the semiconductor layer.

[0122] The effects according to the present disclosure are not limited to the above examples, and various other effects may be included in the specification.

[0123] Although the present disclosure has been specifically shown and described with reference to its exemplary embodiments, those of ordinary skill in the art will understand that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure defined by the appended claims.

[0124] Cross-reference to related applications

[0125] This application claims the benefit and priority of Korean Patent Application No. 10-2023-0195541, filed on December 28, 2023, which is incorporated herein by reference in its entirety for all purposes as if fully set forth herein.

Claims

1. A display device, comprising: a display panel, the display panel being configured to display an image; as well as a strobe signal generating circuit, the strobe signal generating circuit being configured to provide a strobe signal to the display panel, The gating signal generating circuit includes a signal control circuit configured to control the Q node and a signal output circuit configured to operate based on the voltage of the Q node to output the gating signal, and The signal output circuit includes at least one pull-up transistor and at least one pull-down transistor, each of the at least one pull-up transistor and the at least one pull-down transistor including a gate commonly connected to the Q node.

2. The display device according to claim 1, wherein: At least one of the at least one pull-up transistor and the at least one pull-down transistor includes a first gate disposed in a lower layer of a semiconductor layer and a second gate disposed in an upper layer of the semiconductor layer.

3. The display device according to claim 1, wherein: The at least one pull-up transistor includes a first gate disposed in a lower layer of a semiconductor layer and a second gate disposed in an upper layer of the semiconductor layer.

4. The display device according to claim 3, wherein: The first gate is connected to the output end of the signal output circuit.

5. The display device according to claim 4, wherein: When the at least one pull-up transistor is turned on, a first voltage is applied to the first gate, and a second voltage lower than the first voltage is applied to the second gate.

6. The display device according to claim 5, wherein: When the at least one pull-up transistor is turned off, a third voltage lower than the second voltage is applied to the first gate, and the first voltage is applied to the second gate.

7. The display device according to claim 1, wherein: In the at least one pull-up transistor or the at least one pull-down transistor, at least one of the semiconductor layer, the gate insulating layer, and the gate has a different shape.

8. A strobe signal generating circuit, the strobe signal generating circuit comprising: a signal control circuit configured to control the Q node; as well as a signal output circuit configured to operate based on the voltage of the Q node to output a gating signal, The signal output circuit includes at least one pull-up transistor and at least one pull-down transistor, and each of the at least one pull-up transistor and the at least one pull-down transistor includes a gate commonly connected to the Q node.

9. The gating signal generating circuit according to claim 8, wherein: At least one of the pull-up transistor and the pull-down transistor includes a first gate disposed in a lower layer of a semiconductor layer and a second gate disposed in an upper layer of the semiconductor layer.

10. The strobe signal generating circuit according to claim 8, wherein: The at least one pull-up transistor includes a first gate disposed in a lower layer of a semiconductor layer and a second gate disposed in an upper layer of the semiconductor layer.

11. The strobe signal generating circuit according to claim 10, wherein: When the at least one pull-up transistor is turned on, a first voltage is applied to the first gate, and a second voltage lower than the first voltage is applied to the second gate, and When the at least one pull-up transistor is turned off, a third voltage lower than the second voltage is applied to the first gate, and the first voltage is applied to the second gate.

12. The strobe signal generating circuit according to claim 10, wherein: The first gate is connected to the output end of the signal output circuit.

13. The strobe signal generating circuit according to claim 8, wherein: In the at least one pull-up transistor or the at least one pull-down transistor, at least one of the semiconductor layer, the gate insulating layer, and the gate has a different shape.

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