Pixel circuit and display device using same

Abstract

A pixel circuit according to one embodiment of the present specification includes an internal compensation unit including a driving transistor and a capacitor having a first terminal connected to a gate electrode of the driving transistor, and a data line connected to the first electrode of the driving transistor and a second terminal of the capacitor, respectively, the light emitting element is caused to emit light at a gray scale corresponding to a difference between the data voltages charged in the capacitor. Accordingly, the number of bits of data output from the channels of the data driving circuit may be reduced.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority and the benefit of Korean Patent Application No. 10 - 2023 - 0197312, filed on December 29, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] This specification relates to a pixel circuit and a display device using the pixel circuit, and more particularly, to a pixel circuit that expresses a gray level of light emission by applying data voltages to both ends of a capacitor of an internal compensation circuit via dual data lines, and a display device using the pixel circuit. Background art

[0004] With the development of information technology, in the field of display devices for presenting visual information through videos or images, many related technologies have been developed. A display device includes a display panel having a plurality of sub - pixels, a driving circuit configured to supply signals for driving the display panel, a power supply unit configured to supply power to the display panel, and the like. The driving circuit includes a gate driving circuit and a data driving circuit respectively configured to supply a gate signal and a data signal to the display panel.

[0005] Meanwhile, in a display device, a data voltage is applied to the gate electrode of a driving transistor for a relatively long period of time. During this relatively long period of time, a light - emitting element emits light to display a gray level, and thus the driving transistor continuously remains in an on - state, and the driving transistor may deteriorate due to such a long - term on - operation. That is, since a data voltage of the same polarity is applied to the gate electrode of the driving transistor for a long period of time, the interface characteristics between the gate electrode of the driving transistor and the gate insulating layer deteriorate, thereby causing a change in the threshold voltage of the driving transistor, which in turn changes the gray level of light emission of the light - emitting element and deteriorates the image display quality. To compensate for the change in the threshold voltage of the driving transistor, an internal compensation pixel structure has been proposed, which stores the current threshold voltage in a storage capacitor and then adds the current threshold voltage to the data voltage.

[0006] In a general internal compensation pixel structure, during a sampling period for detecting the threshold voltage, a pixel driving voltage (i.e., a high - potential voltage) is applied to one electrode of the storage capacitor through one data line, and a data voltage is applied to the opposite electrode of the storage capacitor through one data line. In this way, in order for a sub - pixel to express gray levels with a predetermined number of bits (e.g., 8 bits), each data output channel in the data output channels of the data driving circuit should be able to output data with a predetermined number of bits (i.e., 8 bits). Summary of the invention

[0007] This specification relates to a pixel circuit capable of reducing the number of bits of data output from a channel of a data driving circuit, and a display device using the pixel circuit.

[0008] This specification also relates to providing a pixel circuit in which a data voltage is applied to both ends of a capacitor of an internal compensation circuit through a pair of data lines to store a potential difference between the data lines in the capacitor, and a light-emitting element emits light with a gray scale corresponding to the stored voltage.

[0009] This specification also relates to providing a display device using a method of connecting one gate line and two data lines to one sub-pixel, in which the data lines are shared through a demultiplexer and time-division driving is applied.

[0010] The object of this specification is not limited to the above object, and those skilled in the art will clearly understand other objects not described herein according to the following description.

[0011] According to an aspect of the present invention, there is provided a pixel circuit including: a light-emitting element; a driving transistor electrically connected to the light-emitting element through a second electrode of the driving transistor to supply current to the light-emitting element and controlled by a voltage applied to a gate electrode of the driving transistor; a capacitor having a first terminal connected to the gate electrode of the driving transistor; and an internal compensation unit including a plurality of switching elements for sensing a threshold voltage of the driving transistor during a sampling period and supplying a current in which the threshold voltage is compensated to the light-emitting element, wherein a data line is connected to the internal compensation unit, and an analog data voltage converted from a digital data signal is supplied through the data line, wherein the light-emitting gray scale of the light-emitting element is adjusted based on the number of bits of the digital data signal, the data line includes a first data line and a second data line, wherein the first data line is electrically connected to a first electrode of the driving transistor, and the second data line is electrically connected to a second terminal of the capacitor, and during the sampling period, a difference between a voltage of the second data line and a voltage of the first data line is charged to a first voltage in the capacitor so that the light-emitting element emits light with a gray scale corresponding to the first voltage.

[0012] According to another aspect of the present invention, there is provided a display device including: a display panel in which a plurality of data lines and a plurality of gate lines cross each other and pixels are arranged; a data driver configured to convert a digital data signal into an analog data voltage and supply the analog data voltage to the plurality of data lines; a gate driver configured to supply a gate signal to the plurality of gate lines; a timing controller configured to transmit the digital data signal to the data driver and generate a signal for controlling the operation timings of the data driver and the gate driver; and a power supply unit configured to generate voltages required to drive the pixels, the data driver, the gate driver, and the timing controller, wherein each pixel in the pixels includes sub-pixels, and each sub-pixel has a pixel circuit including: a light-emitting element; a driving transistor electrically connected to the light-emitting element through a second electrode of the driving transistor to supply current to the light-emitting element and controlled by a voltage applied to a gate electrode of the driving transistor; a capacitor having a first terminal connected to the gate electrode of the driving transistor; and an internal compensation unit including a plurality of switching elements for sensing a threshold voltage of the driving transistor during a sampling period and supplying a current in which the threshold voltage is compensated to the light-emitting element, the internal compensation unit being connected to the data line and adjusting the light emission gray scale of the light-emitting element based on the number of bits of the digital data signal, the data line connected to the internal compensation unit includes a first data line and a second data line, wherein the first data line is electrically connected to a first electrode of the driving transistor, and the second data line is electrically connected to a second terminal of the capacitor, and during the sampling period, a difference between a voltage of the second data line and a voltage of the first data line is charged to a first voltage in the capacitor, so that the light-emitting element emits light with a gray scale corresponding to the first voltage.

[0013] According to another aspect of the present invention, a display device is provided, which includes: a display panel in which a plurality of data lines and a plurality of gate lines cross each other and pixels are arranged; a data driver configured to convert a digital data signal into an analog data voltage and supply the analog data voltage to the plurality of data lines; and a demultiplexing unit configured to distribute the data voltage converted from the digital data signal by the data driver to the plurality of data lines, wherein each pixel in the pixels includes sub-pixels, each sub-pixel having a pixel circuit, one of the plurality of gate lines and two of the plurality of data lines are connected to each of the sub-pixels, the two data lines connected to each of the sub-pixels include a data line to which one of the voltages obtained by dividing and converting from the digital data signal is supplied through one channel of the data driver, and a data line to which the other voltage is supplied through another channel of the data driver by being distributed by the demultiplexing unit, and the pixel circuit includes a light-emitting element, a driving transistor, the second electrode of which is electrically connected to the light-emitting element to supply current to the light-emitting element and is controlled by the voltage applied to the gate electrode of the driving transistor; a capacitor having a first terminal connected to the gate electrode of the driving transistor; and an internal compensation unit including a plurality of switching elements for sensing the threshold voltage of the driving transistor during a sampling period and supplying a current in which the threshold voltage is compensated to the light-emitting element, the first data line and the second data line, which are two data lines connected to each of the sub-pixels, are connected to the internal compensation unit to adjust the light-emitting gray scale of the light-emitting element based on the number of bits of the digital data signal, wherein the first data line is electrically connected to the first electrode of the driving transistor, and the second data line is electrically connected to the second terminal of the capacitor, and during the sampling period, the difference between the voltage of the second data line and the voltage of the first data line is charged to a first voltage in the capacitor, so that the light-emitting element emits light with a gray scale corresponding to the first voltage.

[0014] Details of other embodiments are incorporated in the detailed description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] By referring to the drawings and describing in detail the exemplary embodiments of the present disclosure, the above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art. In the drawings:

[0016] Figure 1 is a block diagram schematically showing a display device according to an embodiment of the present specification;

[0017] Figure 2A and Figure 2B are diagrams respectively showing a pixel circuit and a simplified panel structure according to an embodiment of the related art;

[0018] Figure 3A and Figure 3B are, respectively, a circuit diagram of a pixel circuit and a waveform diagram of a gate signal according to an embodiment of the present specification;

[0019] Figures 4A to 4E is a diagram showing step by step Figure 3A the driving of the pixel circuit shown in;

[0020] Figure 5A and Figure 5B are, respectively, a circuit diagram of a pixel circuit and a waveform diagram of a gate signal according to another embodiment of the present specification;

[0021] Figures 6A to 6C is a diagram showing step by step Figure 5A the driving of the pixel circuit shown in;

[0022] Figure 7 is a diagram showing a simplified panel structure according to an embodiment of the present specification;

[0023] Figure 8 and Figure 9 is a diagram showing an exemplary comparison of the data voltage ranges of the related art and the present invention;

[0024] Figure 10 is a table showing a method of expressing the gray level of a sub-pixel and exemplary data voltage values according to an embodiment of the present specification;

[0025] Figure 11 is a diagram for describing a data driving voltage (SVDD); and

[0026] Figure 12 is a graph comparing the power consumption of the data driving voltage (SVDD) between the related art and the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] The advantages and features of the present invention and methods for implementing them will be clarified by the following embodiments described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various other forms. These embodiments make the disclosure of the present invention complete and provide these embodiments to fully inform those of ordinary skill in the art to which the present invention pertains of the scope of the present disclosure. The present invention is defined only by the scope of the claims.

[0028] The figures, dimensions, ratios, angles, quantities, etc. disclosed in the accompanying drawings used to describe the embodiments of the present invention are merely exemplary and are not limited to the details shown in the present invention. Similar reference numerals always refer to similar elements. In addition, when describing the present invention, the detailed description of well-known technologies will be omitted when it is determined that the detailed description of well-known technologies may unnecessarily obscure the gist of the present invention. Terms such as "including", "having", and "consisting of" used herein are intended to allow the addition of other elements, unless these terms are used together with the term "only". Any reference to the singular may include the plural, unless otherwise explicitly stated.

[0029] Components are interpreted to include the ordinary error range, even if not explicitly stated.

[0030] For describing the positional relationship, for example, when the positional relationship between two parts is described as "on...", "above...", "below...", "next to...", etc., one or more parts may be inserted between the two parts, unless the terms "immediately" or "directly" are used in the expression.

[0031] For describing the time relationship, for example, when the time relationship is described as "after", "subsequently", "next", "before", etc., non - consecutive cases may be included, unless the terms "immediately" or "directly" are used in the expression.

[0032] The features of the various embodiments of this specification can be combined or combined with each other partially or wholly. The embodiments can interact and execute in various ways technically and can be executed independently or in association with each other.

[0033] In the display device of the present specification, a driving circuit, a gate driving circuit, etc., formed on the substrate of the display panel may include transistors. The transistors may be implemented as oxide thin film transistors (TFTs) including oxide semiconductors, low-temperature polycrystalline silicon (LTPS) TFTs including LTPS, etc. Each of the transistors may be implemented as an n-channel transistor or a p-channel transistor (i.e., an n-type transistor or a p-type transistor). For example, the transistors may be implemented as transistors having a metal-oxide-semiconductor field-effect transistor (MOSFET) structure. A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In a transistor, carriers move from the source to the drain. In the case of an n-channel transistor, the carriers are electrons. Therefore, electrons move from the source to the drain, and the source voltage is lower than the drain voltage. In an n-channel transistor, the direction of the current is from the drain to the source because electrons move from the source to the drain. In the case of a p-channel transistor, the carriers are holes. Therefore, the source voltage is higher than the drain voltage so that holes can move from the source to the drain. Since the holes of the p-channel transistor move from the source to the drain, the direction of the current is from the source to the drain. The source and drain of the transistor are not fixed, and the source and drain of the transistor may change according to the applied voltage.

[0034] Hereinafter, the gate-on voltage may be the voltage of the gate signal that can turn on the transistor. The gate-off voltage may be the voltage that can turn off the transistor. In a p-channel transistor, the on-voltage may be a low gate voltage, and the off-voltage may be a high gate voltage. In an n-channel transistor, the gate-on voltage may be a high gate voltage, and the gate-off voltage may be a low gate voltage.

[0035] Hereinafter, a pixel circuit according to an embodiment of the present specification and a display device using the pixel circuit will be described with reference to the drawings.

[0036] Figure 1 is a block diagram schematically showing a display device according to an embodiment of the present specification.

[0037] Referring to Figure 1 , the display device 100 includes a display panel 110, a data driver 120, a demultiplexing unit 130, a gate driver 140, a timing controller 150, and a power supply unit (not shown).

[0038] The display panel 110 is a component that displays an image. The display panel 110 may be implemented as a display panel used in various display devices such as a liquid crystal display device, an organic light-emitting display device, or an electrophoretic display device.

[0039] The display panel 110 includes a display area 110A defined by a plurality of pixels PX, and a non-display area 110B in which various signal lines or pads are formed. In the display area 110A of the display panel 110, a plurality of pixels PX defined by a plurality of data lines DL and a plurality of gate lines GL are arranged. Each pixel among the plurality of pixels PX is a component that displays an image by generating light. One pixel PX includes a plurality of sub-pixels (not shown), and each of the sub-pixels includes a transistor connected to the gate line GL and / or the data line DL and a pixel circuit that operates in response to a gate signal and a data signal supplied by the transistor. Depending on the configuration of the pixel circuit, the pixel PX can be implemented in a liquid crystal display panel including a liquid crystal element or an organic light emitting display panel including an organic light emitting element.

[0040] A plurality of data lines DL and a plurality of gate lines GL extending in different directions and intersecting each other are arranged in the display area 110A and the non-display area 110B of the display panel 110. The plurality of data lines DL are lines for transmitting data signals to the plurality of pixels PX, and the plurality of gate lines GL are lines for transmitting gate signals to the plurality of pixels PX.

[0041] Meanwhile, the period during which all the sub-pixels arranged in the column direction in the display area 110A are driven is referred to as one frame period. One frame period can be divided into a scanning period and a light emitting period. During the scanning period, data is addressed from each of the gate lines GL connected to the sub-pixels to the sub-pixels to write the data of the input image into each of the sub-pixels. During the light emitting period, the sub-pixels are repeatedly turned on and off according to an emission signal after the scanning period. The scanning period can be divided into an initialization period, a sampling period, and a programming period. During the scanning period, the driving circuit is initialized, the threshold voltage of the driving transistor is compensated, and the data voltage is charged. During the light emitting period, a light emitting operation is performed.

[0042] In addition, one vertical period is the period required to write one frame amount of pixel data (i.e., frame data) to all the pixels of the screen, and corresponds to one frame period. One horizontal period 1H is the time required to write the pixel data of one row sharing a gate line to the pixels PX of one pixel line, and corresponds to the time obtained by dividing one frame period by the total number of pixel lines.

[0043] The data driver 120 converts pixel data of an input image as digital data by using a digital-to-analog converter (referred to herein as "DAC") to generate an analog data voltage Vdata. The DAC receives pixel data as digital data and receives a gamma reference voltage from a gamma voltage generation circuit of a power supply unit (not shown). The data driver 120 generates a gamma compensation voltage corresponding to each gray level of the pixel data by using a voltage dividing circuit with the gamma reference voltage. The DACs of the data driver 120 are arranged in each channel of the data driver 120. The DAC converts the pixel data into a gamma compensation voltage through a switch element array that selects voltages corresponding to bits of the pixel data, and outputs the data voltage Vdata. The data voltage Vdata output from each channel of the data driver 120 may be supplied to the data lines DL of the display panel 110, or may be transmitted to the demultiplexing unit 130 through the output line DO and supplied to the data lines DL through the demultiplexing unit 130.

[0044] The demultiplexing unit 130 includes a demultiplexer 131 that demultiplexes the data voltage Vdata output through the channels of the data driver 120 in time division and distributes the time-divided data voltage Vdata to a plurality of data lines DL. Since the data voltage Vdata can be time-divided and distributed to a plurality of data lines DL through the demultiplexing unit 130, the number of channels of the data driver 120 can be reduced. The demultiplexing unit 130 may be omitted, and in this case, the channels of the data driver 120 are directly connected to the data lines DL.

[0045] The gate driver 140 is a component that generates gate signals transmitted to a plurality of pixels PX. The gate driver 140 receives a plurality of clock signals from the timing controller 150, and the levels of the plurality of clock signals are shifted from the clock signals input as transistor-transistor logic (TTL) levels. The gate driver 140 may include a shift register. The shift register may be formed in the non-display area 110B of the display panel 110 in the form of transistors by the gate-in-panel (GIP) method, but the present invention is not limited thereto. The shift register is configured by a plurality of stages that shift and output a scan signal in response to a clock signal and a drive signal. The plurality of stages included in the shift register sequentially output gate signals to a plurality of gate lines GL through a plurality of output terminals.

[0046] The timing controller 150 is a component that transmits control signals to various components of the display device. The timing controller 150 receives timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock through a receiving circuit such as a low-voltage differential signaling (LVDS) interface or a minimized transition differential signaling (TMDS) interface connected to the image board. The timing controller 150 generates control signals for controlling the operation timings of the data driver 120, the gate driver 140, and the demultiplexing unit 130 based on the input timing signals.

[0047] The power supply unit (not shown) may include a charge pump, a regulator, a buck converter, a boost converter, a gamma voltage generation circuit, etc. The power supply unit (not shown) adjusts the DC input voltage from the host system to generate the power required to drive the data driver 120, the gate driver 140, and the display panel 110. The power supply unit (not shown) may output DC voltages such as a gamma reference voltage, a gate-off voltage VGH / VEH, a gate-on voltage VGL / VEL, a pixel driving voltage (high-potential power voltage) ELVDD, a cathode voltage (low-potential power voltage) ELVSS, an initialization voltage Vini, a reference voltage Vref, etc.

[0048] Figure 2A and Figure 2B are diagrams showing a pixel circuit and a simplified panel structure according to an embodiment of the related art, respectively.

[0049] Referring to Figure 2A , in a conventional internal compensation pixel circuit, during a sampling period, the pixel driving voltage ELVDD is applied to a node B which is one electrode of a storage capacitor CST connected to the pixel driving voltage line (high-potential voltage line) ELVDD, and a data voltage is applied through one data line Vdata to a node A which is the other electrode of the storage capacitor CST connected to the gate electrode of the driving transistor D-TFT.

[0050] In this case, referring to Figure 2B , the structure of the display panel 110 may be a structure of the 1G1D (one gate line one data line) concept in which one gate line (not shown) and one data line DL are connected to one pixel PX. Here, the term 1G1D is conceptually used to help understand the description of this specification, and the description of this specification should not be construed as limiting that only one gate line is connected to one pixel PX. In Figure 2B , compared with the embodiments disclosed in this specification, the gate lines are omitted for easy visual and intuitive understanding. As described above, the data voltage DATA1 is supplied to the data line DL through the channel CH of the data driver 120.

[0051] In a conventional internally compensated pixel structure, in order for a sub-pixel to represent a gray scale corresponding to data having a predetermined number of bits (e.g., 8 bits), each of the data output channels of the data driver should be able to output data having a predetermined number of bits (i.e., 8 bits). In other words, in order to represent 256 different gray scales corresponding to 8-bit digital data using pixel data, data voltages corresponding to 8-bit data should be output from the channels of the data driver.

[0052] Hereinafter, a pixel circuit capable of reducing the number of bits of data output from the channels of the data driver will be described with reference to the following drawings.

[0053] Figure 3A And Figure 3B are a circuit diagram of a pixel circuit and a waveform diagram of a gate signal according to an embodiment of the present specification, respectively.

[0054] Referring to Figure 3A , a pixel circuit (or pixel driving circuit) for supplying a driving current to a light emitting element OLED includes a plurality of switching elements T2 to T10 and a capacitor CST. The plurality of switching elements T2 to T10 may be thin film transistors and may include p-channel transistors and n-channel transistors.

[0055] According to an embodiment of the present specification, the pixel circuit is an internally compensated circuit capable of compensating for the threshold voltage of a driving transistor D-TFT through an internal compensation unit.

[0056] Power voltages of a pixel driving voltage ELVDD, a cathode voltage ELVSS, an initialization voltage VINIT, a reset voltage VAR, and a bias stress voltage VOBS are applied to the pixel circuit, and pixel driving signals of a first scan signal SCAN1, a second scan signal SCAN2, a third scan signal SCAN3, a fourth scan signal SCAN4, an emission signal EM, a first data voltage DATA1, and a second data voltage DATA2 are applied to the pixel circuit.

[0057] In one embodiment of the present specification, the first data voltage DATA1 and the second data voltage DATA2 may be data voltages supplied by dividing a digital data signal that is pixel data of an input image to reduce the number of bits of the pixel data and converting the digital data signal into an analog data voltage. In addition, the voltage DATA1 of the first data line may be the data voltage of the lower bits of the digital data signal, and the voltage DATA2 of the second data line may be the data voltage of the higher bits of the digital data signal. In other words, a digital data signal having a predetermined number of bits is divided into a higher-bit data signal and a lower-bit data signal, and the lower-bit analog-converted data voltage is supplied to the first data line, and the higher-bit analog-converted data voltage is supplied to the second data line.

[0058] Each of the scan signals SCAN1 to SCAN4 and the emission signal EM has an on-level pulse or an off-level pulse at a fixed time interval. In one embodiment of the present specification, the on-voltage of the p-channel transistor may be a low gate voltage, and the off-voltage of the p-channel transistor may be a high gate voltage. The on-voltage of the n-channel transistor may be a high gate voltage, and the off-voltage of the n-channel transistor may be a low gate voltage.

[0059] The light-emitting element OLED emits light by using a current whose amount is adjusted in the driving transistor D-TFT according to the data voltage (DATA2 - DATA1) charged in the capacitor CST. The data voltage (DATA2 - DATA1) is the potential difference between two data lines, that is, the difference between the second data voltage DATA2 and the first data voltage DATA1. The light-emitting element OLED may include an anode, a cathode, and an organic compound layer formed between the anode and the cathode. The organic compound layer may include a light-emitting layer, a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer, but the present invention is not limited thereto. The anode of the light-emitting element OLED is connected to the driving transistor D-TFT, and the cathode of the light-emitting element OLED is connected to a cathode voltage line (low-potential voltage line) to which a cathode voltage ELVSS is applied.

[0060] The driving transistor D-TFT is a driving element configured to control the current flowing through the light-emitting element OLED according to the gate-source voltage Vgs. The driving transistor D-TFT includes a source electrode, a drain electrode, and a gate electrode connected to node A.

[0061] The capacitor CST includes two electrodes for forming a capacitance, and the two electrodes are respectively connected to node A and node B.

[0062] The plurality of switching elements T2 to T10 of the pixel circuit according to an embodiment of the present specification may be arranged as follows. The second transistor T2 is controlled by the second scan signal SCAN2 and connects the source electrode of the driving transistor D-TFT to the first data line DATA1. The third transistor T3 is controlled by the first scan signal SCAN1 and connects the gate electrode (i.e., node A) to the drain electrode of the driving transistor D-TFT. The fourth transistor T4 is controlled by the fourth scan signal SCAN4 and connects the gate electrode (i.e., node A) of the driving transistor D-TFT to the initialization voltage line VINIT. The fifth transistor T5 is controlled by the emission signal EM and connects the source electrode of the driving transistor D-TFT to the pixel driving voltage line ELVDD. The sixth transistor T6 is controlled by the emission signal EM and connects the drain electrode of the driving transistor D-TFT to the anode of the light-emitting element OLED. The seventh transistor T7 is controlled by the third scan signal SCAN3 and connects the anode of the light-emitting element OLED to the reset voltage line VAR. The eighth transistor T8 is controlled by the third scan signal SCAN3 and connects the source electrode of the driving transistor D-TFT to the bias stress voltage line VOBS. The ninth transistor T9 is controlled by the second scan signal SCAN2 and connects node B, which is one electrode of the capacitor CST, to the second data line DATA2. The tenth transistor T10 is controlled by the second scan signal SCAN2 and connects node B, which is one electrode of the capacitor CST, to the pixel driving voltage line ELVDD. In an embodiment of the present specification, the driving transistor D-TFT and the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 may be p-channel transistors, and the third transistor T3, the fourth transistor T4, and the tenth transistor T10 may be n-channel transistors.

[0063] Reference will be made to Figure 3B, the operation of the pixel circuit according to an embodiment of the present specification is described by classifying it into five time periods. The first period has four horizontal periods (4H), and in the first period, the first scan signal SCAN1 has a low level, the second scan signal SCAN2 has a high level, the third scan signal SCAN3 has a low level, the fourth scan signal SCAN4 has a low level, and the emission signal EM has a high level, and the levels of the third scan signal SCAN3 and the emission signal EM are changed. The second period has two horizontal periods (2H), and in the second period, all of the first scan signal SCAN1 to the fourth scan signal SCAN4 and the emission signal EM have a high level, and the levels of the first scan signal SCAN1, the third scan signal SCAN3, and the fourth scan signal SCAN4 are changed. The third period has one horizontal period (1H), and in the third period, the first scan signal SCAN1 has a high level, the second scan signal SCAN2 has a low level, the third scan signal SCAN3 has a high level, the fourth scan signal SCAN4 has a low level, and the emission signal EM has a high level, and the levels of the second scan signal SCAN2 and the fourth scan signal SCAN4 are changed. The fourth period has four horizontal periods (4H), and in the fourth period, the first scan signal SCAN1 has a low level, the second scan signal SCAN2 has a high level, the third scan signal SCAN3 has a low level, the fourth scan signal SCAN4 has a low level, and the emission signal EM has a high level, and the levels of the first scan signal SCAN1, the second scan signal SCAN2, and the third scan signal SCAN3 are changed. The fifth period has one horizontal period (1H), and in the fifth period, the first scan signal SCAN1 has a low level, the second scan signal SCAN2 has a high level, the third scan signal SCAN3 has a high level, the fourth scan signal SCAN4 has a low level, and the emission signal EM has a low level, and the levels of the third scan signal SCAN3 and the emission signal EM are changed.

[0064] It should be noted that the present invention is not limited to the structure of the pixel circuit described above, and in addition to Figure 3A the structure shown, it is also possible to form a pixel circuit that performs internal compensation in various ways - for example, a structure in which the potential difference between two data lines is charged at both electrodes of a storage capacitor connected to the gate electrode of a driving transistor and the amount of current of the driving transistor is adjusted to correspond to the charged voltage to cause the light-emitting element to emit light. Hereinafter, with reference to Figure 3B the Figure 3A detailed operation method of the pixel circuit will be described.

[0065] Figures 4A to 4E is a diagram showing step by step Figure 3A the driving of the pixel circuit shown in

[0066] Referring to Figure 4A , in the first period, the third scan signal SCAN3 changes from a high level to a low level, and the emission signal EM changes from a low level to a high level. The seventh transistor T7 is turned on to electrically connect the reset voltage line VAR to the light-emitting element OLED. Since the reset voltage VAR is a voltage lower than the cathode voltage ELVSS, current does not flow to the light-emitting element OLED, and thus, the light-emitting element OLED does not emit light. The eighth transistor T8 is turned on to electrically connect the source electrode of the driving transistor D-TFT to the bias stress voltage line VOBS. The bias stress voltage VOBS is selected as a voltage level capable of forming a specific condition (on-bias stress) between the gate electrode and the source electrode (Vgs) of the driving transistor D-TFT, so that the afterimage visibility caused by hysteresis can be minimized. The tenth transistor T10 is turned on to electrically connect the node B, which is one terminal of the capacitor CST, to the pixel driving voltage line ELVDD. In the first period, the gate electrode of the driving transistor D-TFT maintains the same voltage as when the light-emitting element OLED emits light, and the voltage at the gate electrode becomes Vg = DATA1 - DATA2 + ELVDD + Vth.

[0067] Referring to Figure 4B , in the second period, all of the first scan signal SCAN1, the third scan signal SCAN3, and the fourth scan signal SCAN4 change from a low level to a high level. The third transistor T3 and the fourth transistor T4 are turned on so that the gate electrode of the driving transistor D-TFT is electrically connected to the initialization voltage line VINIT, and the driving transistor D-TFT is turned on. Accordingly, the voltage of the gate electrode of the driving transistor D-TFT is initialized to the initialization voltage VINIT (i.e., Vg = VINIT).

[0068] Referring to Figure 4C , in the third period, the second scan signal SCAN2 and the fourth scan signal SCAN4 change from a high level to a low level. The second transistor T2 and the third transistor T3 are turned on to turn on the driving transistor D-TFT, and the gate electrode (node A) of the driving transistor D-TFT is electrically connected to the first data line DATA1. Accordingly, the sum of the first data voltage DATA1 and the threshold voltage Vth of the driving transistor D-TFT is applied to the node A, which is one terminal of the capacitor CST. In addition, the ninth transistor T9 is turned on and the tenth transistor T10 is turned off so that the node B, which is the other terminal of the capacitor CST, is electrically connected to the second data line DATA2, and the second data voltage DATA2 is applied to the node B. Accordingly, the voltage of the gate electrode of the driving transistor D-TFT becomes Vg = DATA1 + Vth.

[0069] Referring to Figure 4D , in the fourth paragraph, the first scan signal SCAN1 changes from a high level to a low level, the second scan signal SCAN2 changes from a low level to a high level, and the third scan signal SCAN3 changes from a high level to a low level. The seventh transistor T7 and the eighth transistor T8 are turned on, so that the light-emitting element OLED is electrically connected to the reset voltage line VAR, and a bias stress voltage VOBS is applied to the source electrode of the driving transistor D-TFT. The ninth transistor T9 is turned off, and the tenth transistor T10 is turned on again, so that the pixel driving voltage ELVDD is applied to the node B which is one terminal of the capacitor CST. In this case, the node A which is the other terminal of the capacitor CST is in a floating state, and thus, the change in the voltage at the node B is reflected to the node A due to the coupling effect of the capacitor CST. Therefore, the voltage of the gate electrode of the driving transistor D-TFT becomes Vg = DATA1 - DATA2 + ELVDD + Vth.

[0070] Referring to Figure 4E , in the fifth paragraph, the third scan signal SCAN3 changes from a low level to a high level, and the emission signal EM changes from a high level to a low level. When the fifth transistor T5 and the sixth transistor T6 are turned on, the pixel driving voltage line ELVDD is electrically connected to the source electrode of the driving transistor D-TFT, so that the driving transistor D-TFT is turned on, and a driving current is provided to the light-emitting element OLED. When the light-emitting element emits light, the capacitor CST can continuously maintain a constant voltage on the gate electrode of the driving transistor D-TFT, thereby providing a constant driving current to the light-emitting element OLED. The voltage of the gate electrode of the driving transistor D-TFT is maintained at Vg = DATA1 - DATA2 + ELVDD + Vth.

[0071] As described above, the operation of a frame period of the pixel circuit according to an embodiment of the present specification is that during the initialization period, the gate electrode of the driving transistor D-TFT is discharged to the initialization voltage VINIT, during the sampling period, the first data voltage DATA1 and the second data voltage DATA2 are respectively provided to the two terminals of the capacitor CST, and the potential difference between the two data lines is charged to the capacitor CST, during the programming period, the difference (DATA2 - DATA1) between the second data voltage charged in the capacitor CST and the first data voltage is reflected to the voltage of the gate electrode of the driving transistor D-TFT, and finally, during the light-emitting period, a constant driving current is generated in response to the gate electrode voltage of the driving transistor D-TFT being kept constant by the capacitor CST, so as to allow the light-emitting element OLED to emit light.

[0072] Figure 5A andFigure 5B They are a circuit diagram of a pixel circuit and a waveform diagram of a gate signal according to another embodiment of the present specification, respectively.

[0073] Referring to Figure 5A , a pixel circuit (or a pixel driving circuit) for supplying a driving current to a light emitting element OLED includes a plurality of switching elements T1 to T7, T8-1 and T8-2, and a capacitor CST. The plurality of switching elements T1 to T7, T8-1 and T8-2 may be thin film transistors, and may be p-channel transistors.

[0074] The pixel circuit according to another embodiment of the present specification is an internal compensation circuit capable of compensating for the threshold voltage of a driving transistor D-TFT by an internal compensation unit.

[0075] A power voltage of a pixel driving voltage ELVDD, a cathode voltage ELVSS, and an initialization voltage VINIT is applied to the pixel circuit, and pixel driving signals of a first scan signal SCAN(N-1), a second scan signal SCAN(N), an emission signal EM(N), a first data voltage DATA1, and a second data voltage DATA2 are applied to the pixel circuit.

[0076] In another embodiment of the present specification, the first data voltage DATA1 and the second data voltage DATA2 may be data voltages supplied by dividing a digital data signal of pixel data of an input image to reduce the number of bits of the pixel data and converting the digital data signal into an analog data voltage. In addition, the voltage DATA1 of the first data line may be a data voltage of a lower bit of the digital data signal, and the voltage DATA2 of the second data line may be a data voltage of a higher bit of the digital data signal. In other words, a digital data signal having a predetermined number of bits is divided into a higher bit data signal and a lower bit data signal, and the lower bit analog conversion data voltage is supplied to the first data line, and the higher bit analog conversion data voltage is supplied to the second data line.

[0077] Each of the scan signals SCAN(N-1) and SCAN(N) and the emission signal EM(N) has a conduction level pulse or a turn-off level pulse at a fixed time interval. In one embodiment of the present specification, the conduction voltage of the p-channel transistor may be a gate low voltage, and the turn-off voltage of the p-channel transistor may be a gate high voltage.

[0078] The light-emitting element OLED emits light by using a current, the amount of which is adjusted in the driving transistor D-TFT according to the data voltage (DATA2 - DATA1) charged in the capacitor CST. The data voltage (DATA2 - DATA1) is the potential difference between two data lines, that is, the difference between the second data voltage DATA2 and the first data voltage DATA1. The light-emitting element OLED may include an anode, a cathode, and an organic compound layer formed between the anode and the cathode. The organic compound layer may include a light-emitting layer, a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer, but the present invention is not limited thereto. The anode of the light-emitting element OLED is connected to the driving transistor D-TFT through a switching element, and the cathode of the light-emitting element OLED is connected to a cathode voltage line (low-potential voltage line) to which a cathode voltage ELVSS is applied.

[0079] The driving transistor D-TFT is a driving element configured to control the current flowing through the light-emitting element OLED according to the gate-source voltage Vgs. The driving transistor D-TFT includes a source electrode, a drain electrode, and a gate electrode connected to node A.

[0080] The capacitor CST includes two electrodes for forming a capacitance, and the two electrodes are respectively connected to node A and node B.

[0081] The plurality of switching elements T1 to T7, T8-1, and T8-2 of the pixel circuit according to another embodiment of the present specification may be arranged as follows. The first transistor T1 is controlled by the second scan signal SCAN(N) and connects the gate electrode (node A) to the drain electrode of the driving transistor D-TFT. The second transistor T2 is controlled by the second scan signal SCAN(N) and connects the source electrode of the driving transistor D-TFT to the first data line DATA1. The third transistor T3 is controlled by the emission signal EM(N) and connects the source electrode of the driving transistor D-TFT to the pixel driving voltage line ELVDD. The fourth transistor T4 is controlled by the emission signal EM(N) and connects the drain electrode of the driving transistor D-TFT to the anode of the light-emitting element OLED. The fifth transistor T5 is controlled by the first scan signal SCAN(N-1) and connects the gate electrode (node A) of the driving transistor D-TFT to the initialization voltage line VINIT. The sixth transistor T6 is controlled by the second scan signal SCAN(N) and connects the anode of the light-emitting element OLED to the initialization voltage line VINIT. The seventh transistor T7 is controlled by the second scan signal SCAN(N) and connects node B, which is one electrode of the capacitor CST, to the second data line DATA2. The 8-1 transistor T8-1 is controlled by the first scan signal SCAN(N-1) and connects node B, which is one electrode of the capacitor CST, to the pixel driving voltage line ELVDD. The 8-2 transistor T8-2 is controlled by the emission signal EM(N) and connects node B, which is one electrode of the capacitor CST, to the pixel driving voltage line ELVDD. In one embodiment of the present specification, the plurality of switching elements T1 to T7, T8-1, and T8-2 may be the above-described p-channel transistors.

[0082] Reference will be made to Figure 5B, the operation of the pixel circuit according to another embodiment of the present specification is described by classifying it into three time periods. The first period has three horizontal periods (3H), and in the first period, the first scan signal SCAN(N - 1) has a low level, the second scan signal SCAN(N) has a high level, and the emission signal EM(N) has a high level, and the levels of the first scan signal SCAN(N - 1) and the emission signal EM(N) are changed. The second period has three horizontal periods (3H), and in the second period, the first scan signal SCAN(N - 1) has a high level, the second scan signal SCAN(N) has a low level, and the emission signal EM(N) has a high level, and the levels of the first scan signal SCAN(N - 1) and the second scan signal SCAN(N) are changed. The third period has six horizontal periods (6H), and in the third period, the first scan signal SCAN1 has a high level, the second scan signal SCAN2 has a high level, and the third scan signal SCAN3 has a low level, and the levels of the second scan signal SCAN2 and the emission signal EM(N) are changed.

[0083] It should be noted that the present invention is not limited to the structure of the pixel circuit described above with reference to Figure 3A and Figure 3B and, in addition to the Figure 5A shown structure, a pixel circuit performing internal compensation can also be formed in various ways - for example, by charging the potential difference between two data lines at both electrodes of a storage capacitor connected to the gate electrode of a driving transistor and adjusting the amount of current of the driving transistor to correspond to the charged voltage to cause the light-emitting element to emit light. Hereinafter, the detailed operation method of the pixel circuit described with reference to Figure 5B will be described. Figure 5A of the pixel circuit.

[0084] Figures 6A to 6C is a diagram showing step by step Figure 5A the driving of the pixel circuit shown in

[0085] Referring to Figure 6A , in the first period, the first scan signal SCAN(N - 1) changes from a high level to a low level, and the emission signal EM(N) changes from a low level to a high level. The fifth transistor T5 is turned on to electrically connect the gate electrode (node A) of the driving transistor D - TFT to the initialization voltage line VINIT, so that the voltage of the gate electrode of the driving transistor D - TFT is initialized to the initialization voltage VINIT (i.e., Vg = VINIT). The 8 - 1 transistor is turned on to electrically connect node B, which is one electrode of the capacitor CST, to the pixel driving voltage line ELVDD.

[0086] Referring to Figure 6B, in the second stage, the first scan signal SCAN(N - 1) changes from a low level to a high level, and the second scan signal SCAN(N) changes from a high level to a low level. The first transistor T1 and the second transistor T2 are turned on to turn on the driving transistor D-TFT, and the gate electrode (node A) of the driving transistor D-TFT is electrically connected to the first data line DATA1. Thus, the sum of the first data voltage DATA1 and the threshold voltage Vth of the driving transistor D-TFT is applied to node A which is one terminal of the capacitor CST. At the same time, the sixth transistor T6 is turned on to electrically connect the initialization voltage line VINIT to the light-emitting element OLED. Since the initialization voltage VINIT is a voltage lower than the cathode voltage ELVSS, current does not flow to the light-emitting element OLED, and thus, the light-emitting element OLED does not emit light. In addition, the seventh transistor T7 is turned on, and the 8-1 transistor T8-1 and the 8-2 transistor T8-2 are turned off, so that node B which is the other terminal of the capacitor CST is electrically connected to the second data line DATA2, and the second data voltage DATA2 is applied to node B. Thus, the voltage of the gate electrode of the driving transistor D-TFT becomes Vg = DATA1 + Vth.

[0087] Referring to Figure 6C , in the third stage, the second scan signal SCAN(N) changes from a low level to a high level, and the emission signal EM(N) changes from a high level to a low level. When the 8-2 transistor T8-2 is turned on, due to the coupling effect of the capacitor CST, the voltage change at node B is reflected to node A, and the third transistor T3 and the fourth transistor T4 are turned on, and thus, the pixel driving voltage line ELVDD is electrically connected to the source electrode of the driving transistor D-TFT, so that the driving transistor D-TFT is turned on, and a driving current is provided to the light-emitting element OLED. When the light-emitting element emits light, the capacitor CST can continuously maintain a constant voltage on the gate electrode of the driving transistor D-TFT, thereby providing a constant driving current to the light-emitting element OLED. The voltage of the gate electrode of the driving transistor D-TFT becomes Vg = DATA1 - DATA2 + ELVDD + Vth.

[0088] As described above, the operation of the pixel circuit according to another embodiment of the present specification during one frame period is as follows: during the initialization period, the gate electrode of the driving transistor D-TFT is discharged to the initialization voltage VINIT, and during the sampling period, the first data voltage DATA1 and the second data voltage DATA2 are respectively supplied to two terminals of the capacitor CST, and the potential difference between the two data lines is charged to the capacitor CST. During the programming period, the difference (DATA2 - DATA1) between the second data voltage charged in the capacitor CST and the first data voltage is reflected in the voltage of the gate electrode of the driving transistor D-TFT. Finally, during the light emission period, a constant driving current is generated in response to the gate electrode voltage of the driving transistor D-TFT that is kept constant by the capacitor CST, allowing the light emitting element OLED to emit light.

[0089] Hereinafter, a panel structure of a display device including a pixel circuit capable of reducing the number of bits of data output from a channel of the above-described data driver will be described.

[0090] Figure 7 FIG. is a diagram showing a simplified panel structure according to an embodiment of the present specification.

[0091] Referring to Figure 7 , the structure of the display panel 110 according to an embodiment of the present specification may be a structure of the 1G2D (one gate line and two data lines) concept in which one gate line (not shown) and two data lines DL1 and DL2 are connected to one pixel PX. Here, the term 1G2D is conceptually used to assist in understanding the description of the present specification, and the description of the present specification should not be construed as limiting that only one gate line is connected to one pixel PX. In Figure 7 compared with Figure 2B the panel structure of the related art shown in

[0092] the gate line is omitted for easy visual and intuitive understanding. The data driver 120 may divide the digital data signal of the pixel data of the input image, and supply the digital data signal with the reduced number of bits of the pixel data to channels CH1 and CH2 of the data driver 120. As described above, the DACs of the data driver 120 are arranged in each channel of the data driver 120 to output the data voltages DATA1 and DATA2 corresponding to the number of bits of the pixel data, and the output data voltages DATA1 and DATA2 may be supplied to the data lines DL1 and DL2 of the display panel 110, or transmitted to the demultiplexing unit 130 to be supplied to the data lines DL1 and DL2 through the demultiplexer 131.

[0093] In one embodiment of the present specification, two data lines DL1 and DL2 connected to each sub-pixel in the pixel PX include a data line DL1 and a data line DL2, wherein data voltages DATA1 and DATA2 obtained by dividing a digital data signal as pixel data and converting the divided digital data signal into an analog signal are respectively supplied to the data line DL1 through one channel CH1 of the data driver 120, and are supplied to the data line DL2 through another channel CH2 of the data driver 120 after being distributed by the demultiplexer 131 of the demultiplexing unit 130. This may be equally applied to the data lines DL1 and DL2 arranged in Figure 7 For example, in the pixel PX arranged on the right side, the second data line DL2 receives the second data voltage DATA2 through one channel CH2 of the data driver 120, and the first data line DL1 receives the first data voltage DATA1 distributed by the demultiplexer 131 through another channel CH1 of the data driver 120.

[0094] As described above, by time-dividing and distributing the data voltage output from one channel of the data driver 120 to a plurality of data lines using the demultiplexing unit 130, two data lines supplying different data voltages can be provided for each pixel even without adding a separate output channel to the data driver 120.

[0095] Figure 8 and Figure 9 is a diagram showing an exemplary comparison of data voltage ranges of the related art and the present invention.

[0096] Reference Figure 8 When an 8-bit digital data signal is used as pixel data of an input image, conventionally, Figure 2B The structure of the 1G1D (one gate line and one data line) concept in which one gate line (not shown) and one data line DL are connected to one pixel PX is shown as the structure of the display panel 110, and therefore, the luminous grayscale of the light-emitting element is expressed corresponding to the voltage charged by applying the pixel driving voltage ELVDD to one electrode of the capacitor CST of the internal compensation unit of the pixel circuit and applying the data voltage DATA to the other electrode of the capacitor CST.

[0097] Reference Figure 8 In the right figure, in a pixel circuit according to another embodiment of the present specification and a display device using the pixel circuit, the pixel circuit is used as shown in FIG. Figure 7The structure of a 1G2D (one gate line and two data lines) concept where a gate line (not shown) and two data lines DL1 and DL2 are connected to a pixel PX is used as the structure of the display panel 110. Accordingly, the grayscale of the light-emitting element is expressed corresponding to the voltage charged in the capacitor CST having a potential difference obtained by applying the second data voltage DATA2 to one electrode of the capacitor CST in the internal compensation unit of the pixel circuit and applying the first data voltage DATA1 to the other electrode of the capacitor CST between the two data lines. Thus, an 8-bit digital data signal can be expressed by dividing it into four higher bits and four lower bits.

[0098] Figure 9 A set of graphs showing the relationship between the provided data voltages and the grayscale of the light-emitting element when using an 8-bit digital data signal as the pixel data of the input image. Referring to this relationship, in the pixel circuit and display device under the conventional 1G1D concept, it is necessary to supply a data voltage range corresponding to 8 bits from one data line to express the grayscale of the light-emitting element as shown in the left figure. In the pixel circuit and display device according to an embodiment of the present specification, as shown in the right figure, by using the structure of the 1G2D concept, the grayscale of the light-emitting element for 8-bit data can be expressed by supplying data voltage ranges corresponding to the higher 4 bits and lower 4 bits of the data via two data lines.

[0099] In summary, conventionally, in order to express 256 grayscales corresponding to an 8-bit digital data signal of the pixel data of the input image, 8-bit digital data should be converted in the channels of the data driver to output the data voltage. However, in the pixel circuit and display device according to an embodiment of the present specification, 256 grayscales corresponding to the 8-bit digital data signal can be expressed by outputting data voltages corresponding to the higher 4 bits and lower 4 bits as shown in the above example. Therefore, in an embodiment of the present specification, in order to express 2 N types of grayscales corresponding to an N-bit digital data signal (where N is a natural number) used as the pixel data of the input image, data voltages corresponding to the higher N / 2 bits and lower N / 2 bits can be supplied to two data lines connected to the pixel circuit respectively through the channels of the data driver. However, it should be noted that the division of the number of bits of the digital data signal is not necessarily limited to half.

[0100] As described above, the number of bits of the digital data output from the channels of the data driver can be reduced, so that the size of the DAC used in each channel of the data driver can be reduced, thereby reducing the power consumption of the data drive voltage caused by the generation of the dynamic current of the data drive voltage SVDD.

[0101] Figure 10This is a table showing a method for expressing the gray level of an expression sub-pixel and exemplary data voltage values according to an embodiment of the present specification.

[0102] Referring to Figure 10 the left table, in an embodiment of the present specification, when the gray level expressed based on 8-bit pixel data ranges from 0G to 255G and the gray level is divided into higher 4 bits and lower 4 bits, the second data DATA2 expresses the range of 15G to 255G, and the first data DATA1 always expresses the range of 0G to 15G, regardless of the type of gray level to be expressed.

[0103] Figure 10 The right table of Figure 3A is a table showing exemplary data voltage values used in the pixel circuit of Figure 3A The driving voltage used in the pixel circuit of Figure 10 can be exemplified as follows. The range of the data voltage is from 1.0V to 4.0V, the data driving voltage SVDD is 7.0V, the pixel driving voltage ELVDD is 2.9V, the cathode voltage ELVSS is -10.5V, the reset voltage VAR is -13.0V, the initialization voltage VINIT is -5.0V, the bias stress voltage VOBS is 3.8V, the gate high voltage VGH is 7.0V, and the gate low voltage VGL is -13.0V. In addition, the specific values of the data voltage range can be the same as those in

[0104] the right table of

[0105] For the voltage value corresponding to the gray level to be expressed, 0G corresponds to 3.55V, and 255G corresponds to 1.00V, resulting in a voltage difference of 0.01V for each gray level step, and a voltage difference of 0.01V for the lower 4-bit voltage values can represent a gray level difference, and a voltage difference of 0.16V for the higher 4-bit voltage values can represent 16 gray level steps.

[0104] Hereinafter, the effect of reducing the number of bits of data output from the channels of the data driver in the display device according to an embodiment of the present specification will be described.

[0105] First, the size of the DAC is reduced. In an N-bit DAC, the number of required resistors is 2 N and the number of transistors is 2 + 2 2 + 2 3 + … + 2 N . For example, when processing a 10-bit digital data signal, the number of resistors used in the DAC is 1024, and the number of transistors is 2046.

[0106] In the pixel circuit and the display device using the pixel circuit according to an embodiment of the present specification, since the number of bits of the data output from the channel of the data driver can be reduced, as an example, an N / 2-bit DAC, which is half of an N-bit DAC, can be used. When two 5-bit DACs are used instead of a single 10-bit DAC, the number of required resistors becomes 64, and the number of required transistors becomes 124. Therefore, the size of the DAC can be reduced by approximately 84%.

[0107] In addition, power consumption generation of the data driving voltage SVDD can be reduced. The data driving voltage SVDD can be a power source for supplying power to an analog block in a source driver IC included in the data driver, and can be a power source for supplying power to a gamma amplifier in the source driver IC.

[0108] Figure 11 It is a diagram for describing the data driving voltage SVDD.

[0109] More specifically, referring to Figure 11 , according to an embodiment, the data driving voltage SVDD can be a power source supplied to a voltage dividing circuit used by the data driver 120 to generate a gamma compensation voltage corresponding to each gray level of pixel data using a gamma reference voltage input from a gamma voltage generation circuit of a power supply unit, or a power source for connecting to an output buffer of a DAC arranged on each channel of the data driver 120.

[0110] In the example where the data voltages corresponding to the upper 4 bits and the lower 4 bits described with reference to Figure 9 are respectively supplied to two data lines to have half the number of bits of 8-bit pixel data, since the first data voltage constitutes the lower 4 bits, the range of the first data voltage corresponds to 1 / 16 of the total voltage range excluding the upper 4 bits from the case of 8 bits. Therefore, based on the first data voltage, the voltage range can be reduced by one-sixteenth compared to the conventional case of using one data line.

[0111] Referring to Figure 2A , the dynamic current of the data driving voltage SVDD is the current flowing through the driving transistor D-TFT, and is generated when the capacitor CST in the pixel circuit is charged from an initial voltage Vini to the sum of the data voltage and the threshold voltage (Vdata + Vth) through one electrode of the capacitor CST on the node A side. In Figure 2AIn [the figure], since the other electrode of the capacitor on the B side of the node is fixed at the pixel driving voltage ELVDD, it is necessary to use a data voltage Vdata to represent all grayscales. For example, 8-bit pixel data should be used to represent grayscales from 0G to 255G. In this case, since the data voltage increases from 255G to 0G, the dynamic current of the data driving voltage SVDD also increases.

[0112] In the example of Figure 3A describing that data voltages corresponding to the higher 4 bits and the lower 4 bits are respectively supplied to two data lines to have half the number of bits of 8-bit pixel data, the second data voltage DATA2 is applied to the electrode of the capacitor CST on the B side of the node to represent the higher 4 bits, and therefore, the first data voltage DATA1 only needs to represent the lower 4 bits. Referring again to Figure 10 's left table, since the first data voltage DATA1 only needs to represent grayscales from 0G to 15G, regardless of the type of grayscale to be represented, the voltage range is reduced to 1 / 16 compared to the existing situation of representing all 8-bit data. Therefore, the increase in the dynamic current of the data driving voltage SVDD is limited. In the following description, the difference in the power consumption of the data driving voltage SVDD when a single data line is connected to the pixel circuit and when two data lines are connected to the pixel circuit is confirmed through a curve graph.

[0113] Figure 12 is a curve graph comparing the power consumption of the data driving voltage SVDD between the related art and the present invention.

[0114] Referring to Figure 3A , the dynamic current of the data driving voltage SVDD is the current flowing through the driving transistor D-TFT, and is generated when the capacitor CST in the pixel circuit is charged from the initial voltage VINIT to the sum of the first data voltage and the threshold voltage (DATA1 + Vth) through one electrode of the capacitor CST on the A side of the node. Therefore, compared with Figure 12 the power consumption of the data driving voltage SVDD in the conventional situation shown in the left curve graph of Figure 12 , as shown in the right curve graph of

[0115] the power consumption of the data driving voltage SVDD is reduced. The power consumption generated in the range of 0G to 15G is comparable to the conventional situation, and the power consumption generated in all other grayscales is reduced.Finally, according to an embodiment of the present specification, by applying not only the pixel driving voltage ELVDD but also the data voltage to one electrode of the capacitor of the internal compensation unit, the current resistance (IR) drop of the pixel driving voltage ELVDD is circuitously eliminated in terms of the gate-source voltage Vgs of the driving transistor through the coupling effect of the capacitor. Therefore, the occurrence of poor image quality due to the IR drop phenomenon of the pixel driving voltage ELVDD can be prevented.

[0116] Referring to Figure 2A , during the light emission period, the voltage of the gate electrode (node A) of the driving transistor D-TFT is kept constant at Vg = Vdata + Vth, so that Vgs = Vdata + Vth - ELVDD. When the IR drop of the pixel driving voltage ELVDD occurs, Vgs = Vdata + Vth - (ELVDD - ΔV), which causes Vgs to fluctuate, resulting in poor image quality. Here, ΔV represents the IR drop of the pixel driving voltage ELVDD.

[0117] In one embodiment of the present specification shown in Figure 3A , the voltage of the gate electrode (node A) of the driving transistor D-TFT during the light emission period is kept constant at Vg = DATA1 - DATA2 + ELVDD + Vth, so that Vgs = (DATA1 - DATA2 + Vth + ELVDD) - ELVDD. When the IR drop of the pixel driving voltage ELVDD occurs, Vgs = DATA1 - DATA2 + Vth + (ELVDD - ΔV) - (ELVDD - ΔV), so that the IR drop in the pixel driving voltage ELVDD is canceled in terms of the gate-to-source voltage of the driving transistor, resulting in Vgs remaining unchanged.

[0118] As described above, in the pixel circuit according to an embodiment of the present specification and the display device using the pixel circuit, by applying the data voltage to both ends of the capacitor of the internal compensation circuit using the double data lines to store the potential difference between the data lines in the capacitor and allowing the light emitting element to emit light with a gray level corresponding to the stored voltage, the number of bits of the data output from the channel of the data driving circuit can be reduced, thereby reducing the size of the digital-to-analog converter in the data driving circuit and reducing the power consumption of the data driving voltage.

[0119] A display device according to an embodiment of the present specification includes: a display panel in which a plurality of data lines and a plurality of gate lines cross each other and pixels are arranged; a data driver configured to convert a digital data signal into an analog data voltage and supply the analog data voltage to the plurality of data lines; and a demultiplexing unit configured to distribute the data voltage converted from the digital data signal by the data driver to the plurality of data lines, wherein each pixel in the pixels includes sub-pixels, each sub-pixel having a pixel circuit, one of the plurality of gate lines and two of the plurality of data lines are connected to each of the sub-pixels, the two data lines connected to each of the sub-pixels include a data line to which one of the voltages obtained by dividing and converting from the digital data signal is supplied through one channel of the data driver, and a data line to which the other voltage is supplied through another channel of the data driver by being distributed by the demultiplexing unit, and the pixel circuit includes: a light-emitting element; a driving transistor whose second electrode is electrically connected to the light-emitting element to supply current to the light-emitting element and is controlled by a voltage applied to the gate electrode of the driving transistor; a capacitor having a first terminal connected to the gate electrode of the driving transistor; and an internal compensation unit including a plurality of switching elements to sense a threshold voltage of the driving transistor during a sampling period and supply a current in which the threshold voltage is compensated to the light-emitting element, the first data line and the second data line, which are two data lines connected to each of the sub-pixels, are connected to the internal compensation unit to adjust a light-emitting gray scale of the light-emitting element based on the number of bits of the digital data signal, wherein the first data line is electrically connected to the first electrode of the driving transistor, and the second data line is electrically connected to the second terminal of the capacitor, and during the sampling period, a difference between the voltage of the second data line and the voltage of the first data line is charged to a first voltage in the capacitor, and the light-emitting element emits light with a gray scale corresponding to the first voltage.

[0120] In a display device according to an embodiment of the present specification, the demultiplexing unit includes: a demultiplexer connected to one channel of the data driver, the demultiplexer being configured to receive the converted data voltage from the one channel and distribute the converted data voltage to two or more data lines in a time-division manner, the voltages obtained by dividing and converting the digital data signal are respectively data voltages of higher bits and lower bits of the digital data signal, and the data driver supplies one of the divided and converted voltages to one of the first data line and the second data line through the demultiplexer, supplies the lower-bit data voltage to the first data line, and supplies the higher-bit data voltage to the second data line.

[0121] According to an embodiment of the present specification, by applying a data voltage to both ends of a capacitor of an internal compensation unit using two data lines to store a potential difference between the data lines in the capacitor and allowing a light-emitting element to emit light with a gray scale corresponding to the stored voltage, the number of bits of data output from a channel of a data driver can be reduced, thereby reducing the size of a digital-to-analog converter in the data driver.

[0122] According to an embodiment of the present specification, a data range charged in a capacitor of an internal compensation unit by a driving transistor can be reduced according to a reduction in the number of bits of data output from a channel of a data driver, thereby reducing power consumption of a data driving voltage caused by generation of a dynamic current of the data driving voltage SVDD.

[0123] According to an embodiment of the present specification, by applying not only a pixel driving voltage ELVDD but also a data voltage to one electrode of a capacitor of an internal compensation unit, a current resistance (IR) drop of the pixel driving voltage ELVDD is circuitously eliminated in terms of a gate-source voltage Vgs of a driving transistor through a coupling effect of the capacitor of the internal compensation unit. Therefore, occurrence of poor image quality due to an IR drop phenomenon of the pixel driving voltage ELVDD can be prevented.

[0124] The effects of the present specification are not limited to the effects mentioned above, and those skilled in the art will clearly understand other effects not mentioned according to the following description.

[0125] Although embodiments of the present invention have been described in detail above with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various changes and modifications can be made without departing from the technical gist of the present invention. Therefore, the embodiments disclosed herein should be considered as descriptive rather than restrictive of the technical gist of the present invention, and the scope of the technical gist of the present invention is not limited by these embodiments. Therefore, the above embodiments should be understood as being exemplary and not restrictive in any way. The scope of the present invention should be interpreted by the appended claims, and all technical gists within the scope of equivalents of the appended claims should be interpreted as being included within the scope of the present invention.

Claims

1. A pixel circuit, comprising: Light emitting element; a driving transistor electrically connected to the light emitting element through a second electrode of the driving transistor to supply current to the light emitting element and controlled by a voltage applied to a gate electrode of the driving transistor; a capacitor having a first terminal connected to the gate electrode of the drive transistor; as well as an internal compensation unit including a plurality of switching elements for sensing a threshold voltage of the driving transistor during a sampling period and supplying a current in which the threshold voltage is compensated to the light emitting element, wherein a data line is connected to the internal compensation unit, and an analog data voltage converted from a digital data signal is supplied through the data line, and the digital data signal adjusts the light emitting grayscale of the light emitting element based on the number of bits of the digital data signal, wherein the data line comprises a first data line and a second data line, the first data line is electrically connected to the first electrode of the driving transistor, and the second data line is electrically connected to the second terminal of the capacitor, and The light emitting element emits light at a grayscale corresponding to the first voltage by charging the difference between the voltage of the second data line and the voltage of the first data line as a first voltage in the capacitor during the sampling period.

2. The pixel circuit according to claim 1, wherein: The voltage of the first data line is a low-order data voltage of the digital data signal, and Wherein, the voltage of the second data line is a high-bit data voltage of the digital data signal.

3. The pixel circuit according to claim 1, wherein: During a programming period, the first voltage charged in the capacitor is applied to a voltage of the gate electrode of the driving transistor.

4. The pixel circuit according to claim 1, wherein: The first data line is electrically connected to the first electrode of the driving transistor through a first switching element, wherein the second data line is electrically connected to the second terminal of the capacitor through a second switch element, and The first switching element and the second switching element are controlled by the same scan signal and are turned on during the sampling period.

5. The pixel circuit according to claim 4, wherein: A second terminal of the capacitor is electrically connected to a pixel driving voltage line through one or more switching elements that are turned off during the sampling period.

6. A display device, comprising: a display panel in which a plurality of data lines and a plurality of gate lines cross each other and pixels are arranged; a data driver configured to convert a digital data signal into an analog data voltage and supply the analog data voltage to the plurality of data lines; a gate driver configured to supply a gate signal to the plurality of gate lines; a timing controller configured to transmit the digital data signal to the data driver and generate a signal for controlling the operation timing of the data driver and the gate driver; as well as a power supply unit configured to generate voltages required to drive the pixels, the data driver, the gate driver, and the timing controller, Each of the pixels includes sub-pixels, each sub-pixel has a pixel circuit, Wherein, the pixel circuit comprises: Light emitting element; a driving transistor electrically connected to the light emitting element through a second electrode of the driving transistor to supply current to the light emitting element and controlled by a voltage applied to a gate electrode of the driving transistor; a capacitor having a first terminal connected to the gate electrode of the drive transistor; and an internal compensation unit including a plurality of switching elements for sensing a threshold voltage of the driving transistor during a sampling period and supplying a current in which the threshold voltage is compensated to the light emitting element, wherein the plurality of data lines are connected to the internal compensation unit, and the light emitting grayscale of the light emitting element is adjusted based on the number of bits of the digital data signal, wherein the plurality of data lines connected to the internal compensation unit include a first data line and a second data line, the first data line is electrically connected to the first electrode of the driving transistor, and the second data line is electrically connected to the second terminal of the capacitor, and The light emitting element emits light at a grayscale corresponding to the first voltage by charging the difference between the voltage of the second data line and the voltage of the first data line as a first voltage in the capacitor during the sampling period.

7. The display device according to claim 6, wherein: The voltage of the first data line supplied to the pixel circuit is a data voltage of a low bit of the digital data signal, and The voltage of the second data line supplied to the pixel circuit is a high-bit data voltage of the digital data signal.

8. The display device according to claim 6, wherein: During a programming period, the first voltage charged in the capacitor is applied to a voltage of the gate electrode of the driving transistor.

9. The display device according to claim 6, wherein: The first data line is electrically connected to the first electrode of the driving transistor through a first switching element, wherein the second data line is electrically connected to the second terminal of the capacitor through a second switch element, and The first switching element and the second switching element are controlled by the same scan signal and are turned on during the sampling period.

10. The display device according to claim 6, further comprising a demultiplexing unit configured to distribute the data voltage converted from the digital data signal by the data driver to the plurality of data lines, in, One gate line of the plurality of gate lines and two data lines of the plurality of data lines are connected to each of the sub-pixels of the display panel, wherein the two data lines connected to each of the sub-pixels include a data line supplied with one of the voltages obtained by dividing the digital data signal into two parts and converting each part through one channel of the data driver, and a data line supplied with the other of the voltages provided through another channel of the data driver and distributed by the demultiplexing unit, and The first data line and the second data line are the two data lines connected to each of the sub-pixels.

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