Voltage bleeder circuit and display device

Abstract

The invention provides a voltage bleeder circuit and a display device, and relates to the technical field of display. The voltage discharge circuit comprises a switch sub-circuit, one end of which is electrically connected with a ground wire voltage end, the other end of which is electrically connected with a first node, and a control end of which is electrically connected with a driving signal end; the switch sub-circuit can be turned on in response to a turn-on signal of the driving signal; one end of the enabling sub-circuit is electrically connected with the input voltage end, the other end is electrically connected with the output voltage end, and the control end is electrically connected with the first node; the enabling sub-circuit can be switched on in response to the low-level voltage of the first node; one end of the voltage release sub-circuit is electrically connected with the output voltage end, the other end is electrically connected with the ground wire voltage end, and the control end is electrically connected with the first node; the voltage release sub-circuit can be cut off in response to a low level on the first node, and is conducted in response to a high level voltage on the first node; the output voltage end is used for being electrically connected with the display module and the driving board. The problems that the display module flickers and pictures are abnormal can be solved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a voltage discharge circuit and a display device. Background Art

[0002] After the driving boards (such as Tcon boards and X+D boards) of a liquid crystal TV are powered off, a bounce voltage exceeding 5V can easily cause in-plane charge residues, and problems such as flickering and abnormal images may occur during repeated power-on and power-off.

[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0004] An object of the present disclosure is to overcome the deficiencies of the above-mentioned prior art and provide a voltage discharge circuit and a display device.

[0005] According to one aspect of the present disclosure, a voltage discharge circuit is provided. The voltage discharge circuit includes:

[0006] A switch sub-circuit, one end of which is electrically connected to the ground voltage terminal, the other end is electrically connected to a first node, and the control end is electrically connected to the driving signal terminal; the switch sub-circuit can be turned on in response to the conduction signal of the driving signal;

[0007] An enable sub-circuit, one end of which is electrically connected to the input voltage terminal, the other end is electrically connected to the output voltage terminal, and the control end is electrically connected to the first node; the enable sub-circuit can be turned on in response to the low-level voltage of the first node and turned off in response to the high-level voltage on the first node; the input voltage terminal and the first node are electrically connected through a first voltage-dividing resistor;

[0008] A pressure-relief sub-circuit, one end of which is electrically connected to the output voltage terminal, the other end is electrically connected to the ground voltage terminal, and the control end is electrically connected to the first node; the pressure-relief sub-circuit can be turned off in response to the low level on the first node and turned on in response to the high-level voltage on the first node;

[0009] The output voltage terminal is used to be electrically connected to a display module and a driving board.

[0010] In an embodiment of the present disclosure, the pressure-relief sub-circuit includes a pressure-relief unit and a pressure-relief resistor;

[0011] One end of the pressure-relief unit is electrically connected to the output voltage terminal through the pressure-relief resistor, the other end is electrically connected to the ground voltage terminal, and the control end is electrically connected to the first node; the pressure-relief unit can be turned off in response to the low level on the first node and turned on in response to the high-level voltage on the first node.

[0012] In an embodiment of the present disclosure, the pressure relief unit includes a third transistor, and the third transistor is an N-type transistor; one end of the third transistor is electrically connected to the output voltage terminal through the pressure relief resistor, the other end is electrically connected to the ground voltage terminal, and the control end is electrically connected to the first node; the third transistor can be turned off in response to a low level on the first node and turned on in response to a high-level voltage on the first node.

[0013] In an embodiment of the present disclosure, the third transistor is an N-type MOS transistor.

[0014] In an embodiment of the present disclosure, the pressure relief sub-circuit includes a pressure relief unit and a pressure relief resistor;

[0015] One end of the pressure relief unit is electrically connected to the output voltage terminal, the other end is electrically connected to the ground voltage terminal through the pressure relief resistor, and the control end is electrically connected to the first node; the pressure relief unit can be turned off in response to a low level on the first node and turned on in response to a high-level voltage on the first node.

[0016] In an embodiment of the present disclosure, the pressure relief sub-circuit further includes a third voltage-dividing resistor, one end of the third voltage-dividing resistor is electrically connected to the ground voltage terminal, and the other end is electrically connected to the first node.

[0017] In an embodiment of the present disclosure, the resistance value of the pressure relief resistor is not greater than the resistance value of the first voltage-dividing resistor.

[0018] In an embodiment of the present disclosure, the pressure relief resistor is smaller than the third voltage-dividing resistor.

[0019] In an embodiment of the present disclosure, the resistance values of the first voltage-dividing resistor and the pressure relief resistor are both 3.7 - 5.7 kΩ, and the resistance value of the third voltage-dividing resistor is 5.8 - 7.8 kΩ.

[0020] In an embodiment of the present disclosure, the resistance value of the first voltage-dividing resistor is 3.7 - 5.7 kΩ, and the resistance value of the third voltage-dividing resistor is 5.8 - 7.8 kΩ.

[0021] In an embodiment of the present disclosure, the enable sub-circuit includes a first transistor, and the first transistor is a P-type MOS transistor; one end of the first transistor is electrically connected to the input voltage terminal, the other end is electrically connected to the output voltage terminal, and the control end is electrically connected to the first node; the first transistor can be turned on in response to a low-level voltage on the first node and turned off in response to a high-level voltage on the first node.

[0022] In an embodiment of the present disclosure, the switch sub - circuit includes a second transistor and a second voltage - dividing resistor. The second transistor is an NPN - type triode;

[0023] One end of the second transistor is electrically connected to the ground - voltage terminal, the other end is electrically connected to the first node, and the control end is electrically connected to the drive - signal terminal; the second transistor can be turned on in response to the on - signal of the drive signal;

[0024] One end of the second voltage - dividing resistor is electrically connected to the ground - voltage terminal, and the other end is electrically connected to the control end of the second transistor.

[0025] In an embodiment of the present disclosure, the voltage - discharging circuit further includes a first filtering sub - circuit;

[0026] The first filtering sub - circuit includes a filtering resistor and at least one first capacitor;

[0027] One end of the filtering resistor is electrically connected to the first node, and the other end is electrically connected to one end of the enabling sub - circuit through the first capacitor.

[0028] In an embodiment of the present disclosure, the voltage - discharging circuit further includes a second filtering sub - circuit;

[0029] The second filtering sub - circuit includes a second capacitor. One end of the second capacitor is electrically connected to the output - voltage terminal, and the other end is electrically connected to the ground - voltage terminal.

[0030] According to another aspect of the present disclosure, a display device is provided, including the above - mentioned voltage - discharging circuit.

[0031] For the voltage - discharging circuit and the display device of the present disclosure, when the display module is powered on, the main circuit - board terminal provides an on - signal of the drive signal to turn on the switch sub - circuit. The ground voltage is loaded to the first node to turn on the enabling sub - circuit, and the voltage - discharging sub - circuit is turned off. Thus, the voltage at the input - voltage terminal is loaded to the display - module terminal and the drive - board terminal through the enabling sub - circuit to realize the normal display of the display module. When the display module is powered off, the main circuit - board terminal provides an off - signal of the drive signal to turn off the switch sub - circuit. The first node is at a high level, which turns off the enabling sub - circuit and turns on the voltage - discharging sub - circuit. At this time, the display module and the drive board are powered off, and the residual charge in the drive board is discharged to the ground - voltage terminal through the voltage - discharging sub - circuit, so as to realize the timely discharge of the voltage of the drive board. During the repeated power - on and power - off process of the display module, the possibility of the display module flashing and the picture being abnormal is reduced, and the display quality of the display module is improved.

[0032] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0034] Figure 1 It is a simulation diagram of a circuit in the related art, intended to schematically show the bounce voltage when the display module is powered off.

[0035] Figure 2 It is a schematic diagram of a display device in an embodiment of the present disclosure.

[0036] Figure 3 It is a schematic diagram of a display device in an embodiment of the present disclosure.

[0037] Figure 4 It is an equivalent circuit diagram of a voltage discharge circuit in an embodiment of the present disclosure.

[0038] Figure 5 It is an equivalent circuit diagram of a voltage discharge circuit in an embodiment of the present disclosure.

[0039] Figure 6 When the display module is powered on, Figure 4 It is a schematic diagram of the working process of the voltage discharge circuit shown.

[0040] Figure 7 When the display module is powered off, Figure 4 It is a schematic diagram of the working process of the voltage discharge circuit shown.

[0041] Figure 8 It is a simulation diagram generated by using the voltage discharge circuit provided by the present disclosure, intended to schematically show that no bounce voltage is generated.

[0042] Explanation of reference numerals:

[0043] C1, the first capacitor; C2, the second capacitor; DPCB, the driving board; DS, the driving signal; ES, the enabling sub-circuit; FS1, the first filtering sub-circuit; FS2, the second filtering sub-circuit; GND, the ground voltage; MPCB, the main circuit board; N1, the first node; PNL, the display module; Q1, the first transistor; Q2, the second transistor; Q3, the third transistor; R1, the first voltage-dividing resistor; R2, the pressure-relief resistor; R3, the filtering resistor; R4, the current-limiting resistor; R5, the second voltage-dividing resistor; R6, the third voltage-dividing resistor; SW, the switching sub-circuit; VIN, the input voltage; VOUT, the output voltage; VRC, the voltage discharge circuit; VRS, the pressure-relief sub-circuit. Detailed Implementation Modes

[0044] Example implementation modes will now be described more fully with reference to the accompanying drawings. However, the example implementation modes can be implemented in various forms and should not be construed as limited to the implementation modes set forth herein; rather, these implementation modes are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example implementation modes to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0045] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the accompanying drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0046] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second", "third", etc. are used only as labels and are not a limitation on the quantity of their objects.

[0047] In the embodiments of the present disclosure, the transistor includes at least a bipolar transistor and a MOS transistor. Among them, a bipolar transistor refers to an element including at least three terminals: a base, an emitter, and a collector. In the embodiments of the present disclosure, for any bipolar transistor, one of the "emitter" and the "collector" is referred to as one end of the bipolar transistor, and the other is referred to as the other end of the bipolar transistor, and the base is referred to as the control end of the bipolar transistor. A MOS transistor refers to an element including at least three terminals: a gate, a source, and a drain. The MOS transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the source, the channel region, and the drain. The channel region refers to the region where current mainly flows. In the embodiments of the present disclosure, in the case of using MOS transistors with opposite polarities or when the current direction changes during circuit operation, etc., the functions of the "source" and the "drain" are sometimes swapped with each other, that is, the "source" and the "drain" can be swapped with each other. In the embodiments of the present disclosure, for any MOS transistor, one of the "source" and the "drain" is referred to as one end of the MOS transistor, and the other is referred to as the other end of the MOS transistor, and the gate is referred to as the control end of the MOS transistor. In the embodiments of the present disclosure, at least some signals have a conduction signal and a cut-off signal. Among them, for a bipolar transistor, both the conduction signal and the cut-off signal are current signals. For a MOS transistor, both the conduction signal and the cut-off signal are voltage signals. The voltage signal includes a high level and a low level; one of the high level and the low level can be used as the conduction level of the signal, and the conduction level of the signal can cause the controlled MOS transistor to conduct; the other of the high level and the low level can be used as the cut-off level of the signal, and the cut-off level of the signal can cause the controlled MOS transistor to cut off. For example, for a signal that controls a P-type MOS transistor (the signal can be loaded to the control end of the P-type MOS transistor), its conduction level is the low level, and its cut-off level is the high level. For another example, for a signal that controls an N-type MOS transistor (the signal can be loaded to the control end of the N-type MOS transistor), its conduction level is the high level, and its cut-off level is the low level.

[0048] In the related art, refer to Figure 1 , after the driving board DPCB (such as a TCON board and an X+D board) of a liquid crystal TV is powered off, a bounce voltage exceeding 5V easily causes in-plane charge residue. During the repeated power-on and power-off process, due to the existence of many filter capacitors at the driving board end and the energy storage inductor in the boost circuit, the driving board DPCB cannot discharge in time, and problems such as flickering and abnormal images may occur.

[0049] Figure 2 is a schematic structural diagram of a display device according to the present disclosure, Figure 3 is another schematic structural diagram of the display device according to the present disclosure. Refer to Figure 2, the present disclosure improves a display device. The improved display device includes a display module PNL and a driving module for driving the display module PNL. The driving module may include a power manager PMIC, a voltage discharge circuit VRC, a timing controller TCON, a source driver DD, a main circuit board MPCB, a driving circuit board DPCB, etc. The source driver DD can load a driving voltage to the display module PNL so that the display module PNL displays an image.

[0050] The display module PNL can be an organic light-emitting diode (OLED) display panel, a micro light-emitting diode (MicroLED) display panel, a quantum dot-organic light-emitting diode (QD-OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, an LCD (liquid crystal) display module, or other types of display modules. In an embodiment of the present disclosure, the display module PNL is an LCD display module, which includes a backlight module and an LCD display panel stacked in sequence.

[0051] See Figure 2 , the source driver DD has one or more source driving circuits SIC. The source driving circuit SIC receives a clock signal and a data signal from the timing controller TCON, and then loads a driving voltage to the display module PNL according to a predetermined timing. In some embodiments, the source driving circuit SIC can be a source driver chip (Source Driver IC). In one example, the source driver chip can be fixed on a flexible conductive film, and then assembled into a chip on film (COF); the chip on film (COF) is electrically connected to the bonding pads of the display module PNL and can be bent to the backlight side of the display module PNL to reduce the border of the display device.

[0052] In one example, see Figure 2 , the source driver DD has multiple chips on film (COF). At least one source driver chip serving as the source driving circuit SIC is provided on each chip on film (COF); the multiple chips on film (COF) are arranged side by side, and each chip on film (COF) drives multiple data traces.

[0053] See Figure 2 , the source driver DD also has a circuit board to realize the electrical connection between the timing controller TCON, the voltage discharge circuit VRC, the power manager PMIC and the source driving circuit SIC.

[0054] In one example, see Figure 2, a voltage discharge circuit VRC is provided on the main circuit board MPCB, and a power manager PMIC and a timing controller TCON are provided on the driving board DPCB. The source driver DD includes a plurality of source circuit boards SPCB, and each source circuit board SPCB is electrically connected to a plurality of chip-on-film COF; the source circuit board SPCB, the driving board DPCB, and the main circuit board MPCB are electrically connected in sequence. In this way, the power manager PMIC and the timing controller TCON can load the power supply voltage and signals to the source driver circuit SIC through the main circuit board MPCB and the source circuit board SPCB.

[0055] In another example, refer to Figure 3 , a voltage discharge circuit VRC and a timing controller TCON are provided on the main circuit board MPCB, and a power manager PMIC is provided on the driving board DPCB. The source driver DD includes a plurality of source circuit boards SPCB, and each source circuit board SPCB is electrically connected to a plurality of chip-on-film COF; the source circuit board SPCB, the driving board DPCB, and the main circuit board MPCB are electrically connected in sequence. In this way, the power manager PMIC and the timing controller TCON can load the power supply voltage and signals to the source driver circuit SIC through the main circuit board MPCB and the source circuit board SPCB.

[0056] Of course, in other embodiments of the present disclosure, the source driver circuit SIC can be directly provided on the source circuit board SPCB, or the power manager PMIC and the timing controller TCON can be provided on the main circuit board MPCB, or the source driver circuit SIC can be directly bonded to the display module PNL, or other feasible setting methods; the present disclosure does not make special limitations on these setting methods, as long as the source driver circuit SIC can be electrically connected to the timing controller TCON and the power manager PMIC.

[0057] It should be noted that Figure 2 the driving board DPCB shown in Figure 3 is a TCON board, and the driving board DPCB shown in

[0058] Figure 4 is an equivalent circuit diagram of a voltage discharge circuit VRC of the present disclosure. Refer to Figure 4 , in an embodiment of the present disclosure, the voltage discharge circuit VRC is provided on the main circuit board MPCB and is configured to provide voltage to the driving board DPCB and the display module PNL when the display device is powered on; the voltage discharge circuit VRC is further configured to discharge the voltage of the driving board DPCB when the display device is powered off, so as to reduce the charge residue in the plane of the driving board DPCB and reduce the possibility of flicker and abnormal images of the display module PNL during repeated power-on and power-off processes.

[0059] In an implementation manner of the present disclosure, refer to Figure 4 , the voltage discharge circuit VRC includes a switch sub-circuit SW, an enable sub-circuit ES, and a pressure relief sub-circuit VRS. Wherein, one end of the switch sub-circuit SW is electrically connected to the ground voltage terminal (for loading the ground voltage GND), the other end is electrically connected to the first node N1, and the control end is electrically connected to the drive signal terminal (for loading the drive signal DS); the switch sub-circuit SW can be turned on in response to the conduction signal of the drive signal DS. One end of the enable sub-circuit ES is electrically connected to the input voltage terminal (for loading the input voltage VIN), the other end is electrically connected to the output voltage terminal (for loading the output voltage VOUT), and the control end is electrically connected to the first node N1; the enable sub-circuit ES can be turned on in response to the low-level voltage of the first node N1 and turned off in response to the high-level voltage on the first node N1, and the input voltage terminal is electrically connected to the first node N1 through the first voltage dividing resistor R1. One end of the pressure relief sub-circuit VRS is electrically connected to the output voltage terminal, the other end is electrically connected to the ground voltage terminal, and the control end is electrically connected to the first node N1; the pressure relief sub-circuit VRS can be turned off in response to the low level on the first node N1 and turned on in response to the high-level voltage on the first node N1. The output voltage terminal is used to be electrically connected to the display module PNL and the driving board DPCB to provide voltage to the display module PNL and the driving board DPCB. In the implementation manner of the present disclosure, the input voltage VIN is 12V. In some other implementation manners of the present disclosure, the input voltage VIN can be 13V, 13.1V, 13.2V, etc.

[0060] When the display module PNL is powered on, the main circuit board MPCB terminal provides a conduction signal of the drive signal DS to turn on the switch sub-circuit SW, the ground voltage GND is loaded to the first node N1 to turn on the enable sub-circuit ES, and the pressure relief sub-circuit VRS is turned off. Thus, the voltage at the input voltage terminal is loaded to the display module terminal and the driving board terminal through the enable sub-circuit ES to realize the normal display of the display module PNL. When the display module PNL is powered off, the main circuit board MPCB terminal provides a cut-off signal of the drive signal DS to turn off the switch sub-circuit SW, the first node N1 is at a high level, so that the enable sub-circuit ES is turned off and the pressure relief sub-circuit VRS is turned on. At this time, the display module PNL and the driving board DPCB are powered off, and the residual charge on the driving board DPCB surface is discharged to the ground voltage terminal through the pressure relief sub-circuit VRS to realize the timely discharge of the voltage of the driving board DPCB. During the repeated power-on and power-off process of the display module PNL, the possibility of the display module PNL flashing and the picture being abnormal is reduced, and the display quality of the display module PNL is improved. In addition, the first voltage dividing resistor R1 can divide the voltage of the enable sub-circuit ES to protect the enable sub-circuit ES.

[0061] In an implementation manner of the present disclosure, refer toFigure 4 The switch sub - circuit SW includes a second transistor Q2 and a second voltage - dividing resistor R5. The second transistor Q2 is an NPN - type triode. One end of the second transistor Q2 is electrically connected to the ground - voltage terminal, the other end is electrically connected to the first node N1, and the control end is electrically connected to the drive - signal terminal. The second transistor Q2 can be turned on in response to the conduction signal of the drive signal DS. One end of the second voltage - dividing resistor R5 is electrically connected to the ground - voltage terminal, and the other end is electrically connected to the control end of the second transistor Q2. In some other embodiments of the present disclosure, the switch sub - circuit SW may include a P - type MOS transistor or an N - type MOS transistor, or the switch sub - circuit SW may include a PNP - type triode.

[0062] Thus, when the display module PNL is powered on, the main circuit board MPCB provides a conduction signal of the drive signal DS to turn on the second transistor Q2, so as to load the ground voltage GND to the first node N1. When the display module PNL is powered off, the main circuit board MPCB provides a cut - off signal of the drive signal DS to turn off the first transistor Q1, so as to prevent the ground voltage GND from being loaded to the first node N1. In addition, the second voltage - dividing resistor R5 can divide the voltage of the second transistor Q2 to protect the second transistor Q2 from being broken down and improve the reliability of the entire circuit.

[0063] In one embodiment of the present disclosure, refer to Figure 4 The switch sub - circuit SW further includes a current - limiting resistor R4. One end of the current - limiting resistor R4 is electrically connected to the drive - signal terminal, and the other end is electrically connected to the control end of the second transistor Q2. Thus, the current - limiting resistor R4 can play a role in current - limiting.

[0064] In one embodiment of the present disclosure, refer to Figure 4 The enable sub - circuit ES includes a first transistor Q1. The first transistor Q1 is a P - type MOS transistor. One end of the first transistor Q1 is electrically connected to the input - voltage terminal, the other end is electrically connected to the output - voltage terminal, and the control end is electrically connected to the first node N1. The first transistor Q1 can be turned on in response to the low - level voltage of the first node N1 and turned off in response to the high - level voltage on the first node N1. In some other embodiments of the present disclosure, the enable sub - circuit ES may include several first transistors Q1 connected in series or in parallel, or the enable sub - circuit ES may further include a PNP - type triode.

[0065] Thus, when the display module PNL is powered on, the ground voltage GND is applied to the first node N1 to turn on the first transistor Q1. As a result, the voltage at the input voltage terminal is applied to the display module terminal and the driving board terminal through the first transistor Q1 to achieve normal display of the display module PNL. When the display module PNL is powered off, the first node N1 is loaded with the high level of the input voltage terminal, causing the first transistor Q1 to turn off, thereby powering off the display module PNL and the driving board DPCB.

[0066] In an embodiment of the present disclosure, referring to Figure 4 , the voltage relief sub-circuit VRS includes a voltage relief unit and a voltage relief resistor R2. One end of the voltage relief unit is electrically connected to the output voltage terminal through the voltage relief resistor R2, the other end is electrically connected to the ground voltage terminal, and the control end is electrically connected to the first node N1; the voltage relief unit can be turned off in response to the low level on the first node N1 and turned on in response to the high level voltage on the first node N1. Thus, when the display module PNL is powered on, the first node N1 is loaded with the ground voltage GND, causing the voltage relief unit to turn off, so that there is no current on the voltage relief resistor R2, realizing normal power supply of the driving board DPCB. When the display module PNL is powered off, the first node N1 is loaded with the high level of the input voltage terminal, causing the voltage relief unit to turn on, and the residual charge in the driving board DPCB is discharged to the ground voltage terminal through the voltage relief unit to realize timely discharge of the voltage of the driving board DPCB.

[0067] In an embodiment of the present disclosure, referring to Figure 4 , the voltage relief unit includes a third transistor Q3, and the third transistor Q3 is an N-type transistor; one end of the third transistor Q3 is electrically connected to the output voltage terminal through the voltage relief resistor R2, the other end is electrically connected to the ground voltage terminal, and the control end is electrically connected to the first node N1; the third transistor Q3 can be turned off in response to the low level on the first node N1 and turned on in response to the high level voltage on the first node N1.

[0068] Figure 5 is another equivalent circuit diagram of the voltage discharge circuit VRC of the present disclosure. In some other embodiments of the present disclosure, referring to Figure 5 , one end of the voltage relief resistor R2 is electrically connected to the output voltage terminal, and the other end is electrically connected to the ground voltage terminal. In other embodiments of the present disclosure, the voltage relief unit may further include several third transistors Q3 connected in series or in parallel, or the voltage relief unit may further include an NPN-type triode.

[0069] In the related art, the resistance value of the pressure relief resistor R2 is 10 kΩ. If the resistance value of the pressure relief resistor R2 is decreased, when the display module PNL is powered on, a current is generated in the pressure relief resistor R2, which will cause an increase in the power consumption of the entire system. If the resistance value of the pressure relief resistor R2 is increased, when the display module PNL is powered off, due to the small current passing through the pressure relief resistor R2, the discharge efficiency of the pressure relief resistor R2 is low, resulting in the problem of voltage bounce. Through the design of the third transistor Q3, when the display module PNL is powered on, the first node N1 is loaded with the ground voltage GND, making the third transistor Q3 cut off, so that there is no current on the pressure relief resistor R2. While realizing the normal power supply of the driving board DPCB, the power consumption of the system can be reduced. When the display module PNL is powered off, the first node N1 is loaded with the high level of the input voltage terminal, making the third transistor Q3 conduct. The residual charge in the driving board DPCB is discharged to the ground voltage terminal through the third transistor Q3. While realizing the timely discharge of the voltage of the driving board DPCB, the passive discharge in the related art is changed to active discharge. In addition, the resistance value of the pressure relief resistor R2 can be decreased, thereby further increasing the discharge rate.

[0070] In an embodiment of the present disclosure, referring to Figure 4 , the third transistor Q3 is an N-type MOS transistor. In this way, since the N-type MOS transistor has a parasitic diode, when the driving board DPCB is powered off, the parasitic diode can effectively act as a freewheeling function for the inductive load in the boost circuit of the driving board DPCB, avoiding voltage bounce.

[0071] In an embodiment of the present disclosure, referring to Figure 4 , the pressure relief sub-circuit VRS further includes a third voltage dividing resistor R6. One end of the third voltage dividing resistor R6 is electrically connected to the ground voltage terminal, and the other end is electrically connected to the first node N1. In some other embodiments of the present disclosure, a plurality of third voltage dividing resistors R6 may be provided in series or in parallel. In this way, during the operation of the circuit, the third voltage dividing resistor R6 can play a role in voltage division for the third transistor Q3, so as to protect the third transistor Q3 from being broken down.

[0072] In an embodiment of the present disclosure, referring to Figure 4 , the resistance value of the pressure relief resistor R2 is not greater than the resistance value of the first voltage dividing resistor R1, that is, the resistance value of the pressure relief resistor R2 can be less than or equal to the resistance value of the first voltage dividing resistor R1. In this way, when the resistance value of the pressure relief resistor R2 is small, the discharge rate of the driving board DPCB can be increased.

[0073] In an embodiment of the present disclosure, the resistance value of the pressure relief resistor R2 is less than the resistance value of the third voltage dividing resistor R6.

[0074] In an embodiment of the present disclosure, referring to Figure 4, the resistance values of the first voltage-dividing resistor R1 and the voltage-relieving resistor R2 are both 3.7 to 5.7 kΩ. In this embodiment, the resistance values of the first voltage-dividing resistor R1 and the voltage-relieving resistor R2 are both 4.7 kΩ. The resistance value of the third voltage-dividing resistor R6 is 5.8 to 7.8 kΩ. In this embodiment, the resistance value of the third voltage-dividing resistor R6 is 6.8 kΩ. In some other embodiments of the present disclosure, the resistance value of the voltage-relieving resistor R2 is 3.7 kΩ, the resistance value of the first voltage-dividing resistor R1 is 4.7 kΩ, and the resistance value of the third voltage-dividing resistor R6 is 6.8 kΩ. In this way, compared with the related art where the resistance value of the voltage-relieving resistor R2 is 10 kΩ, while reducing the resistance value of the voltage-relieving resistor R2, the power consumption of the system will not increase.

[0075] In an embodiment of the present disclosure, referring to Figure 4 , the resistance value of the first voltage-dividing resistor R1 is 3.7 to 5.7 kΩ, and the resistance value of the third voltage-dividing resistor R6 is 5.8 to 7.8 kΩ. In this embodiment, the resistance value of the first voltage-dividing resistor R1 is 4.7 kΩ, and the resistance value of the third voltage-dividing resistor R6 is 6.8 kΩ.

[0076] In an embodiment of the present disclosure, referring to Figure 4 , the voltage discharge circuit VRC further includes a first filtering sub-circuit FS1; the first filtering sub-circuit FS1 includes a filtering resistor R3 and at least one first capacitor C1. One end of the filtering resistor R3 is electrically connected to the first node N1, and the other end is electrically connected to one end of the enabling sub-circuit ES through the first capacitor C1. In this embodiment, the number of the first capacitors C1 is two. In some other embodiments of the present disclosure, the number of the first capacitors C1 can be 3, 4, 5, etc.

[0077] Referring to Figure 4 , one end of one of the first capacitors C1 is electrically connected to the control end of the first transistor Q1, and the other end is electrically connected to one end of the first transistor Q1; one end of the other first capacitor C1 is electrically connected to the control end of the first transistor Q1, and the other end is electrically connected to the other end of the first transistor Q1. In other words, the two first capacitors C1 are respectively located on both sides of the first transistor Q1. In addition, the resistance value of the filtering resistor R3 is 100 kΩ to achieve the filtering effect on the first transistor Q1 and the input voltage terminal.

[0078] In an embodiment of the present disclosure, referring to Figure 4, the voltage discharge circuit further includes a second filter sub-circuit FS2; the second filter sub-circuit FS2 includes a second capacitor C2, one end of the second capacitor C2 is electrically connected to the output voltage terminal, and the other end is electrically connected to the ground voltage terminal. In some other embodiments of the present disclosure, the second filter sub-circuit FS2 may include a plurality of second capacitors C2 connected in parallel. In this way, filtering between the display module end and the driving board end can be achieved.

[0079] In Figure 4 the example of, the voltage discharge circuit VRC includes a switch sub-circuit SW, an enable sub-circuit ES, a pressure relief sub-circuit VRS, a first filter sub-circuit FS1, and a second filter sub-circuit FS2.

[0080] Among them, the switch sub-circuit SW includes a second transistor Q2, a current limiting resistor R4, and a second voltage dividing resistor R5. The second transistor Q2 is an NPN type triode; one end of the second transistor Q2 is electrically connected to the ground voltage terminal, the other end is electrically connected to the first node N1, and the control end is electrically connected to the driving signal terminal; the second transistor Q2 can be turned on in response to the conduction signal of the driving signal DS. One end of the second voltage dividing resistor R5 is electrically connected to the ground voltage terminal, and the other end is electrically connected to the control end of the second transistor Q2. One end of the current limiting resistor R4 is electrically connected to the driving signal terminal, and the other end is electrically connected to the control end of the second transistor Q2.

[0081] The enable sub-circuit ES includes a first transistor Q1. The first transistor Q1 is a P-type MOS transistor; one end of the first transistor Q1 is electrically connected to the input voltage terminal, the other end is electrically connected to the output voltage terminal, and the control end is electrically connected to the first node N1; the first transistor Q1 can be turned on in response to the low-level voltage of the first node N1 and turned off in response to the high-level voltage on the first node N1.

[0082] The pressure relief sub-circuit VRS includes a third transistor Q3, a pressure relief resistor R2, and a third voltage dividing resistor R6. Among them, the third transistor Q3 is an N-type MOS transistor. One end of the third transistor Q3 is electrically connected to the output voltage terminal through the pressure relief resistor R2, the other end is electrically connected to the ground voltage terminal, and the control end is electrically connected to the first node N1; the third transistor Q3 can be turned off in response to the low level on the first node N1 and turned on in response to the high-level voltage on the first node N1. One end of the third voltage dividing resistor R6 is electrically connected to the ground voltage terminal, and the other end is electrically connected to the first node N1.

[0083] The first filtering sub - circuit FS1 includes a filtering resistor R3 and at least one first capacitor C1. One end of the filtering resistor R3 is electrically connected to the first node N1, and the other end is electrically connected to one end of the enabling sub - circuit ES through the first capacitor C1.

[0084] The second filtering sub - circuit FS2 includes a second capacitor C2. One end of the second capacitor C2 is electrically connected to the output voltage terminal, and the other end is electrically connected to the ground voltage terminal.

[0085] The following combines Figure 6 and Figure 7 to Figure 4 describe the working process of the voltage discharge circuit VRC in

[0086] Power - on stage: Refer to Figure 6 , when the display module PNL is powered on, the main circuit board MPCB provides a conduction signal of the driving signal DS to turn on the second transistor Q2. The ground voltage GND is loaded to the first node N1 to turn on the first transistor Q1 and turn off the third transistor Q3. Thus, the voltage at the input voltage terminal is loaded to the display module terminal and the driving board terminal through the first transistor Q1 to achieve normal display of the display module PNL.

[0087] Power - off stage: Refer to Figure 7 , when the display module PNL is powered off, the main circuit board MPCB provides a cut - off signal of the driving signal DS to turn off the second transistor Q2. The voltage at the input voltage terminal is loaded to the first node N1. Since the first node N1 is at a high level, the first transistor Q1 is turned off and the third transistor Q3 is turned on. At this time, the display module PNL and the driving board DPCB are powered off, and the residual charge on the driving board DPCB is discharged to the ground voltage terminal through the third transistor Q3 to achieve timely discharge of the voltage on the driving board DPCB, reducing the possibility of voltage bounce. During the process of repeatedly powering on and off the display module PNL, the possibility of flashing and abnormal images of the display module PNL is reduced, improving the display quality of the display module PNL.

[0088] Figure 8 This is the simulation diagram when the voltage discharge circuit VRC provided by the present disclosure is working, aiming to illustrate the effects before and after the improvement of the voltage discharge circuit VRC in the present disclosure. Refer to Figure 8 , the voltage of the improved voltage discharge circuit VRC drops smoothly compared with the voltage of the voltage discharge circuit VRC before improvement, and there is no obvious rebound voltage.

[0089] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A voltage discharge circuit, characterized in that, including: a switching sub - circuit, one end electrically connected to the ground voltage terminal, the other end electrically connected to the first node, and the control end electrically connected to the driving signal terminal; the switching sub - circuit can be turned on in response to the conduction signal of the driving signal; an enabling sub - circuit, one end electrically connected to the input voltage terminal, the other end electrically connected to the output voltage terminal, and the control end electrically connected to the first node; the enabling sub - circuit can be turned on in response to the low - level voltage of the first node and turned off in response to the high - level voltage on the first node; the input voltage terminal and the first node are electrically connected through a first voltage - dividing resistor; a pressure - relief sub - circuit, one end electrically connected to the output voltage terminal, the other end electrically connected to the ground voltage terminal, and the control end electrically connected to the first node; the pressure - relief sub - circuit can be turned off in response to the low - level on the first node and turned on in response to the high - level voltage on the first node; the output voltage terminal is used to be electrically connected to a display module and a driving board.

2. The voltage discharge circuit according to claim 1, characterized in that the pressure - relief sub - circuit includes a pressure - relief unit and a pressure - relief resistor; one end of the pressure - relief unit is electrically connected to the output voltage terminal through the pressure - relief resistor, the other end is electrically connected to the ground voltage terminal, and the control end is electrically connected to the first node; the pressure - relief unit can be turned off in response to the low - level on the first node and turned on in response to the high - level voltage on the first node.

3. The voltage discharging circuit according to claim 2, wherein the pressure - relief unit includes a third transistor, and the third transistor is an N - type transistor; one end of the third transistor is electrically connected to the output voltage terminal through the pressure - relief resistor, the other end is electrically connected to the ground voltage terminal, and the control end is electrically connected to the first node; the third transistor can be turned off in response to the low - level on the first node and turned on in response to the high - level voltage on the first node.

4. The voltage discharging circuit according to claim 3, characterized in that the third transistor is an N - type MOS transistor.

5. The voltage discharge circuit according to claim 1, characterized in that, the pressure - relief sub - circuit includes a pressure - relief unit and a pressure - relief resistor; one end of the pressure - relief unit is electrically connected to the output voltage terminal, the other end is electrically connected to the ground voltage terminal through the pressure - relief resistor, and the control end is electrically connected to the first node; the pressure - relief unit can be turned off in response to the low - level on the first node and turned on in response to the high - level voltage on the first node.

6. The voltage discharge circuit according to claim 2, characterized in that, the pressure - relief sub - circuit further includes a third voltage - dividing resistor, one end of the third voltage - dividing resistor is electrically connected to the ground voltage terminal, and the other end is electrically connected to the first node.

7. The voltage discharge circuit according to claim 6, characterized in that, the resistance value of the pressure - relief resistor is not greater than the resistance value of the first voltage - dividing resistor.

8. The voltage discharge circuit according to claim 6, wherein the pressure - relief resistor is less than the third voltage - dividing resistor.

9. The voltage discharge circuit according to claim 6, characterized in that the resistance values of the first voltage - dividing resistor and the pressure - relief resistor are 3.7 - 5.7 kΩ, and the resistance value of the third voltage - dividing resistor is 5.8 - 7.8 kΩ.

10. The voltage discharge circuit according to claim 6, characterized in that, the resistance value of the first voltage - dividing resistor is 3.7 - 5.7 kΩ, and the resistance value of the third voltage - dividing resistor is 5.8 - 7.8 kΩ.

11. The voltage discharge circuit according to claim 1, characterized in that, The enabling sub-circuit includes a first transistor, which is a P-type MOS transistor; one end of the first transistor is electrically connected to the input voltage terminal, the other end is electrically connected to the output voltage terminal, and the control terminal is electrically connected to the first node; the first transistor can be turned on in response to the low-level voltage of the first node and turned off in response to the high-level voltage on the first node.

12. The voltage discharge circuit according to claim 1, characterized in that, The switching sub-circuit includes a second transistor and a second voltage-dividing resistor, and the second transistor is an NPN-type triode; One end of the second transistor is electrically connected to the ground voltage terminal, the other end is electrically connected to the first node, and the control terminal is electrically connected to the drive signal terminal; the second transistor can be turned on in response to the conduction signal of the drive signal; One end of the second voltage-dividing resistor is electrically connected to the ground voltage terminal, and the other end is electrically connected to the control terminal of the second transistor.

13. The voltage discharging circuit according to any one of claims 1 to 12, characterized in that, The voltage discharging circuit further includes a first filtering sub-circuit; The first filtering sub-circuit includes a filtering resistor and at least one first capacitor; One end of the filtering resistor is electrically connected to the first node, and the other end is electrically connected to one end of the enabling sub-circuit through the first capacitor.

14. The voltage discharge circuit according to any one of claims 1 to 12, characterized in that, The voltage discharging circuit further includes a second filtering sub-circuit; The second filtering sub-circuit includes a second capacitor, one end of the second capacitor is electrically connected to the output voltage terminal, and the other end is electrically connected to the ground voltage terminal.

15. A display device, characterized in that, It includes the voltage discharging circuit according to any one of claims 1 to 14.

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