Nanometer relay with neural network structure

Abstract

The invention relates to the technical field of relays, in particular to a neural network structure nanometer relay which comprises an input layer, the side face of the input layer is electrically connected with a first middle layer, a second middle layer and an output layer, an input layer module is arranged in the input layer, and middle layer modules are arranged in the first middle layer and the second middle layer respectively. An input layer module is arranged in the input layer, an intermediate layer module is arranged in the input layer, an output layer module is arranged in the output layer, a rear time management module is arranged on the side surface of the output layer module, and the input layer module, the intermediate layer module, the output layer module and the rear time management module are electrically connected. The neural network structure nanometer relay endows different weight factors according to input data and the importance of a protection algorithm, is suitable for single-input protection, is also suitable for multi-input protection, is suitable for a single protection algorithm, is also suitable for a multi-algorithm fusion protection algorithm, and is suitable for a multi-input protection algorithm. The reliability of the protection output result can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of relays, and specifically to a neural network structure nano-relay. Background Technique

[0002] With the rapid development of China's power system, people's electricity consumption demand has gradually increased, which also brings a huge burden to the stability of the power system. Relay protection is the first line of defense for the safe operation of the power grid and a key technical means to ensure the stability of the power grid and the safety of power equipment. With the development and application of computer technology and the renewal of relay devices, relay protection technology has fully entered the era of microcomputer protection from the most basic electromechanical relays and transistor relays. Microcomputer protection abstracts relays into algorithms and uses software program logic to achieve control and protection. It has the characteristics of small volume, low power consumption, strong programmable ability, convenient maintenance and debugging, and is currently widely used in power grids of various voltage levels.

[0003] When existing microcomputer protection relay devices process multi-channel data or face complex algorithms, they usually reduce the sampling frequency of the protection device so that the CPU can have sufficient processing power within the sampling interval. However, the reduction of the sampling frequency will increase the algorithm error of the microcomputer protection and reduce the reliability of the protection; if the protection reliability is improved by increasing the number of sampling points, the protection action time will be prolonged. Currently, a new relay protection architecture - nano-relay has been proposed. This architecture replaces software algorithms with hardware logic circuits, breaks through the limitations of software interrupt response processing, and improves the quick-acting performance of the protection. However, the nano-relay architecture is fixed and only adapts to specific input and business functions with a fixed sampling frequency, and there is an urgent need to improve the flexibility of the nano-relay to achieve different business functions. Summary of the Invention

[0004] The purpose of the present invention is to provide a neural network structure nano-relay to solve the problems proposed in the above background technique that when microcomputer protection relay devices process multi-channel data or face complex algorithms, they usually reduce the sampling frequency of the protection device so that the CPU can have sufficient processing power within the sampling interval. However, the reduction of the sampling frequency will increase the algorithm error of the microcomputer protection and reduce the reliability of the protection; if the protection reliability is improved by increasing the number of sampling points, the protection action time will be prolonged. Currently, a new relay protection architecture - nano-relay has been proposed. This architecture replaces software algorithms with hardware logic circuits, breaks through the limitations of software interrupt response processing, and improves the quick-acting performance of the protection.

[0005] To achieve the above purpose, the present invention provides the following technical solutions:

[0006] A neural network structure nano-relay includes an input layer. The sides of the input layer are electrically connected to a first intermediate layer, a second intermediate layer, and an output layer respectively. An input layer module is arranged in the input layer. Intermediate layer modules are arranged in the first intermediate layer and the second intermediate layer respectively. An output layer module is arranged in the output layer. A post-time management module is arranged on the side of the output layer module. The input layer module, the intermediate layer modules, the output layer module, and the post-time management module are electrically connected to each other.

[0007] As a preferred solution of the present invention, the input layer, i.e., the neural network data receiving module, can be composed of a data sampling synchronization module and a classification module. The synchronization module is composed of a sampling and interpolation processing sub-module, a D / A conversion sub-module, a data filtering sub-module, a message organization and sending sub-module, etc., and is used to achieve accurate sampling of multi-channel data and eliminate invalid data. The neural network data receiving module interacts with the chip CPU main system, the security sub-system, and the peripheral structure through a bus. The chip CPU main system is an embedded autonomous chip, and the chip CPU main system is composed of a high-performance processing core, a peripheral interface, and a bus interface.

[0008] As a preferred solution of the present invention, the classification module can be composed of a decision tree classification sub-module or a support vector machine classification sub-module, etc. After sampling and processing the data, the obtained data is classified simply and complexly through the classification sub-module, providing a basis for subsequent selective transmission.

[0009] As a preferred solution of the present invention, the input layer module is divided into a transmission control module and a protection algorithm module. The protection algorithm module can be further divided into a simple module and a complex module. The simple module is composed of simple algorithm sub-modules commonly used for relay protection in power systems, including but not limited to addition and subtraction calculation sub-modules, exponential calculation sub-modules, simple differential and integral algorithm sub-modules, DC component calculation sub-modules, etc. The other complex module is composed of relatively complex algorithm sub-modules commonly used for relay protection in power systems. The protection algorithm module also includes equal-interval interpolation and filtering algorithms, which can adapt to different sampling frequencies.

[0010] As a preferred solution of the present invention, the transmission control module can be composed of a rule library sub-module and a scheduling sub-module. The rule library sub-module stipulates which complex electrical quantities should be transmitted to the complex algorithm module and which simple electrical quantities should be transmitted to the corresponding other protection algorithm modules by establishing a rule library. The scheduling sub-module controls the transmission path of the electrical quantities according to the requirements of the rule library and accurately sends different types of electrical quantities to the corresponding protection algorithms for calculation.

[0011] As a preferred solution of the present invention, the output layer module is composed of a result summarization sub-module, and the result summarization sub-module is used to collect the preliminary judgment results output by each protection algorithm module, integrate them into a data structure, and prepare for logical comparison.

[0012] As a preferred solution of the present invention, the input layer, the first intermediate layer, the second intermediate layer, and the output layer all transmit data by setting weights.

[0013] As a preferred solution of the present invention, after the input layer receives the data transmitted from the sensor side, the classification module classifies and processes the data and extracts features. Multiple data are allocated through the rule base sub-module and the scheduling module. The protection algorithm in the intermediate layer module receives the complete data, judges the fault, and outputs the correct data result.

[0014] As a preferred solution of the present invention, the data processing modules in the intermediate layer module are interconnected and combined.

[0015] As a preferred solution of the present invention, the output layer sends the protection action result to the post-time management module, and the post-time management module accelerates or delays the protection action according to the protection action result and the protection algorithm requirements.

[0016] Compared with the prior art, the beneficial effects of the present invention are:

[0017] 1. In the present invention, by setting the coordinated use of the input layer, the first intermediate layer, and the output layer, the neural network structure nano-relay assigns different weight factors according to the importance of the input data and the protection algorithm, which is applicable to both single-input quantity protection and multi-input quantity protection. The neural network structure nano-relay is applicable to both single protection algorithms and protection algorithms with multi-algorithm fusion, which can improve the reliability of the protection output result.

[0018] 2. In the present invention, the neural network structure nano-relay adapts to the sampling frequencies of different sampling devices. When the sampling device frequency is low, a simple calculation module can be selected or the sampling frequency can be increased through an interpolation algorithm; when the sampling device frequency is low, a complex calculation module can be selected or the sampling frequency can be reduced through a filtering algorithm, thereby greatly improving the flexibility of the nano-relay on the premise of ensuring quick action. The neural network structure nano-relay embedded with an autonomous chip can effectively improve the correctness and transmission efficiency of data transmission in the chip, and enhance the safety performance of power service functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic structural diagram of the architecture of the neural network structure nano-relay of the present invention;

[0020] Figure 2Schematic diagram of the internal module association of the nano-relay with the neural network structure of the present invention;

[0021] Figure 3 Schematic diagram of the flow chart of the nano-relay with the neural network structure of the present invention;

[0022] Figure 4 Schematic diagram of the autonomous chip architecture based on the nano-relay of the present invention;

[0023] Figure 5 Schematic diagram of the circuit fault diagram of the present invention;

[0024] Figure 6 Schematic diagram of the nano-relay with a simple neural network structure of the present invention.

[0025] In the figure: 1. Input layer; 2. First intermediate layer; 3. Second intermediate layer; 4. Output layer; 5. Input layer module; 6. Intermediate layer module; 7. Output layer module; 8. Post-time management module. Detailed implementation manners

[0026] Next, in combination with the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0027] Embodiment, please refer to Figures 1 - 6 The present invention provides a technical solution:

[0028] A neural network structure nano-relay includes an input layer 1. The sides of the input layer 1 are electrically connected to a first intermediate layer 2, a second intermediate layer 3, and an output layer 4 respectively. An input layer module 5 is arranged in the input layer 1. Intermediate layer modules 6 are arranged in the first intermediate layer 2 and the second intermediate layer 3 respectively. An output layer module 7 is arranged in the output layer 4. A post-time management module 8 is arranged on the side of the output layer module 7. The input layer module 5, the intermediate layer module 6, the output layer module 7, and the post-time management module 8 are electrically connected. The input layer 1, i.e., the neural network data receiving module, can be composed of a data sampling synchronization module and a classification module. The synchronization module is composed of a sampling and interpolation processing sub-module, a D / A conversion sub-module, a data filtering sub-module, a message organization and sending sub-module, etc., and is used to achieve accurate sampling of multi-channel data and eliminate invalid data. The neural network data receiving module interacts with the chip CPU main system, the security subsystem, and the peripheral structure through a bus. The chip CPU main system is an embedded autonomous chip and is composed of a high-performance processing core, a peripheral interface, and a bus interface. The classification module can be composed of a decision tree classification sub-module or a support vector machine classification sub-module, etc. After sampling and processing the data, the obtained data is simply and complexly classified by the classification sub-module to provide a basis for subsequent selective transmission.

[0029] The input layer module 5 is divided into a conveying control module and a protection algorithm module. The protection algorithm module can be further divided into a simple module and a complex module. The simple module consists of simple algorithm sub-modules commonly used in power system relay protection, including but not limited to addition and subtraction calculation sub-modules, exponential calculation sub-modules, simple differential and integral algorithm sub-modules, DC component calculation sub-modules, etc. The other complex module consists of relatively complex algorithm sub-modules commonly used in power system relay protection. The protection algorithm module also includes equidistant interpolation and filtering algorithms, which can adapt to different sampling frequencies. The conveying control module can be composed of a rule base sub-module and a scheduling sub-module. The rule base sub-module stipulates, by establishing a rule base, which complex electrical quantities should be conveyed to the complex algorithm module and which simple electrical quantities should be conveyed to the corresponding other protection algorithm modules through establishing a rule base. The scheduling sub-module controls the conveying path of electrical quantities according to the requirements of the rule base, and accurately sends different types of electrical quantities to the corresponding protection algorithms for calculation. The output layer module 7 is composed of a result summary sub-module. The result summary sub-module is used to collect the preliminary judgment results output by each protection algorithm module, integrate them into a data structure, and prepare for logical comparison. The input layer 1, the first intermediate layer 2, the second intermediate layer 3, and the output layer 4 all transmit data by setting weights. After the input layer 1 receives the data transmitted from the sensor side, the classification module classifies, processes, and extracts features from the data. Multiple data are distributed through the rule base sub-module and the scheduling module. The protection algorithms in the intermediate layer module 6 receive complete data, judge faults, and output correct data results. The data processing modules in the intermediate layer module 6 are interconnected and combined. The output layer 4 sends the protection action results to the post-time management module 8. The post-time management module 8 accelerates or delays the protection action according to the protection action results and the requirements of the protection algorithm.

[0030] Among them, by designing the structures of the input layer (1), the first intermediate layer (2), and the output layer (4) and their connection methods, the input electrical quantities can be selectively conveyed to the corresponding protection algorithm modules; through the selection of input-output weight coefficients and the combination of interpolation and filtering algorithms, the reasonable selection of output data and protection algorithms is realized, and the flexibility and reliability of the nano-relay are greatly improved on the premise of ensuring rapidity.

[0031] According to Figure 4 and Figure 5 the case analysis, to further demonstrate the superiority of the method proposed by the present invention, for Figure 6The simple nano-relay architecture shown is described. For line overcurrent protection, when the current detected by the protection device is greater than the setting threshold, the protection operates. The setting threshold is generally obtained by multiplying the reliability coefficient by the maximum short-circuit current at the end of the protected line. For line differential protection, without a braking characteristic, if the differential current is greater than the setting current, the protection operates, and the setting current is generally obtained by multiplying the reliability coefficient by the maximum short-circuit current of an external fault of the line; with a braking characteristic, if the differential current is greater than the braking current, the protection operates.

[0032] The setting algorithm for overcurrent protection in a protection relay is

[0033] I dz = k·I1 (1)

[0034] Where I dz is the setting current of the line overcurrent protection, I1 is the maximum short-circuit current at the end of this line, and k is the reliability coefficient.

[0035] And the differential current algorithm is

[0036] I cd = |I1 + I2| (2)

[0037] The braking current algorithm is

[0038] I res = |I1 - I2| (3)

[0039] Where I cd is the differential current, I res is the braking current, I1 is the current measured by the protection at one end of this line, and I2 is the current measured by the protection at the other end of this line.

[0040] When Figure 5 a short-circuit fault occurs in the AB line shown, from Figure 6It can be seen from the above protection formula that if the weight coefficient k1 is 1 and k2 is 0, only the fault current measured by protection 1 is transmitted to the nano-relay, then the braking module of the nano-relay does not meet the action condition, and the module without braking characteristics meets the requirement of If>Izd, that is, the response of the nano-relay is overcurrent protection. If the weight coefficients k1 and k2 are both 1, in general, the braking module and the module without braking characteristics of the nano-relay meet the requirements; at this time, if the weight coefficient k3 is 1 and k4 is 0, the response of the nano-relay is differential protection with braking characteristics; if the weight coefficient k3 is 0 and k4 is 1, the response of the nano-relay is differential protection without braking characteristics; in addition, if the reliability of differential protection with braking characteristics is higher than that of differential protection without braking characteristics, the weight coefficient k3 can be in the range of 0-0.5, and the weight coefficient k4 can be in the range of 0.5-1. At this time, the protection output result combines the differential protection with braking characteristics and without braking characteristics. In addition, if the sampling frequency changes, the neural network structure nano-relay is still applicable. From the above analysis, it can be seen that the neural network structure nano-relay not only reflects the flexibility of the protection algorithm but also improves the reliability of the protection output results.

[0041] At the same time, the chip CPU main system writes the differential current, unbalanced current, and braking current data into the shared memory, sends a data security authentication message notification to the security subsystem, and starts the security core. The security core responds to the interrupt, switches from the sleep state to the working state, and obtains the differential current, unbalanced current, and braking current data to be authenticated from the CPU main system shared memory through the high-speed bus according to the multi-channel data security authentication requirements, and performs security authentication and false data identification on these data. After the processing is completed, the security core sends the processing results to the chip CPU main system and writes the results back to the shared memory.

[0042] The chip CPU main system extracts the differential current, unbalanced current, braking current data from the shared memory and the security authentication and false data identification results sent by the security core, and sends overcurrent protection and differential current protection execution instructions without braking characteristics / with braking characteristics to the nano-relay on the premise that the data meets the security authentication. The internal interactive sub-module of the nano-relay chip obtains the chip CPU main system instructions through the high-speed bus, and assigns specific weight coefficient values ​​according to the instructions (if the instruction of the nano-relay is differential protection with braking characteristics, the weight coefficient k3 is 1 and k4 is 0; if the instruction of the nano-relay is differential protection without braking characteristics, the weight coefficient k3 is 0 and k4 is 1; if the instruction of the nano-relay is overcurrent protection, the weight coefficient k1 is 1 and k2 is 0), starts a series of parallel calculations and data flexible configuration calculations such as collection and processing, power-specific algorithms, and result judgment, and finally writes the results into the shared memory of the chip CPU main system. On the one hand, the nano-relay power protection business export action, on the other hand, the stored data can be used for fault analysis, printing and other services.

[0043] The neural network structure nano-relay conducts information interaction with the chip CPU main system and the security subsystem through a high-speed bus, which can effectively improve the correctness and transmission efficiency of data transmission within the chip and enhance the security performance of power service functions compared with the off-chip series structure interaction mode.

[0044] The working process of the present invention: When the neural network structure nano-relay designed by this solution is in operation, it first checks whether the device is in normal use and conducts information interaction with the chip CPU main system, the security subsystem, and the peripheral structure through the bus. This architecture adopts the advanced microcontroller bus architecture and does not require communication between boards. The nano-relay integrates a power algorithm module, and uses ASIC logic circuits to implement hardware acceleration for algorithms such as pre-data processing, network communication, and data management, providing high-efficiency data parallel processing and high-performance data computing functions. The chip CPU main system consists of a high-performance processing core, a peripheral interface, and a bus interface, featuring high scalability and high power consumption efficiency, and can meet the requirements of power service functions such as real-time control and management communication. The security subsystem is embedded with a national cryptography algorithm security module and a security CPU core based on a security mechanism, providing security services such as data encryption and decryption, and identity authentication, and can implement functions such as source and channel encryption and chip secure startup according to the requirements of power service scenarios. The chip CPU main system writes message data into the shared memory, sends a message notification to the security subsystem, and starts the security core. The security core responds to the interrupt, switches from the sleep state to the working state, and obtains the data to be processed from the shared memory of the CPU main system through the high-speed bus according to the message command and message parameters, and conducts data security authentication and encryption and decryption services. After the processing is completed, the security core sends the processing result to the chip CPU main system and writes the result back to the shared memory. The chip CPU main system determines the data security attribute according to the security authentication result sent by the security core, and sends a message notification to the nano-relay on the premise that the data meets the security authentication. The internal interaction sub-module of the nano-relay chip obtains the instructions of the chip CPU main system through the high-speed bus, assigns specific weight coefficient values according to the instructions, and starts a series of parallel calculations and flexible data configuration calculations such as acquisition processing, power-specific algorithms, and result determination, and finally writes the result into the shared memory of the chip CPU main system. The nano-relay assigns different weight factors according to the importance of the input data and the protection algorithm, which is applicable to both single-input quantity protection and multi-input quantity protection; it is applicable to both single protection algorithms and different fusion protection algorithms; at the same time, it also adapts to the sampling frequencies of different sampling devices, thus greatly improving the flexibility of the nano-relay while ensuring fast operation.

[0045] Although embodiments of the present invention have been shown and described, those of ordinary skill in the art will appreciate that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A neural network structure nano relay, comprising an input layer (1), characterized in that: The side surfaces of the input layer (1) are electrically connected to the first intermediate layer (2), the second intermediate layer (3) and the output layer (4), the input layer (1) is provided with an input layer module (5), the first intermediate layer (2) and the second intermediate layer (3) are provided with intermediate layer modules (6), the output layer (4) is provided with an output layer module (7), the side surfaces of the output layer module (7) are provided with a post-time management module (8), and the input layer module (5), the intermediate layer module (6), the output layer module (7) and the post-time management module (8) are electrically connected to each other.

2. A neural network structure nano relay according to claim 1, characterized in that: The input layer (1), i.e., the neural network data receiving module, can be composed of a data sampling synchronization module and a classification module. The synchronization module is composed of a sampling and interpolation processing submodule, a D / A conversion submodule, a data filtering submodule, a message organization and sending submodule, etc., for realizing accurate sampling of multi-channel data and eliminating invalid data. The neural network data receiving module exchanges information with the chip CPU main system, the security subsystem, and the peripheral structure through the bus. The chip CPU main system is an embedded independent chip, and the chip CPU main system is composed of a high-performance processing core, a peripheral interface, and a bus interface.

3. A neural network structure nano relay according to claim 2, characterized in that: The classification module may be composed of a decision tree classification submodule or a support vector machine classification submodule, etc. After the data is sampled and processed, the classification submodule performs simple and complex classification on the obtained data to provide a basis for subsequent selective transmission.

4. The neural network structure nano relay according to claim 1, characterized in that: The input layer module (5) is divided into a transmission control module and a protection algorithm module. The protection algorithm module can be further divided into a simple module and a complex module. The simple module is composed of simple algorithm submodules commonly used in power system relay protection, including but not limited to addition and subtraction calculation submodule, exponential calculation submodule, simple differential and integral algorithm submodule, DC component calculation submodule, etc. The other complex module is composed of more complex algorithm submodules commonly used in power system relay protection. The protection algorithm module also includes equal interval interpolation and filtering algorithms, which can be adapted to different sampling frequencies.

5. The neural network structure nano relay according to claim 4, characterized in that: The transmission control module can be composed of a rule base submodule and a scheduling submodule. The rule base submodule establishes a rule base to stipulate which complex electrical quantities should be transmitted to the complex algorithm module and which simple electrical quantities should be transmitted to other corresponding protection algorithm modules. The scheduling submodule controls the transmission path of the electrical quantities in accordance with the requirements of the rule base, and accurately sends different types of electrical quantities to the corresponding protection algorithms for calculation.

6. The neural network structure nano relay according to claim 1, characterized in that: The output layer module (7) is composed of a result summary submodule, which is used to collect the preliminary judgment results output by each protection algorithm module and integrate them into a data structure for logical comparison.

7. The neural network structure nano relay according to claim 1, characterized in that: The input layer (1), the first intermediate layer (2), the second intermediate layer (3) and the output layer (4) all transfer data by setting weights.

8. The neural network structure nano relay according to claim 1, characterized in that: After the input layer (1) receives the data transmitted by the sensor side, the classification module classifies and processes the data and extracts features. Multiple data are distributed through the rule base submodule and the scheduling module. The protection algorithm in the middle layer module (6) receives the complete data, judges the fault and outputs the correct data result.

9. The neural network structure nano relay according to claim 1, characterized in that: The data processing modules in the middle layer module (6) are interconnected and combined.

10. The neural network structure nano relay according to claim 1, characterized in that: The output layer (4) sends the protection action result to the post-time management module (8), and the post-time management module (8) accelerates or delays the protection action according to the protection action result and the protection algorithm requirements.

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