Preparation method of semiconductor packaging structure capable of avoiding Cu diffusion
By retaining the packaging layer on the Cu metal column during the grinding process and patterning the Cu metal column, the chip pollution problem caused by Cu diffusion is solved, and the high reliability and stability of the packaging structure is achieved.
Patent Information
- Application Number
- CN202311855783.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-29
- Publication Date
- 2025-07-01
AI Technical Summary
In the prior art, Cu metal diffuses during the grinding of silicon chips, causing contamination, causing chip function failure.
When grinding thinned silicon chips, the packaging layer on the Cu metal column is retained, and only the composite interface of the packaging layer/silicon chip is ground, and the Cu metal column is exposed through the patterned packaging layer for electrical connection to avoid Cu metal residue on the silicon chip.
It effectively avoids Cu metal diffusion pollution, ensures stable chip electrical performance, prevents Cu/Si from being grinded simultaneously, and improves the reliability of the packaging structure.
Smart Images
Figure CN120237012A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor manufacturing, and relates to a method for preparing a semiconductor packaging structure that avoids Cu diffusion. Background Art
[0002] The rapid development of electronic products is the main driving force for the evolution of current packaging technologies. Miniaturization, high density, high frequency, high speed, high reliability, and low cost are the mainstream development directions of advanced packaging.
[0003] Existing consumer electronic product packaging generally adopts Package on Package (POP) stacked packaging. With the increase in the functional integration of electronic products, the packaging structure becomes highly concentrated. The heat generated during the operation of the chip will cause irreversible damage to the chip itself. Therefore, the heat dissipation problem of the packaging structure needs to be considered, and the heat dissipation requirement for product packaging is getting higher and higher.
[0004] Such as Figure 1 and Figure 2 , in a traditional packaging structure, generally, a grinding method is used to thin and expose the back surface of the underlying silicon chip 10 to increase heat dissipation. And during the grinding process, to facilitate subsequent electrical connection, the copper (Cu) metal pillars 20 around the silicon (Si) chip 10 will be ground simultaneously to expose the surface of the Cu metal pillars 20 for subsequent electrical connection. That is, during grinding, the composite interface of the Cu metal pillars 20 / silicon chip 10 / package layer 30 will be ground synchronously, and then the upper chip will be stacked and packaged. However, during the grinding process of the composite interface of the Cu metal pillars 20 / silicon chip 10 / package layer 30, Cu metal 40 will remain on the back surface of the silicon chip 10. Since Cu metal has a large diffusion coefficient, especially Cu metal is extremely easy to diffuse in silicon material, the residual Cu metal 40 will quickly diffuse into the underlying silicon chip 10, causing Cu contamination and resulting in the functional failure of chips sensitive to Cu, such as problems like a decrease in breakdown voltage and leakage.
[0005] Therefore, it is necessary to provide a method for preparing a semiconductor packaging structure that avoids Cu diffusion. Summary of the Invention
[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for preparing a semiconductor packaging structure that avoids Cu diffusion, which is used to solve the problem of Cu contamination caused by Cu metal diffusion in the prior art.
[0007] To achieve the above object and other related objects, the present invention provides a method for preparing a semiconductor packaging structure that avoids Cu diffusion, including the following steps:
[0008] Provide a support substrate;
[0009] Form a first redistribution layer on the support substrate;
[0010] Form Cu metal pillars on the first redistribution layer, and the Cu metal pillars are electrically connected to the first redistribution layer;
[0011] Provide a first silicon chip, and bond the first silicon chip to the first redistribution layer in a flip-chip manner, and the first silicon chip is electrically connected to the first redistribution layer;
[0012] Form a first encapsulation layer, and the first encapsulation layer covers the first redistribution layer, the Cu metal pillars and the first silicon chip;
[0013] Perform grinding to thin the first silicon chip. After grinding, the first encapsulation layer exposes the first silicon chip and covers the Cu metal pillars;
[0014] Pattern the first encapsulation layer to form a groove exposing the Cu metal pillars in the first encapsulation layer;
[0015] Form a second redistribution layer on the first encapsulation layer, and the second redistribution layer is electrically connected to the Cu metal pillars;
[0016] Form a heat dissipation metal block on the second redistribution layer, and the vertical projection of the heat dissipation metal block is located on the first silicon chip;
[0017] Provide a second chip, and bond the second chip to the second redistribution layer in a flip-chip manner, and the second chip is electrically connected to the second redistribution layer, and the heat dissipation metal block is located below the second chip;
[0018] Form a second encapsulation layer, and the second encapsulation layer covers the second redistribution layer, the heat dissipation metal block and the second chip;
[0019] Remove the support substrate to expose the first redistribution layer;
[0020] Form metal bumps on the first redistribution layer, and the metal bumps are electrically connected to the first redistribution layer.
[0021] Optionally, the method of patterning the first encapsulation layer to form the groove includes laser drilling, etching or mechanical drilling.
[0022] Optionally, the method of forming the Cu metal pillars includes electroplating.
[0023] Optionally, the thickness of the first encapsulation layer on the Cu metal pillars before grinding is greater than 15 μm.
[0024] Optionally, the method for forming the heat dissipation metal block includes electroplating or thermally conductive bonding.
[0025] Optionally, the heat dissipation metal block includes a Cu metal block, a Ni metal block, or an Au metal block.
[0026] Optionally, the metal wiring in the second rewiring layer includes a metal seed diffusion barrier layer, and the metal seed diffusion barrier layer is in direct contact with the first silicon chip.
[0027] Optionally, the material of the metal seed diffusion barrier layer includes one or a combination of Ni metal, Au metal, Sn metal, Ag metal, and Ti metal.
[0028] Optionally, the vertical projection of the heat dissipation metal block covers the heat source area of the first silicon chip.
[0029] Optionally, the semiconductor package structure is a wafer-level semiconductor package structure. After forming the metal bumps, it further includes a step of dicing.
[0030] As described above, in the method for preparing the semiconductor package structure that avoids Cu diffusion according to the present invention, the encapsulation layer located on the Cu metal pillars is retained when grinding and thinning the first silicon chip, and only the composite interface of the encapsulation layer / silicon chip is ground. Then, the Cu metal pillars are exposed by patterning the encapsulation layer for electrical connection. Therefore, Cu metal residue on the first silicon chip can be avoided during thinning, thereby avoiding simultaneous grinding of Cu / Si and avoiding Cu metal diffusion contamination. Description of the Drawings
[0031] Figure 1 Shows a schematic structural diagram of the prior art after forming the encapsulation layer.
[0032] Figure 2 Shows a schematic structural diagram of the prior art after grinding.
[0033] Figure 3 Shows a schematic process flow diagram for preparing a semiconductor package structure in an embodiment of the present invention.
[0034] Figures 4 to 13 Shows a schematic structural diagram presented in each step during the preparation of the semiconductor package structure in an embodiment of the present invention.
[0035] Description of the Reference Numerals
[0036] 10 Silicon chip
[0037] 20 Cu metal pillar
[0038] 30 Encapsulation layer
[0039] 40 Residual Cu metal
[0040] 100 Support substrate
[0041] 101 Separation layer
[0042] 210 First redistribution layer
[0043] 211 First metal wiring
[0044] 212 First dielectric layer
[0045] 220 Second redistribution layer
[0046] 221 Second metal wiring
[0047] 222 Second dielectric layer
[0048] 300 Cu metal pillar
[0049] 410 First silicon chip
[0050] 420 Second chip
[0051] 510 First underfill layer
[0052] 520 Second underfill layer
[0053] 610 First encapsulation layer
[0054] 611 Groove
[0055] 620 Second encapsulation layer
[0056] 700 Heat dissipation metal block
[0057] 810 First metal bump
[0058] 820 Second metal bump
[0059] 830 Third metal bump Detailed implementation manners
[0060] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0061] When describing the embodiments of the present invention in detail, for the convenience of description, the cross-sectional views showing the device structure may be locally enlarged out of the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention herein. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.
[0062] For the convenience of description, spatial relationship terms such as "beneath", "below", "lower than", "under", "above", "on" may be used herein to describe the relationship between an element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation, in addition to the directions depicted in the drawings. Embodiments may include those in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.
[0063] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. In actual implementation, the type, quantity, and ratio of each component may be arbitrarily changed, and the component layout type may also be more complex.
[0064] As Figure 3 , this embodiment provides a method for preparing a semiconductor packaging structure for avoiding Cu diffusion, including the following steps:
[0065] S1: Provide a support substrate;
[0066] S2: Form a first redistribution layer on the support substrate;
[0067] S3: Form Cu metal pillars on the first redistribution layer, and the Cu metal pillars are electrically connected to the first redistribution layer;
[0068] S4: Provide a first silicon chip, and bond the first silicon chip to the first redistribution layer in a flip-chip manner, and the first silicon chip is electrically connected to the first redistribution layer;
[0069] S5: Form a first encapsulation layer, and the first encapsulation layer covers the first redistribution layer, the Cu metal pillars, and the first silicon chip;
[0070] S6: Grind to thin the first silicon chip. After grinding, the first encapsulation layer exposes the first silicon chip and covers the Cu metal pillars;
[0071] S7: Pattern the first encapsulation layer to form a groove in the first encapsulation layer that exposes the Cu metal pillars;
[0072] S8: Form a second redistribution layer on the first encapsulation layer, and the second redistribution layer is electrically connected to the Cu metal pillars;
[0073] S9: Form a heat dissipation metal block on the second redistribution layer, and the projection of the heat dissipation metal block along the vertical direction is located on the first silicon chip;
[0074] S10: Provide a second chip, and bond the second chip to the second redistribution layer in a flip - chip manner. The second chip is electrically connected to the second redistribution layer, and the heat dissipation metal block is located below the second chip;
[0075] S11: Form a second encapsulation layer that covers the second redistribution layer, the heat dissipation metal block, and the second chip;
[0076] S12: Remove the support substrate to expose the first redistribution layer;
[0077] S13: Form metal bumps on the first redistribution layer, and the metal bumps are electrically connected to the first redistribution layer.
[0078] The following combines the description with the attached Figures 4 to 13 illustrations to further introduce the preparation of the semiconductor encapsulation structure.
[0079] First, refer to Figure 3 and Figure 4 to perform step S1: Provide a support substrate 100.
[0080] Specifically, the support substrate 100 may include, such as, a glass substrate, a metal substrate, a semiconductor substrate, etc., to provide support for subsequent processes through the support substrate 100. The size of the support substrate 100 is not limited here, and preferably it is wafer - level.
[0081] Among them, for the convenience of removing the support substrate 100 subsequently, in this embodiment, preferably, a separation layer 101 is formed on the surface of the support substrate 100. The separation layer 101 includes but is not limited to tape and polymer layers. For example, the separation layer 101 can be a photothermal conversion layer formed by a photothermal conversion (LTHC) coating material, so that subsequent processes such as light / radiation (such as laser) can be used to decompose the LTHC coating material under heat to release the support substrate 100, improving the convenience of the separation operation.
[0082] Next, refer to Figure 3 and Figure 5, perform step S2 to form a first redistribution layer 210 on the support substrate 100.
[0083] Specifically, the first redistribution layer 210 includes a first metal wiring 211 and a first dielectric layer 212. The first dielectric layer 212 can be formed of a polymer such as polybenzoxazole (PBO), polyimide, etc., or formed of an inorganic dielectric material such as silicon nitride, silicon oxide, etc.; the first metal wiring 211 can include, for example, copper, tungsten, or their alloys, etc. There is no excessive limitation here on the specific structure and material selection of the first redistribution layer 210.
[0084] Next, refer to Figure 3 and Figure 6 , perform step S3 to form Cu metal pillars 300 on the first redistribution layer 210, and the Cu metal pillars 300 are electrically connected to the first redistribution layer 210.
[0085] Specifically, the Cu metal pillars 300 can be formed by means of photolithography, etching, electroplating, but are not limited thereto.
[0086] Next, refer to Figure 3 and Figure 7 , perform step S4 to provide a first silicon chip 410, and bond the first silicon chip 410 to the first redistribution layer 210 in a flip-chip manner, and the first silicon chip 410 is electrically connected to the first redistribution layer 210.
[0087] Specifically, the first silicon chip 410 can be an SoC chip, but is not limited thereto. Among them, the front surface of the first silicon chip 410 has first metal bumps 810, such as solder ball bumps, copper pillar bumps, etc. After bonding the first silicon chip 410 in a flip-chip manner, one end of the first metal bump 810 is electrically connected to the pad (not shown) of the first silicon chip 410, and the other end of the first metal bump 810 is electrically connected to the first redistribution layer 210, and the back surface of the first silicon chip 410 is away from the first redistribution layer 210.
[0088] Among them, after bonding the first silicon chip 410, the gap between the first silicon chip 410 and the first redistribution layer 210 can have a first underfill layer 510 formed by means such as dispensing, etc., so as to apply the first underfill layer 510 as a protective layer for the first silicon chip 410 and the first redistribution layer 210. There is no excessive limitation here on the material of the first underfill layer 510.
[0089] Next, refer to Figure 3 and Figure 8, perform step S5 to form the first encapsulation layer 610, and the first encapsulation layer 610 covers the first redistribution layer 210, the Cu metal posts 300, and the first silicon chip 410.
[0090] Specifically, the method for forming the first encapsulation layer 610 may include but is not limited to compression molding, transfer molding, and spin coating. The material of the first encapsulation layer 610 may include but is not limited to epoxy resin and polyamide. There is no excessive limitation on the material and preparation method of the first encapsulation layer 610 here.
[0091] Next, refer to Figure 3 and Figure 9 , perform step S6 to grind and thin the first silicon chip 410. After grinding, the first encapsulation layer 610 exposes the first silicon chip 410 and covers the Cu metal posts 300.
[0092] Specifically, the grinding method may include, for example, chemical mechanical polishing (CMP) to remove part of the first encapsulation layer 610 and expose the back surface of the first silicon chip 410, so as to thin the first silicon chip 410 by grinding for heat dissipation and reduce the package size.
[0093] Among them, when grinding the composite interface of the silicon layer / encapsulation layer composed of the first silicon chip 410 and the first encapsulation layer 610, since the first encapsulation layer 610 covers the Cu metal posts 300, the Cu metal posts 300 are not ground, thus avoiding the influence of Cu metal on the electrical performance of the first silicon chip 410.
[0094] Among them, to avoid the exposure of the Cu metal posts 300 during grinding, the thickness of the first encapsulation layer 610 on the Cu metal posts 300 should be at least greater than the grinding tolerance, such as 15μm - 30μm, specifically 15μm, 20μm, 25μm, 30μm, etc.
[0095] Next, refer to Figure 3 and Figure 10 , perform step S7 to pattern the first encapsulation layer 610 and form a groove 611 exposing the Cu metal posts 300 in the first encapsulation layer 610.
[0096] Specifically, the method for patterning the first encapsulation layer 610 to form the groove 611 may include laser drilling, etching, or mechanical drilling. There is no excessive limitation on the patterning method, the size and morphology of the formed groove 611, etc. here.
[0097] Next, refer to Figure 3 and Figure 11, perform step S8 to form a second redistribution layer 220 on the first encapsulation layer 610, and the second redistribution layer 220 is electrically connected to the Cu metal pillar 300.
[0098] Specifically, the second redistribution layer 220 includes a second metal wiring 221 and a second dielectric layer 222. The second dielectric layer 222 can be formed of a polymer such as polybenzoxazole (PBO), polyimide, etc., or formed of an inorganic dielectric material such as silicon nitride, silicon oxide, etc.; the second metal wiring 221 can include, for example, copper, tungsten, or their alloys, etc. No excessive restrictions are imposed here on the specific structure and material selection of the second redistribution layer 220.
[0099] When preparing the second redistribution layer 220, the second metal wiring 221 fills the groove 611, so that the second redistribution layer 220 can be electrically connected to the Cu metal pillar 300.
[0100] Among them, preferably when preparing the second redistribution layer 220, the second metal wiring 221 includes a metal seed diffusion barrier layer (not shown), and the metal seed diffusion barrier layer is in direct contact with the first silicon chip 410, so that heat dissipation of the first silicon chip 410 can be achieved through the metal wiring in direct contact with the first silicon chip 410, and the presence of the metal seed diffusion barrier layer can prevent diffusion of, for example, Cu metal wiring in the first silicon chip 410.
[0101] The material of the metal seed diffusion barrier layer can include, for example, one or a combination of Ni metal, Au metal, Sn metal, Ag metal, and Ti metal. No excessive restrictions are imposed here on the specific type.
[0102] Next, refer to Figure 3 and Figure 12 , perform step S9 to form a heat dissipation metal block 700 on the second redistribution layer 220, and the vertical projection of the heat dissipation metal block 700 is located on the first silicon chip 410.
[0103] Specifically, preferably the vertical projection of the heat dissipation metal block 700 covers the heat source area of the first silicon chip 410. The method of forming the heat dissipation metal block 700 can include, for example, electroplating or thermal conductive bonding. The heat dissipation metal block 700 can include, for example, a Cu metal block, a Ni metal block, or an Au metal block, etc. No restrictions are imposed here on the preparation method, material, morphology, etc. of the heat dissipation metal block 700.
[0104] Next, refer to Figure 3 and Figure 12, perform step S10, provide the second chip 420, bond the second chip 420 to the second redistribution layer 220 in a flip-chip manner, the second chip 420 is electrically connected to the second redistribution layer 220, and the heat dissipation metal block 700 is located below the second chip 420.
[0105] Specifically, the second chip 420 may include a DDR chip made of silicon, and the type of the second chip 420 is not overly restricted here.
[0106] Among them, the front surface of the second chip 420 has second metal bumps 820, such as solder ball bumps, copper pillar bumps, etc. After bonding the second chip 420 in a flip-chip manner, one end of the second metal bump 820 is electrically connected to the pad (not shown) of the second chip 420, and the other end of the second metal bump 820 is electrically connected to the second redistribution layer 220, and the back surface of the second chip 420 is away from the second redistribution layer 220.
[0107] After bonding the second chip 420, the gap between the second chip 420 and the second redistribution layer 220 may have a second underfill layer 520 formed by means such as dispensing, so as to apply the second underfill layer 520 as a protective layer for the second chip 420 and the second redistribution layer 220. The material of the second underfill layer 520 is not overly restricted here.
[0108] Next, refer to Figure 3 and Figure 12 , perform step S11, form a second encapsulation layer 620, and the second encapsulation layer 620 covers the second redistribution layer 220, the heat dissipation metal block 700 and the second chip 420.
[0109] Specifically, the method for forming the second encapsulation layer 620 may include but is not limited to compression molding, transfer molding and spin coating, and the material of the second encapsulation layer 620 may include but is not limited to epoxy resin and polyamide. The material and preparation method of the second encapsulation layer 620 are not overly restricted here.
[0110] Next, refer to Figure 3 and Figure 13 , perform step S12, remove the support substrate 100 to expose the first redistribution layer 210, and perform step S13, form metal bumps on the first redistribution layer 210.
[0111] Specifically, the metal bump is the third metal bump 830, and the third metal bump 830 is electrically connected to the first redistribution layer 210. Among them, the third metal bump 830 may include, for example, solder ball bumps, copper pillar bumps, etc., and the specific types and materials of the third metal bump 830 are not overly restricted here.
[0112] Further, when the semiconductor package structure is wafer-level fabricated, such as 6 inches, 8 inches, 12 inches, etc., after performing step 14 to form the metal bumps, a cutting step, such as mechanical cutting, laser cutting, etc., can also be carried out to fabricate a single semiconductor package structure.
[0113] In summary, for the method of fabricating the semiconductor package structure that avoids Cu diffusion of the present invention, the encapsulation layer located on the Cu metal pillar is retained when grinding and thinning the first silicon chip, and only the composite interface of the encapsulation layer / silicon chip is ground. Then, the Cu metal pillar is exposed by patterning the encapsulation layer for electrical connection. Therefore, Cu metal residue on the first silicon chip can be avoided during thinning, thereby avoiding simultaneous grinding of Cu / Si and preventing Cu metal diffusion pollution.
[0114] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A method for preparing a semiconductor package structure to avoid Cu diffusion, characterized in that, It includes the following steps: Provide a support substrate; Form a first redistribution layer on the support substrate; Form Cu metal pillars on the first redistribution layer, and the Cu metal pillars are electrically connected to the first redistribution layer; Provide a first silicon chip, and bond the first silicon chip to the first redistribution layer in a flip-chip manner, and the first silicon chip is electrically connected to the first redistribution layer; Form a first encapsulation layer, and the first encapsulation layer covers the first redistribution layer, the Cu metal pillars and the first silicon chip; Perform grinding to thin the first silicon chip. After grinding, the first encapsulation layer exposes the first silicon chip and covers the Cu metal pillars; Pattern the first encapsulation layer to form a groove exposing the Cu metal pillars in the first encapsulation layer; Form a second redistribution layer on the first encapsulation layer, and the second redistribution layer is electrically connected to the Cu metal pillars; Form a heat dissipation metal block on the second redistribution layer, and the vertical projection of the heat dissipation metal block is located on the first silicon chip; Provide a second chip, and bond the second chip to the second redistribution layer in a flip-chip manner. The second chip is electrically connected to the second redistribution layer, and the heat dissipation metal block is located below the second chip; Form a second encapsulation layer, and the second encapsulation layer covers the second redistribution layer, the heat dissipation metal block and the second chip; Remove the support substrate to expose the first redistribution layer; Form metal bumps on the first redistribution layer, and the metal bumps are electrically connected to the first redistribution layer.
2. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1, characterized in that: The method of patterning the first encapsulation layer to form the groove includes a laser drilling method, an etching method or a mechanical drilling method.
3. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1, characterized in that: The method of forming the Cu metal pillars includes an electroplating method.
4. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1, characterized in that: The thickness of the first encapsulation layer on the Cu metal pillars before grinding is greater than 15 μm.
5. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1, characterized in that: The method of forming the heat dissipation metal block includes an electroplating method or a thermal conductive bonding method.
6. The method for manufacturing a semiconductor package structure for preventing Cu diffusion according to claim 1, wherein: The heat dissipation metal block includes a Cu metal block, a Ni metal block or an Au metal block.
7. The method for manufacturing a semiconductor package structure for avoiding Cu diffusion according to claim 1, characterized in that: The metal wiring in the second redistribution layer includes a metal seed diffusion barrier layer, and the metal seed diffusion barrier layer is in direct contact with the first silicon chip.
8. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 7, characterized in that: The material of the metal seed diffusion barrier layer includes one or a combination of Ni metal, Au metal, Sn metal, Ag metal and Ti metal.
9. The method for manufacturing a semiconductor package structure for preventing Cu diffusion according to claim 1, wherein: The vertical projection of the heat dissipation metal block covers the heat source area of the first silicon chip.
10. The method for manufacturing a semiconductor package structure for preventing Cu diffusion according to claim 1, wherein: The semiconductor package structure is a wafer-level semiconductor package structure. After forming the metal bumps, it further includes a step of dicing.