Preparation method of semiconductor packaging structure capable of avoiding Cu diffusion
By thinning and forming a thermally conductive layer on the back of the silicon wafer, avoiding diffusion of Cu metal and forming grooves in the packaging layer to improve heat dissipation performance, Cu pollution and heat dissipation problems are solved, and an efficient semiconductor packaging structure is achieved.
Patent Information
- Application Number
- CN202311863918.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-29
- Publication Date
- 2025-07-01
AI Technical Summary
In the prior art, Cu contamination caused by Cu metal diffusion, which damages the chip function. Especially when Cu metal remains on the back of the silicon chip, Cu metal is very easy to diffuse in the silicon material, causing chip function failure.
By thinning on the back of the silicon wafer and forming a back gold thermal conductive layer, the direct grinding of Cu metal columns and the silicon chip is avoided, and the possibility of Cu diffusion is reduced. At the same time, grooves are formed in the packaging layer to make the dielectric layer or heat conducting member come into contact with the silicon chip, thereby improving the heat dissipation performance.
It effectively avoids diffusion pollution of Cu metal, improves the heat dissipation performance of semiconductor packaging structures, and reduces process steps and costs.
Smart Images
Figure CN120237015A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor manufacturing, and relates to a method for preparing a semiconductor packaging structure that avoids Cu diffusion. Background Art
[0002] The rapid development of electronic products is the main driving force for the evolution of current packaging technologies. Miniaturization, high density, high frequency, high speed, high reliability, and low cost are the mainstream development directions of advanced packaging.
[0003] Existing consumer electronic product packages generally adopt Package on Package (POP) stacked packaging. With the increasing integration of electronic product functions, the packaging structure becomes highly concentrated, and the heat generated during the operation of the chip will cause irreversible damage to the chip itself. Therefore, it is necessary to consider the heat dissipation problem of the packaging structure, and thus the heat dissipation requirements for product packaging are getting higher and higher.
[0004] Such as Figure 1 and Figure 2 , in the traditional packaging structure, generally, a grinding method is adopted to thin and expose the back surface of the underlying silicon chip 10 to increase heat dissipation. And during the grinding process, in order to facilitate subsequent electrical connection, the copper (Cu) metal pillars 20 around the silicon (Si) chip 10 will be ground simultaneously to expose the surface of the Cu metal pillars 20 for subsequent electrical connection, that is, during grinding, the composite interface of the Cu metal pillars 20 / silicon chip 10 / package layer 30 will be ground synchronously, and then the upper chip will be stacked and packaged. However, during the grinding process of the composite interface of the Cu metal pillars 20 / silicon chip 10 / package layer 30, Cu metal 40 will remain on the back surface of the silicon chip 10. Since Cu metal has a large diffusion coefficient, especially Cu metal is extremely easy to diffuse in the silicon material, the remaining Cu metal 40 will quickly diffuse into the underlying silicon chip 10, causing Cu contamination and resulting in the functional failure of the chips sensitive to Cu, such as problems like reduced breakdown voltage and leakage.
[0005] Therefore, it is necessary to provide a method for preparing a semiconductor packaging structure that avoids Cu diffusion. Summary of the Invention
[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for preparing a semiconductor packaging structure that avoids Cu diffusion, so as to solve the problem of Cu contamination caused by Cu metal diffusion in the prior art.
[0007] To achieve the above purpose and other related purposes, the present invention provides a method for preparing a semiconductor packaging structure that avoids Cu diffusion, including the following steps:
[0008] Provide a first support substrate and a silicon wafer, and bond the silicon wafer to the first support substrate;
[0009] Thin the silicon wafer from the back side of the silicon wafer;
[0010] Remove the first support substrate, cut the silicon wafer, and form a first silicon chip;
[0011] Provide a second support substrate;
[0012] Form a first redistribution layer on the second support substrate;
[0013] Form Cu metal pillars on the first redistribution layer, and the first ends of the Cu metal pillars are electrically connected to the first redistribution layer;
[0014] Bond the first silicon chip to the first redistribution layer in a flip-chip manner, and the first silicon chip is electrically connected to the first redistribution layer;
[0015] Form a first encapsulation layer, the first encapsulation layer covers the first redistribution layer, the Cu metal pillars and the first silicon chip, and exposes the second ends of the Cu metal pillars;
[0016] Pattern the first encapsulation layer, and form a groove in the first encapsulation layer, the groove exposes the first silicon chip;
[0017] Form a second redistribution layer on the first encapsulation layer, and the second redistribution layer is electrically connected to the second ends of the Cu metal pillars;
[0018] Provide a second chip, bond the second chip to the second redistribution layer in a flip-chip manner, and the second chip is electrically connected to the second redistribution layer;
[0019] Form a second encapsulation layer, the second encapsulation layer covers the second redistribution layer and the second chip;
[0020] Remove the second support substrate, and expose the first redistribution layer;
[0021] Form metal bumps on the first redistribution layer, and the metal bumps are electrically connected to the first redistribution layer.
[0022] Optionally, after forming the second redistribution layer, form the groove exposing the first silicon chip by patterning the second redistribution layer and the first encapsulation layer.
[0023] Optionally, the method for forming the groove includes a UV laser method.
[0024] Optionally, between thinning the silicon wafer and cutting the silicon wafer, there is further a step of forming a back gold heat conducting layer on the back surface of the silicon wafer.
[0025] Optionally, a heat conducting member is further formed in the groove.
[0026] Optionally, the method for exposing the Cu metal posts by the first encapsulation layer includes a grinding method.
[0027] Optionally, the thickness of the first encapsulation layer located on the first silicon chip is greater than 10 μm.
[0028] Optionally, there is further a step of forming a heat dissipating metal block on the second redistribution layer, and the vertical projection of the heat dissipating metal block is located on the first silicon chip.
[0029] Optionally, the vertical projection of the heat dissipating metal block covers the heat source area of the first silicon chip.
[0030] Optionally, the semiconductor package structure is a wafer-level semiconductor package structure. After forming the metal bumps, there is further a step of cutting.
[0031] As described above, in the method for manufacturing the semiconductor package structure for avoiding Cu diffusion of the present invention, before mounting, the silicon wafer is first thinned to a target thickness, such that the first encapsulation layer covers the silicon chip and exposes the Cu metal posts, and then a groove is opened on the back surface of the silicon chip, such that the dielectric layer or the formed heat conducting member is in contact with the silicon chip to improve the heat dissipation performance, and Cu / Si grinding can be avoided, and Cu metal diffusion pollution can be avoided. Thus, while avoiding Cu metal pollution, the semiconductor package structure can achieve good heat dissipation, reduce process steps, and lower costs. Description of the Drawings
[0032] Figure 1 It shows a schematic structural diagram of the prior art after forming the encapsulation layer.
[0033] Figure 2 It shows a schematic structural diagram of the prior art after grinding.
[0034] Figure 3 It shows a schematic process flow diagram for manufacturing the semiconductor package structure in an embodiment of the present invention.
[0035] Figures 4 to 18 It shows a schematic structural diagram presented in each step when manufacturing the semiconductor package structure in an embodiment of the present invention.
[0036] Description of the Reference Numerals
[0037] 10 Silicon chip
[0038] 20 Cu metal post
[0039] 30 Encapsulation layer
[0040] 40 Residual Cu metal
[0041] 110 First support substrate
[0042] 111 First separation layer
[0043] 120 Second support substrate
[0044] 121 Second separation layer
[0045] 210 First redistribution layer
[0046] 211 First metal wiring
[0047] 212 First dielectric layer
[0048] 220 Second redistribution layer
[0049] 221 Second metal wiring
[0050] 222 Second dielectric layer
[0051] 300 Cu metal pillar
[0052] 400 Silicon wafer
[0053] 410 First silicon chip
[0054] 411 Back gold heat conduction layer
[0055] 420 Second chip
[0056] 510 First underfill layer
[0057] 520 Second underfill layer
[0058] 610 First encapsulation layer
[0059] 611 Groove
[0060] 620 Second encapsulation layer
[0061] 700 Heat dissipation metal block
[0062] 810 First metal bump
[0063] 820 Second metal bump
[0064] 830 Third metal bump
[0065] 900 Adhesive layer Detailed implementation manners
[0066] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0067] When detailing the embodiments of the present invention, for the convenience of description, the cross-sectional views showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.
[0068] For the convenience of description, spatial relationship terms such as "beneath", "below", "lower than", "under", "above", "on" etc. may be used here to describe the relationship between an element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation besides the directions depicted in the drawings. Embodiments may include those where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features such that the first and second features may not be in direct contact. Additionally, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.
[0069] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation may be arbitrarily changed, and the component layout type may also be more complex.
[0070] As Figure 3 , this embodiment provides a method for preparing a semiconductor package structure for avoiding Cu diffusion, including the following steps:
[0071] S1: Provide a first support substrate and a silicon wafer, and bond the silicon wafer to the first support substrate;
[0072] S2: Thin the silicon wafer from the back side of the silicon wafer;
[0073] S3: Remove the first support substrate, cut the silicon wafer, and form a first silicon chip;
[0074] S4: Provide a second support substrate;
[0075] S5: Form a first redistribution layer on the second support substrate;
[0076] S6: Form Cu metal pillars on the first redistribution layer, with the first end of the Cu metal pillars electrically connected to the first redistribution layer;
[0077] S7: Bond the first silicon chip to the first redistribution layer in a flip-chip manner, with the first silicon chip electrically connected to the first redistribution layer;
[0078] S8: Form a first encapsulation layer, which encapsulates the first redistribution layer, the Cu metal pillars, and the first silicon chip, and exposes the second end of the Cu metal pillars;
[0079] S9: Pattern the first encapsulation layer to form a groove in the first encapsulation layer, with the groove exposing the first silicon chip;
[0080] S10: Form a second redistribution layer on the first encapsulation layer, with the second redistribution layer electrically connected to the second end of the Cu metal pillars;
[0081] S11: Provide a second chip, bond the second chip to the second redistribution layer in a flip-chip manner, with the second chip electrically connected to the second redistribution layer;
[0082] S12: Form a second encapsulation layer, which encapsulates the second redistribution layer and the second chip;
[0083] S13: Remove the second support substrate to expose the first redistribution layer;
[0084] S14: Form metal bumps on the first redistribution layer, with the metal bumps electrically connected to the first redistribution layer.
[0085] The following is combined with the attached Figures 4 to 18 , and a further introduction to the preparation of the semiconductor package structure is given.
[0086] First, refer to Figure 3 and Figure 4 , and perform step S1 to provide a first support substrate 110 and a silicon wafer 400, and bond the silicon wafer 400 to the first support substrate 110.
[0087] Specifically, the size of the silicon wafer 400 may include, for example, 6 inches, 8 inches, 12 inches, etc. The silicon wafer 400 is composed of a plurality of independent first silicon chips 410, and the first silicon chips 410 may include SoC chips, but are not limited thereto.
[0088] Among them, the front surface of the first silicon chip 410 has first metal bumps 810, such as solder ball bumps, copper pillar bumps, etc. One end of the first metal bump 810 is electrically connected to a pad (not shown) of the first silicon chip 410, and the other end of the first metal bump 810 can be electrically connected to a subsequent first redistribution layer 210 for electrical connection.
[0089] Such as Figure 5 , the silicon wafer 400 can be bonded to the first support substrate 110 through an adhesive layer 900. The first support substrate 110 can include, for example, a glass substrate, a metal substrate, a semiconductor substrate, etc., to provide support for the silicon wafer 400 through the first support substrate 110, so as to facilitate the thinning of the silicon wafer 400.
[0090] Among them, to facilitate the subsequent removal of the first support substrate 110, in this embodiment, it is preferably that a first separation layer 111 is formed on the surface of the first support substrate 110. The first separation layer 111 includes but is not limited to a tape and a polymer layer. For example, the first separation layer 111 can be selected as a photothermal conversion layer formed by a photothermal conversion (LTHC) coating material, so that subsequent light / radiation (such as laser) can be used to decompose the LTHC coating material under heat to release the first support substrate 110, improving the convenience of the separation operation.
[0091] Next, refer to Figure 3 And Figure 6 , perform step S2 to thin the silicon wafer 400 from the back surface of the silicon wafer 400.
[0092] Such as Figure 6 , when thinning the silicon wafer 400, chemical mechanical polishing (CMP) etc. can be used to make the silicon wafer 400 reach the target thickness and reduce the package size. The thickness of the thinned silicon wafer 400 is not overly limited here.
[0093] Next, refer to Figure 3 And Figure 7 , remove the first support substrate 110, cut the silicon wafer 400 to form the first silicon chip 410.
[0094] Specifically, the cutting step can adopt mechanical cutting, laser cutting, etc. to prepare the single-body first silicon chip 410. Among them, after removing the first support substrate 110 and the first separation layer 111, the back surface of the silicon wafer 400 can be bonded to a support film such as a blue film, and then cut to prepare the first silicon chip 410.
[0095] Next, refer to Figure 3 And Figure 8, perform step S4 to provide a second support substrate 120.
[0096] Specifically, the second support substrate 120 may include, such as, a glass substrate, a metal substrate, a semiconductor substrate, etc., to provide support for subsequent processes through the second support substrate 120. The size of the second support substrate 120 is not limited herein, and preferably it is wafer-level.
[0097] Among them, for the convenience of removing the second support substrate 120 subsequently, in this embodiment, preferably, a second separation layer 121 is formed on the surface of the second support substrate 120. The second separation layer 121 includes but is not limited to a tape and a polymer layer. For example, the second separation layer 121 can be selected as a photothermal conversion layer formed by a photothermal conversion (LTHC) coating material, so that subsequently, such as light / radiation (such as laser) can be used to decompose the LTHC coating material under heat to release the second support substrate 120, improving the convenience of the separation operation.
[0098] Next, refer to Figure 3 and Figure 9 , perform step S5 to form a first redistribution layer 210 on the second support substrate 120.
[0099] Specifically, the first redistribution layer 210 includes a first metal wiring 211 and a first dielectric layer 212. The first dielectric layer 212 can be formed by a polymer such as polybenzoxazole (PBO), polyimide, etc., or formed by an inorganic dielectric material such as silicon nitride, silicon oxide, etc.; the first metal wiring 211 can include, such as, copper, tungsten, or their alloys, etc. The specific structure and material selection of the first redistribution layer 210 are not overly restricted herein.
[0100] Next, refer to Figure 3 and Figure 10 , perform step S6 to form a Cu metal pillar 300 on the first redistribution layer 210. The first end of the Cu metal pillar 300 is electrically connected to the first redistribution layer 210.
[0101] Specifically, the Cu metal pillar 300 can be formed by means of photolithography, etching, electroplating, but is not limited thereto.
[0102] Next, refer to Figure 3 and Figure 11 , perform step S7 to bond the first silicon chip 410 to the first redistribution layer 210 in a flip-chip manner. The first silicon chip 410 is electrically connected to the first redistribution layer 210.
[0103] Specifically, after the first silicon chip 410 is bonded in a flip-chip manner, one end of the first metal bump 810 is electrically connected to a pad (not shown) of the first silicon chip 410, and the other end of the first metal bump 810 is electrically connected to the first redistribution layer 210. The back surface of the first silicon chip 410 is away from the first redistribution layer 210.
[0104] Among them, after the first silicon chip 410 is bonded, a first underfill layer 510 formed by means such as dispensing may be provided between the first silicon chip 410 and the first redistribution layer 210, so that the first underfill layer 510 can be used as a protective layer for the first silicon chip 410 and the first redistribution layer 210. The material of the first underfill layer 510 is not overly restricted here.
[0105] Next, referring to Figure 3 、 Figure 12 and Figure 13 perform step S8 to form a first encapsulation layer 610. The first encapsulation layer 610 covers the first redistribution layer 210, the Cu metal pillar 300, and the first silicon chip 410, and exposes the second end of the Cu metal pillar 300.
[0106] Specifically, the method for forming the first encapsulation layer 610 may include but is not limited to compression molding, transfer molding, and spin coating. The material of the first encapsulation layer 610 may include but is not limited to epoxy resin and polyamide. The material and preparation method of the first encapsulation layer 610 are not overly restricted here.
[0107] Among them, the grinding method may include chemical mechanical polishing (CMP) etc. to remove part of the first encapsulation layer 610 and expose the Cu metal pillar 300, so that the exposed Cu metal pillar 300 is convenient for subsequent electrical connection.
[0108] Among them, when grinding, since the first encapsulation layer 610 covers the first silicon chip 410, it can block the diffusion of Cu metal onto the first silicon chip 410 to avoid affecting the electrical performance of the first silicon chip 410.
[0109] To avoid the exposure of the first silicon chip 410 during grinding, the thickness of the thermally conductive grinding protective layer should be at least greater than the grinding tolerance. For example, the thickness of the first encapsulation layer 610 on the first silicon chip 410 can be 10μm - 30μm, specifically 10μm, 15μm, 20μm, 25μm, 30μm, etc.
[0110] Next, referring to Figure 3 and Figure 14, perform step S9 to pattern the first encapsulation layer 610, and form a groove 611 in the first encapsulation layer 610, where the groove 611 exposes the first silicon chip 410.
[0111] Specifically, the first encapsulation layer 610 can be patterned by using a UV laser method or the like, so as to facilitate the heat dissipation of the first silicon chip 410 through a dielectric layer, a metal layer, etc. formed in the groove 611 subsequently. The specific morphology and size of the groove 611 are not overly restricted here. Preferably, the projection of the groove 611 along the vertical direction covers the heat source area of the first silicon chip 410.
[0112] Next, refer to Figure 3 and Figure 15 , perform step S10 to form a second redistribution layer 220 on the first encapsulation layer 610, and the second redistribution layer 220 is electrically connected to the second end of the Cu metal pillar 300.
[0113] Specifically, the second redistribution layer 220 includes a second metal wiring 221 and a second dielectric layer 222. The second dielectric layer 222 can be formed of a polymer such as polybenzoxazole (PBO), polyimide, etc., or formed of an inorganic dielectric material such as silicon nitride, silicon oxide, etc.; the second metal wiring 221 can include copper, tungsten, or their alloys, etc. The specific structure and material selection of the second redistribution layer 220 are not overly restricted here.
[0114] Among them, the second dielectric layer 222 can fill the groove 611 to achieve heat dissipation of the first silicon chip 410.
[0115] Furthermore, a heat conducting member (not shown) in contact with the first silicon chip 410, such as an indium sheet, graphene, a copper sheet, etc., can also be formed in the groove 611 to achieve heat dissipation of the first silicon chip 410. Among them, when a copper sheet is used, the copper sheet and the first silicon chip 410 need to be isolated by a material with a low diffusion coefficient and good thermal conductivity.
[0116] Next, refer to Figure 3 and Figure 16 , perform step S11 to provide a second chip 420, and bond the second chip 420 to the second redistribution layer 220 in a flip-chip manner, and the second chip 420 is electrically connected to the second redistribution layer 220.
[0117] Specifically, the second chip 420 can include a DDR chip made of silicon material. The type of the second chip 420 is not overly restricted here.
[0118] Among them, the front surface of the second chip 420 has second metal bumps 820, such as solder ball bumps, copper pillar bumps, etc. After bonding the second chip 420 in a flip-chip manner, one end of the second metal bump 820 is electrically connected to the pad (not shown) of the second chip 420, and the other end of the second metal bump 820 is electrically connected to the second redistribution layer 220. The back surface of the second chip 420 is away from the second redistribution layer 220.
[0119] After bonding the second chip 420, the gap between the second chip 420 and the second redistribution layer 220 may have a second underfill layer 520 formed by means such as dispensing, etc., so as to apply the second underfill layer 520 as a protective layer for the second chip 420 and the second redistribution layer 220. The material of the second underfill layer 520 is not overly restricted here.
[0120] Furthermore, after step S10 and before step S11, a step of forming a heat dissipation metal block 700 may further be included, such as forming a Cu metal block, Ni metal block, Au metal block, etc., to improve the heat dissipation effect.
[0121] Next, refer to Figure 3 and Figure 16 , and perform step S12 to form a second encapsulation layer 620, and the second encapsulation layer 620 covers the second redistribution layer 220 and the second chip 420.
[0122] Specifically, the method of forming the second encapsulation layer 620 may include but is not limited to compression molding, transfer molding, and spin coating. The material of the second encapsulation layer 620 may include but is not limited to epoxy resin and polyamide. The material and preparation method of the second encapsulation layer 620 are not overly restricted here.
[0123] Next, refer to Figure 3 and Figure 17 , and perform step S13 to remove the second support substrate 120, expose the first redistribution layer 210, and perform step S14 to form metal bumps on the first redistribution layer 210.
[0124] Specifically, the metal bumps are third metal bumps 830, and the third metal bumps 830 are electrically connected to the first redistribution layer 210. Among them, the third metal bumps 830 may include, for example, solder ball bumps, copper pillar bumps, etc. The specific type and material of the third metal bumps 830 are not overly restricted here.
[0125] Further, when the semiconductor package structure is prepared at the wafer level, such as 6-inch, 8-inch, 12-inch, etc., after performing step 14 to form the metal bumps, a cutting step, such as mechanical cutting, laser cutting, etc., can be further performed to prepare a single semiconductor package structure.
[0126] Referring to Figure 18 , in another embodiment, after step S2, a step of forming a back gold thermal conductive layer 411 on the back surface of the silicon wafer 400 may further be included to protect the first silicon chip 410 through the back gold thermal conductive layer 411 and avoid damage to the first silicon chip 410 when the groove 611 is opened.
[0127] Among them, the material of the back gold thermal conductive layer 411 may be composed of one or a combination of Ni metal, Au metal, Sn metal, Ag metal, Ti metal, and V metal, including a single layer or a stacked layer, or a composite back gold thermal conductive layer is formed by combining a metal layer composed of the above materials with an Al metal layer or a Cu metal layer, etc., so as to avoid Cu metal diffusion and avoid damage to the first silicon chip 410 at the same time.
[0128] In another embodiment, the first encapsulation layer 410 may not be patterned first, but the second redistribution layer 220 may be formed first, and then the groove 611 that penetrates the second redistribution layer 220 and the first encapsulation layer 610 and exposes the first silicon chip 410 is formed, so as to avoid the pollution caused to the preparation of the second redistribution layer 220 when the groove 611 is opened in the first encapsulation layer 410, thereby improving the electrical performance. Similarly, the back surface of the first silicon chip 410 may have the back gold thermal conductive layer 411, and / or after the groove 611 is formed, a heat conductive member may be formed in the groove 611, and / or a heat dissipation metal block 700 may be formed on the second redistribution layer 220, which will not be elaborated here.
[0129] In summary, the preparation method of the semiconductor package structure for avoiding Cu diffusion according to the present invention enables the first encapsulation layer to cover the silicon chip and expose the Cu metal pillars, and then a groove is opened on the back surface of the silicon chip, so that the dielectric layer or the formed heat conductive member is in contact with the silicon chip to improve the heat dissipation performance, and Cu / Si simultaneous grinding can be avoided, and Cu metal diffusion pollution can be avoided. Thus, while avoiding Cu metal pollution, the semiconductor package structure can achieve good heat dissipation, reduce process steps, and lower costs.
[0130] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A method for preparing a semiconductor package structure for avoiding Cu diffusion, characterized in that Including the following steps: Providing a first support substrate and a silicon wafer, and bonding the silicon wafer to the first support substrate; Thinning the silicon wafer from the back surface of the silicon wafer; Removing the first support substrate, cutting the silicon wafer to form a first silicon chip; Providing a second support substrate; Forming a first redistribution layer on the second support substrate; Forming Cu metal pillars on the first redistribution layer, with the first end of the Cu metal pillars electrically connected to the first redistribution layer; Bonding the first silicon chip to the first redistribution layer in a flip-chip manner, with the first silicon chip electrically connected to the first redistribution layer; Forming a first encapsulation layer, the first encapsulation layer covering the first redistribution layer, the Cu metal pillars and the first silicon chip, and exposing the second end of the Cu metal pillars; Patterning the first encapsulation layer to form a groove in the first encapsulation layer, the groove exposing the first silicon chip; Forming a second redistribution layer on the first encapsulation layer, the second redistribution layer electrically connected to the second end of the Cu metal pillars; Providing a second chip, bonding the second chip to the second redistribution layer in a flip-chip manner, with the second chip electrically connected to the second redistribution layer; Forming a second encapsulation layer, the second encapsulation layer covering the second redistribution layer and the second chip; Removing the second support substrate to expose the first redistribution layer; Forming metal bumps on the first redistribution layer, the metal bumps electrically connected to the first redistribution layer.
2. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1, wherein: After forming the second redistribution layer, the groove exposing the first silicon chip is formed by patterning the second redistribution layer and the first encapsulation layer.
3. The method for manufacturing a semiconductor package structure for preventing Cu diffusion according to claim 1 or 2, characterized in that: The method for forming the groove includes a UV laser method.
4. The method for manufacturing a semiconductor package structure for preventing Cu diffusion according to claim 1 or 2, characterized in that: Between thinning the silicon wafer and cutting the silicon wafer, there is also a step of forming a backside gold thermal conductive layer on the back surface of the silicon wafer.
5. The method for manufacturing a semiconductor package structure for preventing Cu diffusion according to claim 1 or 2, characterized in that: A heat conductive member is also formed in the groove.
6. The method for preparing a semiconductor package structure for avoiding Cu diffusion according to claim 1 or 2, characterized in that: The method for the first encapsulation layer to expose the Cu metal pillars includes a grinding method.
7. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 6, characterized in that: The thickness of the first encapsulation layer located on the first silicon chip is greater than 10 μm.
8. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1 or 2, characterized in that: There is also a step of forming a heat dissipation metal block on the second redistribution layer, and the vertical projection of the heat dissipation metal block is located on the first silicon chip.
9. The method for manufacturing a semiconductor package structure for avoiding Cu diffusion according to claim 8, wherein: The vertical projection of the heat dissipation metal block covers the heat source area of the first silicon chip.
10. The method for manufacturing a semiconductor package structure for preventing Cu diffusion according to claim 1 or 2, characterized in that: The semiconductor package structure is a wafer-level semiconductor package structure. After forming the metal bumps, there is also a step of cutting.