Preparation method of semiconductor packaging structure capable of avoiding Cu diffusion
By forming a thermally conductive grinding protective layer on the back of the silicon wafer, the diffusion problem of Cu metal during the silicon chip grinding process is solved, and the effect of avoiding Cu pollution and good heat dissipation is achieved, simplifying the process steps and reducing costs.
Patent Information
- Application Number
- CN202311864441.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-29
- Publication Date
- 2025-07-01
AI Technical Summary
In the prior art, Cu metal diffuses during the grinding of silicon chips, causing pollution, affecting chip functions, and leading to problems such as reduced breakdown voltage and leakage.
A thermally conductive grinding protective layer is formed on the back of the silicon wafer, including a metal diffusion barrier layer and a heat-dissipating metal layer. It is prepared by chemical or electroplating method to avoid Cu/Si simultaneous grinding to form a composite silicon wafer. The Cu metal column is exposed and heat dissipated in the subsequent process.
Effectively avoid Cu metal diffusion pollution, achieve good heat dissipation, reduce process steps, and reduce costs.
Smart Images
Figure CN120237016A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor manufacturing, and relates to a preparation method of a semiconductor package structure for avoiding Cu diffusion. Background Art
[0002] The rapid development of electronic products is the main driving force for the evolution of current packaging technologies. Miniaturization, high density, high frequency, high speed, high reliability, and low cost are the mainstream development directions of advanced packaging.
[0003] Existing consumer electronic product packages generally adopt Package on Package (POP) stacked packaging. With the increase in the functional integration of electronic products, the packaging structure becomes highly concentrated, and the heat generated during the operation of the chip will cause irreversible damage to the chip itself. Therefore, the heat dissipation problem of the packaging structure needs to be considered, and the heat dissipation requirements for product packaging are getting higher and higher.
[0004] Such as Figure 1 and Figure 2 , in the traditional packaging structure, generally, the grinding method is used to thin and expose the back surface of the underlying silicon chip 10 to increase heat dissipation. And during the grinding process, in order to facilitate subsequent electrical connection, the copper (Cu) metal pillars 20 around the silicon (Si) chip 10 will be ground simultaneously to expose the surface of the Cu metal pillars 20 for subsequent electrical connection, that is, during grinding, the composite interface of the Cu metal pillars 20 / silicon chip 10 / package layer 30 will be ground synchronously, and then the upper chip will be stacked and packaged. However, during the grinding process of the composite interface of the Cu metal pillars 20 / silicon chip 10 / package layer 30, Cu metal 40 will remain on the back surface of the silicon chip 10. Since Cu metal has a large diffusion coefficient, especially Cu metal is extremely easy to diffuse in the silicon material, the remaining Cu metal 40 will quickly diffuse into the underlying silicon chip 10, causing Cu pollution and resulting in the functional failure of Cu-sensitive chips, such as problems like reduced breakdown voltage and leakage.
[0005] Therefore, it is necessary to provide a preparation method of a semiconductor package structure for avoiding Cu diffusion. Summary of the Invention
[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a preparation method of a semiconductor package structure for avoiding Cu diffusion, which is used to solve the problem of Cu pollution caused by Cu metal diffusion in the prior art.
[0007] To achieve the above object and other related objects, the present invention provides a preparation method of a semiconductor package structure for avoiding Cu diffusion, including the following steps:
[0008] Provide a first support substrate and a silicon wafer, and bond the silicon wafer to the first support substrate;
[0009] Thin the silicon wafer from the back side of the silicon wafer, and form a thermally conductive grinding protective layer on the back side of the silicon wafer to form a composite silicon wafer;
[0010] Remove the first support substrate, and cut the composite silicon wafer to form a first composite silicon chip;
[0011] Provide a second support substrate;
[0012] Form a first redistribution layer on the second support substrate;
[0013] Form Cu metal pillars on the first redistribution layer, and the Cu metal pillars are electrically connected to the first redistribution layer;
[0014] Bond the first composite silicon chip to the first redistribution layer in a flip-chip manner, and the first composite silicon chip is electrically connected to the first redistribution layer;
[0015] Form a first encapsulation layer, and the first encapsulation layer covers the first redistribution layer, the Cu metal pillars and the first composite silicon chip;
[0016] Perform grinding to expose the thermally conductive grinding protective layer and the Cu metal pillars;
[0017] Form a second redistribution layer on the first encapsulation layer, and the second redistribution layer is electrically connected to the Cu metal pillars;
[0018] Provide a second chip, bond the second chip to the second redistribution layer in a flip-chip manner, and the second chip is electrically connected to the second redistribution layer;
[0019] Form a second encapsulation layer, and the second encapsulation layer covers the second redistribution layer and the second chip;
[0020] Remove the second support substrate to expose the first redistribution layer;
[0021] Form metal bumps on the first redistribution layer, and the metal bumps are electrically connected to the first redistribution layer.
[0022] Optionally, the thermally conductive grinding protective layer includes a metal diffusion barrier layer and a heat dissipation metal layer that are stacked from bottom to top and are in contact with the silicon wafer, and the diffusion coefficient of the metal diffusion barrier layer is less than that of the Cu metal pillars.
[0023] Optionally, the material of the metal diffusion barrier layer includes one or a combination of Ni metal, Au metal, Sn metal, Ag metal, and Ti metal; the heat dissipation metal layer includes a Cu layer, a Ni layer, or an Au layer.
[0024] Optionally, the method for forming the metal diffusion barrier layer includes electroplating or electroless plating; the method for forming the heat dissipation metal layer includes electroplating or electroless plating.
[0025] Optionally, the heat dissipation metal layer and the second redistribution layer are isolated by a dielectric layer in the second redistribution layer.
[0026] Optionally, the thermally conductive grinding protection layer includes a thermally conductive organic DAF film in contact with the silicon wafer.
[0027] Optionally, the thermally conductive organic DAF film is in direct contact with the metal wiring layer in the second redistribution layer.
[0028] Optionally, the thickness of the thermally conductive grinding protection layer is greater than 15 μm.
[0029] Optionally, the vertical projection of the thermally conductive grinding protection layer covers the heat source area of the first composite silicon chip.
[0030] Optionally, the semiconductor package structure is a wafer-level semiconductor package structure, and after forming the metal bumps, it further includes a cutting step.
[0031] As described above, in the method for manufacturing a semiconductor package structure that avoids Cu diffusion according to the present invention, before mounting, the silicon wafer is first thinned to a target thickness, and then a thermally conductive grinding protection layer is fabricated. The thermally conductive grinding protection layer can avoid simultaneous grinding of Cu / Si, prevent Cu metal diffusion pollution, and the thermally conductive grinding protection layer with good thermal conductivity can also be used as a heat conductor, thereby achieving good heat dissipation while avoiding Cu metal contamination, reducing process steps, and lowering costs. Description of the Drawings
[0032] Figure 1 Shows a schematic structural diagram of the prior art after forming the encapsulation layer.
[0033] Figure 2 Shows a schematic structural diagram of the prior art after grinding.
[0034] Figure 3 Shows a schematic process flow diagram for manufacturing a semiconductor package structure according to an embodiment of the present invention.
[0035] Figures 4 to 17 Shows a schematic structural diagram of each step in the process of manufacturing a semiconductor package structure according to an embodiment of the present invention.
[0036] Description of Reference Numerals
[0037] 10 Silicon Chip
[0038] 20 Cu metal column
[0039] 30 Encapsulation layer
[0040] 40 Residual Cu metal
[0041] 110 first supporting substrate
[0042] 111 First separation layer
[0043] 120 second supporting substrate
[0044] 121 Second separation layer
[0045] 210 First rewiring layer
[0046] 211 First Metal Wiring
[0047] 212 first dielectric layer
[0048] 220 Second rewiring layer
[0049] 221 Second Metal Wiring
[0050] 222 second dielectric layer
[0051] 300 Cu Metal Pillar
[0052] 400 Silicon Wafer
[0053] 410 The first composite silicon chip
[0054] 411 First Silicon Chip
[0055] 412 Metal Diffusion Barrier
[0056] 413 heat dissipation metal layer
[0057] 420 Second Chip
[0058] 510 First bottom filling layer
[0059] 520 Second bottom filling layer
[0060] 610 First packaging layer
[0061] 620 Second packaging layer
[0062] 700 Adhesive Layer
[0063] 810 First metal bump
[0064] 820 Second metal bump
[0065] 830 Third metal bump Detailed implementation manners
[0066] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0067] When detailing the embodiments of the present invention, for the convenience of description, the cross-sectional views showing the device structure will be enlarged locally out of the general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.
[0068] For the convenience of description, spatial relationship terms such as "beneath", "below", "lower than", "under", "above", "on" etc. may be used here to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation besides the directions depicted in the drawings. Embodiments where the first and second features are formed in direct contact may be included, and embodiments where additional features are formed between the first and second features such that the first and second features may not be in direct contact may also be included. Additionally, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.
[0069] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0070] As Figure 3 , this embodiment provides a method for preparing a semiconductor packaging structure for avoiding Cu diffusion, including the following steps:
[0071] S1: Provide a first support substrate and a silicon wafer, and bond the silicon wafer to the first support substrate
[0072] S2: Thin the silicon wafer from the back surface of the silicon wafer, and form a thermally conductive grinding protective layer on the back surface of the silicon wafer to form a composite silicon wafer;
[0073] S3: Remove the first support substrate, and cut the composite silicon wafer to form a first composite silicon chip;
[0074] S4: Provide a second support substrate;
[0075] S5: Form a first redistribution layer on the second support substrate;
[0076] S6: Form Cu metal pillars on the first redistribution layer, and the Cu metal pillars are electrically connected to the first redistribution layer;
[0077] S7: Bond the first composite silicon chip to the first redistribution layer in a flip-chip manner, and the first composite silicon chip is electrically connected to the first redistribution layer;
[0078] S8: Form a first encapsulation layer, and the first encapsulation layer covers the first redistribution layer, the Cu metal pillars and the first composite silicon chip;
[0079] S9: Perform grinding to expose the thermal conductive grinding protection layer and the Cu metal pillars;
[0080] S10: Form a second redistribution layer on the first encapsulation layer, and the second redistribution layer is electrically connected to the Cu metal pillars;
[0081] S11: Provide a second chip, bond the second chip to the second redistribution layer in a flip-chip manner, and the second chip is electrically connected to the second redistribution layer;
[0082] S12: Form a second encapsulation layer, and the second encapsulation layer covers the second redistribution layer and the second chip;
[0083] S13: Remove the second support substrate to expose the first redistribution layer;
[0084] S14: Form metal bumps on the first redistribution layer, and the metal bumps are electrically connected to the first redistribution layer.
[0085] The following combines the description with the attached Figures 4 to 17 , and further introduces the preparation of the semiconductor encapsulation structure.
[0086] First, refer to Figure 3 and Figure 4 , execute step S1, provide a first support substrate 110 and a silicon wafer 400, and bond the silicon wafer 400 to the first support substrate 110.
[0087] Specifically, the size of the silicon wafer 400 may include, for example, 6 inches, 8 inches, 12 inches, etc. The silicon wafer 400 is composed of a plurality of independent first silicon chips 411. The first silicon chips 411 may include SoC chips, but are not limited thereto.
[0088] Among them, on the front surface of the first silicon chip 411, there are first metal bumps 810, such as solder ball bumps, copper pillar bumps, etc. One end of the first metal bump 810 is electrically connected to the pad (not shown) of the first silicon chip 411, and the other end of the first metal bump 810 can be electrically connected to the subsequent first redistribution layer 210 for electrical connection.
[0089] Such as Figure 5 , the silicon wafer 400 can be bonded to the first support substrate 110 through an adhesive layer 700. The first support substrate 110 may include, for example, a glass substrate, a metal substrate, a semiconductor substrate, etc., to provide support for the silicon wafer 400 through the first support substrate 110 to facilitate thinning of the silicon wafer 400.
[0090] Among them, to facilitate subsequent removal of the first support substrate 110, in this embodiment, preferably, a first separation layer 111 is formed on the surface of the first support substrate 110. The first separation layer 111 includes but is not limited to tape and polymer layers. For example, the first separation layer 111 can be a photothermal conversion layer formed by a photothermal conversion (LTHC) coating material, so that subsequent light / radiation (such as laser) can be used to decompose the LTHC coating material under heat to release the first support substrate 110, improving the convenience of the separation operation.
[0091] Next, referring to Figure 3 , Figure 6 and Figure 7 , perform step S2 to thin the silicon wafer 400 from the back surface of the silicon wafer 400 and form a thermally conductive grinding protection layer on the back surface of the silicon wafer 400 to form a composite silicon wafer.
[0092] Such as Figure 6 , when thinning the silicon wafer 400, chemical mechanical polishing (CMP) etc. can be used to make the silicon wafer 400 reach the target thickness. The thickness of the thinned silicon wafer 400 is not overly restricted here.
[0093] Next, referring to Figure 7 , form a thermally conductive grinding protection layer on the back surface of the silicon wafer 400 to form a composite silicon wafer.
[0094] In this embodiment, a metal diffusion barrier layer 412 and a heat dissipation metal layer 413 that are stacked from bottom to top and in contact with the silicon wafer 400 are formed on the back surface of the silicon wafer 400, and the diffusion coefficient of the metal diffusion barrier layer 412 is less than that of the Cu metal pillar 300. That is, the thermal conductive grinding protection layer is composed of the metal diffusion barrier layer 412 and the heat dissipation metal layer 413, but is not limited thereto. The thermal conductive grinding protection layer may further include a thermally conductive organic DAF film (not shown). Thus, by providing the thermal conductive grinding protection layer, simultaneous grinding of Cu / Si can be avoided, Cu metal diffusion contamination can be avoided, and the thermal conductive grinding protection layer with good thermal conductivity can also be used as a heat conducting member. Thus, while avoiding Cu metal contamination, good heat dissipation can be achieved, reducing process steps and costs.
[0095] Among them, the material of the metal diffusion barrier layer 412 may include, for example, one or a combination of Ni metal, Au metal, Sn metal, Ag metal, and Ti metal; the heat dissipation metal layer 413 may include, for example, a Cu layer, a Ni layer, or an Au layer. The method for forming the metal diffusion barrier layer 412 may include electroplating or electroless plating; the method for forming the heat dissipation metal layer 413 may include electroplating or electroless plating. There is no excessive limitation here on the materials and preparation methods of the metal diffusion barrier layer 412 and the heat dissipation metal layer 413.
[0096] When using the thermally conductive organic DAF film, it can be adhered to the thermally conductive organic DAF film through a binder with good thermal conductivity.
[0097] There is no excessive limitation here on the specific types and preparation methods of the thermal conductive grinding protection layer.
[0098] Next, refer to Figure 3 and Figure 8 , remove the first support substrate 110, cut the composite silicon wafer to form the first composite silicon chip 410.
[0099] Specifically, the cutting step may adopt, for example, mechanical cutting, laser cutting, etc. to prepare the monomeric first composite silicon chip 410. Among them, after removing the first support substrate 110 and the first separation layer 111, the back surface of the composite silicon wafer can be bonded to a support film such as a blue film, and then cutting can be performed to prepare the first composite silicon chip 410.
[0100] Next, refer to Figure 3 and Figure 9 , perform step S4 to provide a second support substrate 120.
[0101] Specifically, the second support substrate 120 may include a glass substrate, a metal substrate, a semiconductor substrate, etc., to provide support for subsequent processes through the second support substrate 120. The size of the second support substrate 120 is not limited here, and preferably it is wafer-level.
[0102] Wherein, to facilitate the subsequent removal of the second support substrate 120, in this embodiment, preferably, a second separation layer 121 is formed on the surface of the second support substrate 120. The second separation layer 121 includes but is not limited to tape and polymer layers. For example, the second separation layer 121 can be a photothermal conversion layer formed of a photothermal conversion (LTHC) coating material, so that subsequently, light / radiation (such as laser) can be used to decompose the LTHC coating material under heat to release the second support substrate 120, improving the convenience of the separation operation.
[0103] Next, refer to Figure 3 and Figure 10 , and perform step S5 to form a first redistribution layer 210 on the second support substrate 120.
[0104] Specifically, the first redistribution layer 210 includes a first metal wiring 211 and a first dielectric layer 212. The first dielectric layer 212 can be formed of a polymer such as polybenzoxazole (PBO), polyimide, etc., or formed of an inorganic dielectric material such as silicon nitride, silicon oxide, etc.; the first metal wiring 211 can include copper, tungsten, or their alloys, etc. The specific structure and material selection of the first redistribution layer 210 are not overly restricted here.
[0105] Next, refer to Figure 3 and Figure 11 , and perform step S6 to form Cu metal pillars 300 on the first redistribution layer 210, and the Cu metal pillars 300 are electrically connected to the first redistribution layer 210.
[0106] Specifically, the Cu metal pillars 300 can be formed by means of photolithography, etching, electroplating, but are not limited thereto.
[0107] Next, refer to Figure 3 and Figure 12 , and perform step S7 to bond the first composite silicon chip 410 to the first redistribution layer 210 in a flip-chip manner, and the first composite silicon chip 410 is electrically connected to the first redistribution layer 210.
[0108] Specifically, after the first composite silicon chip 410 is bonded in a flip-chip manner, one end of the first metal bump 810 is electrically connected to a pad (not shown) of the first silicon chip 411, and the other end of the first metal bump 810 is electrically connected to the first redistribution layer 210. The back surface of the first composite silicon chip 410, i.e., the heat dissipation metal layer 413, is away from the first redistribution layer 210.
[0109] Wherein, after the first composite silicon chip 410 is bonded, a first underfill layer 510 formed by means such as dispensing may be provided in the gap between the first composite silicon chip 410 and the first redistribution layer 210, so that the first underfill layer 510 can be used as a protective layer for the first composite silicon chip 410 and the first redistribution layer 210. The material of the first underfill layer 510 is not overly restricted herein.
[0110] Next, referring to Figure 3 and Figure 13 , perform step S8 to form a first encapsulation layer 610, which encapsulates the first redistribution layer 210, the Cu metal pillar 300, and the first composite silicon chip 410.
[0111] Specifically, the method for forming the first encapsulation layer 610 may include but is not limited to compression molding, transfer molding, and spin coating. The material of the first encapsulation layer 610 may include but is not limited to epoxy resin and polyamide. The material and preparation method of the first encapsulation layer 610 are not overly restricted herein.
[0112] Next, referring to Figure 3 and Figure 14 , perform step S9 to grind and expose the thermally conductive grinding protective layer and the Cu metal pillar 300.
[0113] Specifically, the grinding method may include, for example, chemical mechanical polishing (CMP) to remove part of the first encapsulation layer 610 and expose the thermally conductive grinding protective layer and the Cu metal pillar 300, so that the thermally conductive grinding protective layer, i.e., the heat dissipation metal layer 413, exposed by grinding is convenient for heat dissipation, and the exposed Cu metal pillar 300 is convenient for subsequent electrical connection.
[0114] Wherein, during grinding, since the diffusion coefficient of the metal diffusion barrier layer 412 is small, the metal diffusion barrier layer 412 can block the diffusion of Cu metal to the first silicon chip 411, thereby avoiding affecting the electrical performance of the first silicon chip 411.
[0115] Among them, to avoid the exposure of the first silicon chip 411 during grinding, the thickness of the thermally conductive grinding protective layer should be at least greater than the grinding tolerance. For example, the thickness of the thermally conductive grinding protective layer can be 15μm to 30μm, specifically 15μm, 20μm, 25μm, 30μm, etc.
[0116] Next, refer to Figure 3 and Figure 15 , perform step S10 to form a second redistribution layer 220 on the first encapsulation layer 610, and the second redistribution layer 220 is electrically connected to the Cu metal pillar 300.
[0117] Specifically, the second redistribution layer 220 includes a second metal wiring 221 and a second dielectric layer 222. The second dielectric layer 222 can be formed of a polymer such as polybenzoxazole (PBO), polyimide, etc., or formed of an inorganic dielectric material such as silicon nitride, silicon oxide, etc.; the second metal wiring 221 can include, for example, copper, tungsten, or their alloys, etc. There is no excessive limitation on the specific structure and material selection of the second redistribution layer 220 here.
[0118] Among them, when the thermally conductive grinding protective layer uses the thermally conductive organic DAF film, it is preferred that when preparing the second redistribution layer 220, the second metal wiring 221 is in direct contact with the first composite silicon chip 410, that is, the second metal wiring 221 is in direct contact with the heat dissipation metal layer 413, so that the heat dissipation of the first composite silicon chip 410 can be realized through the metal wiring in direct contact with the first composite silicon chip 410.
[0119] When the thermally conductive grinding protective layer uses the stack of the metal diffusion barrier layer 412 and the heat dissipation metal layer 413, the heat dissipation metal layer 413 and the second redistribution layer can be isolated through the dielectric layer in the second redistribution layer, that is, the second dielectric layer 222.
[0120] Next, refer to Figure 3 and Figure 16 , perform step S11 to provide a second chip 420, and bond the second chip 420 to the second redistribution layer 220 in a flip-chip manner, and the second chip 420 is electrically connected to the second redistribution layer 220.
[0121] Specifically, the second chip 420 can include a DDR chip made of silicon material, etc. There is no excessive limitation on the type of the second chip 420 here.
[0122] Among them, the front surface of the second chip 420 has second metal bumps 820, such as solder ball bumps, copper pillar bumps, etc. After bonding the second chip 420 in a flip-chip manner, one end of the second metal bump 820 is electrically connected to the pad (not shown) of the second chip 420, and the other end of the second metal bump 820 is electrically connected to the second redistribution layer 220, and the back surface of the second chip 420 is away from the second redistribution layer 220.
[0123] After bonding the second chip 420, a second underfill layer 520 formed by methods such as dispensing may be provided in the gap between the second chip 420 and the second redistribution layer 220, so as to use the second underfill layer 520 as a protective layer for the second chip 420 and the second redistribution layer 220. The material of the second underfill layer 520 is not overly limited herein.
[0124] Next, referring to Figure 3 and Figure 16 , perform step S12 to form a second encapsulation layer 620, and the second encapsulation layer 620 covers the second redistribution layer 220 and the second chip 420.
[0125] Specifically, the method of forming the second encapsulation layer 620 may include but is not limited to compression molding, transfer molding, and spin coating. The material of the second encapsulation layer 620 may include but is not limited to epoxy resin and polyamide. The material and preparation method of the second encapsulation layer 620 are not overly limited herein.
[0126] Next, referring to Figure 3 and Figure 17 , perform step S13 to remove the second support substrate 120 to expose the first redistribution layer 210, and perform step S14 to form metal bumps on the first redistribution layer 210.
[0127] Specifically, the metal bumps are third metal bumps 830, and the third metal bumps 830 are electrically connected to the first redistribution layer 210. Among them, the third metal bumps 830 may include solder ball bumps, copper pillar bumps, etc. The specific type and material of the third metal bumps 830 are not overly limited herein.
[0128] Furthermore, when the semiconductor package structure is prepared at the wafer level, such as 6 inches, 8 inches, 12 inches, etc., after performing step 14 to form the metal bumps, a cutting step, such as mechanical cutting, laser cutting, etc., may be further performed to prepare a single semiconductor package structure.
[0129] In summary, for the preparation method of the semiconductor packaging structure for avoiding Cu diffusion, before chip mounting, the silicon wafer is first thinned to the target thickness, and then a thermally conductive grinding protection layer is fabricated. The thermally conductive grinding protection layer can avoid simultaneous grinding of Cu / Si, prevent Cu metal diffusion pollution, and the thermally conductive grinding protection layer with good thermal conductivity can also be used as a heat-conducting component. Therefore, while avoiding Cu metal pollution, good heat dissipation can be achieved, reducing process steps and costs.
[0130] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A method for preparing a semiconductor package structure for avoiding Cu diffusion, characterized in that Including the following steps: Providing a first support substrate and a silicon wafer, and bonding the silicon wafer to the first support substrate; Thinning the silicon wafer from the back surface thereof, and forming a thermal conductive grinding protection layer on the back surface of the silicon wafer to form a composite silicon wafer; Removing the first support substrate, and cutting the composite silicon wafer to form a first composite silicon chip; Providing a second support substrate; Forming a first redistribution layer on the second support substrate; Forming Cu metal pillars on the first redistribution layer, and the Cu metal pillars are electrically connected to the first redistribution layer; Bonding the first composite silicon chip to the first redistribution layer in a flip-chip manner, and the first composite silicon chip is electrically connected to the first redistribution layer; Forming a first encapsulation layer, and the first encapsulation layer covers the first redistribution layer, the Cu metal pillars and the first composite silicon chip; Performing grinding to expose the thermal conductive grinding protection layer and the Cu metal pillars; Forming a second redistribution layer on the first encapsulation layer, and the second redistribution layer is electrically connected to the Cu metal pillars; Providing a second chip, and bonding the second chip to the second redistribution layer in a flip-chip manner, and the second chip is electrically connected to the second redistribution layer; Forming a second encapsulation layer, and the second encapsulation layer covers the second redistribution layer and the second chip; Removing the second support substrate to expose the first redistribution layer; Forming metal bumps on the first redistribution layer, and the metal bumps are electrically connected to the first redistribution layer.
2. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1, wherein: The thermal conductive grinding protection layer includes a metal diffusion barrier layer in contact with the silicon wafer and a heat dissipation metal layer stacked from bottom to top, and the diffusion coefficient of the metal diffusion barrier layer is less than that of the Cu metal pillars.
3. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 2, wherein: The material of the metal diffusion barrier layer includes one or a combination of Ni metal, Au metal, Sn metal, Ag metal and Ti metal; The heat dissipation metal layer includes a Cu layer, a Ni layer or an Au layer.
4. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 2, wherein: The method for forming the metal diffusion barrier layer includes electroplating or electroless plating; the method for forming the heat dissipation metal layer includes electroplating or electroless plating.
5. The method for manufacturing a semiconductor package structure for preventing Cu diffusion according to claim 2, wherein: The heat dissipation metal layer and the second redistribution layer are isolated through a dielectric layer in the second redistribution layer.
6. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1, wherein: The thermal conductive grinding protection layer includes a thermally conductive organic DAF film in contact with the silicon wafer.
7. The method for preparing a semiconductor package structure for avoiding Cu diffusion according to claim 6, wherein: The thermally conductive organic DAF film is in direct contact with a metal wiring layer in the second redistribution layer.
8. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1, wherein: The thickness of the thermal conductive grinding protection layer is greater than 15 μm.
9. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1, wherein: The projection of the thermal conductive grinding protection layer along the vertical direction covers the heat source area of the first composite silicon chip.
10. The method for preparing a semiconductor package structure for avoiding Cu diffusion according to claim 1, wherein: The semiconductor package structure is a wafer-level semiconductor package structure, and after forming the metal bumps, it further includes a step of cutting.