Preparation method of semiconductor packaging structure capable of avoiding Cu diffusion
By covering the composite metal column structure of the metal diffusion barrier layer on the Cu metal column, the problem of diffusion pollution of Cu metal during the polishing of silicon chips is solved, and the reliability and heat dissipation effect of the packaging structure are improved.
Patent Information
- Application Number
- CN202311867148.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-29
- Publication Date
- 2025-07-01
AI Technical Summary
In the prior art, Cu metal diffuses during the grinding of silicon chips, causing contamination, causing chip function failure.
A composite metal column structure is adopted with a metal diffusion barrier layer covered on Cu metal columns, and only the metal diffusion barrier layer is ground to avoid Cu metal residue on the silicon chip during the grinding process.
It effectively avoids diffusion pollution of Cu metal, ensures stable chip electrical performance, and improves the reliability and heat dissipation effect of the packaging structure.
Smart Images
Figure CN120237018A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor manufacturing, and relates to a method for preparing a semiconductor package structure to avoid Cu diffusion. Background Art
[0002] The rapid development of electronic products is the main driving force for the evolution of current packaging technologies. Miniaturization, high density, high frequency, high speed, high reliability, and low cost are the mainstream development directions of advanced packaging.
[0003] Existing consumer electronic product packages generally adopt Package on Package (POP) stacked packaging. With the increase in the functional integration of electronic products, the packaging structure becomes highly concentrated, and the heat generated during the operation of the chip will cause irreversible damage to the chip itself. Therefore, the heat dissipation problem of the packaging structure needs to be considered, and the heat dissipation requirements for product packaging are getting higher and higher.
[0004] Such as Figure 1 and Figure 2 , in a traditional packaging structure, generally, a grinding method is used to thin and expose the back surface of the underlying silicon chip 10 to increase heat dissipation. And during the grinding process, in order to facilitate subsequent electrical connection, the copper (Cu) metal pillars 20 around the silicon (Si) chip 10 will be ground simultaneously to expose the surface of the Cu metal pillars 20 for subsequent electrical connection, that is, during grinding, the composite interface of the Cu metal pillars 20 / silicon chip 10 / package layer 30 will be ground synchronously, and then the upper chip will be stacked and packaged. However, during the grinding process of the composite interface of the Cu metal pillars 20 / silicon chip 10 / package layer 30, Cu metal 40 will remain on the back surface of the silicon chip 10. Since Cu metal has a large diffusion coefficient, especially Cu metal is extremely easy to diffuse in the silicon material, the remaining Cu metal 40 will quickly diffuse into the underlying silicon chip 10, causing Cu contamination and resulting in the functional failure of the chips sensitive to Cu, such as problems like a decrease in breakdown voltage and leakage.
[0005] Therefore, it is necessary to provide a method for preparing a semiconductor package structure to avoid Cu diffusion. Summary of the Invention
[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for preparing a semiconductor package structure to avoid Cu diffusion, which is used to solve the problem of Cu contamination caused by Cu metal diffusion in the prior art.
[0007] To achieve the above purpose and other related purposes, the present invention provides a method for preparing a semiconductor package structure to avoid Cu diffusion, including the following steps:
[0008] Provide a support substrate;
[0009] Form a first redistribution layer on the support substrate;
[0010] Form a composite metal column on the first redistribution layer, the composite metal column including a Cu metal column and a metal diffusion barrier layer located on the Cu metal column, the Cu metal column being electrically connected to the first redistribution layer, and the diffusion coefficient of the metal diffusion barrier layer being less than that of the Cu metal column;
[0011] Provide a first silicon chip, and bond the first silicon chip to the first redistribution layer in a flip-chip manner, the first silicon chip being electrically connected to the first redistribution layer;
[0012] Form a first encapsulation layer, the first encapsulation layer covering the first redistribution layer, the composite metal column, and the first silicon chip;
[0013] Perform grinding to thin the first silicon chip, and after grinding, the first encapsulation layer exposes the metal diffusion barrier layer and the first silicon chip;
[0014] Form a second redistribution layer on the first encapsulation layer, the second redistribution layer being electrically connected to the composite metal column;
[0015] Form a heat dissipation metal block on the second redistribution layer, and the vertical projection of the heat dissipation metal block is located on the first silicon chip;
[0016] Provide a second chip, and bond the second chip to the second redistribution layer in a flip-chip manner, the second chip being electrically connected to the second redistribution layer, and the heat dissipation metal block being located below the second chip;
[0017] Form a second encapsulation layer, the second encapsulation layer covering the second redistribution layer, the heat dissipation metal block, and the second chip;
[0018] Remove the support substrate to expose the first redistribution layer;
[0019] Form metal bumps on the first redistribution layer, the metal bumps being electrically connected to the first redistribution layer.
[0020] Optionally, the material of the metal diffusion barrier layer includes one or a combination of Ni metal, Au metal, Sn metal, Ag metal, and Ti metal.
[0021] Optionally, the method for forming the Cu metal column includes electroplating; the method for forming the metal diffusion barrier layer includes electroplating.
[0022] Optionally, the thickness of the metal diffusion barrier layer in the composite metal column is greater than 15 μm.
[0023] Optionally, the method for forming the heat dissipation metal block includes electroplating or thermally conductive bonding.
[0024] Optionally, the heat dissipation metal block includes a Cu metal block, a Ni metal block, or an Au metal block.
[0025] Optionally, the metal wiring in the second rewiring layer includes a metal seed diffusion barrier layer, and the metal seed diffusion barrier layer is in direct contact with the first silicon chip.
[0026] Optionally, the material of the metal seed diffusion barrier layer includes one or a combination of Ni metal, Au metal, Sn metal, Ag metal, and Ti metal.
[0027] Optionally, the projection of the heat dissipation metal block in the vertical direction covers the heat source area of the first silicon chip.
[0028] Optionally, the semiconductor package structure is a wafer-level semiconductor package structure. After forming the metal bumps, it further includes a step of dicing.
[0029] As described above, in the method for preparing the semiconductor package structure for avoiding Cu diffusion of the present invention, a composite metal column having a Cu metal column and a metal diffusion barrier layer located on the Cu metal column is prepared, and during the grinding process, only the metal diffusion barrier layer is ground. Therefore, Cu metal residue on the first silicon chip can be avoided while thinning, thereby avoiding simultaneous grinding of Cu / Si and avoiding Cu metal diffusion contamination. Description of the Drawings
[0030] Figure 1 It shows a schematic structural diagram of the prior art after forming the encapsulation layer.
[0031] Figure 2 It shows a schematic structural diagram of the prior art after grinding.
[0032] Figure 3 It shows a schematic process flow diagram for preparing the semiconductor package structure in an embodiment of the present invention.
[0033] Figures 4 to 12 It shows a schematic structural diagram presented in each step when preparing the semiconductor package structure in an embodiment of the present invention.
[0034] Description of the Reference Numerals
[0035] 10 Silicon chip
[0036] 20 Cu metal column
[0037] 30 Encapsulation layer
[0038] 40 Residual Cu Metal
[0039] 100 Support Substrate
[0040] 101 Separation Layer
[0041] 210 First Redistribution Layer
[0042] 211 First Metal Wiring
[0043] 212 First Dielectric Layer
[0044] 220 Second Redistribution Layer
[0045] 221 Second Metal Wiring
[0046] 222 Second Dielectric Layer
[0047] 300 Composite Metal Column
[0048] 301 Cu Metal Column
[0049] 302 Metal Diffusion Barrier Layer
[0050] 410 First Silicon Chip
[0051] 420 Second Chip
[0052] 510 First Underfill Layer
[0053] 520 Second Underfill Layer
[0054] 610 First Encapsulation Layer
[0055] 620 Second Encapsulation Layer
[0056] 700 Heat Dissipation Metal Block
[0057] 810 First Metal Bump
[0058] 820 Second Metal Bump
[0059] 830 Third Metal Bump Detailed Implementation Manner
[0060] The following describes the implementation manners of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0061] When describing the embodiments of the present invention in detail, for the convenience of description, the cross-sectional views showing the device structure will be enlarged locally not in accordance with the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention herein. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.
[0062] For the convenience of description, spatial relationship terms such as "beneath", "below", "lower than", "under", "above", "on" etc. may be used herein to describe the relationship between an element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation, in addition to the directions depicted in the drawings. Embodiments may include those in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.
[0063] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation may be arbitrarily changed, and the component layout type may also be more complex.
[0064] As Figure 3 , this embodiment provides a method for preparing a semiconductor packaging structure for avoiding Cu diffusion, including the following steps:
[0065] S1: Provide a support substrate;
[0066] S2: Form a first redistribution layer on the support substrate;
[0067] S3: Form a composite metal pillar on the first redistribution layer, the composite metal pillar includes a Cu metal pillar and a metal diffusion barrier layer located on the Cu metal pillar, the Cu metal pillar is electrically connected to the first redistribution layer, and the diffusion coefficient of the metal diffusion barrier layer is less than that of the Cu metal pillar;
[0068] S4: Provide a first silicon chip, and bond the first silicon chip to the first redistribution layer in a flip-chip manner, the first silicon chip is electrically connected to the first redistribution layer;
[0069] S5: Form a first encapsulation layer, the first encapsulation layer covers the first redistribution layer, the composite metal pillar, and the first silicon chip;
[0070] S6: Perform grinding to thin the first silicon chip, and after grinding, the first encapsulation layer exposes the metal diffusion barrier layer and the first silicon chip;
[0071] S7: Form a second redistribution layer on the first encapsulation layer, and the second redistribution layer is electrically connected to the composite metal pillar;
[0072] S8: Form a heat dissipation metal block on the second redistribution layer, and the projection of the heat dissipation metal block along the vertical direction is located on the first silicon chip;
[0073] S9: Provide a second chip, and bond the second chip to the second redistribution layer in a flip-chip manner. The second chip is electrically connected to the second redistribution layer, and the heat dissipation metal block is located below the second chip;
[0074] S10: Form a second encapsulation layer, and the second encapsulation layer covers the second redistribution layer, the heat dissipation metal block and the second chip;
[0075] S11: Remove the support substrate to expose the first redistribution layer;
[0076] S12: Form metal bumps on the first redistribution layer, and the metal bumps are electrically connected to the first redistribution layer.
[0077] The following combines the specification appendix Figures 4 to 12 to further introduce the preparation of the semiconductor encapsulation structure.
[0078] First, refer to Figure 3 and Figure 4 , and perform step S1 to provide a support substrate 100.
[0079] Specifically, the support substrate 100 may include, such as, a glass substrate, a metal substrate, a semiconductor substrate, etc., to provide support for subsequent processes through the support substrate 100. The size of the support substrate 100 is not limited here, and preferably it is wafer-level.
[0080] Among them, for the convenience of removing the support substrate 100 subsequently, in this embodiment, preferably, a separation layer 101 is formed on the surface of the support substrate 100. The separation layer 101 includes but is not limited to tapes and polymer layers. For example, the separation layer 101 can be selected as a photothermal conversion layer formed by a photothermal conversion (LTHC) coating material, so that subsequently, such as light / radiation (such as laser) can be used to decompose the LTHC coating material under heat to release the support substrate 100, improving the convenience of the separation operation.
[0081] Next, refer to Figure 3 and Figure 5, perform step S2 to form a first redistribution layer 210 on the support substrate 100.
[0082] Specifically, the first redistribution layer 210 includes a first metal wiring 211 and a first dielectric layer 212. The first dielectric layer 212 can be formed of a polymer such as polybenzoxazole (PBO), polyimide, etc., or formed of an inorganic dielectric material such as silicon nitride, silicon oxide, etc.; the first metal wiring 211 can include, for example, copper, tungsten, or their alloys, etc. There is no excessive limitation here on the specific structure and material selection of the first redistribution layer 210.
[0083] Next, refer to Figure 3 and Figure 6 , perform step S3 to form a composite metal pillar 300 on the first redistribution layer 210. The composite metal pillar 300 includes a Cu metal pillar 301 and a metal diffusion barrier layer 302 located on the Cu metal pillar 301. The Cu metal pillar 301 is electrically connected to the first redistribution layer 210, and the diffusion coefficient of the metal diffusion barrier layer 302 is less than that of the Cu metal pillar 301.
[0084] Specifically, the Cu metal pillar 301 and the metal diffusion barrier layer 302 can be formed by means of photolithography, etching, electroplating, but are not limited thereto.
[0085] Among them, the material of the metal diffusion barrier layer 302 can include one or a combination of, for example, Ni metal, Au metal, Sn metal, Ag metal, and Ti metal. For example, the metal diffusion barrier layer 302 can include an NiSnAg layer, a Ti layer, an Ni layer, etc., and the metal diffusion barrier layer 302 can be a single layer or a stacked layer. There is no excessive limitation here.
[0086] Since the diffusion coefficient of the metal diffusion barrier layer 302 is less than that of the Cu metal pillar 301, in the subsequent grinding process, the metal diffusion barrier layer 302 can be used as a grinding stop layer. When grinding to the metal diffusion barrier layer 302, simultaneous grinding of Cu / Si can be avoided, thereby preventing the Cu metal in the Cu metal pillar 301 from diffusing into the first silicon chip 410 and avoiding Cu metal diffusion contamination.
[0087] Among them, to avoid the problem that the Cu metal pillar 301 is exposed due to the too thin metal diffusion barrier layer 302 in the grinding process, it is preferred that the thickness of the metal diffusion barrier layer 302 in the composite metal pillar 300 is at least greater than the grinding tolerance, that is, at least greater than 15 μm, such as 15 μm to 30 μm, and specifically can be 15 μm, 20 μm, 25 μm, 30 μm, etc.
[0088] Next, refer to Figure 3 andFigure 7 Step S4 is then performed to provide a first silicon chip 410, which is flip-chip bonded onto the first redistribution layer 210 such that the first silicon chip 410 is electrically connected to the first redistribution layer 210.
[0089] Specifically, the first silicon chip 410 may be a SoC chip, but is not limited thereto. The front surface of the first silicon chip 410 has first metal bumps 810, such as solder bumps or copper pillar bumps. After the first silicon chip 410 is flip-chip bonded, one end of the first metal bump 810 is electrically connected to a pad (not shown) of the first silicon chip 410, and the other end of the first metal bump 810 is electrically connected to the first redistribution layer 210, with the back surface of the first silicon chip 410 facing away from the first redistribution layer 210.
[0090] Thereafter, after the first silicon chip 410 is bonded, a first underfill layer 510 may be formed in the gap between the first silicon chip 410 and the first redistribution layer 210 by means such as dispensing, and the first underfill layer 510 is used as a protective layer for the first silicon chip 410 and the first redistribution layer 210. The material of the first underfill layer 510 is not overly restricted herein.
[0091] Next, referring to Figure 3 and Figure 8 Step S5 is then performed to form a first encapsulation layer 610 that encapsulates the first redistribution layer 210, the composite metal pillar 300, and the first silicon chip 410.
[0092] Specifically, the method of forming the first encapsulation layer 610 may include but is not limited to compression molding, transfer molding, and spin coating, and the material of the first encapsulation layer 610 may include but is not limited to epoxy resin and polyamide. The material and preparation method of the first encapsulation layer 610 are not overly restricted herein.
[0093] Next, referring to Figure 3 and Figure 9 Step S6 is then performed to grind and thin the first silicon chip 410 such that after grinding, the first encapsulation layer 610 exposes the metal diffusion barrier layer 302 and the first silicon chip 410.
[0094] Specifically, the grinding method may include, for example, chemical mechanical polishing (CMP), etc., to remove part of the first encapsulation layer 610, expose the metal diffusion barrier layer 302 and the back surface of the first silicon chip 410, so as to thin the first silicon chip 410 by grinding for heat dissipation, reduce the package size, and the exposed metal diffusion barrier layer 302 can facilitate subsequent electrical connection.
[0095] Among them, when grinding the composite interface of the metal diffusion barrier layer / silicon layer / encapsulation layer composed of the metal diffusion barrier layer 302, the first silicon chip 410, and the first encapsulation layer 610, since the diffusion coefficient of the metal diffusion barrier layer 302 is small, the metal diffusion barrier layer 302 will not affect the electrical performance of the first silicon chip 410.
[0096] Among them, to avoid the exposure of the Cu metal pillar 301 during grinding, the thickness of the metal diffusion barrier layer 302 should be at least greater than the grinding tolerance. For example, the thickness of the metal diffusion barrier layer 302 can be 15μm - 30μm, specifically 15μm, 20μm, 25μm, 30μm, etc.
[0097] Next, refer to Figure 3 and Figure 10 , perform step S7 to form a second redistribution layer 220 on the first encapsulation layer 610, and the second redistribution layer 220 is electrically connected to the composite metal pillar 300.
[0098] Specifically, the second redistribution layer 220 includes a second metal wiring 221 and a second dielectric layer 222. The second dielectric layer 222 can be formed by polymers such as polybenzoxazole (PBO), polyimide, etc., or formed by inorganic dielectric materials such as silicon nitride, silicon oxide, etc.; the second metal wiring 221 can include, for example, copper, tungsten, or their alloys, etc. The specific structure and material selection of the second redistribution layer 220 are not overly restricted here.
[0099] Among them, preferably when preparing the second redistribution layer 220, the second metal wiring 221 includes a metal seed diffusion barrier layer (not shown), and the metal seed diffusion barrier layer is in direct contact with the first silicon chip 410. Thus, heat dissipation of the first silicon chip 410 can be achieved through the metal wiring in direct contact with the first silicon chip 410, and the presence of the metal seed diffusion barrier layer can prevent the diffusion of, for example, Cu metal wiring into the first silicon chip 410.
[0100] The material of the metal seed diffusion barrier layer can include, for example, one or a combination of Ni metal, Au metal, Sn metal, Ag metal, and Ti metal. The specific types are not overly restricted here.
[0101] Next, referring to Figure 3 and Figure 10 , step S8 is performed to form a heat dissipation metal block 700 on the second rewiring layer 220, and the vertical projection of the heat dissipation metal block 700 is located on the first silicon chip 410.
[0102] Specifically, preferably, the vertical projection of the heat dissipation metal block 700 covers the heat source area of the first silicon chip 410. The method for forming the heat dissipation metal block 700 may include, for example, electroplating or thermal conductive bonding. The heat dissipation metal block 700 may include, for example, a Cu metal block, a Ni metal block, or an Au metal block, etc. The preparation method, material, morphology, etc. of the heat dissipation metal block 700 are not limited herein.
[0103] Next, referring to Figure 3 and Figure 11 , step S9 is performed to provide a second chip 420, and the second chip 420 is flip-chip bonded to the second rewiring layer 220. The second chip 420 is electrically connected to the second rewiring layer 220, and the heat dissipation metal block 700 is located below the second chip 420.
[0104] Specifically, the second chip 420 may include, for example, a DDR chip made of silicon. The type of the second chip 420 is not overly restricted herein.
[0105] Among them, the front surface of the second chip 420 has second metal bumps 820, such as solder ball bumps, copper pillar bumps, etc. After the second chip 420 is flip-chip bonded, one end of the second metal bump 820 is electrically connected to the pad (not shown) of the second chip 420, and the other end of the second metal bump 820 is electrically connected to the second rewiring layer 220. The back surface of the second chip 420 is away from the second rewiring layer 220.
[0106] After the second chip 420 is bonded, the gap between the second chip 420 and the second rewiring layer 220 may have a second underfill layer 520 formed by, for example, dispensing, etc., so as to use the second underfill layer 520 as a protective layer for the second chip 420 and the second rewiring layer 220. The material of the second underfill layer 520 is not overly restricted herein.
[0107] Next, referring to Figure 3 and Figure 11 , step S10 is performed to form a second encapsulation layer 620, and the second encapsulation layer 620 covers the second rewiring layer 220, the heat dissipation metal block 700, and the second chip 420.
[0108] Specifically, the method for forming the second encapsulation layer 620 may include, but is not limited to, compression molding, transfer molding, and spin coating. The material of the second encapsulation layer 620 may include, but is not limited to, epoxy resin and polyamide. There is no excessive limitation on the material and preparation method of the second encapsulation layer 620 here.
[0109] Next, referring to Figure 3 and Figure 12 , perform step S11 to remove the support substrate 100 to expose the first redistribution layer 210, and perform step S12 to form metal bumps on the first redistribution layer 210.
[0110] Specifically, the metal bumps are the third metal bumps 830, and the third metal bumps 830 are electrically connected to the first redistribution layer 210. Among them, the third metal bumps 830 may include, such as solder ball bumps, copper pillar bumps, etc. There is no excessive limitation on the specific type and material of the third metal bumps 830 here.
[0111] Furthermore, when the semiconductor package structure is prepared at the wafer level, such as 6 inches, 8 inches, 12 inches, etc., after performing step 12 to form the metal bumps, a cutting step, such as mechanical cutting, laser cutting, etc., may also be performed to prepare a single semiconductor package structure.
[0112] In summary, in the preparation method of the semiconductor package structure for avoiding Cu diffusion of the present invention, a composite metal pillar having a Cu metal pillar and a metal diffusion barrier layer located on the Cu metal pillar is prepared, and during the grinding process, only the metal diffusion barrier layer is ground. Therefore, Cu metal residue on the first silicon chip can be avoided during thinning, thereby avoiding simultaneous grinding of Cu / Si and avoiding Cu metal diffusion contamination.
[0113] The above embodiments merely illustrate the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A method for preparing a semiconductor package structure for avoiding Cu diffusion, characterized in that It includes the following steps: Provide a support substrate; Form a first redistribution layer on the support substrate; Form a composite metal pillar on the first redistribution layer. The composite metal pillar includes a Cu metal pillar and a metal diffusion barrier layer located on the Cu metal pillar. The Cu metal pillar is electrically connected to the first redistribution layer, and the diffusion coefficient of the metal diffusion barrier layer is less than that of the Cu metal pillar; Provide a first silicon chip, and bond the first silicon chip to the first redistribution layer in a flip-chip manner. The first silicon chip is electrically connected to the first redistribution layer; Form a first encapsulation layer that encapsulates the first redistribution layer, the composite metal pillar, and the first silicon chip; Perform grinding to thin the first silicon chip, and after grinding, the first encapsulation layer exposes the metal diffusion barrier layer and the first silicon chip; Form a second redistribution layer on the first encapsulation layer. The second redistribution layer is electrically connected to the composite metal pillar; Form a heat dissipation metal block on the second redistribution layer, and the projection of the heat dissipation metal block in the vertical direction is located on the first silicon chip; Provide a second chip, and bond the second chip to the second redistribution layer in a flip-chip manner. The second chip is electrically connected to the second redistribution layer, and the heat dissipation metal block is located below the second chip; Form a second encapsulation layer that encapsulates the second redistribution layer, the heat dissipation metal block, and the second chip; Remove the support substrate to expose the first redistribution layer; Form metal bumps on the first redistribution layer. The metal bumps are electrically connected to the first redistribution layer.
2. The method for manufacturing a semiconductor package structure for preventing Cu diffusion according to claim 1, wherein: The material of the metal diffusion barrier layer includes one or a combination of Ni metal, Au metal, Sn metal, Ag metal, and Ti metal.
3. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1, wherein: The method for forming the Cu metal pillar includes electroplating; the method for forming the metal diffusion barrier layer includes electroplating.
4. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1, characterized in that: The thickness of the metal diffusion barrier layer in the composite metal pillar is greater than 15 μm.
5. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1, characterized in that: The method for forming the heat dissipation metal block includes electroplating or thermal conductive bonding.
6. The method for manufacturing a semiconductor package structure for preventing Cu diffusion according to claim 1, wherein: The heat dissipation metal block includes a Cu metal block, a Ni metal block, or an Au metal block.
7. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1, characterized in that: The metal wiring in the second redistribution layer includes a metal seed diffusion barrier layer, and the metal seed diffusion barrier layer is in direct contact with the first silicon chip.
8. The manufacturing method of the semiconductor packaging structure for avoiding Cu diffusion according to claim 7, characterized in that: The material of the metal seed diffusion barrier layer includes one or a combination of Ni metal, Au metal, Sn metal, Ag metal, and Ti metal.
9. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1, wherein: The projection of the heat dissipation metal block in the vertical direction covers the heat source area of the first silicon chip.
10. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1, characterized in that: The semiconductor package structure is a wafer-level semiconductor package structure. After forming the metal bumps, it further includes a step of dicing.