Automatic Wafer Defect Detection Method and System Based on Vision Driving

Abstract

The present invention provides a method and system for automatic detection of wafer defects based on vision drive, which relates to the technical field of image data processing. By importing the design shape data of the wafer, a docking part for defect detection is processed; the docking part is assembled on a splicing and assembly mechanism to perform edge splicing with the wafer to obtain a spliced part; a macro vision lens is driven to collect a set of splicing images of the spliced part; a defect recognition model is called to recognize defect features in the set of splicing images, and a defect detection result is returned. After the splicing and assembly mechanism separates the spliced part, wafer sorting processing is performed according to the defect detection result. The present invention solves the technical problem in the prior art that it is difficult to effectively identify slight edge defects such as microcracks and micro notches due to the tiny size of wafer edge defects and low visual contrast, and achieves the technical effect of realizing automatic detection and recognition of wafer defects with high sensitivity and high precision.

Description

Technical Field

[0001] The present invention relates to the technical field of image data processing, and particularly to an automatic wafer defect detection method and system based on vision driving. Background Art

[0002] In the processes of wafer manufacturing, cutting, handling, and packaging, etc., micro-cracks, small notches, and slight chipping defects are likely to occur at the edge part of the wafer. Although the scale of such edge defects is small, they have a significant impact on the subsequent process quality and reliability of the wafer. Existing wafer defect detection methods mostly rely on high-resolution optical imaging technology, combined with image processing and feature recognition algorithms, to identify defects on the surface or edge of the wafer. Some methods introduce deep learning models or template matching means to improve the degree of detection automation. Although the above methods have been widely used in conventional defect detection, there are still significant deficiencies in dealing with slight edge defects of wafers: First, the size of wafer edge defects is tiny and the image contrast is low, and traditional image acquisition and enhancement technologies are difficult to effectively extract defect features; second, the edge structure is complex and variable, and existing template matching methods are difficult to cover different design shapes, with poor adaptability; third, the textures of defects such as micro-cracks and micro-notches are blurred, and false detection or missed detection is likely to occur. The above problems jointly restrict the sensitivity and accuracy of wafer defect recognition. Summary of the Invention

[0003] The present invention provides an automatic wafer defect detection method and system based on vision driving, which solves the technical problem in the prior art that it is difficult to effectively identify slight edge defects such as micro-cracks and micro-notches due to the tiny size of wafer edge defects and low visual contrast, and achieves the technical effects of improving the accuracy, sensitivity, and detection efficiency of wafer edge defect recognition, and realizing automatic detection and recognition of wafer defects with high sensitivity and high accuracy.

[0004] In view of the above problems, on the one hand, the present invention provides an automatic wafer defect detection method based on vision driving, and the method includes: importing the design shape data of the wafer, and processing a docking part for defect detection according to the design shape data of the wafer; assembling the docking part on a splicing and assembling mechanism, and the splicing and assembling mechanism splices the edges of the wafer and the docking part to obtain a spliced part; driving a macro vision lens to collect images of the spliced part to obtain a set of spliced images; calling a defect recognition model to identify defect features in the set of spliced images, returning a defect detection result to the docking part, and after the splicing and assembling mechanism separates the spliced part, sorting the wafer according to the defect detection result.

[0005] Preferably, a docking component for defect detection is processed according to the design shape data of the wafer. The method further includes: extracting key contour parameters from the design shape data, at least including the curvature of the wafer edge, the number and positions of corner points, and the bonding notch; modeling based on the extracted key contour parameters to obtain a contour solid model, generating corresponding compensated contour parameters based on the contour solid model; obtaining a docking component model according to the compensated contour parameters, and machining the entity docking component after exporting the docking component model.

[0006] Preferably, a docking component model is designed according to the compensated contour parameters under an assembly constraint structure. The assembly constraint structure includes a positioning groove, an expansion joint, and an assembly adsorption interface; wherein, the positioning groove is used to align with the wafer, the expansion joint is used to prevent thermal expansion and contraction, and the assembly adsorption interface is used to assemble the docking component on a splicing assembly mechanism.

[0007] Preferably, the splicing assembly mechanism splices the edges of the wafer and the docking component. The method includes: wherein, the splicing assembly mechanism includes a base platform, a displacement component, and a guiding and positioning module; after placing the wafer on the base platform, controlling the relative positions of the wafer and the docking component according to the displacement component, and the guiding and positioning module assisting the wafer and the docking component to perform edge alignment and splicing.

[0008] Preferably, a defect recognition model is called to recognize defect features in the splicing image set. The method includes: shearing the splicing image set to obtain a first splicing gap image set; performing image enhancement processing on the first splicing gap image set to output a second splicing gap image set; recognizing the gap defect features of the second splicing gap image set according to the defect recognition model, and performing defect type recognition on the gap defect features to output a defect detection result, wherein the defect detection result includes the defect type.

[0009] Preferably, the gap defect features include gap width, abnormal curvature, crack texture, and edge jump.

[0010] Preferably, defect type recognition is performed on the gap defect features to output a defect detection result. The method includes: establishing sample feature values of gap defects and corresponding defect type sample labels; performing quantitative analysis on the gap defect features to obtain gap defect feature indicators; the defect recognition model performing defect type label mapping on the gap defect feature indicators according to the sample feature values of the gap defects to output a defect detection result.

[0011] Preferably, after the splicing and assembling mechanism separates the splicing parts, the wafers are sorted according to the defect detection results. The method includes: the splicing and assembling mechanism is connected to a sorting line, the sorting line includes a plurality of sorting channels, and each sorting channel is provided with a corresponding defect type label that can be sorted; the splicing and assembling mechanism determines the matching sorting channel according to the defect detection results; after the splicing and assembling mechanism separates the splicing parts, the wafers are sorted into the matching sorting channel for processing.

[0012] Preferably, the macro vision lens is connected to the lateral illumination module. The method includes: after the lateral illumination module performs lateral illumination on the splicing parts, driving the macro vision lens to collect images of the splicing parts.

[0013] On the other hand, the present invention also provides a wafer defect automatic detection system based on vision drive. The system includes: a docking part processing module for importing the design shape data of the wafer and processing the docking parts for defect detection according to the design shape data of the wafer; a splicing and assembling module for assembling the docking parts on a splicing and assembling mechanism, and the splicing and assembling mechanism performs edge splicing on the wafer and the docking parts to obtain a splicing part; a splicing image acquisition module for driving a macro vision lens to collect images of the splicing part to obtain a set of splicing images; a defect detection module for calling a defect recognition model to identify defect features in the set of splicing images, returning a defect detection result to the docking part, and after the splicing and assembling mechanism separates the splicing parts, sorting the wafers according to the defect detection results.

[0014] One or more technical solutions provided in the present invention have at least the following beneficial effects:

[0015] By importing the design shape data of the wafer and processing the docking parts for defect detection according to the design shape data of the wafer, personalized customized splicing aids are realized, ensuring that the contour of the docking part is precisely matched with the target wafer, providing a prerequisite for subsequent splicing and detection. Assembling the docking parts on a splicing and assembling mechanism, and the splicing and assembling mechanism performs edge splicing on the wafer and the docking parts to obtain a splicing part, and indirectly reflects the morphological characteristics of the wafer edge through the gap state. Driving a macro vision lens to collect images of the splicing part to obtain a set of splicing images, calling a defect recognition model to identify defect features in the set of splicing images, returning a defect detection result to the docking part, and after the splicing and assembling mechanism separates the splicing parts, sorting the wafers according to the defect detection results.

[0016] In summary, the present invention utilizes a dummy mold (docking part) that precisely fits the edge of the target wafer to form a stable splicing structure, collects the image of the splicing gap through a macro vision lens, and indirectly magnifies the characteristics of minute defects on the edge. By combining image enhancement and a defect recognition model, high-precision recognition of edge defects such as microcracks, micro notches, and slight chipping that are difficult to directly detect is achieved. Through the linkage of the splicing assembly and sorting mechanisms, automated defect detection and grading processing are completed, significantly improving the accuracy, sensitivity, and detection efficiency of wafer edge defect recognition.

[0017] The above description is only an overview of the technical solution of the present invention. In order to be able to more clearly understand the technical means of the present invention, it can be implemented in accordance with the content of the description. And in order to make the above and other purposes, features, and advantages of the present invention more obvious and understandable, the following specifically illustrates the specific embodiments of the present invention. Brief Description of the Drawings

[0018] Figure 1 It is a flowchart of the automatic wafer defect detection method based on vision drive provided by an embodiment of the present invention.

[0019] Figure 2 It is a flowchart of processing the docking part for defect detection in the automatic wafer defect detection method based on vision drive provided by an embodiment of the present invention.

[0020] Figure 3 It is a structural diagram of the automatic wafer defect detection system based on vision drive provided by an embodiment of the present invention.

[0021] Description of the reference numerals: The docking part processing module 10, the splicing assembly module 20, the splicing image acquisition module 30, and the defect detection module 40. Detailed Embodiments

[0022] The embodiments of the present invention provide an automatic wafer defect detection method and system based on vision drive. By introducing a spliceable dummy mold and combining high-precision image acquisition and recognition models, the defect characteristics are indirectly magnified, realizing vision-driven automatic wafer defect detection. It solves the technical problem in the prior art that it is difficult to effectively identify slight edge defects such as microcracks and micro notches due to the tiny size of wafer edge defects and low visual contrast, achieving the technical effects of improving the accuracy, sensitivity, and detection efficiency of wafer edge defect recognition and realizing high-sensitivity and high-precision automatic detection and recognition of wafer defects.

[0023] Embodiment 1, as Figure 1 shown, the embodiments of the present invention provide an automatic wafer defect detection method based on vision drive, and the method includes:

[0024] Step S100: Import the design shape data of the wafer and process the docking part for defect detection according to the design shape data of the wafer.

[0025] Specifically, the design shape data of the wafer refers to the set of geometric structure parameters of the wafer in the design stage, including information such as the edge profile, arc curvature, chamfer shape, and corner position. The docking part refers to a pseudo-mold component used to assist in splicing detection, and its edge structure highly matches the shape of the target wafer and is used to form an observable splicing gap.

[0026] Import the two-dimensional or three-dimensional shape data of the wafer to be detected from the manufacturing database or design drawings, and extract the key profile features of the edge area of the wafer, including parameters such as curvature change, number and position of corner points, position and shape of edge notches, etc. Based on the design shape data of the wafer, construct the edge mating area of the docking part to form a contour model with a mirror compensation relationship. Subsequently, use three-dimensional modeling software to complete the design of the docking part solid model, and process the docking part solid model into a physical component actually used for detection through a CNC numerical control machine tool or a 3D printing device to obtain the docking part for defect detection. Appropriate assembly tolerances and edge buffer structures can be introduced during processing to ensure subsequent assembly accuracy and detection stability. Exemplarily, if the target wafer is designed with a circular edge structure with two irregular protrusions, the edge area of the docking part is synchronously designed as a concave contour that fits reversely with this structure. During the solid processing of the docking part, a five-axis machining center can be used to perform high-precision engraving on the curved edge, or SLA precision stereolithography 3D printing rapid prototyping can be adopted.

[0027] This step achieves high-precision adaptation of the docking part to the target wafer at the contour level, providing a prerequisite for subsequent splicing to form a standard gap structure, thereby enhancing the identifiability of micro-defects and improving the matching degree and accuracy of defect detection.

[0028] Step S200: Assemble the docking part on the splicing and assembly mechanism, and the splicing and assembly mechanism splices the edges of the wafer and the docking part to obtain a spliced part.

[0029] Specifically, the splicing and assembly mechanism refers to a mechanical device used to achieve precise splicing positioning and fixing of the wafer and the docking part, including component parts such as a base platform, a displacement component, and a guiding and positioning module. Install the processed docking part on the fixed card slot or adsorption platform of the splicing and assembly mechanism, and ensure that its edge faces the direction of the wafer to be detected. Subsequently, place the wafer on the moving platform or suspended bracket of the splicing mechanism, and precisely adjust the position of the wafer through the displacement component driven by a servo motor to achieve high-precision alignment with the docking part in the edge area. When the edges of the wafer and the docking part are in full contact, a spliced part is obtained, and the spliced part forms a stable gap area, providing the geometric reference conditions required for detection.

[0030] This step constructs a standardized splicing gap area by achieving stable splicing of the wafer and the high-precision docking component, which helps to accurately reflect the minute geometric anomalies at the wafer edge during subsequent image acquisition, enhancing the accuracy and reliability of the detection process.

[0031] Step S300: Drive the macro vision lens to perform image acquisition on the splicing component to obtain a set of splicing images.

[0032] Specifically, the macro vision lens refers to an industrial imaging lens with a high magnification ratio and a short focal length, capable of clearly acquiring detailed images of a target area at the micron level. The set of splicing images refers to a dataset of images obtained by continuously shooting or imaging the gap area of the splicing component from multiple angles. After the splicing component is stabilized, the macro vision lens is driven by the control system to perform segment-by-segment or full-area imaging on the splicing gap area to obtain a complete set of splicing images. For example, an industrial microscope lens with a magnification of 10× is used to gradually scan the gap area between the wafer and the docking component at a resolution of 10 μm, combined with a red light side illumination module to form a high-contrast image; several images are collected for each segment of the splicing gap, and finally a dataset containing hundreds of images is formed for subsequent identification.

[0033] This step realizes high-definition acquisition of the splicing gap through high-resolution macro imaging means, effectively capturing the minute defect features in the edge area, providing an accurate image basis for the subsequent defect recognition model, and improving the overall wafer edge defect detection accuracy and detail restoration ability.

[0034] Step S400: Invoke the defect recognition model to identify the defect features in the set of splicing images, return the defect detection result to the docking component, and after the splicing assembly mechanism separates the splicing component, sort the wafer according to the defect detection result.

[0035] Specifically, the defect recognition model refers to an intelligent recognition system constructed based on image feature extraction and classification algorithms, composed of a deep learning network or a machine learning model, and is used to judge whether there are defects and the types of defects in the image. The defect detection result refers to the detection result output by the defect recognition model, including information such as the presence or absence of defects and the types of defects. The sorting process refers to the operation process of classifying wafers into different processing channels or process segments according to the detection results.

[0036] After obtaining the set of spliced images, a pre-trained defect recognition model is called to process the images. The defect recognition model first shears and enhances the splicing gap regions in the spliced images to highlight the edge features, then extracts typical defect features such as gap width variation, curvature anomaly, texture break, and edge jump, and classifies and discriminates these typical defect features based on the sample training labels. After the recognition is completed, the defect detection results are fed back to the control system, which controls the splicing and assembly mechanism to release the splicing state between the wafer and the docking part, and selects a suitable sorting channel for transfer operations according to the recognition results. For example, wafers detected with chipping defects are pushed to the repair area, and wafers without defects enter the normal processing flow.

[0037] This step realizes an automated recognition process from image data to defect judgment, and combines mechanical execution mechanisms to complete the rapid sorting process of wafers, improving the intelligent level and processing efficiency of defect detection, and can quickly complete the large-volume and fine-grained edge defect classification and screening tasks.

[0038] Further, as Figure 2 shown, step S100 includes:

[0039] Step S110: Extract key contour parameters from the design shape data, including at least the wafer edge curvature, the number and positions of corner points, and the bonding notch.

[0040] Step S120: Model a contour solid model according to the extracted key contour parameters, and generate corresponding compensation contour parameters based on the contour solid model.

[0041] Step S130: Obtain a docking part model according to the compensation contour parameters, and after exporting the docking part model, process it to obtain a solid docking part.

[0042] Specifically, by reading the wafer design file, a geometric feature extraction algorithm is used to identify the key features in the edge region of the wafer, and at least the key profile parameters including the wafer edge curvature, the number and position of corner points, and the bonding notch are extracted. Among them, the edge curvature refers to the curvature value of the contour line at any point on the wafer edge, which is an important parameter for judging the smoothness of the edge; the number and position of corner points refer to the number of feature points with geometric mutations (such as straight line turning, acute angles) on the edge and their coordinates; the bonding notch refers to the structural vacant area reserved for the bonding process or process compatibility during wafer design, including rectangular grooves, semi-circular holes, etc. First, discrete points of the edge curvature are extracted and fitted, the curvature change of each section of the contour is calculated, and the high-curvature regions (such as arc turning, concave and convex sections) of the edge are identified. Then, based on corner detection algorithms (such as Harris corner detection algorithm, Speeded Up Robust Features algorithm), obvious geometric turning points on the edge are obtained, and their coordinate information is extracted. Finally, by using contour scanning and morphological recognition means, it is detected whether there are design notches on the wafer edge, such as structural features like missing corners, notches, alignment slots, etc., providing a complete geometric basis for constructing the compensation structure, which helps to accurately fit the shape of the docking part and the wafer contour in the subsequent process, and improves the overall splicing accuracy.

[0043] Taking the extracted key profile parameters as input, a three-dimensional solid model of the wafer edge contour is established using 3D modeling software or procedural modeling tools to obtain the contour solid model. Subsequently, a set of compensation profile parameters is constructed based on compensation strategies such as mirroring, curvature inverse mapping, and curved edge projection to ensure that the docking part is complementary to the wafer structure in the edge region. During the compensation process, micro-gap control, tolerance distribution, and mechanical registration requirements are introduced to ensure that a controllable splicing gap can be achieved after processing, and finally, the compensation profile parameters for driving the docking part modeling are obtained. For example, if a certain section of the wafer edge is an inner concave arc with a radius of 1.2 mm, the corresponding position of the docking part is designed as an outer convex arc with a radius of 1.2 mm, and the overall contour direction is mirrored, and the groove area also needs to be compensated and filled accordingly. Among them, the contour solid model refers to the three-dimensional edge structure model obtained by modeling the extracted two-dimensional contour parameters. The compensation profile parameters refer to the reverse or symmetric structure parameters that the docking part needs to form based on the original contour model, which are used to achieve the matching compensation of geometric fitting.

[0044] After obtaining the complete compensation profile parameters, these parameters are input into the CAD modeling platform to automatically generate the docking component model, including parts such as the edge compensation area, base positioning structure, and assembly interface. Subsequently, the docking component model is exported in a standard manufacturing format, and a suitable manufacturing process is selected for machining, such as precision CNC milling, laser cutting, or 3D printing. During the machining process, the cutting path and layer thickness distribution are optimized according to the material selection and tolerance setting to ensure that the machining accuracy is better than ±0.02 mm. After machining, post-processing such as deburring, sandblasting, and polishing is carried out to ensure that the edge quality of the physical docking component meets the requirements for splicing imaging. Among them, the docking component model refers to the three-dimensional docking component CAD model completed based on the compensation profile parameters. The physical docking component refers to the actual physical component manufactured from the docking component model and is used for auxiliary detection of wafer edge splicing.

[0045] The above steps transform the virtual design model into an actual usable detection tool by designing and machining the physical docking component, ensuring that the docking component fits closely with the wafer edge to form a high-quality splicing component, providing a reliable basis for subsequent visual inspection.

[0046] Furthermore, based on the compensation profile parameters, the docking component model is designed under the assembly constraint structure, and the assembly constraint structure includes a positioning groove, an expansion joint, and an assembly adsorption interface; wherein, the positioning groove is used to align with the wafer, the expansion joint is used to prevent thermal expansion and contraction, and the assembly adsorption interface is used to assemble the docking component onto the splicing assembly mechanism.

[0047] Specifically, the assembly constraint structure refers to the auxiliary structure introduced in the docking component model to achieve precise splicing, stable fixation, and thermal compensation between the docking component and the wafer, including a positioning groove, an expansion joint, and an assembly adsorption interface. Among them, the positioning groove is a geometric groove provided on the docking component body and is used to match the wafer edge or positioning point during the assembly process to ensure position consistency. The expansion joint is a narrow slit structure provided in the key connection or edge area of the docking component to buffer the thermal expansion and contraction caused by environmental temperature changes and prevent assembly stress or warping. The assembly adsorption interface refers to the interface structure provided at the bottom or side of the docking component and is used to connect with the splicing assembly mechanism (such as an adsorption platform or a mechanical fixture) to achieve rapid positioning and release.

[0048] To ensure the stability and accuracy of the docking component during the actual assembly process, when designing the docking component model according to the compensation profile parameters, it is necessary to comprehensively consider the mechanical and thermal conditions during the assembly process and add three types of assembly constraint structures: positioning grooves, expansion joints, and assembly adsorption interfaces. First, the positioning grooves are set according to the reference points, corner points, or calibration hole positions on the wafer edge. Their shapes can be L-shaped, V-shaped, or rectangular grooves, used to achieve mechanical limit fitting with the wafer edge. Then, considering that materials (such as aluminum alloy or resin) may thermally expand or contract under ambient temperature fluctuations, in order to avoid structural deformation or abnormal splicing gaps, several expansion joints are designed at the edge or connection area of the docking component. Their widths are generally from 0.1 mm to 0.3 mm, and their shapes can be sawtooth, S-shaped, or linear gaps, used to provide stress release space. Finally, several adsorption interfaces are designed at the bottom of the docking component, such as vacuum holes, magnetic adsorption grooves, or pressing bosses, used to achieve mechanical or pneumatic adsorption connection with the splicing assembly mechanism, facilitating automated loading and unloading and rapid positioning. Exemplarily, in a docking component for detecting edge defects of a 50-mm-diameter wafer, two V-shaped positioning grooves with a depth of 2 mm are set to align with the corner points of the upper and lower edges of the wafer respectively to ensure the correct splicing direction. Serpentine expansion joints with a width of 0.2 mm are arranged on both sides of its edge to absorb the material size fluctuations caused by a temperature difference of ±5°C. At the same time, three 1-mm-diameter vacuum adsorption holes are set on the bottom surface to match the negative pressure suction cups of the splicing assembly mechanism, thus completing the rapid assembly and fixation of the docking component.

[0049] The above steps significantly improve the assembly accuracy and structural stability between the docking component and the wafer by introducing assembly constraint structures such as positioning grooves, expansion joints, and adsorption interfaces, reduce the detection deviation caused by thermal expansion and contraction or error accumulation, ensure that the docking component is always in an accurate and controllable position during the actual splicing detection process, and thus improve the reliability and repeatability of defect detection.

[0050] Further, the splicing assembly mechanism includes a base platform, a displacement component, and a guiding and positioning module. Step S200 includes:

[0051] After placing the wafer on the base platform, control the relative positions of the wafer and the docking component according to the displacement component, and the guiding and positioning module assists in aligning the edges of the wafer and the docking component for splicing.

[0052] Specifically, the splicing assembly mechanism includes a base platform, a displacement component, and a guiding and positioning module. The base platform is a basic platform for carrying the wafer or the docking component, providing a stable support surface and used in conjunction with adsorption or limit structures. The displacement component is a driving structure that can precisely control the positions of the wafer or the docking component. Common types include electric slide tables, lead screw modules, or linear motor platforms. The guiding and positioning module is an auxiliary structure for aligning the edges of the wafer and the docking component during the splicing process, including mechanical limit blocks, vision calibration systems, or elastic clamping mechanisms.

[0053] When performing the splicing step S200, first place the wafer to be detected on the base platform of the splicing and assembly mechanism. The base platform provides a flat and stable bearing surface and is provided with vacuum suction holes or limit frames to prevent the wafer from moving. Subsequently, start the displacement component, which is composed of a precision electric slide or an XYZ three-axis platform. By precisely controlling the stroke of the drive motor or stepper motor, micron-level displacement adjustment of the wafer relative to the docking component in the plane is achieved. After the wafer approaches the predetermined position of the docking component, the guiding and positioning module starts to work to ensure precise splicing of the wafer edge and the docking component edge. The guiding and positioning module can use mechanical alignment blocks fixed at key reference positions or combine with a camera vision recognition system for dynamic deviation correction. For example, by identifying whether the gap width between the wafer edge and the docking component edge is uniform, the fine movement of the displacement component is adjusted in real time to achieve the optimal docking position. After alignment, the splicing and assembly mechanism fixes the wafer and the docking component to form a spliced component and enters the image acquisition process of the next step. For example, in a set of splicing and assembly mechanisms for 100-mm-diameter circular wafers, the base platform is a granite platform with a vacuum chuck that can fix the wafer without moving in the X-Y direction. The displacement component uses an electric slide with a high-precision ball screw, and the minimum stepping accuracy can reach 5 μm. The guiding and positioning module is arranged on both sides of the platform and is composed of two groups of symmetric spring limit blocks, which can automatically clamp the wafer edge and guide it to align with the preset splicing edge of the docking component. In addition, a set of high-magnification vision alignment system is equipped to judge the splicing accuracy by real-time identifying the uniformity of the gap width.

[0054] In this step, by integrating the base platform, the displacement component, and the guiding and positioning module, high-precision and automated edge splicing of the wafer and the docking component is achieved, effectively reducing the splicing offset problem caused by human operation errors or position deviations, ensuring that the splicing gap is accurate and continuous, providing a reliable image basis for subsequent visual defect recognition, and improving the defect detection accuracy.

[0055] Further, the macro vision lens is connected to the lateral illumination module. After the lateral illumination module performs lateral illumination on the spliced component, the macro vision lens is driven to perform image acquisition on the spliced component.

[0056] Specifically, the lateral illumination module is an illumination device with a special light source arrangement. The light irradiates the side of the object to be detected at an oblique angle or in the horizontal direction to enhance the visual contrast of the small features on the object surface or edge.

[0057] After the splicing is completed, in order to capture the tiny defects in the gap between the chip and the docking piece with high precision, the side lighting module is started to illuminate the spliced piece. The side lighting is usually composed of a ring-shaped LED light source, a linear cold light source or a light guide strip, which is installed in a horizontal or low-angle position in the splicing area so that the light is irradiated to the gap area at a shallow incident angle. This lighting method can significantly enhance the light and shadow changes at the edges of the gap, curvature anomalies or cracks, making tiny defects appear as obvious features in the image. Subsequently, the macro vision lens is started to capture the image and clearly record the detailed changes in the gap contour. The entire image acquisition process is usually carried out in a line scan or area array manner. The gap area is fully scanned through a preset path or automatic following algorithm, and finally a complete set of spliced images is obtained for use in subsequent defect recognition models.

[0058] Furthermore, in step S400, a defect recognition model is called to perform defect feature recognition on the stitched image set, including:

[0059] Step S410: cutting the stitched image set to obtain a first stitched gap image set.

[0060] Step S420: performing image enhancement processing on the first stitching seam image set, and outputting a second stitching seam image set.

[0061] Step S430: identifying the seam defect features of the second stitching seam image set according to the defect recognition model, performing defect type recognition on the seam defect features, and outputting a defect detection result, wherein the defect detection result includes the defect type.

[0062] Furthermore, the gap defect characteristics include gap width, curvature anomaly, crack texture and edge jump.

[0063] Specifically, after image acquisition is completed, first, the stitched image set is cropped to extract the effective region in the image that contains the gap between the wafer and the docking part, forming the first stitched gap image set. The cropping method can adopt image coordinate region extraction, image segmentation algorithm, or automatic cropping method based on edge detection to ensure obtaining an image that clearly and centrally reflects the defect region. Subsequently, each image in the first stitched gap image set is subjected to image enhancement processing to improve the stability and accuracy of subsequent model recognition. The enhancement processing includes, but is not limited to, histogram equalization, edge enhancement, pseudo-color mapping, etc., to make the gap edges and crack details in the image more prominent. The processed images are used as the second stitched gap image set and input into the defect recognition model. This defect recognition model is trained based on a large number of samples and can identify various gap defect features such as gap width change, abnormal curvature, crack texture, edge jump, etc. Quantitative analysis is performed on these gap defect features, defect feature values are extracted, and specific defect types such as "slight chipping", "micro-crack", "edge warping", etc. are output in combination with preset thresholds or model labels. Finally, the defect detection result is output.

[0064] The above steps, through multi-level processing flows such as image cropping, enhancement processing, and model recognition, achieve automatic and accurate recognition and classification of gap defect features in stitched gap images, significantly improving the recognition ability for fine features such as micro-cracks and edge jumps, and enhancing the accuracy and reliability of automatic detection of wafer edge defects.

[0065] Further, step S430 includes:

[0066] Step S431: Establish the characteristic values of gap defect samples and the corresponding defect type sample labels.

[0067] Step S432: Perform quantitative analysis on the gap defect features to obtain gap defect feature indicators.

[0068] Step S433: The defect recognition model performs defect type label mapping on the gap defect feature indicators according to the characteristic values of gap defect samples and outputs the defect detection result.

[0069] Specifically, the characteristic values of gap defect samples are the characteristic data values extracted from a large number of known defect images, including characteristic parameters such as the maximum gap width, average curvature, crack direction texture consistency, edge gradient change rate, and the number of jump points in the gap contour, and are used to establish the training data set of the defect recognition model. The defect type sample labels are the defect categories manually or expert-labeled corresponding to the characteristic values, such as "edge micro-notch", "slight chipping", "crack initiation", "jump curve point", etc., and are used to supervise the training of the defect recognition model. The gap defect feature indicators are the quantitative feature sets representing the defects contained in a certain image, and are in the same group of characteristic parameters as the characteristic values of gap defect samples in form.

[0070] Before constructing and training the defect recognition model, a large number of spliced gap image samples containing different edge defects are collected, and the corresponding defect types (such as micro notches, micro cracks, irregular edges, etc.) in the spliced gap images are labeled by manual annotation and expert review to obtain defect type sample labels. Then, image processing algorithms are used to extract features from the spliced gap image samples, and the above five types of feature parameters are calculated. The feature parameter extraction results are used as the feature values of the gap defect samples, and together with the defect type sample labels, they form the training dataset for the defect recognition model. Subsequently, algorithms such as random forest, support vector machine, convolutional neural network, etc. are used to model and train the training set, and finally the defect recognition model is obtained.

[0071] An example of calculating the feature values of the gap defect samples is as follows: First, the edge of the gap area is extracted by the edge detection algorithm to obtain the edge curves on both sides. Based on the edge coordinate data, each row of the image is scanned along the splicing direction, and the abscissas of the left and right edge points of the gap are recorded to obtain the width sequence of the entire gap, and then the maximum gap width is extracted. The second derivative is calculated by polynomial fitting or sliding window difference for each side edge curve, and its absolute value is taken as the local curvature. The average value of all local curvatures is obtained as the average contour curvature. The spliced gap area is divided into multiple sub-blocks according to the window size (such as 16×16 pixels), and the Gabor filter bank is used to perform direction response on each sub-block to calculate the texture similarity or consistency variance to obtain the texture consistency index. A boundary band is set around the gap edge, and the Sobel operator is used to calculate the gray gradient amplitude map. The average gradient values on both sides of the edge are statistically calculated and the difference is obtained. The gray gradient change rate index is obtained. The edge contour sequence of the gap is extracted, pixel points are sampled according to the longitudinal sequence, the change rate of the horizontal displacement of adjacent points is calculated, and the number of points whose horizontal displacement change rate exceeds the preset jump threshold is statistically calculated to obtain the jump point number index of the gap contour.

[0072] Taking a convolutional neural network as an example, the specific training process of the defect recognition model is as follows: Construct a network structure that includes multiple convolutional layers, pooling layers, and fully connected layers. The convolutional layer is used to extract local features in the image, the pooling layer is used to reduce the feature dimension and prevent overfitting, and the fully connected layer is used to comprehensively analyze and classify the extracted features. During the model training process, the extracted gap defect feature indicators and the image pixel data are input into the convolutional neural network together. The convolutional layer and the pooling layer are used to extract features from the image data to obtain high-level feature representations. Then, these high-level feature representations are fused with the gap defect feature indicators and input into the fully connected layer for classification. The fully connected layer uses the softmax activation function to output the probability distribution of each defect type. According to the difference between the probability distribution and the true label, the loss function (such as cross-entropy loss) is calculated. Through the backpropagation algorithm and an optimizer (such as the Adam optimizer), the parameters of the model are continuously adjusted to minimize the loss function, and a trained defect recognition model is obtained.

[0073] During the actual detection process, image analysis is performed on the input second spliced gap image set, image features with the same dimension as the training samples are extracted, and quantitative analysis is performed on them to obtain a set of structured gap defect feature indicators. The extracted gap defect feature indicators are input into the trained defect recognition model. The defect recognition model calculates the probability distribution or similarity score of the current gap defect feature indicators in the multi-classifier according to the feature distribution rules and label mapping relationships learned during the training stage, and outputs the most matching defect type label. For example, if the input features have the highest similarity to the "slight chipping" sample feature values, the output defect type is "slight chipping". Finally, this defect type label is fed back to the subsequent sorting logic as the wafer defect detection result.

[0074] Further, after the splicing and assembling mechanism separates the splicing parts in step S400, sorting the wafer according to the defect detection result includes:

[0075] Step S440: The splicing and assembling mechanism is connected to the sorting line, and the sorting line includes multiple sorting channels, and each sorting channel is set with a corresponding defect type label that can be sorted.

[0076] Step S450: The splicing and assembling mechanism determines the matching sorting channel according to the defect detection result.

[0077] Step S460: After the splicing and assembling mechanism separates the splicing parts, the wafer is sorted into the matching sorting channel for processing.

[0078] Specifically, the sorting line is a conveying device that automatically transports wafers after wafer inspection. It is provided with multiple outlets or paths (sorting channels) for classifying and transporting wafers. The sorting channels are physical branches of the sorting line, and the wafers are automatically introduced into the corresponding processing channels according to the defect types in the defect detection results. The defect type label is a classification identifier defined according to the identified defect type and is used to correspond to the specific sorting channel.

[0079] After completing the stitching image acquisition and defect recognition, an automatic sorting operation is performed on the current wafer according to the obtained defect detection results. First, the stitching and assembly mechanism is connected to a preset sorting line, which is provided with multiple physical channels, and each channel is marked with a corresponding defect type label, such as "slight notch channel", "crack channel", "qualified wafer channel", etc., so as to realize the classified collection of wafers of different types. Subsequently, according to the specific defect type in the defect detection results, such as edge crack, jumping edge or complete and defect-free edge, the mapping relationship between the label and the channel is automatically compared to determine the matching sorting channel that the current wafer should enter. Finally, the stitching and assembly mechanism controls the adsorption fixture or the robotic arm assembly to dissociate the docking part in the stitching part from the wafer, and orderly transports the wafer to the corresponding channel, completing the entire detection and sorting process and realizing the closed-loop linkage with the detection link.

[0080] In summary, the automatic wafer defect detection method based on vision drive provided by the embodiments of the present invention has the following beneficial effects:

[0081] In the embodiments of the present invention, by designing a docking part that matches the edge contour of the wafer and performing precise edge stitching with the wafer, high-precision image acquisition and defect recognition in the gap area are realized. First, by importing the design shape data of the wafer, key contour parameters such as edge curvature, corner position, and bonding notch are extracted. Based on these key contour parameters, a contour solid model is constructed and compensated contour parameters are generated. A docking part model including a positioning groove, an expansion joint, and an assembly adsorption interface is designed to realize the geometric adaptation and thermal stress release between the docking part and the wafer. Then the docking part is assembled onto the stitching and assembly mechanism, and high-precision edge stitching is realized under the coordinated action of the base platform, the guiding and positioning module, and the displacement component. After stitching, the stitching area image is collected by a macro vision lens combined with lateral illumination to obtain a set of stitching images with clear edge textures and gap features. Further, a defect recognition model is constructed and trained with a large number of manually labeled and expert-reviewed image samples. Multidimensional feature parameters such as the maximum gap width, average curvature, texture consistency, edge gradient change rate, and contour jump point number are extracted, and the mapping relationship between the features and the defect type labels is established. In the detection stage, feature indicators are extracted for the actual stitching image, and the corresponding defect type is output through model inference. Finally, combined with the defect detection results, the stitching and assembly mechanism is controlled to realize the separation of the stitching part, and the wafer is automatically sorted to the corresponding channel for processing.

[0082] Overall, the embodiments of the present invention utilize a dummy mold (docking part) that precisely fits the edge of the target wafer to form a stable splicing structure, collect images of the splicing gap through a macro vision lens, and indirectly magnify the tiny defect features at the edge. Combining image enhancement and a defect recognition model, high-precision recognition of edge defects such as microcracks, micro-notches, and slight chipping that are difficult to directly detect is achieved. Through the linkage of the splicing assembly and sorting mechanism, automated defect detection and grading processing are completed, significantly improving the accuracy, sensitivity, and detection efficiency of wafer edge defect recognition.

[0083] Embodiment 2, as Figure 3 shown, based on the same inventive concept as the foregoing Embodiment 1, the embodiments of the present invention provide a vision-driven automatic wafer defect detection system, and the system includes:

[0084] A docking part processing module 10, configured to import the design shape data of the wafer and process a docking part for defect detection according to the design shape data of the wafer.

[0085] A splicing assembly module 20, configured to assemble the docking part on a splicing assembly mechanism, and the splicing assembly mechanism splices the edges of the wafer and the docking part to obtain a spliced part.

[0086] A splicing image acquisition module 30, configured to drive a macro vision lens to acquire images of the spliced part and obtain a set of splicing images.

[0087] A defect detection module 40, configured to call a defect recognition model to identify defect features in the set of splicing images, return a defect detection result to the docking part, and after the splicing assembly mechanism separates the spliced part, sort the wafer according to the defect detection result.

[0088] Further, the docking part processing module 10 is further configured to perform the following steps:

[0089] Extract key contour parameters from the design shape data, at least including the wafer edge curvature, the number and positions of corner points, and bonding notches; model a contour solid model according to the extracted key contour parameters, generate corresponding compensated contour parameters based on the contour solid model; obtain a docking part model according to the compensated contour parameters, and after exporting the docking part model, process it to obtain a solid docking part.

[0090] Further, the docking part processing module 10 is further configured to perform the following steps:

[0091] Under the assembly constraint structure, a docking component model is designed according to the compensation profile parameters. The assembly constraint structure includes a positioning groove, an expansion joint, and an assembly adsorption interface. Among them, the positioning groove is used to align with the wafer, the expansion joint is used to prevent thermal expansion and contraction, and the assembly adsorption interface is used to assemble the docking component on the splicing assembly mechanism.

[0092] Further, the splicing assembly mechanism includes a base platform, a displacement component, and a guiding and positioning module. The splicing assembly module 20 is further configured to perform the following steps:

[0093] After placing the wafer on the base platform, control the relative position of the wafer and the docking component according to the displacement component, and the guiding and positioning module assists in edge alignment and splicing of the wafer and the docking component.

[0094] Further, the macro vision lens is connected to the lateral illumination module. The splicing image acquisition module 30 is further configured to perform the following steps:

[0095] After laterally illuminating the splicing component according to the lateral illumination module, drive the macro vision lens to perform image acquisition on the splicing component.

[0096] Further, the defect detection module 40 is further configured to perform the following steps:

[0097] Shear the splicing image set to obtain a first splicing gap image set; perform image enhancement processing on the first splicing gap image set and output a second splicing gap image set; identify the gap defect features of the second splicing gap image set according to the defect recognition model, perform defect type recognition on the gap defect features, and output a defect detection result, where the defect detection result includes the defect type.

[0098] Further, the gap defect features include gap width, abnormal curvature, crack texture, and edge jump.

[0099] Further, the defect detection module 40 is further configured to perform the following steps:

[0100] Establish gap defect sample feature values and corresponding defect type sample labels; perform quantitative analysis on the gap defect features to obtain gap defect feature indicators; the defect recognition model performs defect type label mapping on the gap defect feature indicators according to the gap defect sample feature values and outputs a defect detection result.

[0101] Further, the defect detection module 40 is further configured to perform the following steps:

[0102] The splicing and assembling mechanism is connected to the sorting line, and the sorting line includes a plurality of sorting channels, and each sorting channel is provided with a corresponding defect type label that can be sorted; the splicing and assembling mechanism determines the matching sorting channel according to the defect detection result; after the splicing and assembling mechanism separates the spliced parts, the wafers are sorted into the matching sorting channels for processing.

[0103] Through the foregoing detailed description of the method for automatically detecting wafer defects based on vision drive in this specification, those skilled in the art can clearly know the system for automatically detecting wafer defects based on vision drive in this embodiment. For the system disclosed in Embodiment 2, since it corresponds to the method disclosed in Embodiment 1, it has corresponding functional modules and beneficial effects. For the relevant parts, refer to the description in the method part.

[0104] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An automatic wafer defect detection method based on vision drive, characterized in that The method includes: Importing the design shape data of the wafer, processing a docking part for defect detection according to the design shape data of the wafer, constructing an edge fitting area of the docking part based on the wafer design shape data, and forming a contour model with a mirror compensation relationship; Assembling the docking part on a splicing and assembling mechanism, and the splicing and assembling mechanism splices the edges of the wafer and the docking part to obtain a spliced part; Driving a macro vision lens to collect images of the spliced part to obtain a set of splicing images. After the spliced part is stabilized, the macro vision lens is driven by a control system to image the splicing gap area segment by segment or globally to obtain a complete set of splicing images; Invoking a defect recognition model to identify defect features in the set of splicing images, returning a defect detection result to the docking part, and after the splicing and assembling mechanism separates the spliced part, sorting the wafer according to the defect detection result.

2. The automatic wafer defect detection method based on vision drive according to claim 1, wherein Processing a docking part for defect detection according to the design shape data of the wafer, and the method further includes: Extracting key contour parameters from the design shape data, including at least the wafer edge curvature, the number and positions of corner points, and bonding notches; Modeling based on the extracted key contour parameters to obtain a contour solid model, and generating corresponding compensation contour parameters based on the contour solid model; Obtaining a docking part model according to the compensation contour parameters, and after exporting the docking part model, processing to obtain a physical docking part.

3. The automatic wafer defect detection method based on vision drive according to claim 2, wherein Designing a docking part model according to the compensation contour parameters under an assembly constraint structure, and the assembly constraint structure includes a positioning groove, an expansion joint, and an assembly adsorption interface; Wherein, the positioning groove is used to align with the wafer, the expansion joint is used to prevent thermal expansion and contraction, and the assembly adsorption interface is used to assemble the docking part on the splicing and assembling mechanism.

4. The automatic wafer defect detection method based on vision driving according to claim 3, characterized in that, The splicing and assembling mechanism splices the edges of the wafer and the docking part, and the method Includes: Wherein, the splicing and assembling mechanism includes a base platform, a displacement component, and a guiding and positioning module; After placing the wafer on the base platform, controlling the relative positions of the wafer and the docking part according to the displacement component, and the guiding and positioning module assisting the wafer and the docking part to perform edge alignment and splicing.

5. The automatic wafer defect detection method based on vision drive according to claim 1, characterized in that, Invoking a defect recognition model to identify defect features in the set of splicing images, and the method includes: Clipping the set of splicing images to obtain a set of first splicing gap images; Performing image enhancement processing on the set of first splicing gap images to output a set of second splicing gap images; Identifying the gap defect features in the set of second splicing gap images according to the defect recognition model, identifying the defect types of the gap defect features, and outputting a defect detection result, wherein the defect detection result includes defect types.

6. The automatic wafer defect detection method based on vision driving according to claim 5, wherein The gap defect features include gap width, abnormal curvature, crack texture, and edge jump.

7. The automatic wafer defect detection method based on vision drive according to claim 5, characterized in that, Identifying the defect types of the gap defect features and outputting a defect detection result, and the method includes: Establishing sample feature values of gap defects and corresponding sample labels of defect types; Performing quantitative analysis on the gap defect features to obtain gap defect feature indexes; The defect recognition model performs defect type label mapping on the seam defect characteristic indicators according to the seam defect sample characteristic values, and outputs a defect detection result.

8. The automatic wafer defect detection method based on vision drive according to claim 1, wherein After the splicing and assembly mechanism separates the spliced parts, it sorts the wafers according to the defect detection result. The method includes: The splicing and assembly mechanism is connected to a sorting line. The sorting line includes a plurality of sorting channels, and each sorting channel is set with a corresponding defect type label that can be sorted. The splicing and assembly mechanism determines a matching sorting channel according to the defect detection result. After the splicing and assembly mechanism separates the spliced parts, it sorts the wafers to the matching sorting channel for processing.

9. The automatic wafer defect detection method based on vision drive according to claim 1, characterized in that The macro vision lens is connected to the lateral illumination module. The method includes: After performing lateral illumination on the spliced parts according to the lateral illumination module, the macro vision lens is driven to perform image acquisition on the spliced parts.

10. An automatic wafer defect detection system based on vision drive, characterized in that, The system is used to execute the vision-driven automatic wafer defect detection method according to any one of claims 1-9, including: A docking part processing module, which is used to import the design shape data of the wafer, process the docking part for defect detection according to the design shape data of the wafer, construct the edge fitting area of the docking part based on the wafer design shape data, and form a contour model with a mirror compensation relationship. A splicing and assembly module, which is used to assemble the docking part on the splicing and assembly mechanism. The splicing and assembly mechanism performs edge splicing on the wafer and the docking part to obtain a spliced part. A splicing image acquisition module, which is used to drive the macro vision lens to perform image acquisition on the spliced part to obtain a set of splicing images. After the spliced part is stabilized, the macro vision lens is driven by the control system to perform segmented or global imaging on the splicing gap area to obtain a complete set of splicing images. A defect detection module, which is used to call the defect recognition model to identify the defect characteristics of the set of splicing images, return the defect detection result to the docking part, and the splicing and assembly mechanism sorts the wafers according to the defect detection result after separating the spliced parts.

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