Method of manufacturing semiconductor package by using carrier substrate

Abstract

A method of manufacturing a semiconductor package is provided. The method may use a carrier substrate and may include: forming a first adhesive layer on a device substrate; forming a second adhesive layer on the first adhesive layer; bonding the device substrate to the carrier substrate by bonding the second adhesive layer to the carrier substrate; thinning the device substrate by grinding the device substrate; after thinning the device substrate, stacking a first semiconductor chip on the device substrate; and separating the carrier substrate from the device substrate at an interface between the first adhesive layer and the second adhesive layer.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2023-0197702, filed with the Korean Intellectual Property Office on December 29, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a method of manufacturing a semiconductor package, and more particularly, to a method of manufacturing a semiconductor package by using a carrier substrate. Background Art

[0003] Recently, as the integration degree of semiconductor devices has increased and the performance of peripheral devices has improved, a structure in which chips are stacked vertically rather than horizontally has been adopted. In the case of a vertical stacking structure, when a wire bonding method is used, the package structure and process can be complex. Therefore, through-silicon vias (or through-silicon vias, TSVs) that simplify the package structure while reducing the transmission path are applied. In addition, a carrier wafer is used to stably perform subsequent processes on a device wafer including TSVs. For reference, the process of temporarily bonding a carrier wafer to a device wafer and separating the carrier wafer from the device wafer is called a wafer support system (WSS) process. Summary of the Invention

[0004] The inventive concept provides a method of manufacturing a semiconductor package by using a carrier substrate, in which process stability is maintained, and thus, a semiconductor package with improved reliability can be manufactured.

[0005] In addition, the problems to be solved by the technical idea of the inventive concept are not limited to the above, and other problems can be clearly understood by those of ordinary skill in the art from the following description.

[0006] According to an embodiment of the inventive concept, a method of manufacturing a semiconductor package may use a carrier substrate. The method may include: forming a first adhesive layer on a device substrate; forming a second adhesive layer on the first adhesive layer; bonding the device substrate to the carrier substrate by bonding the second adhesive layer to the carrier substrate; thinning the device substrate by grinding the device substrate; after thinning the device substrate, stacking a first semiconductor chip on the device substrate; and separating the carrier substrate from the device substrate at an interface between the first adhesive layer and the second adhesive layer.

[0007] According to an embodiment of the inventive concept, a method of manufacturing a semiconductor package may use a carrier substrate. The method may include: forming a first adhesive layer on a device substrate; curing the first adhesive layer at a first temperature; forming a second adhesive layer on the first adhesive layer; bonding the device substrate to the carrier substrate by bonding the carrier substrate to the second adhesive layer; curing the second adhesive layer at a second temperature higher than the first temperature; thinning the device substrate by grinding the device substrate; stacking a plurality of first semiconductor chips on the device substrate; sealing the plurality of first semiconductor chips on the device substrate with a sealing material; and separating the carrier substrate from the device substrate at an interface between the first adhesive layer and the second adhesive layer. The first adhesive layer and the second adhesive layer may include the same material.

[0008] According to an embodiment of the inventive concept, a method of manufacturing a semiconductor package may use a carrier substrate. The method may include: forming a first adhesive layer and a second adhesive layer on a device substrate, the first adhesive layer and the second adhesive layer including the same material and being cured at different temperatures to form an interface between the first adhesive layer and the second adhesive layer; bonding the device substrate to the carrier substrate by bonding the carrier substrate to the second adhesive layer; thinning the device substrate by grinding the device substrate; stacking first semiconductor chips on the device substrate; and separating the carrier substrate from the device substrate at an interface between the first adhesive layer and the second adhesive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings.

[0010] Figure 1A and Figure 1B are cross-sectional views schematically showing a method of manufacturing a semiconductor package by using a carrier substrate according to an embodiment and a method of manufacturing a semiconductor package by using a carrier substrate according to a comparative example, respectively.

[0011] Figures 2A to 2L is a cross-sectional view showing in detail a method of manufacturing a semiconductor package by using a carrier substrate according to an embodiment of Figure 1A The cross-sectional view shows in detail a method of manufacturing a semiconductor package by using a carrier substrate according to an embodiment of

[0012] Figures 3A to 3C are cross-sectional views and graphs for explaining problems in a method of manufacturing a semiconductor package by using a carrier substrate according to a comparative example of Figure 1B The cross-sectional view and graph are for explaining problems in a method of manufacturing a semiconductor package by using a carrier substrate according to a comparative example of

[0013] Figure 4A and Figure 4B are conceptual diagrams for explaining a process of separating a carrier substrate in a method of manufacturing a semiconductor package by using a carrier substrate according to an embodiment of Figure 1A and in a method of manufacturing a semiconductor package by using a carrier substrate according to a comparative example of Figure 1B The conceptual diagrams are for explaining a process of separating a carrier substrate in a method of manufacturing a semiconductor package by using a carrier substrate according to an embodiment of

[0014] Figure 5 Shows, in a method of manufacturing a semiconductor package by using a carrier substrate according to an embodiment of Figure 1A and in a comparative example according to Figure 1B a graph of the change amount of peel strength in a method of manufacturing a semiconductor package by using a carrier substrate.

[0015] Figures 6A to 6D is a cross-sectional view showing a method of manufacturing a semiconductor package by using a carrier substrate according to an embodiment. Detailed Description of the Invention

[0016] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of..." modify the entire list of elements when following the list of elements, rather than modifying individual elements of the list. For example, "at least one of A, B, and C" and similar language (e.g., "at least one selected from the group consisting of A, B, and C" and "at least one of A, B, or C") can be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C (such as, by way of example, ABC, AB, BC, and AC).

[0017] When the terms "about" or "substantially" are used in connection with a numerical value in this specification, it is intended that the associated numerical value include manufacturing or operational errors near the stated numerical value (e.g., ±10%). In addition, when the words "generally" and "substantially" are used in connection with a geometric shape, it is intended that the geometric shape not require precision, but rather that the tolerance for the shape be within the disclosed range. Further, whether the numerical value or shape is modified by "about" or "substantially", it will be understood that these values and shapes should be interpreted as including manufacturing or operational errors near the stated numerical value or shape (e.g., ±10%). The concept that elements are "substantially the same" may indicate that the elements may be exactly the same, and may also indicate that the elements may be determined to be the same considering errors or deviations that occur during the process.

[0018] Although the term "equal to" is used in the description of the exemplary embodiments, it should be understood that some imprecision may exist. Thus, when an element is referred to as "equal to" another element, it should be understood that the element or value may be "equal to" the other element within the desired manufacturing or operational tolerance range (e.g., ±10%).

[0019] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and their repeated description is omitted.

[0020] Figure 1A and Figure 1BSchematic cross-sectional views of a method of manufacturing a semiconductor package using a carrier substrate according to an embodiment and a method of manufacturing a semiconductor package using a carrier substrate according to a comparative example are shown, respectively.

[0021] Referring to Figure 1A , in a method of manufacturing a semiconductor package using a carrier substrate (hereinafter, simply referred to as "a method of manufacturing a semiconductor package") according to an embodiment, the carrier substrate 200 may be bonded to the device substrate 100 by using two adhesive layers 310 and 320. In the method of manufacturing a semiconductor package, before the thinning process of thinning the device substrate 100, the device substrate 100 including through-silicon vias (or through-silicon vias, TSVs) (refer to Figure 2A 110 in

[0022] Figure 2A

[0023]

[0024] Both the device substrate 100 and the carrier substrate 200 may have a circular flat shape. Therefore, in some embodiments, the device substrate 100 and the carrier substrate 200 may be referred to as a device wafer and a carrier wafer, respectively. The carrier substrate 200 may have a diameter greater than that of the device substrate 100. In addition, the carrier substrate 200 may have a thickness greater than that of the device substrate 100. However, in some embodiments, the carrier substrate 200 may have substantially the same diameter as the device substrate 100. In addition, before the device substrate 100 is thinned, the carrier substrate 200 may have substantially the same thickness as the device substrate 100.

[0024] In Figure 1A Figure 2A Figure 2A

[0025] ​​​In the method of manufacturing a semiconductor package according to the present embodiment, in order to bond the device substrate 100 and the carrier substrate 200, an adhesive layer 300 including a first adhesive layer 310 and a second adhesive layer 320 may be used. In addition, the first adhesive layer 310 and the second adhesive layer 320 may include substantially the same material, but after the first adhesive layer 310 and the second adhesive layer 320 are cured at different temperatures, an interface IF may (for example, may be formed) between the first adhesive layer 310 and the second adhesive layer 320. In addition, when the first adhesive layer 310 and the second adhesive layer 320 combine the carrier substrate 200 and the device substrate 100 in an initial state, the first adhesive layer 310 and the second adhesive layer 320 may provide a high bonding force. In addition, in a subsequent debonding process of debonding the carrier substrate 200 from the device substrate 100, the interface IF between the first adhesive layer 310 and the second adhesive layer 320 may facilitate the debonding of the carrier substrate 200. For example, as Figure 1A shown, in the debonding process between the device substrate 100 and the carrier substrate 200, debonding may occur at the interface IF having a relatively low adhesive force. Refer to Figures 2A to 2L for a more detailed description of the formation, curing and bonding of the first adhesive layer 310 and the second adhesive layer 320, the debonding of the carrier substrate 200 via the interface IF, etc.

[0026] Refer to Figure 1B , on the other hand, in the case of the method of manufacturing a semiconductor package according to a comparative example, the carrier wafer C-W may be bonded to the device wafer D-W by using an adhesive layer ADH including a release layer RL and an adhesive layer GL. Since the device wafer D-W and the carrier wafer C-W are substantially the same as the device substrate 100 and the carrier substrate 200, respectively, their detailed descriptions are omitted.

[0027] The adhesive layer ADH may include a release layer RL and an adhesive layer GL. The release layer RL may be directly formed on the device wafer D-W. The release layer RL may include, for example, thermosetting resins (such as epoxy resins and silicone resins). In addition, the release layer RL may also include any one of silsesquioxane resins and thermoplastic resins. The release layer RL may be formed to have a thin thickness of about 100 nm to about 500 nm. The release layer RL may be formed according to the shape of the upper surface of the device wafer D-W (for example, formed according to the thin coating shape of the upper surface of the device wafer D-W and the external connection terminals).

[0028] On the other hand, the release layer RL may have a double-layer structure of a precursor layer and a chemical vapor deposition (CVD) layer. For example, the precursor may be adsorbed and coated on the device wafer DW, and then, a reaction gas may be supplied to cause chemical replacement with the adsorbed precursor, so that the release layer RL has a double-layer structure in which the precursor layer is on the lower part and the CVD layer is on the upper part. In addition, in some embodiments, a process of curing the release layer RL may be included. For example, curing of the release layer RL may include providing oxygen radicals to react with the upper part of the release layer.

[0029] The glue layer GL may include vinyl functionalized polysiloxane oligomer resin, Si-H functionalized polysiloxane oligomer resin, polysiloxane-based materials, acrylic-based materials, etc. In addition, the glue layer GL may selectively include a catalyst, an inhibitor, a curing agent, etc. The glue layer GL may include, for example, at least one of a non-conductive film (NCF), an anisotropic conductive film (ACF), an ultraviolet (UV) film, an instant adhesive, a thermosetting adhesive, a laser curable adhesive, an ultrasonic curable adhesive, and a non-conductive paste (NCP).

[0030] As from Figure 1B It is understandable that in the case of the method for manufacturing a semiconductor package according to the comparative example, in the process of debonding the carrier wafer CW from the device wafer DW, debonding may occur at the interface between the release layer RL and the device wafer DW. However, in the case of the method for manufacturing a semiconductor package according to the comparative example, because the adhesive layer ADH includes the release layer RL, there may be problems (such as initial low peel strength, expansion and cracking due to outgassing during the assembly process, and cracking occurring in the device wafer DW or the carrier wafer CW during the debonding process of the carrier wafer CW due to excessive increase in peel strength after the assembly process). Here, the peel strength may refer to the adhesion strength. Referring to Figures 3A to 3C , Figure 4B and Figure 5 Problems of the method of manufacturing a semiconductor package according to the comparative example are described in more detail.

[0031] On the other hand, in the case of the method of manufacturing a semiconductor package according to the present embodiment, the adhesive layer 300 may include only the first adhesive layer 310 and the second adhesive layer 320. In addition, the interface may be maintained between the first adhesive layer 310 and the second adhesive layer 320 that have been cured at different temperatures, thereby solving all of the above problems. For example, since the first adhesive layer 310 and the second adhesive layer 320 are bonded with a relatively high peel strength, the problem of the initial low peel strength can be solved. In addition, in the case of the first adhesive layer 310 and the second adhesive layer 320, since the outgassing phenomenon can hardly occur, the problem caused by the outgassing phenomenon of the release layer RL can be solved. In addition, since the peel strength does not increase significantly even after the assembly process, the problem of cracking in the device substrate 100 or the carrier substrate 200 during the de-bonding process of the carrier substrate 200 can be solved. As a result, the method of manufacturing a semiconductor package according to the present embodiment can solve all of the above problems and can allow a reliable semiconductor package to be manufactured.

[0032] On the other hand, the method of manufacturing a semiconductor package according to the present embodiment may be fundamentally based on the wafer support system (WSS) process. As a reference, in the WSS process, due to the recent introduction of high bandwidth memory (HBM) packages, thermocompression (TC) bonding and 2.5-dimensional (2.5D) packaging structures are increasing rapidly. In this case, the 2.5D packaging structure may be a relative concept of a three-dimensional (3D) packaging structure in which all semiconductor chips are vertically stacked without an interposer. The 2.5D packaging structure can exponentially and rapidly improve signal transmission between chips. Generally, HBM packages are manufactured by each memory company in a 3D packaging structure, and HBM packages can be combined with a graphics processing unit (GPU) in a 2.5D packaging structure.

[0033] With the recent development of artificial intelligence (AI), the number of neural processors (NPUs) / GPUs / central processing units (CPUs) / application processors (APs) that require 2.5D and / or 3D packages, along with the demand for HBM packages, is inevitably increasing. Specifically, in the case of HBM packages, the TSV process may be necessary. The TSV process may be a process of manufacturing lines that penetrate vertically up and down. Refer to Figure 2A for a more detailed description of TSV.

[0034] On the other hand, in order to perform a TSV process on a device wafer and, after the TSV process, to perform an assembly process of stacking chips on the device wafer, a process of temporarily attaching the device wafer to a carrier wafer and de-bonding the carrier wafer after the assembly process is performed. In this way, the process of attaching the carrier wafer to the device wafer to perform subsequent processes on the device wafer and then de-bonding the carrier wafer can be referred to as the WSS process.

[0035] Generally, when thinning a device wafer by using a back grinding process, warping may occur on the device wafer. Therefore, after the back grinding process, the device wafer can be pasted onto an annular frame for subsequent processes. However, as Figure 2A shown, when performing a TSV process on a device wafer, external connection terminals or bumps may be placed on the front surface of the device wafer, and thus, the device wafer may not be attachable to the annular frame. For this reason, the WSS process can be performed on the device wafer on which the TSV process has been performed.

[0036] In the WSS process, the wafer can be thinned by attaching the front surface of the device wafer including bumps to the carrier wafer with a temporary adhesive and grinding the back surface of the device wafer. Since the device wafer is bonded to the carrier wafer, the thinned device wafer can be non-bending. In addition, since the carrier wafer also has a wafer shape, subsequent processes can be performed as they are in semiconductor equipment. Therefore, an assembly process of stacking memory chips on the thinned device wafer can be performed. After the assembly process, by separating the carrier wafer from the device wafer and performing a singulation process on the annular frame, semiconductor packages can be individualized. Each of the individualized semiconductor packages can correspond to, for example, an HBM package.

[0037] As a result, WSS can be referred to as a system in which the carrier wafer is bonded before the back grinding process and subsequent processes are processed to be performed on the device wafer thinned by using the back grinding process, and WSS can be referred to as a system in which the carrier wafer is substantially bonded to the device wafer. In addition, the WSS process can include a bonding process of attaching the carrier wafer to the device wafer and a de-bonding process of separating the carrier wafer again after completion of the subsequent processes on the device wafer. On the other hand, the de-bonding process can include a process of cleaning with a cleaning solution so that no adhesive layer components remain on the wafer.

[0038] In addition, the conditions to be considered in the bonding process of the WSS process may be: uniform overall thickness of the bonded wafers, void-free at the bonding part, good alignment between the two wafers, no adhesive contamination at the edges of the wafers, and less bending of the device wafer. In addition, the considerations to be considered in the debonding process of the WSS process may be: when separating the carrier wafer, there should be no damage (such as cracking and breaking) in each of the two wafers, no adhesive layer residue left, and no bump deformation of the device wafer should occur.

[0039] The relatively difficult and important process in the WSS process may be the debonding process. Therefore, various debonding methods are being proposed and developed, and temporary adhesives suitable for each method are also being developed. For example, thermal methods, peeling methods after laser irradiation, chemical dissolution methods, chemical cleaning methods after mechanical peeling, etc. can be applied to the debonding process.

[0040] Figures 2A to 2L is a cross-sectional view showing in detail a method of manufacturing a semiconductor package by using a carrier substrate 200 according to an Figure 1A embodiment in

[0041] Referring to Figure 2A , in the method of manufacturing a semiconductor package according to the present embodiment, first, a first adhesive layer 310a may be formed on the device substrate 100a. The device substrate 100a may include a semiconductor wafer (such as a silicon wafer), but is not limited thereto. For example, the device substrate 100a may include compound semiconductors (such as silicon-on-insulator (SOI), silicon germanium, silicon carbide, and gallium arsenide). However, the material of the device substrate 100a is not limited thereto. The device substrate 100 may have a circular flat shape. Therefore, the device substrate 100a may be referred to as a device wafer.

[0042] An active region may be formed in the upper part of the device substrate 100a. Therefore, in Figure 1AIn this case, the upper surface of the device substrate 100a may correspond to the front surface as the active surface, and the lower surface of the device substrate 100a may correspond to the back surface as the passive surface. In addition, a plurality of TSVs 110 penetrating the active region may be formed inside the device substrate 100a. An integrated circuit may be formed in the active region. The integrated circuit may include, for example, memory devices (such as dynamic random access memory (RAM) (DRAM), static RAM (SRAM), and flash memory). In addition, the integrated circuit may include logic devices constituting a central processing unit (CPU), a digital signal processor (DSP), a processor combining a CPU and a DSP, an application specific integrated circuit (ASIC), a microelectromechanical system (MEMS) device, an optoelectronic device, etc., and combinations of logic devices. By performing an individualized process on the device substrate 100 in a subsequent process, the memory device or the logic device of the device substrate 100a may be separated into a semiconductor chip shape. For example, in the method of manufacturing a semiconductor package according to the present embodiment, the device substrate 100a may include a plurality of semiconductor chips and may be separated into individual semiconductor chips by performing an individualized process. In addition, each of the semiconductor chips of the device substrate 100a may include a logic device. For example, each of the semiconductor chips of the device substrate 100a may include a buffer chip or a control chip.

[0043] The TSV 110 may be formed by forming a through hole having a specific depth from the upper surface to the lower surface of the device substrate 100a and then filling the through hole with a conductive material. For example, the through hole may be formed by using a deep reactive ion etching (DRIE) process. The TSV 110 may have a columnar shape and may include a barrier layer on the surface and a buried conductive layer in the TSV 110. The barrier layer may include at least one material selected from Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and NiB. The buried conductive layer may include at least one material selected from Cu, Cu alloys (such as CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, and CuW), W, W alloys, Ag, Au, Al, In, Ni, Ru, and Co. On the other hand, a via insulating layer may be disposed between the TSV 110 and the device substrate 100a. The via insulating layer may include oxides, nitrides, carbides, polymers, or combinations thereof.

[0044] After forming the TSV 110, pads may be formed on the exposed surface of the TSV 110 on the upper surface of the device substrate 100a. The pads may include at least one of Al, Cu, Ni, W, Pt, and Au. On the other hand, a protective layer may be formed on the upper surface of the device substrate 100a, and the TSV 110 or the pads may penetrate the protective insulating layer. In some embodiments, a redistribution layer or a redistribution layer may be formed on the upper part of the device substrate 100a. In this case, separate pads may be formed on the redistribution layer or the redistribution layer. In addition, the TSV 110 may be connected to the distribution elements of the redistribution layer or the redistribution layer, and may be connected to the pads via the distribution elements of the redistribution layer or the redistribution layer. On the other hand, in some embodiments, the TSV 110 may also be formed in a structure that penetrates the redistribution layer.

[0045] External connection terminals 120 may be disposed on the pads. The external connection terminals 120 may include pillars and solder layers. In some embodiments, the external connection terminals 120 may also include only the solder layer. The pillars may include, for example, Ni, Cu, Pd, Pt, Au, or a combination thereof. According to an embodiment, a diffusion barrier layer and / or an adhesion layer may be formed between the pillar and the solder layer. The solder layer may be disposed on the pillar and may have a spherical shape or a ball shape. The solder layer may include at least one of, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and their alloys. For example, the solder layer may include at least one of Sn, Pb, Sn-Pb, Sn-Ag, Sn-Au, Sn-Cu, Sn-Bi, Sn-Zn, Sn-Ag-Cu, Sn-Ag-Bi, Sn-Ag-Zn, Sn-Cu-Bi, Sn-Cu-Zn, Sn-Bi-Zn, etc. On the other hand, according to an embodiment, an intermediate layer (such as an intermetallic compound (IMC)) may be formed on the contact interface between the solder layer and the pillar.

[0046] The first glue layer 310a may be formed by applying a liquid glue on the device substrate 100a via a spin coating method. As Figure 2A shown, the first glue layer 310a may be formed to completely cover the external connection terminals 120. For example, the first glue layer 310a may be formed to have a thickness of about 50 μm or more. However, the thickness of the first glue layer 310a is not limited thereto.

[0047] The first adhesive layer 310a may include vinyl-functionalized polysiloxane oligomer resin, Si-H-functionalized polysiloxane oligomer resin, polysiloxane-based materials, acrylic materials, etc. In addition, the first adhesive layer 310a may selectively include a catalyst, a polymerization inhibitor, a curing agent, etc. The first adhesive layer 310a may include at least one of, for example, a non-conductive film (NCF), an anisotropic conductive film (ACF), an ultraviolet (UV) film, an instant adhesive, a thermosetting adhesive, a laser-curable adhesive, an ultrasonic-curable adhesive, and a non-conductive paste (NCP). However, the material of the first adhesive layer 310a is not limited thereto. In the method for manufacturing a semiconductor package according to the present embodiment, the first adhesive layer 310a may include, for example, a curing agent and may be hardened by curing at a specific temperature.

[0048] Referring to Figure 2B , after the first adhesive layer 310a is formed, the first curing 1st-C may be performed. In the method for manufacturing a semiconductor package according to the present embodiment, the temperature of the first curing 1st-C may be about 160°C to about 180°C. However, the temperature of the first curing 1st-C is not limited thereto. The first adhesive layer 310 that is hardened by using the first curing 1st-C may be formed.

[0049] Referring to Figure 2C , after the first curing 1st-C is performed, the second adhesive layer 320a may be formed on the first adhesive layer 310. The second adhesive layer 320a may also be formed by applying a liquid adhesive on the first adhesive layer 310 via a spin coating method. As Figure 2C shown, the second adhesive layer 320a may be formed thinner than the first adhesive layer 310. For example, the second adhesive layer 320a may be formed thinner than the first adhesive layer 310 with a thickness of about 50 μm or less. However, the thickness of the second adhesive layer 320a is not limited thereto.

[0050] On the other hand, the second adhesive layer 320a may include substantially the same material as the first adhesive layer 310. For example, in the method for manufacturing a semiconductor package according to the present embodiment, the second adhesive layer 320a, like the first adhesive layer 310a, may include a curing agent and may be hardened by curing at a specific temperature. However, since the second adhesive layer 320a has not been cured, as Figure 2C shown, an interface IF may be formed between the hardened first adhesive layer 310 and the liquid second adhesive layer 320a.

[0051] Referring to Figure 2D, after forming the second adhesive layer 320a, the carrier substrate 200 can be adhered to the second adhesive layer 320a to bond the carrier substrate 200 to the device substrate 100a. The carrier substrate 200 can include silicon, glass, ceramics, organic materials, or plastics. However, the material of the carrier substrate 200 is not limited thereto. The carrier substrate 200 can have a circular flat shape. Thus, the carrier substrate 200 can also be referred to as a carrier wafer.

[0052] The carrier substrate 200 can have a diameter larger than that of the device substrate 100a. In addition, the carrier substrate 200 can have a thickness larger than that of the device substrate 100a. However, in some embodiments, the carrier substrate 200 can have substantially the same diameter as the device substrate 100a. In addition, before the device substrate 100a is thinned, the carrier substrate 200 can also have substantially the same thickness as the device substrate 100a. Hereinafter, the structure in which the carrier substrate 200 is bonded to the device substrate 100a can be referred to as a "bonding structure". In this case, the bonding structure can correspond to the above-mentioned WSS. For example, there may be no release layer between the device substrate 100a and the carrier substrate 200.

[0053] Referring to Figure 2E , after forming the bonding structure, a second curing 2nd-C can be performed. In the method of manufacturing a semiconductor package according to the present embodiment, the temperature of the first curing 1st-C and the temperature of the second curing 2nd-C can be different from each other. For example, the temperature of the second curing 2nd-C can be higher than the temperature of the first curing 1st-C. The temperature of the second curing 2nd-C can be about 190°C to about 220°C. However, the temperature of the second curing 2nd-C is not limited thereto. The second adhesive layer 320 can be formed by hardening via the second curing 2nd-C. On the other hand, when the first adhesive layer 310 and the second adhesive layer 320 are hardened at different curing temperatures, the interface between the first adhesive layer 310 and the second adhesive layer 320 can be maintained even after the second curing 2nd-C.

[0054] Referring to Figure 2F , after the second curing 2nd-C, the device substrate 100a can be thinned by using a thinning process. The bonding structure can be flipped so that the carrier substrate 200 is at the lower part and the device substrate 100 is at the upper part. The process of flipping the bonding structure can correspond to the process of actually placing the bonding structure on the substrate chuck of the back grinding B-G process. For example, the unbonded surface of the carrier substrate 200 can be mounted on the upper surface of the substrate chuck. Thereafter, by removing the back surface portion (i.e., a part of the passive layer portion) of the device substrate 100a via the back grinding B-G process, the device substrate 100a can be thinned so that the device substrate 100 can be formed.

[0055] As can be seen from Figure 2FVisibly, the upper surface of the TSV 110 can be exposed on the upper surface of the device substrate 100 by using a back grinding B-G process. On the other hand, when the bonding structure is turned upside down, Figure 2F the positions of the upper surface and the lower surface in Figure 2F can be exchanged with each other compared to the positions of the upper surface and the lower surface in the previous figures. For example, in

[0056] Referring to Figure 2G , after the thinning process, a back surface protection layer 130 can be formed on the upper surface of the device substrate 100. The back surface protection layer 130 can include a dielectric layer (such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer). In addition, the back surface protection layer 130 can be formed in a multi-layer structure (such as a silicon oxide layer / silicon nitride layer / silicon oxide layer).

[0057] On the other hand, a back surface pad 110p can be formed on the upper surface of the TSV 110. The back surface pad 110p can be formed in a structure that penetrates the back surface protection layer 130. In some embodiments, the TSV 110 can penetrate the back surface protection layer 130, and the back surface pad 110p can be formed on the upper surface of the TSV 110 and the back surface protection layer 130. The back surface pad 110p can include substantially the same material as the TSV. Optionally, according to an embodiment, the back surface pad 110p can include a conductive material different from the conductive material of the TSV.

[0058] Referring to Figure 2H , thereafter, an assembly process can be performed on the device substrate 100. In this case, the assembly process can represent a process of stacking chips on each of the chips in the device substrate 100. Hereinafter, the chips in the device substrate 100 can be referred to as "first semiconductor chips (refer to 100c in Figure 2L ), and the chips stacked on the first semiconductor chips 100c can be referred to as "second semiconductor chips 140". For reference, the device substrate 100 can include a plurality of first semiconductor chips 100c. In addition, a plurality of second semiconductor chips 140 can be stacked on each of the first semiconductor chips 100c. For example, a stack of second semiconductor chips 140 can be formed on each of the plurality of first semiconductor chips 100c. For example, in the method of manufacturing a semiconductor package according to the present embodiment, the first semiconductor chips 100c and the plurality of second semiconductor chips 140 on the first semiconductor chips 100c can constitute an HBM package.

[0059] To briefly describe the HBM package, the HBM package can include the first semiconductor chips 100c, the plurality of second semiconductor chips 140, and a sealing material (refer to Figure 2IAmong them (180). The first semiconductor chip 100c may include, for example, a buffer chip or a control chip. In addition, each of the second semiconductor chips 140 may include a memory chip (e.g., a DRAM chip). The first semiconductor chip 100c as a buffer chip may be disposed at the lowermost part of the HBM package, integrating the signals of the second semiconductor chips 140 to send them to the outside, and additionally sending signals and power from the outside to the second semiconductor chips 140.

[0060] As Figure 2H shown, the first semiconductor chip 100c and the second semiconductor chips 140 may include TSVs 110 and 150. However, the uppermost second semiconductor chip 140 among the second semiconductor chips 140 may not include a TSV. In the method of manufacturing a semiconductor package according to the present embodiment, four second semiconductor chips 140 are stacked on the first semiconductor chip 100c, but the number of the second semiconductor chips 140 is not limited thereto. For example, two, three, five or more second semiconductor chips 140 may be stacked on the first semiconductor chip 100c. On the other hand, the external connection terminals 120 may be disposed on the lower surface of the first semiconductor chip 100c. In addition, the bumps 160 and the chip bonding layer 170 may be disposed between the first semiconductor chip 100c and the second semiconductor chips 140 and between the second semiconductor chips 140 adjacent to each other. The encapsulant 180 may cover and seal the second semiconductor chips 140 on the first semiconductor chip 100c. Refer to Figure 2I to describe the encapsulant 180 in more detail.

[0061] In the assembly process, the second semiconductor chips 140 may be stacked on the first semiconductor chip 100c or the underlying second semiconductor chips 140 by using the bumps 160 and the chip bonding layer 170. In the process of stacking the second semiconductor chips 140, the second semiconductor chips 140 may be stacked by using a thermocompression bonding (TCB) method. For example, in the thermocompression bonding (TCB) method, heat and compression may be applied to the second semiconductor chips 140 on the first semiconductor chip 100c. In addition, in the TCB method, the chip bonding layer 170 may include, for example, NCF.

[0062] Refer to Figure 2I , after the second semiconductor chips 140 are stacked on the first semiconductor chip 100c, the second semiconductor chips 140 on the device substrate 100 may be sealed with the encapsulant 180. In some embodiments, the process of sealing with the encapsulant 180 may also be included in the assembly process.

[0063] The encapsulant 180 can cover and encapsulate the second semiconductor chip 140 and the chip bonding layer 170 on the first semiconductor chip 100c. The encapsulant 180 can encapsulate the second semiconductor chip 140 to protect the second semiconductor chip 140 from external physical and chemical damage. The encapsulant 180 can include, for example, an epoxy molding compound (EMC). However, the encapsulant 180 is not limited thereto, and can include various materials (such as epoxy-based materials, thermosetting materials, thermoplastic materials, and UV curable materials). In addition, the encapsulant 180 can include a resin and can contain fillers.

[0064] The encapsulant 180 can encapsulate all of the second semiconductor chips 140 on the device substrate 100. In other words, the encapsulation process using the encapsulant 180 can be performed at the wafer level. In addition, as Figure 2I shown, the encapsulant 180 can cover the upper surface of the second semiconductor chip 140 disposed at the uppermost portion. However, the encapsulant 180 is not limited thereto, but can also not cover the upper surface of the uppermost second semiconductor chip 140. In other words, the upper surface of the uppermost second semiconductor chip 140 can be exposed on the encapsulant 180.

[0065] Refer to Figure 2J and Figure 2K After the encapsulant 180 is formed, the carrier substrate 200 can be separated from the device substrate 100. The method of separating the carrier substrate 200 can use, for example, a chemical cleaning method after a mechanical peeling process. However, the method of separating the carrier substrate 200 is not limited thereto. For example, a thermal method, a peeling method after laser irradiation, a chemical dissolution method, etc. can be used as the method of separating the carrier substrate 200.

[0066] Figure 2J shows a process of mechanically peeling the carrier substrate 200 using a blade 400. Although not shown, the device substrate 100, the second semiconductor chip 140, and the encapsulant 180 can be fixed to a vacuum chuck (refer to 500 in Figure 4A ).

[0067] Figure 2K shows a state in which the first adhesive layer 310 has been removed from the device substrate 100 after cleaning the device substrate 100 with a cleaning liquid. By removing the first adhesive layer 310, the external connection terminals 120 can be presented as protruding on the front surface of the device substrate 100.

[0068] Refer to Figure 2L, by using a singulation S process (such as a sawing process or a dicing process) to individualize the device substrate 100 and the upper structural members of the device substrate 100, a plurality of semiconductor packages 1000 can be formed. Each of the semiconductor packages 1000 can correspond to, for example, an HBM package. Accordingly, each of the semiconductor packages 1000 can include a first semiconductor chip 100c, a plurality of second semiconductor chips 140, external connection terminals 120, and a sealing material 180.

[0069] Although the process of manufacturing an HBM package has been described so far, the method of manufacturing a semiconductor package according to the present embodiment is not limited thereto. For example, the method of manufacturing a semiconductor package according to the present embodiment can be applied to all methods of manufacturing a semiconductor package that can be manufactured by using WSS.

[0070] Figures 3A to 3C are cross-sectional views and graphs for explaining problems in a method of manufacturing a semiconductor package by using a carrier substrate 200 in a comparative example according to Figure 1B . Figure 3B is a graph related to outgassing of the release layer RL, Figure 3C is a graph related to outgassing of the device wafer D-W.

[0071] Referring to Figure 3A , in the method of manufacturing a semiconductor package according to the comparative example, as a result of the TCB process in the assembly process after the thinning process of the device wafer D-W, Chip Warp (chip warp) and Wafer Warp (wafer warp) may occur in the carrier wafer C-W and the core chip C-C. In addition, as a result of the warping, peeling may occur at the interface between the device wafer D-W and the release layer RL, and during or after the TCB process after the peeling, swelling and / or cracking may occur in the device wafer D-W or the core chip C-C. In Figure 3A , part A where peeling is likely to occur is indicated by a circular dotted line.

[0072] The peeling phenomenon may be due to the low initial peeling strength at the release layer RL before the assembly process. Various conditions have been changed to increase the initial peeling strength of the release layer RL and reduce the increase in the peeling strength after the thermal process (i.e., after the assembly process), but the problem of the initial low peeling strength has not been solved. For reference, after the thermal process of the assembly process, the peeling strength of the release layer RL may increase excessively, and the high peeling strength of the release layer RL may cause cracking problems in the device wafer D-W or the carrier wafer C-W during the separation process of the carrier wafer C-W. Relative to Figures 4A to 5 to describe in more detail the problems caused by the high peeling strength of the release layer RL during the separation process of the carrier wafer C-W.

[0073] Due to the TCB process in the assembly process, heat may be transferred to the device wafer D-W. As a result, outgassing may occur in the buffer chip of the device wafer D-W and the release layer RL. The outgassing in the buffer chip and the release layer RL may cause expansion and / or cracking in the device wafer D-W or the core chip C-C together with the above-mentioned warping.

[0074] Referring to Figure 3B , the dotted line in the vertical direction in the graph may represent the volatilization temperature Vol, and it can be confirmed that the mass of the release layer RL rapidly decreases due to outgassing at a temperature equal to or higher than the volatilization temperature Vol. Generally, the TCB process may be performed at a high temperature (such as about 200 °C to about 300 °C) that usually exceeds the volatilization temperature Vol. Therefore, a large amount of outgassing may occur in the release layer RL. Various methods (such as reducing the thickness of the release layer RL and changing the material of the release layer RL) are being proposed to reduce the outgassing of the release layer RL.

[0075] Referring to Figure 3C , in the case of the device wafer D-W, moisture absorption may occur naturally, and the absorbed moisture may be outgassed during the TCB process. In Figure 3C , it can be confirmed that as the temperature increases, the evaporation rate rapidly increases in a shorter time. Therefore, in order to remove the moisture pre-absorbed before the assembly process, a dehumidification baking process may be applied.

[0076] In the case of the method for manufacturing a semiconductor package according to the present embodiment, since only two adhesive layers 310 and 320 are used without the release layer RL, the problems of the low peel strength of the initial release layer RL, outgassing from the release layer RL, and the high peel strength of the release layer RL during the separation process of the carrier wafer C-W can all be limited and / or solved.

[0077] Figure 4A and Figure 4B are respectively conceptual diagrams for explaining the process of separating the carrier substrate in the method for manufacturing a semiconductor package by using a carrier substrate according to the embodiment of Figure 1A and in the method for manufacturing a semiconductor package by using a carrier substrate according to the comparative example of Figure 1B .

[0078] Referring to Figure 4A , in the method for manufacturing a semiconductor package according to the present embodiment, a chemical cleaning method may be used after mechanical peeling during the separation process of the carrier substrate 200. Figure 4AThe mechanical stripping process is conceptually shown. The combined structure that has completed the assembly process and the sealing material process can be fixed to the vacuum chuck 500 via the use of vacuum adsorption. The lower surface of the sealing material of the combined structure can be placed on the vacuum chuck 500 to be vacuum adsorbed. On the other hand, the flexible board 600 can be combined to the upper surface of the carrier substrate 200, and the blade 400 combined to the flexible board 600 can be inserted into the adhesive layer 300 of the combined structure. Thereafter, when the flexible force FF is applied to the flexible board 600 in the vertical direction, and the roller force RF is additionally applied to the flexible board 600 via the roller 700, the carrier substrate 200 can be separated from the device substrate 100 in the moving direction of the roller 700.

[0079] In the separation process of the carrier substrate 200, as Figure 4A As shown in FIG. 1 , separation may occur at the interface IF between the first adhesive layer 310 and the second adhesive layer 320. In other words, in the adhesive layer 300, the adhesive force at the interface IF between the first adhesive layer 310 and the second adhesive layer 320 may be the lowest, and thus, in the separation process of the carrier substrate 200, separation may occur at the interface IF. In addition, due to the low peel strength at the interface IF, the problem of cracks occurring in the carrier substrate 200 or the device substrate 100 during the separation process of the carrier substrate 200 may be solved. In addition, because Figure 4A The chemical cleaning process has not been performed yet, so the first glue layer 310 on the device substrate 100 can remain intact.

[0080] Reference Figure 4B , even in the case of the method of manufacturing a semiconductor package according to the comparative example, a chemical cleaning method may be used after mechanical peeling in the separation process of the carrier wafer CW. Figure 4A As described above, a mechanical peeling process may be performed. However, in the case of the method for manufacturing a semiconductor package according to the comparative example, the adhesive layer ADH may include a glue layer GL and a release layer RL. In addition, the separation process of the carrier wafer CW may include a process after a thermal process caused by an assembly process occurs, and as a result, the peeling strength of the release layer RL may be too high. Therefore, in the separation process of the carrier wafer CW, cracks may occur in the carrier wafer CW or the device wafer DW. For reference, in Figure 4B PKG may denote a package including a device wafer and a core chip, VC may denote a vacuum chuck, FP may denote a flexible board, BL may denote a blade, and RR may denote a roller.

[0081] Figure 5 It is shown that according to Figure 1A In a method of manufacturing a semiconductor package by using a carrier substrate according to an embodiment of the present invention, and in a method of manufacturing a semiconductor package by using a carrier substrate according to Figure 1BGraph of the change in peel strength in the method of manufacturing a semiconductor package using a carrier substrate for a comparative example. The x-axis may represent the heat treatment temperature for a time period of about 1 hour, and the y-axis may represent the peel strength. Further, only the adhesive may correspond to the method of manufacturing a semiconductor package according to an embodiment, and w / RL may correspond to the method of manufacturing a semiconductor package according to a comparative example.

[0082] Referring Figure 5 , in the case of the method of manufacturing a semiconductor package according to the present embodiment, the adhesive layer 300 may include only the first adhesive layer 310 and the second adhesive layer 320. Further, the interface IF may be maintained between the first adhesive layer 310 and the second adhesive layer 320 cured at different temperatures. Accordingly, compared to the state where heat treatment has not been performed, after heat treatment at about 200°C for about 1 hour, the increase in peel strength may be as low as (24.3 - 20.9) / 20.9×100% = 16%. Further, in the case of the method of manufacturing a semiconductor package according to an embodiment, compared to the adhesion between the first adhesive layer 310 and the second adhesive layer 320 before the thermal process (e.g., the TCB process including application of heat and compression) of the assembly process is performed, performing the thermal process (e.g., application of heat and compression) may increase the adhesion between the first adhesive layer 310 and the second adhesive layer 320 by an amount greater than 0% and less than or equal to 20%.

[0083] On the other hand, in the case of the method of manufacturing a semiconductor package according to a comparative example, the adhesive layer ADH may include a release layer RL and an adhesive layer GL. Accordingly, compared to the state where heat treatment has not been performed, after heat treatment at about 200°C for about 1 hour, the increase in peel strength may be very high, being (10.0 - 3.8) / 3.8×100% = 163%. Further, although not shown in the graph, when the adhesive layer ADH is heat treated at about 250°C or higher for about 1 hour, the peel strength of the adhesive layer ADH may rapidly increase.

[0084] On the other hand, the state where the heat treatment is not performed may correspond to the initial state where the assembly process has not been performed, and the heat treatment continued at 200 °C or higher temperature for about 1 hour may correspond to the thermal process of the assembly process. In the state where the heat treatment has not been performed, the peel strength of the adhesive layer 300 of the method for manufacturing a semiconductor package according to the embodiment may be about 20.9 N / m, and the peel strength of the adhesive layer ADH of the method for manufacturing a semiconductor package according to the comparative example may be about 3.8 N / m. Therefore, it can be confirmed that the initial peel strength of the adhesive layer 300 according to the embodiment is higher than that of the adhesive layer 300 according to the comparative example by (20.9 - 3.8) / 3.8×100% = 450%. Therefore, the method for manufacturing a semiconductor package according to the embodiment can solve the peeling and problems related to the peeling caused by low peel strength. In addition, in the method for manufacturing a semiconductor package according to the present embodiment, since only the adhesive layer 300 including the first adhesive layer 310 and the second adhesive layer 320 has a low change in peel strength after the thermal process, the problem of cracking occurring in the carrier substrate 200 or the device substrate 100 during the separation process of the carrier substrate 200 can be solved.

[0085] Figures 6A to 6D is a cross-sectional view showing a method for manufacturing a semiconductor package by using a carrier substrate 200 according to an embodiment. The repeated descriptions given with reference to Figures 2A to 2L are briefly described or omitted.

[0086] With reference to Figure 6A , in the method for manufacturing a semiconductor package according to the present embodiment, first, a first adhesive layer 310a may be formed on the device substrate 100a. The process of forming the first adhesive layer 310a on the device substrate 100a may be the same as the process of forming the first adhesive layer 310a on the device substrate 100a described with reference to Figure 2A .

[0087] With reference to Figure 6B , after the first adhesive layer 310a is formed, a first curing 1st-C may be performed. In the method for manufacturing a semiconductor package according to the present embodiment, the temperature of the first curing 1st-C may be about 160 °C to about 180 °C. However, the temperature of the first curing 1st-C is not limited thereto. The first adhesive layer 310 that can be cured by using the first curing 1st-C may be formed.

[0088] With reference to Figure 6C, after the first curing 1st-C, a surface treatment may be performed on the upper surface of the first adhesive layer 310. In the method of manufacturing a semiconductor package according to the present embodiment, the surface treatment of the first adhesive layer 310 may include plasma treatment P-P. By using the plasma treatment P-P, the surface curvature (i.e., surface roughness) of the first adhesive layer 310 may be adjusted. For example, by increasing the surface roughness via using the plasma treatment P-P, the peel strength with respect to the second adhesive layer 320 may be enhanced in a subsequent process. Conversely, by decreasing the surface roughness via using the plasma treatment P-P, the peel strength with respect to the second adhesive layer 320 may be decreased.

[0089] On the other hand, in the method of manufacturing a semiconductor package of the present embodiment, plasma treatment P-P has been described for the surface treatment, but the surface treatment is not limited thereto. For example, the surface treatment may include chemical treatment, physical treatment, etc. of the upper surface of the first adhesive layer 310.

[0090] Referring to Figure 6D , after the plasma treatment P-P, a second adhesive layer 320a may be formed on the first adhesive layer 310. The second adhesive layer 320a may also be formed by coating a liquid adhesive on the first adhesive layer 310 via using a spin coating method. The process of forming the second adhesive layer 320a may be the same as the process of forming the second adhesive layer 320a described with reference to Figure 2C .

[0091] On the other hand, in the method of manufacturing a semiconductor package of the present embodiment, the second adhesive layer 320a may include substantially the same material as the first adhesive layer 310. For example, like the first adhesive layer 310a, the second adhesive layer 320a may also contain a curing agent and may be hardened by curing.

[0092] After forming the second adhesive layer 320a, a semiconductor package may be manufactured by performing the operations in Figures 2D to 2L . The method of manufacturing a semiconductor package of the present embodiment may further include a surface treatment (e.g., plasma treatment P-P) of the first adhesive layer 310. Therefore, the adhesion between the first adhesive layer 310 and the second adhesive layer 320 may be adjusted. Therefore, it may be feasible to flexibly cope with the initial low adhesion problem and the excessive increase in adhesion after a thermal process. As a result, a reliable semiconductor package may be manufactured.

[0093] Although the inventive concept has been specifically shown and described with reference to embodiments of the inventive concept, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for manufacturing a semiconductor package, the method using a carrier substrate, the method comprising: forming a first glue layer on the device substrate; forming a second adhesive layer on the first adhesive layer; bonding the device substrate to the carrier substrate by bonding a second glue layer to the carrier substrate; thinning the device substrate by grinding the device substrate; After thinning the device substrate, stacking a first semiconductor chip on the device substrate; as well as The carrier substrate is separated from the device substrate at an interface between the first glue layer and the second glue layer.

2. The method according to claim 1, further comprising: After forming the first adhesive layer, curing the first adhesive layer at a first temperature; as well as After bonding the device substrate to the carrier substrate, the second glue layer is cured at a second temperature.

3. The method according to claim 2, wherein: The first adhesive layer and the second adhesive layer include the same material, and The first temperature and the second temperature are different from each other.

4. The method according to claim 2, wherein: The first temperature is 160°C to 180°C, and The second temperature is 190°C to 220°C.

5. The method according to claim 2, further comprising: After curing the first glue layer at the first temperature, plasma treatment is performed on a surface of the first glue layer.

6. The method according to claim 1, wherein: There is no release layer between the device substrate and the carrier substrate.

7. The method according to claim 1, wherein: The device substrate includes a plurality of second semiconductor chips, and The step of stacking the first semiconductor chips includes forming a stack of the first semiconductor chips on each of the plurality of second semiconductor chips.

8. The method according to claim 7, wherein: The step of stacking the first semiconductor chip includes applying heat and compression to the first semiconductor chip on the device substrate, and Applying heat and compression increases adhesion between the first adhesive layer and the second adhesive layer by an amount greater than 0% and less than or equal to 20% compared to adhesion between the first adhesive layer and the second adhesive layer before applying heat and compression.

9. The method according to claim 7, further comprising: After stacking the first semiconductor chip on the device substrate, the first semiconductor chip on the device substrate is sealed with a sealing material.

10. The method according to claim 9, further comprising: After separating the carrier substrate, forming a semiconductor package from the device substrate and the first semiconductor chip, Each of the semiconductor packages includes a corresponding second semiconductor chip among the plurality of second semiconductor chips and a corresponding stack of first semiconductor chips on the corresponding second semiconductor chip among the plurality of second semiconductor chips.

11. The method according to claim 10, wherein: Each of the semiconductor packages includes a high bandwidth memory package, Each of the first semiconductor chips includes a memory chip, and Each of the plurality of second semiconductor chips includes a buffer chip.

12. A method of manufacturing a semiconductor package, the method using a carrier substrate, the method comprising: forming a first glue layer on the device substrate; curing the first adhesive layer at a first temperature; forming a second adhesive layer on the first adhesive layer; bonding the device substrate to the carrier substrate by bonding the carrier substrate to the second glue layer; curing the second adhesive layer at a second temperature higher than the first temperature; thinning the device substrate by grinding the device substrate; stacking a plurality of first semiconductor chips on a device substrate; sealing the plurality of first semiconductor chips on the device substrate with a sealing material; as well as separating the carrier substrate from the device substrate at the interface between the first glue layer and the second glue layer, The first adhesive layer and the second adhesive layer include the same material.

13. The method according to claim 12, wherein: The device substrate includes a plurality of second semiconductor chips, and The step of stacking the plurality of first semiconductor chips includes forming a stack of the plurality of first semiconductor chips on each of the plurality of second semiconductor chips.

14. The method according to claim 13, further comprising: After separating the carrier substrate, a semiconductor package is formed from the device substrate and the plurality of first semiconductor chips.

15. The method according to claim 14, wherein: Each of the semiconductor packages includes a high bandwidth memory package, and A high bandwidth memory package includes: corresponding stacks of the plurality of first semiconductor chips on corresponding second semiconductor chips among the plurality of second semiconductor chips, a sealing material sealing the corresponding stacks of the plurality of first semiconductor chips, and external connection terminals below the lower surface of the corresponding second semiconductor chip among the plurality of second semiconductor chips.

16. A method of manufacturing a semiconductor package, the method using a carrier substrate, and the method comprising: forming a first glue layer and a second glue layer on the device substrate, wherein the first glue layer and the second glue layer include the same material and are cured at different temperatures to form an interface between the first glue layer and the second glue layer; bonding the device substrate to the carrier substrate by bonding the carrier substrate to the second glue layer; thinning the device substrate by grinding the device substrate; stacking a first semiconductor chip on a device substrate; as well as The carrier substrate is separated from the device substrate at an interface between the first glue layer and the second glue layer.

17. The method according to claim 16, wherein: The steps of forming the first adhesive layer and the second adhesive layer include: forming a first glue layer by coating glue on the device substrate; curing the first adhesive layer at a first temperature; forming a second glue layer by coating the glue on the first glue layer; and After bonding the device substrate to the carrier substrate, the second glue layer is cured at a second temperature, the second temperature being higher than the first temperature.

18. The method according to claim 17, further comprising: Before forming the first glue layer and the second glue layer on the device substrate, external connection terminals are arranged on the device substrate. In the step of forming the first glue layer, the first glue layer is formed to cover the external connection terminals.

19. The method according to claim 16, wherein: No release layer is formed on the device substrate.

20. The method of claim 16, further comprising: After stacking the first semiconductor chip, sealing the first semiconductor chip on the device substrate with a sealing material; as well as After separating the device substrate, a semiconductor package is formed from the device substrate and the first semiconductor chip, wherein: The device substrate includes a plurality of second semiconductor chips, The step of stacking the first semiconductor chips includes: forming a stack of the first semiconductor chips on each of the second semiconductor chips, and The semiconductor packages each include corresponding ones of the second semiconductor chips.

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