Chip, manufacturing method thereof and semiconductor packaging piece with chip

Abstract

The chip of the present invention comprises: a top surface; a plurality of side surfaces; the bottom surface is connected with the plurality of side surfaces; the circuit layer is formed on the bottom surface; the platform surrounds the top face and is parallel to the top face and the bottom face, the distance between the platform and the bottom face is smaller than that between the top face and the bottom face, and the platform is perpendicularly connected with the side faces. The invention also provides a method for manufacturing the chip and a semiconductor package with the chip.

Description

Technical Field

[0001] The present invention relates to a chip, a manufacturing method thereof, and a semiconductor package having the chip, and more particularly to a chip that can prevent separation from a molding layer, a manufacturing method thereof, and a semiconductor package having the chip. Background Art

[0002] Please refer to Figure 1 , there is a semiconductor package made by a flip chip technology, which includes a chip 110 disposed on a substrate 120. A circuit layer 116 is provided on the front surface of the chip 110, and it is electrically connected to the substrate 120 by a plurality of metal bumps 130. A molding layer 140 is further formed on the substrate 120, which covers a plurality of side surfaces of the chip 110 and does not cover the top surface of the chip 110.

[0003] A heat sink (not shown) can be disposed on the top of the above semiconductor package to help the chip 110 dissipate heat. However, since the molding layer 140 does not cover the top of the chip 110, the difference in the coefficient of thermal expansion between the chip 110 and the molding layer 140 causes the side surface of the chip 110 to be easily separated from the molding layer 140. Summary of the Invention

[0004] In view of this, the present invention provides a chip, a manufacturing method thereof, and a semiconductor package having the chip to solve the above problems.

[0005] To achieve the above object, the chip of the present invention includes: a top surface; a plurality of side surfaces; a bottom surface connecting the plurality of side surfaces; a circuit layer formed on the bottom surface; and a platform surrounding the top surface and parallel to the top surface and the bottom surface, the distance from the platform to the bottom surface is less than the distance from the top surface to the bottom surface, and the platform is perpendicularly connected to the plurality of side surfaces.

[0006] The semiconductor package of the present invention includes: a substrate; the above chip disposed on the substrate; a plurality of bumps disposed between the substrate and the bottom surface of the chip and electrically connected to the circuit layer of the chip; and a molding layer formed on the substrate and covering the plurality of side surfaces and the platform of the chip, wherein the molding layer exposes the top surface of the chip.

[0007] The manufacturing method of the chip of the present invention includes: providing a wafer having a front surface and a back surface opposite to the front surface, wherein a circuit layer is provided on the front surface; grinding the back surface of the wafer with a grinding wheel to thin the wafer to a predetermined thickness; forming a plurality of grooves on the back surface of the wafer; and using a tool to cut the wafer from the front surface of the wafer and cut to the position of the plurality of grooves.

[0008] According to the semiconductor package of the present invention, since the molding layer covers the platform, it hooks the chip like a hook, making it not easy to separate from the molding layer.

[0009] In order to make the above and other objects, features, and advantages of the present invention more apparent, the following specific embodiments of the present invention are given below, and in conjunction with the accompanying drawings, a detailed description is provided as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of various components can be arbitrarily increased or decreased.

[0011] Figure 1 Schematic diagram of an existing semiconductor package.

[0012] Figure 2 Schematic diagram of the semiconductor package of the present invention.

[0013] Figures 3 to 8 Show Figure 2 The manufacturing method of the chip in.

[0014] Symbol description:

[0015] 110 Chip

[0016] 116 Circuit layer

[0017] 120 Substrate

[0018] 130 Bump

[0019] 140 Molding layer

[0020] 210 Chip

[0021] 211 Top surface

[0022] 212 Bottom surface

[0023] 213 Side surface

[0024] 216 Circuit layer

[0025] 220 Substrate

[0026] 230 Bump

[0027] 240 Molding layer

[0028] 241 Top surface

[0029] 242 Bottom surface

[0030] 250 Platform

[0031] 253 Outer peripheral edge

[0032] 260 Heat sink

[0033] 270 solder balls

[0034] 310 wafers

[0035] 311 back side

[0036] 312 front side

[0037] 316 circuit layer

[0038] 360 protective film

[0039] 370 grooves

[0040] 391 grinding wheel

[0041] 392 cutting tool

[0042] d depth

[0043] D thickness

[0044] W1 width

[0045] W2 thickness Detailed implementation manners

[0046] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first component above or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component such that the first component and the second component are not in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0047] In addition, spatial relative terms such as "underlying", "below", "lower", "overlying", "upper", and the like may be used herein for ease of description to describe the relationship of one component or element to another or other components or elements as illustrated in the figures. Except for the orientation depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0048] In the present invention, the symbol ">" means greater than; the symbol "<" means less than; the symbol "≧" means greater than or equal to; the symbol "≦" means less than or equal to.

[0049] Please refer toFigure 2 , the semiconductor package of the present invention includes a chip 210, which is disposed on a substrate 220 and electrically connected to the substrate 220 by a plurality of metal bumps 230.

[0050] Specifically, the chip 210 has opposite top surface 211, bottom surface 212 and a plurality of side surfaces 213, wherein the bottom surface 212 is the active surface and is provided with a circuit layer 216 thereon. The top surface 211 and the bottom surface 212 are located in different planes. The bottom surface 212 is perpendicularly connected to the plurality of side surfaces 213. The circuit layer 216 of the chip 210 is electrically connected to the substrate 220 by the plurality of metal bumps 230.

[0051] In addition, a platform 250 is formed on the chip 210 and surrounds the top surface 211. The platform 250 is substantially planar and parallel to the top surface 211 and the bottom surface 212. The distance from the platform 250 to the bottom surface 212 is less than the distance from the top surface 211 to the bottom surface 212, that is, the platform 250 is lower than the top surface 211. Therefore, a step (gap) is formed between the top surface 211 and the platform 250. The outer peripheral edge 253 of the platform 250 is connected to the plurality of side surfaces 213. The platform 250 is perpendicularly connected to the plurality of side surfaces 213.

[0052] A molding layer 240 is formed on the substrate 220 and is made of a potting material, such as composed of an epoxy resin material, but not limited thereto. The molding layer 240 has opposite top surface 241 and bottom surface 242, wherein the bottom surface 242 is in contact with the substrate 220. The molding layer 240 covers the plurality of side surfaces 213 and the platform 250 of the chip 210 and is not formed on the top surface 211 of the chip 210. The molding layer 240 exposes the top surface 211 of the chip 210. The top surface 241 of the molding layer 240 is connected to the top surface 211 of the chip 210 and is flush with the top surface 211 of the chip 210.

[0053] The semiconductor package of the present invention further includes a heat sink 260, which is attached to the top surface 211 of the chip 210. The heat sink 260 can be made of copper or other heat-conductive materials to help the chip 210 dissipate heat. In addition, a plurality of solder balls 270 are provided on the bottom surface of the substrate 220, and the plurality of solder balls 270 are electrically connected to the substrate 220. The chip 210 can be electrically connected to an external circuit through the substrate 220 by the plurality of solder balls 270.

[0054] According to the semiconductor package of the present invention, the distance from the top surface 211 to the platform 250 of the chip 210, that is, the depth of the platform 250 is defined as d, and the distance from the top surface 211 to the bottom surface 212 of the chip 210, that is, the thickness of the chip 210 is defined as D, wherein D and d have the following relationship:

[0055] 1 / 2 < d / D < 2 / 3

[0056] In the semiconductor package according to the present invention, since the molding layer covers the platform, it hooks the chip like a hook, making it difficult for the chip to separate from the molding layer.

[0057] Please refer to Figures 3 to 8 , which shows Figure 2 the manufacturing method of the chip 210 therein. First, as Figure 3 shown, an unprocessed wafer 310 is provided. The wafer 310 has a front surface 312 and a back surface 311 opposite to the front surface 312. In addition, a circuit layer 316 is provided on the front surface 312 of the wafer 310.

[0058] Then, as Figure 4 shown, a protective film 360 is attached to the front surface 312 of the wafer 310 to protect the circuit layer 316 from being damaged.

[0059] Next, as Figure 5 shown, the protective film 360 on the wafer 310 is held by a holding surface (not shown) of a workbench, and the back surface 311 of the wafer 310 is ground with a grinding wheel 391 to thin the wafer 310 to a predetermined thickness. Figure 6 Shown is that the wafer 310 has a thickness D after grinding.

[0060] Then, as Figure 7 shown, a plurality of grooves 370 are formed on the back surface 311 of the wafer 310 with a tool or a laser beam. The depth of the plurality of grooves 370 is d and the width is W1.

[0061] In one embodiment, the thickness D of the wafer 310 and the depth d of the plurality of grooves 370 have the following relationship:

[0062] 1 / 2 < d / D < 2 / 3

[0063] In another embodiment of the present invention, the plurality of grooves 370 can be formed on the back surface 311 of the wafer 310 first, and then the wafer 310 is thinned.

[0064] Then, as Figure 8 shown, the protective film 360 attached to the front surface 312 of the wafer 310 is removed. Then, a tool 392 with a thickness of W2 is used to cut the wafer 310 from the front surface 312 of the wafer 310 and cut to the position of the plurality of grooves 370. Then the wafer 310 is separated, and a plurality of chips 210 shown in Figure 2 can be obtained.

[0065] In one embodiment, the width W1 of the plurality of grooves 370 and the thickness W2 of the tool have the following relationship:

[0066] 1 / 2 < W2 / W1 < 1

[0067] The obtained chip 210 can be disposed on the substrate 220 by flip-chip technology and electrically connected to the substrate 220 by using a plurality of metal bumps 230. Then, a molding layer 240 is formed on the substrate 220, a plurality of solder balls 270 are formed on the bottom surface of the substrate 220, and a heat sink 260 is attached to the top surface 211 of the chip 210, thereby obtaining a semiconductor package as Figure 2 shown.

[0068] Although the present invention has been disclosed in the foregoing embodiments, it is not intended to limit the present invention. Any person having ordinary knowledge in the technical field to which the present invention pertains may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the appended claims.

Claims

1. A chip, characterized in that, Comprising: Top surface; A plurality of side surfaces; Bottom surface, connecting the plurality of side surfaces; A circuit layer formed on the bottom surface; and A platform surrounding the top surface and parallel to the top surface and the bottom surface, the distance from the platform to the bottom surface being less than the distance from the top surface to the bottom surface, and the platform being perpendicularly connected to the plurality of side surfaces.

2. The chip according to claim 1, wherein The distance from the top surface to the platform is defined as d, and the distance from the top surface to the bottom surface is defined as D, where D and d have the following relationship: 1 / 2 < d / D < 2 / 3.

3. A semiconductor package, characterized in that, Comprising: A substrate; The chip according to claim 1 or 2, disposed on the substrate; A plurality of bumps disposed between the substrate and the bottom surface of the chip and electrically connected to the circuit layer of the chip; And A molding layer formed on the substrate and covering the plurality of side surfaces and the platform of the chip, wherein the molding layer exposes the top surface of the chip.

4. The semiconductor package according to claim 3, wherein The top surface of the molding layer is flush with the top surface of the chip.

5. The semiconductor package according to claim 3 or 4, characterized in that, Further comprising: A heat sink attached to the top surface of the chip.

6. A method for manufacturing a chip, characterized in that, Comprising: Providing a wafer having a front surface and a back surface opposite to the front surface, wherein a circuit layer is provided on the front surface; Grinding the back surface of the wafer with a grinding wheel to thin the wafer to a predetermined thickness; Forming a plurality of grooves on the back surface of the wafer; And Using a cutter to cut the wafer from the front surface of the wafer and cutting to the position of the plurality of grooves.

7. The manufacturing method of the chip according to claim 6, characterized in that, The thickness of the thinned wafer is defined as D, and the depth of the plurality of grooves is defined as d, where D and d have the following relationship: 1 / 2 < d / D < 2 / 3.

8. The manufacturing method of the chip as described in claim 6, characterized in that, The width of the plurality of grooves is defined as W1, and the thickness of the cutter is defined as W2, where W1 and W2 have the following relationship: 1 / 2 < W2 / W1 < 1.

9. The manufacturing method of the chip according to claim 6, characterized in that, The plurality of grooves are formed on the back surface of the wafer before thinning the wafer.

10. The manufacturing method of the chip according to claim 6, wherein, Further comprising: Before grinding the wafer, attaching a protective film to the front surface of the wafer; and After grinding the wafer, removing the protective film attached to the front surface of the wafer.

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