Thin film transistor and display device including the same

Abstract

A thin film transistor and a display device including the same are provided. The thin film transistor includes: a first gate electrode; a first gate insulating layer on the first gate electrode; an active layer on the first gate insulating layer; a second gate insulating layer on the active layer; and a second gate electrode on the second gate insulating layer, in which the active layer includes a channel portion, and the channel portion includes: a first channel portion overlapping the first gate electrode; and a second channel portion overlapping the second gate electrode, and wherein, in a plan view, the first gate electrode and the second gate electrode do not overlap each other.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit and priority of Korean Patent Application No. 10 - 2023 - 0195028, filed on December 28, 2023, which is hereby incorporated by reference herein for all purposes as if fully set forth herein. Technical field

[0003] The present disclosure relates to thin - film transistors and display devices including the same. Specifically, embodiments of the present disclosure relate to thin - film transistors having a dual - gate structure and display devices including the same. Background art

[0004] Since thin - film transistors can be fabricated on a glass substrate or a plastic substrate, thin - film transistors are widely used as switching elements or driving elements in display devices such as liquid - crystal display devices or organic - light - emitting display devices.

[0005] Based on the material constituting the active material layer, thin - film transistors can be classified into: amorphous silicon thin - film transistors, in which amorphous silicon is used as the active material layer; polycrystalline silicon thin - film transistors, in which polycrystalline silicon is used as the active material layer; and oxide semiconductor thin - film transistors, in which an oxide semiconductor is used as the active material layer.

[0006] Among them, oxide semiconductor thin - film transistors (oxide semiconductor TFTs) having high mobility and capable of having a large resistance change according to the oxygen content have the advantage that desired properties can be easily obtained. In addition, since the oxide constituting the active layer can be formed at a relatively low temperature in the manufacturing process of oxide semiconductor thin - film transistors, the manufacturing cost of oxide semiconductor thin - film transistors is low. Due to the properties of the oxide, the oxide semiconductor is transparent, so oxide semiconductor thin - film transistors are advantageous for realizing transparent display devices.

[0007] A display device may include switching transistors and driving transistors. Generally, it is advantageous for a switching transistor to have a small s - factor (threshold swing) to improve on - off characteristics. At the same time, it is advantageous for a driving transistor to have a large s - factor to exhibit grayscale. However, since thin - film transistors generally have a small s - factor to ensure on - off characteristics, it is difficult to exhibit grayscale when these thin - film transistors are applied to the driving transistors of a display device.

[0008] Therefore, when thin - film transistors are applied to the driving transistors of a display device, thin - film transistors having a large s - factor are required to easily exhibit grayscale. Summary of the invention

[0009] One aspect of the present disclosure is to provide a thin film transistor having a large s factor. One aspect of the present disclosure is to provide a thin film transistor that has a large s factor in the threshold voltage region and can easily exhibit grayscale.

[0010] In addition, one aspect of the present disclosure is to provide a thin film transistor having excellent current characteristics.

[0011] Another aspect of the present disclosure is to provide a display device that includes a thin film transistor having a large s factor as a driving transistor and thus has excellent grayscale display ability.

[0012] According to one aspect of the present disclosure, the above and other objects can be achieved by providing a thin film transistor including: a first gate electrode; a first gate insulating layer on the first gate electrode; an active layer on the first gate insulating layer; a second gate insulating layer on the active layer; and a second gate electrode on the second gate insulating layer, wherein the active layer includes: a channel portion; a first connection portion contacting one side of the channel portion; and a second connection portion contacting the other side of the channel portion, wherein the channel portion may include: a first channel portion overlapping with the first gate electrode; and a second channel portion overlapping with the second gate electrode, and wherein, in a plan view, the first gate electrode and the second gate electrode do not overlap with each other.

[0013] The first channel portion may not overlap with the second gate electrode, and the second channel portion may not overlap with the first gate electrode.

[0014] In a plan view, the first channel portion and the second channel portion may be spaced apart from each other.

[0015] The spacing distance between the first channel portion and the second channel portion is 0 μm or greater and 1 μm or less.

[0016] The thickness of the first gate insulating layer may be 2 to 3 times the thickness of the second gate insulating layer.

[0017] When the direction connecting the first connection portion and the second connection portion in a plan view is referred to as the longitudinal direction of the channel portion, and the direction perpendicular to the longitudinal direction of the channel portion is referred to as the width direction of the channel portion, the ratio of the width of the first channel portion to the width of the second channel portion may be in the range of 8:2 to 2:8.

[0018] The ratio of the length of the first channel portion to the length of the second channel portion is in the range of 1:2 to 2:1.

[0019] The width of the first channel portion may be greater than the width of the second channel portion.

[0020] The length of the first channel portion may be less than the length of the second channel portion.

[0021] The length of the first channel portion may be greater than the length of the second channel portion.

[0022] The first channel portion and the second channel portion may have the same length.

[0023] The first channel portion and the second channel portion may have the same width.

[0024] The width of the first channel portion may be less than the width of the second channel portion.

[0025] The length of the first channel portion may be greater than the length of the second channel portion.

[0026] The active layer may include at least one of the following: an IGZO (InGaZnO)-based oxide semiconductor material, an IZO (InZnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, an FIZO (FeInZnO)-based oxide semiconductor material, a ZnO-based oxide semiconductor material, an SIZO (SiInZnO)-based oxide semiconductor material, a ZnON (zinc oxide nitride)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor, and an IWZO (InWZnO)-based oxide semiconductor material.

[0027] According to another embodiment of the present disclosure, a display device is provided, which includes: a pixel driving circuit; and a display element connected to the pixel driving circuit, wherein the pixel driving circuit includes the thin film transistor described above.

[0028] The pixel driving circuit includes a driving transistor and a switching transistor, and the thin film transistor may be applied to the driving transistor.

[0029] Technical effects of the present disclosure

[0030] The thin film transistor according to an embodiment of the present disclosure includes gate electrodes disposed on both sides of the active layer and not overlapping with each other, and thus the thin film transistor may have a large s-factor value.

[0031] By using a thin-film transistor having a large s factor as a driving transistor, a display device according to an embodiment of the present disclosure can have excellent gray-scale performance capabilities.

[0032] In addition to the above effects, other features and advantages of the present disclosure will be described below, or those skilled in the art can clearly understand other features and advantages of the present disclosure from the description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. The above and other objects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0034] Figure 1A is a plan view of a thin-film transistor according to an embodiment of the present disclosure.

[0035] Figure 1B is along Figure 1A sectional view taken along line I-I' of.

[0036] Figure 1C is along Figure 1A sectional view taken along line II-II' of.

[0037] Figure 2A is a plan view of a thin-film transistor according to another embodiment of the present disclosure.

[0038] Figure 2B is along Figure 2A sectional view taken along line III-III' of.

[0039] Figure 2C is along Figure 2A sectional view taken along line IV-IV' of.

[0040] Figure 3A and Figure 3B are sectional views of thin-film transistors according to another embodiment of the present disclosure, respectively.

[0041] Figure 4 is a sectional view of a thin-film transistor according to another embodiment of the present disclosure.

[0042] Figure 5 is a sectional view of a thin-film transistor according to another embodiment of the present disclosure.

[0043] Figure 6 is a plan view of a thin-film transistor according to another embodiment of the present disclosure.

[0044] Figure 7is a plan view of a thin film transistor according to another embodiment of the present disclosure.

[0045] Figure 8 is a plan view of a thin film transistor according to another embodiment of the present disclosure.

[0046] Figure 9 is a plan view of a thin film transistor according to another embodiment of the present disclosure.

[0047] Figure 10 is a plan view of a thin film transistor according to another embodiment of the present disclosure.

[0048] Figure 11 is a plan view of a thin film transistor according to another embodiment of the present disclosure.

[0049] Figure 12 is a plan view of a thin film transistor according to another embodiment of the present disclosure.

[0050] Figure 13 is a plan view of a thin film transistor according to another embodiment of the present disclosure.

[0051] Figure 14A 、 14B and 14C are respectively diagrams showing the threshold voltages of the thin film transistor.

[0052] Figure 15A 、 15B and 15C are respectively diagrams showing the threshold voltages of the thin film transistor.

[0053] Figure 16A 、 16B and 16C are respectively diagrams showing the threshold voltages of the thin film transistor.

[0054] Figures 17A to 17G is a schematic process diagram of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.

[0055] Figure 18 is a schematic diagram of a display device according to another embodiment of the present disclosure.

[0056] Figure 19 is Figure 18 a circuit diagram of one pixel of

[0057] Figure 20 is Figure 19 a plan view of the pixel of

[0058] Figure 21 is along Figure 20 a cross-sectional view taken along the V-V' line of Detailed Description

[0059] Advantages, features, and implementation methods of the present disclosure will be clarified by embodiments described with reference to the following accompanying drawings. However, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments described herein. Instead, these embodiments are provided to make the present disclosure thorough and complete, and will fully explain the present disclosure to those skilled in the art.

[0060] The shapes, sizes, ratios, angles, and quantities disclosed in the accompanying drawings used to describe the embodiments of the present disclosure are merely examples, and thus, the present disclosure is not limited to the details shown. Throughout the specification, like reference numerals refer to like elements. In the following description, when a detailed description of a related known function or configuration is determined to unnecessarily obscure the gist of the present disclosure, the detailed description will be omitted.

[0061] When using "comprising", "having", and "including" described in this specification, another part may be added unless "only~" is used. Unless otherwise specified, terms in the singular form may include the plural form.

[0062] When interpreting an element, the element is interpreted as including an error range even though there is no explicit description.

[0063] When describing positional relationships, for example, when a positional relationship is described as "on", "above", "below", and "adjacent to", unless "exactly" or "directly" is used, one or more parts may be arranged between the other two parts.

[0064] As shown in the figure, spatial relative terms such as "below", "beneath", "lower", "above", and "upper" may be used herein to easily describe the relationship of one or more elements to one or more other elements. It should be understood that these terms are also intended to cover different orientations of the device in addition to the orientation depicted in the figure. For example, if the device shown in the figure is turned upside down, the device described as being "below" or "beneath" another device may be arranged "above" the other device. Thus, the exemplary term "below or beneath" may include the orientations of "below or beneath" and "above". Similarly, the exemplary term "above" or "on" may include the orientations of "above" and "below or beneath".

[0065] When describing temporal relationships, for example, when a temporal order is described as "after", "subsequent", "next", and "before", discontinuous cases may be included unless "exactly" or "directly" is used.

[0066] It should be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present invention, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0067] The term "at least one" should be understood to include any and all combinations of one or more of the related listed items. For example, the meaning of "at least one of the first item, the second item, or the third item" represents all combinations of two or more of the first item, the second item, and the third item, as well as the first item, the second item, or the third item.

[0068] As can be fully understood by those skilled in the art, the features of various embodiments of the present disclosure can be partially or fully coupled or combined with each other, and can interoperate with each other in various ways and be technically driven. The embodiments of the present disclosure can be executed independently of each other or can be executed together in an interdependent relationship.

[0069] Hereinafter, a thin film transistor and a display device including the thin film transistor according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the same or similar elements are represented by the same reference numerals, even if they are depicted in different drawings.

[0070] In an embodiment of the present disclosure, for ease of description, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode can be used interchangeably. The source electrode can be the drain electrode, and the drain electrode can be the source electrode. In addition, the source electrode in any embodiment of the present disclosure can be the drain electrode in another embodiment of the present disclosure, and the drain electrode in any embodiment of the present disclosure can be the source electrode in another embodiment of the present disclosure.

[0071] In some embodiments of the present disclosure, for ease of explanation, the source connection portion and the source electrode are distinguished, and the drain connection portion and the drain electrode are distinguished, but the embodiments of the present disclosure are not limited thereto. The source connection portion can be the source electrode, and the drain connection portion can also be the drain electrode. In addition, the source connection portion can be the drain electrode, and the drain connection portion can also be the source electrode.

[0072] Figure 1A is a plan view of a thin film transistor 100 according to an embodiment of the present disclosure, Figure 1B is along Figure 1A sectional view taken along line I-I' of, and Figure 1C is along Figure 1A sectional view taken along line II-II' of.

[0073] Reference Figure 1A 、 1B and 1C, a thin film transistor 100 according to an embodiment of the present disclosure includes a first gate electrode 151, a first gate insulating layer 141 on the first gate electrode 151, an active layer 130 on the first gate insulating layer 141, a second gate insulating layer 142 on the active layer 130, and a second gate electrode 152 on the second gate insulating layer 142.

[0074] Reference Figure 1B and 1C , a thin film transistor 100 according to an embodiment of the present disclosure may be disposed on a base substrate 110.

[0075] Glass or plastic may be used as the base substrate 110. A transparent plastic having a flexible property, such as polyimide, may be used as the plastic. When polyimide is used as the base substrate 110, a heat-resistant polyimide capable of withstanding high temperatures may be used in consideration of a high-temperature deposition process performed on the base substrate 110.

[0076] Although Figure 1B and 1C are not shown, a buffer layer may be disposed on the base substrate 110 (see Figure 5 ). The buffer layer may protect the active layer 130. The upper surface above the base substrate 110 may be flattened through the buffer layer.

[0077] The first gate electrode 151 is disposed on the base substrate 110.

[0078] The first gate electrode 151 may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The first gate electrode 151 may have a multilayer structure including at least two conductive films, each conductive film having different physical properties.

[0079] The first gate insulating layer 141 is disposed on the first gate electrode 151. The first gate insulating layer 141 protects the active layer 130.

[0080] The first gate insulating layer 141 may include at least one of silicon oxide, silicon nitride, and a metal-based oxide. The first gate insulating layer 141 may have a single-layer structure or a multilayer structure. According to an embodiment of the present disclosure, the first gate insulating layer 141 may serve as a buffer layer to block oxygen (O2) or moisture (H2O) permeating from the base substrate 110. To this end, the first gate insulating layer 141 may be made of an oxide such as silicon oxide.

[0081] Reference Figure 1B and1C , the first gate insulating layer 141 may be disposed on the entire surface of the base substrate 110 which is not patterned.

[0082] The active layer 130 is disposed on the first gate insulating layer 141. At least a portion of the active layer 130 overlaps with the first gate electrode 151.

[0083] The active layer 130 may include a semiconductor material. According to an embodiment of the present disclosure, the active layer 130 may include an oxide semiconductor material.

[0084] The active layer 130 may include at least one of the following: an IGZO (InGaZnO)-based oxide semiconductor material, an IZO (InZnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, a FIZO (FeInZnO)-based oxide semiconductor material, a ZnO-based oxide semiconductor material, a SIZO (SiInZnO)-based oxide semiconductor material, a ZnON (zinc oxynitride)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, and an IWZO (InWZnO)-based oxide semiconductor material.

[0085] According to an embodiment of the present disclosure, the active layer 130 includes a channel portion 130n, a first connection portion 130a, and a second connection portion 130b. The first connection portion 130a contacts one side of the channel portion 130n, and the second connection portion 130b contacts the other side of the channel portion 130n.

[0086] The first connection portion 130a and the second connection portion 130b may be formed by selective conduction to the active layer 130. In detail, the first connection portion 130a and the second connection portion 130b may be formed by selective conduction of an oxide semiconductor material constituting the active layer 130. The first connection portion 130a and the second connection portion 130b may be referred to as a conduction portion.

[0087] According to an embodiment of the present disclosure, selective conductorization refers to improving the conductivity of a selected portion of the active layer 130 or providing conductivity to a selected portion in the active layer 130. Giving conductivity to a selected portion may also be referred to as selective conductorization. A portion may be selectively conductorized by selective conductorization. According to an embodiment of the present disclosure, selective conductorization may be achieved by doping a dopant in a selected region. Therefore, the first connection portion 130a and the second connection portion 130b may include a dopant.

[0088] According to an embodiment of the present disclosure, doping can be performed by injecting dopant ions. According to an embodiment of the present disclosure, dopants for conductorization may include at least one of boron (B), fluorine (F), phosphorus (P), and hydrogen (H).

[0089] Selective conductorization may also be referred to as selective metallization, and the first connection portion 130a and the second connection portion 130b may be referred to as metallization portions.

[0090] The selectively conductorized portion of the active layer 130 has excellent electrical conductivity and can thus be used as a wiring portion.

[0091] However, embodiments of the present disclosure are not limited thereto, and electrical conductivity can be imparted to the first connection portion 130a and the second connection portion 130b by other methods. For example, electrical conductivity can be imparted to the first connection portion 130a and the second connection portion 130b by plasma treatment. Specifically, in the patterning process of the second gate insulating layer 142 or the second gate electrode 152, selective conductorization can be performed by plasma treatment to form the first connection portion 130a and the second connection portion 130b.

[0092] According to an embodiment of the present disclosure, the first connection portion 130a of the active layer 130 may be a source region, and the second connection portion 130b may be a drain region. However, embodiments of the present disclosure are not limited thereto, and the first connection portion 130a may be a drain region, while the second connection portion 130b may be a source region.

[0093] According to an embodiment of the present disclosure, the non-conductorized region of the active layer 130 may become the channel portion 130n.

[0094] According to an embodiment of the present disclosure, the channel portion 130n may include a first channel portion CN1 overlapping with the first gate electrode 151 and a second channel portion CN2 overlapping with the second gate electrode 152. The gate electrodes 151 and 152 and the channel portion 130n will be described later.

[0095] The second gate insulating layer 142 is disposed on the active layer 130. The second gate insulating layer 142 protects the channel portion 130n.

[0096] The second gate insulating layer 142 may include at least one of silicon oxide, silicon nitride, and metal-based oxides. The second gate insulating layer 142 may have a single-layer structure or a multi-layer structure. The second gate insulating layer 142 may have the same composition as the first gate insulating layer 141 or may have a different composition from the first gate insulating layer 141.

[0097] Reference Figure 1B and 1C, the second gate insulating layer 142 may be disposed on the entire surface of the base substrate 110. In this case, the second gate insulating layer 142 may not be patterned, and selected portions of the active layer 130 may be selectively made conductive by, for example, selective ion doping, selective hydrogen implantation, or selective ultraviolet irradiation. Through selective conductivity, a first connection portion 130a and a second connection portion 130b may be formed.

[0098] However, embodiments of the present disclosure are not limited thereto, and the second gate insulating layer 142 may have a patterned structure.

[0099] The second gate electrode 152 is disposed on the second gate insulating layer 142. The second gate electrode 152 overlaps at least a portion of the active layer 130.

[0100] The second gate electrode 152 may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The second gate electrode 152 may have a multi-layer structure including at least two conductive layers each having different physical properties. The second gate electrode 152 may be made of the same material as the first gate electrode 151 or may be made of a material different from the first gate electrode 151.

[0101] Reference Figures 1A to 1C , the first gate electrode 151 and the second gate electrode 152 are spaced apart from each other, and the active layer 130 is located therebetween. Although Figures 1A to 1C not shown, the first gate electrode 151 and the second gate electrode 152 may be connected to each other through contact holes formed in the outer region of the active layer 130.

[0102] According to an embodiment of the present disclosure, the same voltage may be applied to the first gate electrode 151 and the second gate electrode 152. The voltage applied to the first gate electrode 151 and the second gate electrode 152 may be referred to as a gate voltage.

[0103] According to an embodiment of the present disclosure, the active layer 130 is disposed between the first gate electrode 151 and the second gate electrode 152, and the channel portion 130n may be defined by the first gate electrode 151 and the second gate electrode 152.

[0104] Reference Figure 1B and 1C , the interlayer insulating film 160 may be disposed on the second gate electrode 152. The interlayer insulating film 160 may be made of an organic or inorganic insulating material. The interlayer insulating film 160 may be a composite film of an organic film and an inorganic film.

[0105] The thin film transistor 100 according to an embodiment of the present disclosure may include a source electrode 171 and a drain electrode 172 disposed on an interlayer insulating film 160. However, embodiments of the present disclosure are not limited thereto, and the source electrode 171 and the drain electrode 172 may be interchanged. In addition, the first connection portion 130a and the second connection portion 130b may serve as the source electrode and the drain electrode, respectively.

[0106] Reference Figure 1A and 1B , the source electrode 171 and the drain electrode 172 may be connected to the active layer 130 through contact holes CH1 and CH2, respectively. Specifically, the source electrode 171 may contact the first connection portion 130a through the contact hole CH1. The drain electrode 172 may be spaced apart from the source electrode 171 and may contact the second connection portion 130b through the contact hole CH2.

[0107] Hereinafter, the channel portion 130n and the gate electrodes 151 and 152 of the thin film transistor 100 will be described in more detail.

[0108] As described above, the channel portion 130n includes a first channel portion CN1 overlapping with the first gate electrode 151 and a second channel portion CN2 overlapping with the second gate electrode 152.

[0109] According to an embodiment of the present disclosure, in a plan view, the first gate electrode 151 and the second gate electrode 152 do not overlap each other. Therefore, according to an embodiment of the present disclosure, the first channel portion CN1 and the second channel portion CN2 do not overlap each other.

[0110] In addition, according to an embodiment of the present disclosure, the first channel portion CN1 does not overlap with the second gate electrode 152, and the second channel portion CN2 does not overlap with the first gate electrode 151.

[0111] Reference Figure 1A , both the first channel portion CN1 and the second channel portion CN2 extend from the first connection portion 130a to the second connection portion 130b. The first channel portion CN1 and the second channel portion CN2 may be arranged side by side from the first connection portion 130a to the second connection portion 130b and may be spaced apart from each other at a predetermined interval.

[0112] According to an embodiment of the present disclosure, the thickness of the first gate insulating layer 141 may be 2 to 3 times the thickness of the second gate insulating layer 142. Reference Figure 1B and 1C, the first gate insulating layer 141 is used to insulate and separate the first gate electrode 151 and the active layer 130, and the first gate insulating layer 141 is disposed between the base substrate 110 and the active layer 130 to protect the active layer 130. For example, the first gate insulating layer 141 serves as a protective layer for the active layer 130 by blocking the penetration of moisture or oxygen from the base substrate 110.

[0113] The second gate insulating layer 142 is used to insulate the active layer 130 and the second gate electrode 152, and to protect the active layer 130.

[0114] According to an embodiment of the present disclosure, since the first gate insulating layer 141 has the function of protecting the active layer 130 from oxygen or moisture penetrating from the base substrate 110, the first gate insulating film 141 can be designed such that the thickness t1 of the first gate insulating film 141 is greater than the thickness t2 of the second gate insulating layer 142.

[0115] For example, the thickness t1 of the first gate insulating layer 141 may be 2 to 3 times the thickness t2 of the second gate insulating layer 142. The thicknesses of the gate insulating layers 141 and 142 may be defined by the distances between the gate electrodes 151 and 152 and the active layer 130.

[0116] Specifically, based on Figure 1B , 1C , and the cross-sectional views of FIGS. 2B and 2C, the thickness t1 of the first gate insulating layer 141 may be defined as the distance between the upper surface of the first gate electrode 151 and the lower surface of the active layer 130. In addition, the thickness t2 of the second gate insulating layer 142 may be defined as the distance between the upper surface of the active layer 130 and the lower surface of the second gate electrode 152. In this case, based on the cross-sectional view, the upper side surface is defined as the upper surface, and the lower side surface is defined as the lower surface.

[0117] According to an embodiment of the present disclosure, the distance between the first channel portion CN1 and the first gate electrode 151 is greater than the distance between the second channel portion CN2 and the second gate electrode 152. Therefore, the electric field applied to the first channel portion CN1 is relatively weaker than the electric field applied to the second channel portion CN2. And as a result, the s-factor (subthreshold swing; SS) of the thin film transistor 100 can be increased by the first channel portion CN1.

[0118] In addition, according to an embodiment of the present disclosure, since the first gate insulating layer 141 should be used as a buffer layer to block the penetration of oxygen (O2) or moisture from the base substrate 110, the first gate insulating film 141 can be made of an oxide such as silicon oxide. Since silicon oxide has a relatively low dielectric constant, a relatively weak electric field can be applied to the first channel portion CN1, and thus, the s-factor of the thin film transistor 100 can be increased by the first channel portion CN1.

[0119] Meanwhile, when the first gate electrode 151 and the second gate electrode 152 overlap, the electric fields of both the first gate electrode 151 and the second gate electrode 152 are applied to the first channel portion CN1 that is shorter in length than the second channel portion CN2. Specifically, there is a portion in the first channel portion CN1 where two electric fields are applied, and in the threshold voltage section, the current change in the first channel portion CN1 can be increased. As a result, the effect of increasing the s-factor by the first channel portion CN1 can be reduced, and the s-factor of the thin film transistor 100 can be decreased. Therefore, according to an embodiment of the present disclosure, in order to prevent the decrease of the s-factor, the first gate electrode 151 and the second gate electrode 152 are designed not to overlap with each other.

[0120] Specifically, according to an embodiment of the present disclosure, in a plan view, the first gate electrode 151 and the second gate electrode 152 can be spaced apart from each other without overlapping. Figure 1A A layout state in which the first gate electrode 151 and the second gate electrode 152 are spaced apart is shown in a plan view. Since the first gate electrode 151 and the second gate electrode 152 are spaced apart, the first channel portion CN1 and the second channel portion CN2 can be arranged to be spaced apart from each other.

[0121] However, the embodiment of the present disclosure is not limited thereto, and the edges of the first gate electrode 151 and the second gate electrode 152 can be set to be in contact with each other in a plan view (see Figure 2A ), and thus, in a plan view (see Figure 2A ), the edges of the first channel portion CN1 and the second channel portion CN2 can be set to be in contact with each other. If a completely precise process without errors is possible, the edges of the first channel portion CN1 and the second channel portion CN2 can be designed to be in contact with each other in a plan view.

[0122] According to an embodiment of the present disclosure, the spacing distance between the first gate electrode 151 and the second gate electrode 152 in a plan view may be 0 or greater and 1 μm or less. Accordingly, the spacing distance w0 between the first channel portion CN1 and the second channel portion CN2 may be 0 or greater and 1 μm or less. The state where "the spacing distance w0 between the first channel portion CN1 and the second channel portion CN2 is 0 μm" means that the edges of the first channel portion CN1 and the second channel portion CN2 are in contact with each other in a plan view.

[0123] According to an embodiment of the present disclosure, the spacing distance between the first gate electrode 151 and the second gate electrode 152 in a plan view may be greater than 0 μm and less than or equal to 1 μm. Further, in a plan view, the spacing distance between the first gate electrode 151 and the second gate electrode 152 may be in the range of 0.1 μm to 1 μm. Accordingly, the spacing distance w0 between the first channel portion CN1 and the second channel portion CN2 may be greater than 0 μm and less than or equal to 1 μm, and more specifically, may be in the range of 0.1 μm to 1 μm.

[0124] Referring Figure 1A and 1B , the width of the first channel portion CN1 is w1, and the width of the second channel portion CN2 is w2. When the spacing distance w0 between the first channel portion CN1 and the second channel portion CN2 exceeds 1 μm, the total width (w1 + w2 + w0) of the active layer 130 increases. And thus, as the size of the thin film transistor 100 increases, it may be difficult to miniaturize the device. Further, when the spacing distance w0 between the first channel portion CN1 and the second channel portion CN2 exceeds 1 μm, the effective channel width (w1 + w2) of the thin film transistor 100 may decrease, thereby negatively affecting the drive current in the thin film transistor 100, and thus, the on-current of the thin film transistor 100 may decrease. According to an embodiment of the present disclosure, the effective channel width of the thin film transistor 100 is defined as the sum (w1 + w2) of the width w1 of the first channel portion CN1 and the width w2 of the second channel portion CN2.

[0125] Specifically, in an apparatus using the thin film transistor 100, such as in a display device, the area that the thin film transistor 100 can occupy is limited, and the entire width (w1 + w2 + w0) of the active layer 130 is also limited. When the total width (w1 + w2 + w0) of the active layer 130 is limited, if the spacing distance w0 between the first channel portion CN1 and the second channel portion CN2 exceeds 1 μm, the effective channel width (w1 + w2) determined by the width w1 of the first channel portion CN1 and the width w2 of the second channel portion CN2 is reduced by more than 1 μm. When the effective channel width (w1 + w2) of the thin film transistor 100 is reduced, the area where current can flow in the thin film transistor 100 is reduced, and the on-current of the thin film transistor 100 is reduced.

[0126] As described above, in order to prevent an increase in the size of the apparatus and a reduction in the width (w1 + w2) of the effective channel portion 130n of the thin film transistor 100, the spacing distance w0 between the first channel portion CN1 and the second channel portion CN2 can be set to 1 μm or less. However, embodiments of the present disclosure are not limited thereto, and if the size of the thin film transistor 100 is not limited, the spacing distance w0 between the first channel portion CN1 and the second channel portion CN2 can exceed 1 μm.

[0127] According to an embodiment of the present disclosure, the first channel portion CN1 and the second channel portion CN2 are spaced apart in a direction Dr2 perpendicular to the first direction Dr1, and the first direction Dr1 extends from the first connection portion 130a to the second connection portion 130b. According to an embodiment of the present disclosure, the spacing distance w0 between the first channel portion CN1 and the second channel portion CN2 is measured along the second direction Dr2, and the second direction Dr2 is perpendicular to the first direction Dr1 extending from the first connection portion 130a to the second connection portion 130b.

[0128] Reference Figure 1A , the first direction Dr1 extending from the first connection portion 130a to the second connection portion 130b can be referred to as the "longitudinal direction" of the channel. In addition, the second direction Dr2 perpendicular to the first direction Dr1 can be referred to as the "width direction" of the channel. According to an embodiment of the present disclosure, the distance between both ends of the channel portion 130n measured along the first direction Dr1 extending from the first connection portion 130a to the second connection portion 130b is defined as the "channel length", and the distance between both ends of the channel portion 130n measured along the second direction Dr2 perpendicular to the first direction Dr1 is defined as the "channel width".

[0129] In addition, according to an embodiment of the present disclosure, the width w1 of the first channel portion CN1 is defined by the first gate electrode 151, and the width w2 of the second channel portion CN2 is defined by the second gate electrode 152. Specifically, the width of the region in the channel portion 130n that overlaps with the first gate electrode 151 is defined as the width w1 of the first channel portion CN1. In addition, the width of the region that overlaps with the second gate electrode 152 is defined as the width w2 of the second channel portion CN2.

[0130] According to an embodiment of the present disclosure, the width w1 of the first channel portion CN1 and the width w2 of the second channel portion CN2 can be designed differently according to the purpose of the thin film transistor 100. According to an embodiment of the present disclosure, the s-factor of the thin film transistor 100 is mainly determined by the first channel portion CN1, and the on-current of the thin film transistor 200 is mainly determined by the second channel portion CN2. According to the s-factor and on-current required for the thin film transistor 100, the width w1 of the first channel portion CN1 and the width w2 of the second channel portion CN2 can be determined.

[0131] According to an embodiment of the present disclosure, as Figure 1A shown, in the region overlapping with the active layer 130, the width of the first gate electrode 151 is greater than the width of the second gate electrode 152. Therefore, the width w1 of the first channel portion CN1 is greater than the width w2 of the second channel portion CN2 (w1 > w2).

[0132] In the width of the entire channel portion 130n, when the width w1 of the first channel portion CN1 is less than 20% and the width w2 of the second channel portion CN2 exceeds 80%, the s-factor of the thin film transistor 100 may not be large enough. On the other hand, in the width of the entire channel portion 130n, when the width w1 of the first channel portion CN1 exceeds 80% and the width w2 of the second channel portion CN2 is less than 20%, the on-current of the thin film transistor 100 can be reduced. Considering this correlation, according to an embodiment of the present disclosure, the ratio of the width w1 of the first channel portion CN1 to the width w2 of the second channel portion CN2 can be designed in the range of 8:2 to 2:8.

[0133] More specifically, according to an embodiment of the present disclosure, the ratio of the width w1 of the first channel portion CN1 to the width w2 of the second channel portion CN2 can be in the range of 3:7 to 7:3. In addition, the ratio of the width w1 of the first channel portion CN1 to the width w2 of the second channel portion CN2 can be in the range of 4:6 to 6:4, and in the range of 4.5:5.5 to 5.5:4.5.

[0134] The length L1 of the first channel portion CN1 and the length L2 of the second channel portion CN2 are designed such that the thin film transistor 100 can effectively have switching characteristics. If the lengths L1 and L2 of the first channel portion CN1 and the second channel portion CN2 are short, it is beneficial for miniaturization of the device.

[0135] According to an embodiment of the present disclosure, the ratio (L1:L2) of the length L1 of the first channel portion CN1 to the length L2 of the second channel portion CN2 may be in the range of 1:2 to 2:1.

[0136] If the length L1 of the first channel portion CN1 is less than 1 / 2 of the length L2 of the second channel portion CN2, it may be difficult to ensure the effective channel length of the first channel portion CN1. For example, when the maximum channel length of the thin film transistor 100 used as a driving transistor is designed to be 6 μm, the length L2 of the second channel portion CN2 may be 6 μm, and the maximum length L1 of the first channel portion CN1 may be 3 μm. However, if the length L1 of the first channel portion CN1 is 3 μm or less, it may be difficult to ensure an effective channel length. On the other hand, when the length L1 of the first channel portion CN1 exceeds twice the length L2 of the second channel portion CN2, it may be difficult to minimize the thin film transistor 100 due to the increase in the channel length.

[0137] Conversely, if the length L2 of the second channel portion CN2 is less than 1 / 2 of the length L1 of the first channel portion CN1, it may be difficult to ensure the effective channel length of the second channel portion CN2. In addition, when the length L2 of the second channel portion CN2 exceeds twice the length L1 of the first channel portion CN1, it may be difficult to minimize the thin film transistor 100 due to the increase in the channel length.

[0138] Reference Figure 1A , the width w1 of the first channel portion CN1 may be greater than the width w2 of the second channel portion CN2 (w1>w2). When the width w1 of the first channel portion CN1 that determines the s-factor of the thin film transistor 100 is greater than the width w2 of the second channel portion CN2, the thin film transistor 100 may have an advantage in increasing the s-factor.

[0139] In addition, reference Figure 1A , the length L1 of the first channel portion CN1 may be less than the length L2 of the second channel portion CN2 (L1<L2). By reducing the length L1 of the first channel portion CN1 to which a relatively weak electric field is applied, a decrease in the current flowing through the thin film transistor 100 can be prevented. In addition, by making the length L2 of the second channel portion CN2 to which a relatively strong electric field is applied relatively greater than the length L1 of the first channel portion CN1, the thin film transistor 100 can allow a stable current to flow in the on-current state.

[0140] Figure 2A is a plan view of a thin film transistor 200 according to another embodiment of the present disclosure, Figure 2B is a cross-sectional view taken along line III-III’ of Figure 2A and Figure 2C is a cross-sectional view taken along line IV-IV’ of Figure 2A . Hereinafter, descriptions of components that have been described may be omitted to avoid redundancy.

[0141] Referring to Figure 2A , 2B and 2C, in the plan view, the edges of the first channel portion CN1 and the second channel portion CN2 may be set to contact each other. If an exact process without error is possible, in the plan view, the edges of the first channel portion CN1 and the second channel portion CN2 may be designed to contact each other. In the structure of the thin film transistor 200 shown in Figure 2A , 2B and 2C, the spacing distance w0 between the first channel portion CN1 and the second channel portion CN2 may be 0 μm.

[0142] Figure 3A and 3B are cross-sectional views of a thin film transistor 300 according to another embodiment of the present disclosure, respectively. Specifically, Figure 3A corresponds to a cross-sectional view taken along I-I’ of Figure 1A , while Figure 3B corresponds to a cross-sectional view taken along II-II’ of Figure 1A .

[0143] Referring to Figure 3A and 3B , the second gate insulating layer 142 may have a patterned structure. Even if the second gate insulating layer 142 is patterned, the second gate insulating layer 142 is designed to cover the entire upper surface of the channel portion 130n. Referring to Figure 3A and 3B , the second gate insulating layer 142 covers at least the portion of the active layer 130 that overlaps with the first gate electrode 151 and the portion of the active layer 130 that overlaps with the second gate electrode 152.

[0144] In the process of patterning the second gate insulating layer 142, the active layer 130 may be selectively made conductive to form a first connection portion 130a and a second connection portion 130b.

[0145] Figure 4 is a cross-sectional view of a thin film transistor 400 according to another embodiment of the present disclosure.

[0146] Referring to Figure 4, the active layer 130 may have a multi-layer structure. According to an embodiment of the present disclosure, the active layer 130 may include a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 on the first oxide semiconductor layer 131. The first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 may be made of different oxide semiconductor materials.

[0147] For example, the first oxide semiconductor layer 131 may include a gallium (Ga)-based oxide semiconductor material having excellent stability. The first oxide semiconductor layer 131 containing the gallium (Ga)-based oxide semiconductor material may have a stable layer structure. The second oxide semiconductor layer 132 may be made of an oxide semiconductor material having excellent mobility. In this case, the main channel may be formed in the second oxide semiconductor layer 132. However, the embodiments of the present disclosure are not limited thereto, and the first oxide semiconductor layer 131 may have excellent mobility, and the second oxide semiconductor layer 132 may have a stable layer structure.

[0148] According to an embodiment of the present disclosure, the on-current of the thin film transistor 400 is mainly determined by the second channel portion CN2. The second channel portion CN2 is a region of the active layer 130 overlapping with the second gate electrode 152 and is driven by the voltage applied to the second gate electrode 152. In Figure 4 the shown thin film transistor 400, since the second oxide semiconductor layer 132 is disposed closer to the second gate electrode 152 than the first oxide semiconductor layer 131, it can be said that the driving characteristics of the second channel portion CN2 can be determined by the second oxide semiconductor layer 132. Therefore, it can be said that the on-current characteristics of the thin film transistor 400 are mainly affected by the second oxide semiconductor layer 132. Determine Figure 4 the second oxide semiconductor layer 132 that determines the on-current of the shown thin film transistor 400 may have a higher mobility than the first oxide semiconductor layer 131. Specifically, in order to improve the on-current characteristics of the thin film transistor 400, the mobility of the second oxide semiconductor layer 132 disposed closer to the second gate electrode 152 may be greater than the mobility of the first oxide semiconductor layer 131.

[0149] For the stability of the channel portion 130n, the first oxide semiconductor layer 131 in contact with the first gate insulating layer 141 may be made of an oxide semiconductor material having excellent stability. Generally, an oxide semiconductor material having excellent stability contains a relatively large amount of gallium (Ga) and has a relatively low mobility. Therefore, for the structural stability of the thin film transistor 400 and the stability of the channel portion 130n, the mobility of the first oxide semiconductor layer 131 may be lower than the mobility of the second oxide semiconductor layer 132.

[0150] Figure 5 A cross-sectional view of a thin-film transistor 500 according to another embodiment of the present disclosure.

[0151] Reference Figure 5 , a light-shielding layer 111 may be disposed on the base substrate 110. The light-shielding layer 111 may be made of a material having a light-shielding property. The light-shielding layer 111 blocks light incident from the outside and protects the active layer 130.

[0152] Reference Figure 5 , a buffer layer 120 may be disposed on the light-shielding layer 111. The buffer layer 120 may include at least one of silicon oxide, silicon nitride, and metal-based oxide. The buffer layer 120 protects the active layer 130. In addition, the buffer layer 120 may flatten the surface of the upper portion above the base substrate 110 on which the light-shielding layer 111 is disposed.

[0153] Reference Figure 5 , a first gate electrode 151 may be disposed on the buffer layer 120.

[0154] The light-shielding layer 111 may be connected to the source electrode 171. By connecting the light-shielding layer 111 to the source electrode 171, a certain voltage can be applied to the light-shielding layer 111. Therefore, the light-shielding layer 111 can be prevented from being in a floating state.

[0155] Figure 6 A plan view of a thin-film transistor 600 according to another embodiment of the present disclosure. Figure 6 One embodiment showing the dimensions of the first channel portion CN1, the second channel portion CN2, the first gate electrode 151, and the second gate electrode 152 being changed as needed is shown.

[0156] Reference Figure 6 , the first channel portion CN1 and the second channel portion CN2 may have the same length (L1 = L2). Specifically, in another embodiment of the present disclosure, the length L1 of the first channel portion CN1 and the length L2 of the second channel portion CN2 of the thin-film transistor 600 may be the same. An embodiment in which the length L1 of the first channel portion CN1 and the length L2 of the second channel portion CN2 are the same can be used as a reference for comparing how the performance of the thin-film transistor changes according to changes in the length L1 and the length L2.

[0157] In addition, in Figure 6 , the width w1 of the first channel portion CN1 is greater than the width w2 of the second channel portion CN2 (w1 > w2). Figure 6 The thin-film transistor 600 of

[0158] Figure 7 A plan view of a thin-film transistor 700 according to another embodiment of the present disclosure.Figure 7 One embodiment is shown in which the dimensions of the first channel portion CN1, the second channel portion CN2, the first gate electrode 151, and the second gate electrode 152 are changed as needed.

[0159] Reference Figure 7 , the length L1 of the first channel portion CN1 may be greater than the length L2 of the second channel portion CN2 (L1 > L2). In addition, in Figure 7 , the width w1 of the first channel portion CN1 is greater than the width w2 of the second channel portion CN2 (w1 > w2).

[0160] Figure 8 800 is a plan view of a thin film transistor according to another embodiment of the present disclosure.

[0161] Reference Figure 8 , the first channel portion CN1 and the second channel portion CN2 may have the same width (w1 = w2). Specifically, in another embodiment of the present disclosure, the width w1 of the first channel portion CN1 and the width w2 of the second channel portion CN2 of the thin film transistor 800 may be the same. In addition, reference Figure 8 , the length L1 of the first channel portion CN1 may be less than the length L2 of the second channel portion CN2 (L1 < L2).

[0162] Figure 9 900 is a plan view of a thin film transistor according to another embodiment of the present disclosure.

[0163] Reference Figure 9 , the first channel portion CN1 and the second channel portion CN2 may have the same width (w1 = w2). In addition, the length L1 of the first channel portion CN1 and the length L2 of the second channel portion CN2 may be the same (L1 = L2).

[0164] Figure 10 1000 is a plan view of a thin film transistor according to another embodiment of the present disclosure.

[0165] Reference Figure 10 , the first channel portion CN1 and the second channel portion CN2 may have the same width (w1 = w2). In addition, the length L1 of the first channel portion CN1 may be greater than the length L2 of the second channel portion CN2 (L1 > L2).

[0166] Figure 11 1100 is a plan view of a thin film transistor according to another embodiment of the present disclosure.

[0167] Reference Figure 11, the width w1 of the first channel portion CN1 may be smaller than the width w2 of the second channel portion CN2 (w1 < w2). Specifically, in another embodiment of the present disclosure, the width w1 of the first channel portion CN1 of the thin film transistor 1100 may be smaller than the width w2 of the second channel portion CN2 (w1 < w2). In addition, referring to Figure 11 , the length L1 of the first channel portion CN1 may be smaller than the length L2 of the second channel portion CN2 (L1 < L2).

[0168] Figure 12 is a plan view of the thin film transistor 1200 according to another embodiment of the present disclosure.

[0169] Referring to Figure 12 , the width w1 of the first channel portion CN1 may be smaller than the width w2 of the second channel portion CN2 (w1 < w2). In addition, referring to Figure 12 , the length L1 of the first channel portion CN1 may be equal to the length L2 of the second channel portion CN2 (L1 = L2).

[0170] Figure 13 is a plan view of the thin film transistor 1300 according to another embodiment of the present disclosure.

[0171] Referring to Figure 13 , the width w1 of the first channel portion CN1 may be smaller than the width w2 of the second channel portion CN2 (w1 < w2). In addition, referring to Figure 13 , the length L1 of the first channel portion CN1 may be greater than the length L2 of the second channel portion CN2 (L1 > L2).

[0172] As described above, according to an embodiment of the present disclosure, the thickness t2 of the second gate insulating layer 142 mainly used to insulate the active layer 130 and the second gate electrode 152 is smaller than the thickness t1 of the first gate insulating layer 141 used as a protective layer to protect the active layer 130 by blocking the penetration of moisture or oxygen from the base substrate 110 (t1 > t2). According to an embodiment of the present disclosure, the second channel portion CN2 affected by the second gate electrode 152 disposed on the second gate insulating layer 142 having a small thickness t2 plays a main role in determining the on-current of the thin film transistor 1300.

[0173] In the thin film transistor 1300 according to another embodiment of the present invention, in the total width of the channel portion 130n, the portion occupied by the second channel portion CN2 that determines the on-current is large, and the second channel portion CN2 is a short channel having a short length, so that the thin film transistor 1300 can have excellent on-current characteristics.

[0174] Figure 14A , 14BAnd 14C are respectively diagrams of the threshold voltages (Vth) of thin film transistors 100, 600, and 700.

[0175] Specifically, Figure 14A 、 14B And 14C show diagrams of the threshold voltages for thin film transistors 100, 600, 700, where the width w1 of the first channel portion CN1 is greater than the width w2 of the second channel portion CN2 (w1 > w2).

[0176] The diagram of the threshold voltage Vth for a thin film transistor shows the drain - source current I DS versus the gate voltage V GS relationship.

[0177] In Figure 14A 、 14B and the diagrams shown in 14C, the section where the current increases rapidly before the thin film transistor is fully turned on can be called the threshold voltage Vth section. According to an embodiment of the present invention, the s - factor is defined as the reciprocal of the slope of the diagram of the drain - source current I DS versus the gate voltage V GS . If the slope of the diagram is steep, the s - factor is small; if the slope of the diagram is small, the s - coefficient is large. When the s - factor is large, the rate of change of the drain - source current I DS with respect to the change in the gate voltage in the threshold voltage Vth region is small.

[0178] When the s - factor is large, since the rate of change of the drain - source current I DS with respect to the gate voltage V GS is small in the threshold voltage Vth section, it is easy to control the magnitude of the drain - drain current I GS by adjusting the gate voltage V DS . In a current - driven display device, such as an organic light - emitting display device, the gray scale of a pixel can be controlled by adjusting the magnitude of the drain - source current I DS of the driving thin film transistor, and the magnitude of the drain / source current I DS of the driving thin film transistor can be determined by the gate voltage. Therefore, in an organic light - emitting display device, the larger the s - factor of the driving thin film transistor (driving TR), the easier it is to adjust the gray scale of the pixel.

[0179] In Figure 14A 、 14BIn the thin film transistors measured in FIGS. 14A and 14C, the thickness t1 of the first gate insulating layer 141 is 400 nm, and the thickness t2 of the second gate insulating layer 142 is 150 nm. In the following, for other thin film transistors to be measured, the thickness t1 of the first gate insulating layer 141 is 400 nm, and the thickness t2 of the second gate insulating layer 142 is 150 nm.

[0180] exist Figure 14A , 14B In FIG. 14C , the dotted line is a diagram of the threshold voltage of the thin film transistor according to the comparative example. In addition to the gate electrode, each thin film transistor according to the comparative example has a gate electrode according to Figure 1A , 6 In each thin film transistor according to the comparative example, only the second gate electrode 152 is used as a gate electrode, which extends in the width direction Dr2 of the active layer 130 so that the second gate electrode 152 overlaps the entire channel portion 130n. The same is true for the following illustrations.

[0181] exist Figure 14A , 14B and 14C, the solid lines represent the Figure 1A The thin film transistor 100 (w1>w2, L1<L2), Figure 6 The thin film transistor 600 (w1>w2, L1=L2) and Figure 7 The threshold voltage of the thin film transistor 700 (w1>w2, L1>L2) is shown in FIG.

[0182] refer to Figure 14A , 14B 14C , it can be seen that the thin film transistors 100 , 600 , and 700 according to the embodiments of the present disclosure have excellent s-factor characteristics compared to the thin film transistors of the comparative examples.

[0183] For details, refer to Figure 14A According to the embodiments of the present disclosure Figure 1A The thin film transistor 100 may have an s factor of 0.45. Figure 14B According to another embodiment of the present disclosure Figure 6 The thin film transistor 600 may have an s factor of 0.42. Figure 14C According to another embodiment of the present disclosure Figure 7 The thin film transistor 700 may have an s factor of 0.38.

[0184] As described above, each of the thin film transistors 100 , 600 , and 700 according to the embodiments of the present disclosure has a large s factor and may be used as a driving thin film transistor (driving TR) of an organic light emitting display device.

[0185] Figure 15A , 15B and 15C are diagrams of the threshold voltages of thin film transistors 800, 900, and 1000, respectively.

[0186] Specifically, Figure 15A , 15B and 15C show diagrams of the threshold voltages for thin film transistors 800, 900, 1000, where the width w1 of the first channel portion CN1 is the same as the width w2 of the second channel portion CN2 (w1 = w2).

[0187] In Figure 15A , 15B and 15C, the dashed lines are diagrams of the threshold voltages of the thin film transistors according to the comparative example. The structure of the thin film transistor according to the comparative example is as described above.

[0188] In Figure 15A , 15B and 15C, the solid lines respectively represent the thin film transistors for Figure 8 800 (w1 = w2, L1 < L2), Figure 9 900 (w1 = w2, L1 = L2) and Figure 10 1000 (w1 = w2, L1 > L2) of the threshold voltage diagrams.

[0189] Referring to Figure 15A , 15B and 15C, it can be seen that compared with the thin film transistors of the comparative example, the thin film transistors 800, 900, and 1000 according to the embodiments of the present disclosure have excellent s-factor characteristics.

[0190] Specifically, referring to Figure 15A , Figure 8 the thin film transistor 800 can have an s-factor of 0.38. Referring to Figure 15B , Figure 9 the thin film transistor 900 can have an s-factor of 0.41. In addition, referring to Figure 15C , Figure 10 the thin film transistor 1000 can have an s-factor of 0.32.

[0191] As described above, each of the thin film transistors 800, 900, and 1000 according to the embodiments of the present disclosure has a large s-factor and can be used as a driving thin film transistor (driving TR) of an organic light emitting display device.

[0192] Figure 16A , 16B and 16C are diagrams of the threshold voltages of thin film transistors 1100, 1200, and 1300, respectively.

[0193] Specifically, Figure 16A , 16B and 16C show threshold voltage diagrams for thin film transistors 1100, 1200, and 1300, where the width w1 of the first channel portion CN1 is less than the width w2 of the second channel portion CN2 (w1 < w2).

[0194] In Figure 16A , 16B and 16C, the dashed line is the threshold voltage diagram of the thin film transistor according to the comparative example. The structure of the thin film transistor according to the comparative example is as described above.

[0195] In Figure 16A , 16B and 16C, the solid lines respectively represent the threshold voltage diagrams of the thin film transistors 1100 (w1 < w2, L1 < L2) for Figure 11 , Figure 12 the thin film transistor 1200 (w1 < w2, L1 = L2) for Figure 13 , and the thin film transistor 1300 (w1 < w2, L1 > L2) for

[0196] Referring to Figure 16A and 16B , it can be seen that, compared with the thin film transistor of the comparative example, the thin film transistors 1100 and 1200 according to the embodiments of the present disclosure have excellent s-factor characteristics. Specifically, referring to Figure 16A , Figure 11 the thin film transistor 1100 can have an s-factor of 0.32. Referring to Figure 16B , Figure 12 the thin film transistor 1200 can have an s-factor of 0.32.

[0197] As described above, the thin film transistors 1100 and 1200 according to the embodiments of the present disclosure have a large s-factor, and thus can be used as driving thin film transistors (driving TRs) of an organic light emitting display device.

[0198] In addition, referring to Figure 16C , it can be seen that, compared with the thin film transistor of the comparative example, the Figure 13 thin film transistor 1300 according to the embodiments of the present disclosure has excellent on-current characteristics. Specifically, referring to Figure 16C , Figure 13 the thin film transistor 1300 can have an on-current of 5.3 μA. According to the embodiments of the present disclosure, the on-current can be defined as the current (I DS ) at a voltage of 5V greater than the threshold voltage (Vth).

[0199] Therefore, the thin film transistor 1300 according to an embodiment of the present disclosure has excellent on-current characteristics and can thus be used as a switching transistor (switching TR) of an organic light emitting display device. In addition, the thin film transistor 1300 according to an embodiment of the present disclosure can be used as a driving thin film transistor (driving TR) of an organic light emitting display device.

[0200] Hereinafter, a method of manufacturing a thin film transistor 300 according to another embodiment of the present disclosure will be described with reference to Figures 17A to 17G FIGS.

[0201] Figures 17A to 17G is a schematic process diagram of a method of manufacturing a thin film transistor 300 according to an embodiment of the present disclosure.

[0202] Referring to Figure 17A FIG.

[0203] Referring to Figure 17B FIG.

[0204] Referring to Figure 17C FIG.

[0205] In addition, referring to Figure 17C FIG.

[0206] Referring to Figure 17D FIG.

[0207] In the process of forming the second gate electrode pattern 152p, the second gate insulating material layer 142m may be etched to form the second gate insulating layer 142. For example, the second gate insulating layer 142 may be formed by an etching process using the second gate electrode pattern 152p as a mask. However, another embodiment of the present disclosure is not limited thereto, and the second gate insulating layer 142 may not be patterned.

[0208] Referring to Figure 17D, the active layer 130 can be selectively made conductive. In the process of forming the second gate insulating layer 142, the active layer 130 can be selectively made conductive. Alternatively, after the second gate insulating layer 142 is formed, the active layer 130 can be selectively made conductive through a separate process.

[0209] For example, the active layer 130 can be selectively doped with dopants.

[0210] Reference Figure 17D , the active layer 130 can be selectively made conductive through a doping process using the first photoresist pattern 250 and the second gate electrode pattern 152p as masks. The region of the active layer 130 not protected by the second gate electrode pattern 152p can be selectively made conductive.

[0211] The dopants can include at least one of boron (B), phosphorus (P), and fluorine (F). The dopants can be doped in an ionic state. According to an embodiment of the present disclosure, selective conductivity can be achieved by ion doping through ion implantation.

[0212] However, the embodiments of the present disclosure are not limited thereto, and the active layer 130 can be selectively made conductive during the plasma process for forming the second gate insulating layer 142.

[0213] Reference Figure 17D , as a result of the selective conductivity of the active layer 130, a first connection portion 130a and a second connection portion 130b are formed. According to an embodiment of the present disclosure, the channel portion 130n of the active layer 130 is not made conductive.

[0214] Reference Figure 17E , a part of the first photoresist pattern 250 is removed to form a second photoresist pattern 255.

[0215] Reference Figure 17F , the second gate electrode pattern 152p is etched through an etching process using the second photoresist pattern 255 as a mask to form a second gate electrode 152. After the second gate electrode 152 is formed, the second photoresist pattern 255 is removed.

[0216] Reference Figure 17G , after the second photoresist pattern 255 is removed, an interlayer insulating film 160 is formed on the second gate electrode 152, and a source electrode 171 and a drain electrode 172 are formed on the interlayer insulating film 160. The source electrode 171 and the drain electrode 172 are spaced apart from each other and are respectively connected to the active layer 130.

[0217] Hereinafter, a display device according to another embodiment of the present disclosure will be described. The display device according to another embodiment of the present disclosure may include at least one of the above-described thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300.

[0218] Figure 18 is a schematic diagram of a display device 1400 according to another embodiment of the present disclosure.

[0219] The display device 1400 according to another embodiment of the present disclosure may include a display panel 310, a gate driver 320, a data driver 330, and a controller 340.

[0220] In some embodiments of the present disclosure, for ease of explanation, the source region and the source electrode are distinguished, and the drain region and the drain electrode are distinguished, but the embodiments of the present disclosure are not limited thereto. The source region may be the source electrode, and the drain region may be the drain electrode. In addition, the source region may be the drain electrode, and the drain region may be the source electrode.

[0221] The controller 340 controls the gate driver 320 and the data driver 330.

[0222] The controller 340 generates a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 using, for example, signals provided from an external system (not shown). In addition, the controller 340 samples the input image data input from the external system, realigns it, and provides the realigned digital image data RGB to the data driver 330.

[0223] The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock G CLK . In addition, the gate control signal GCS may include a control signal for controlling the shift register 350.

[0224] The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

[0225] The data driver 330 provides a data voltage to the data line DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the controller 340 into an analog data voltage and provides the data voltage to the data line DL.

[0226] The gate driver 320 may include a shift register 350. The shift register 350 sequentially provides gate pulses to the gate lines GL within one frame using a start signal and a gate clock transmitted from the controller 340.

[0227] Using the shift register 350, the gate driver 320 may sequentially provide gate pulses GP to the gate lines GL during one frame. Here, one frame refers to a period during which an image is output through the display panel. In addition, the gate driver 320 provides a gate-off signal G that can turn off the switching element to the gate lines GL during the remaining period within one frame when no gate pulse GP is provided. off Hereinafter, the gate pulse GP and the gate-off signal G off are collectively referred to as a scan signal SS.

[0228] According to an embodiment of the present disclosure, the gate driver 320 may be mounted in the display panel 310. In this way, a structure in which the gate driver 320 is directly mounted in the display panel 310 is referred to as a gate-in-panel GIP structure.

[0229] Figure 19 is Figure 18 the circuit diagram of the pixel P, Figure 20 is Figure 19 the plan view of the pixel P, and Figure 21 is Figure 20 the cross-sectional view along the V-V’ line of

[0230] Figure 19 The circuit diagram of

[0231] is an equivalent circuit diagram of the pixel P for a display device 1400 including an organic light-emitting diode OLED as a display element 710.

[0232] The display device 1400 includes a pixel driving circuit PDC and a display element 710 connected to the pixel driving circuit PDC. The pixel driving circuit PDC may include at least one of the above-described thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, and 1300.

[0233] The first thin film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS provided through the gate line GL.

[0234] The data line DL supplies a data voltage Vdata to the pixel driving circuit PDC, and the first thin film transistor TR1 controls the application of the data voltage Vdata.

[0235] The driving power line PL supplies a driving voltage Vdd to the display element 710, and the second thin film transistor TR2 controls the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving the organic light emitting diode OLED as the display element 710.

[0236] The above-mentioned thin film transistor can be used as Figure 19 the first thin film transistor TR1 or the second thin film transistor TR2. In particular, as the second thin film transistor TR2 serving as a driving transistor, the above-mentioned thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300 can be applied.

[0237] When the first thin film transistor TR1 is turned on by a scan signal SS applied from the gate driver 320 via the gate line GL, the data voltage Vdata supplied from the data line DL is supplied to the gate electrode of the second thin film transistor TR2 connected to the display element 710. The data voltage Vdata is charged into the capacitor Ct formed between the gate electrode and the source electrode of the second thin film transistor TR2. Figure 19 The capacitor Ct of

[0238] is a storage capacitor. According to the data voltage Vdata, the amount of current supplied to the organic light emitting diode OLED serving as the display element 710 through the second thin film transistor TR2 is controlled, so that the gray scale of the light emitted from the display element 710 can be controlled.

[0239] Refer to Figure 20 and Figure 21 , the first thin film transistor TR1 and the second thin film transistor TR2 are provided on the base substrate 110.

[0240] The base substrate 110 can be made of glass or plastic. As the base substrate 110, a plastic having a flexible property, such as polyimide (PI), can be used.

[0241] Refer to Figure 21 , the data line DL, the driving power line PL, and the first bridge electrode BR21 can be provided on the base substrate 110. In addition, the first gate electrode G21 of the second thin film transistor TR2, and the first capacitor electrode CE1 can be provided on the base substrate 110.

[0242] Refer to Figure 20 and Figure 21, the first gate electrode G21 of the second thin film transistor TR2, and the first capacitor electrode CE1 can be integrally formed as a whole. For example, the first gate electrode G21 of the second thin film transistor TR2 can extend to become the first capacitor electrode CE1.

[0243] Although not shown, a light-shielding layer can be provided on the base substrate 110. The light-shielding layer can be provided to overlap with the channel portions of the active layers A1 and A2.

[0244] The first gate insulating layer 141 is provided on the first capacitor electrode CE1, the data line DL, the driving power line PL, the first bridge electrode BR21, and the first gate electrode G21 of the second thin film transistor TR2. The first gate insulating layer 141 is made of an insulating material and can have dielectric properties. In addition, the first gate insulating layer 141 can be used to protect the channel portions of the active layers A1 and A2 from moisture or oxygen penetrating from the outside.

[0245] The active layers A1 and A2 are provided on the first gate insulating layer 141. Each of the active layers A1 and A2 can include an oxide semiconductor material. Each of the active layers A1 and A2 can include an oxide semiconductor layer made of an oxide semiconductor material.

[0246] Each of the active layers A1 and A2 can include a channel portion, a first connection portion, and a second connection portion. The first connection portion can be used as a source connection, and the second connection portion can be used as a drain connection. Refer to Figure 20 and Figure 21 , the first connection portion of the first thin film transistor TR1 can be the source electrode S1, and the second connection portion of the first thin film transistor TR1 can be the drain electrode D1.

[0247] A part of the active layer A2 of the second thin film transistor TR2 can be made conductive to become the second capacitor electrode CE2. The second capacitor electrode CE2 overlaps with the first capacitor electrode CE1. The capacitor Ct is formed by the first capacitor electrode CE1 and the second capacitor electrode CE2.

[0248] The source electrode S1 of the first thin film transistor TR1 can be connected to the data line DL through a contact hole. The drain electrode D1 of the first thin film transistor TR1 can be connected to the first bridge electrode BR21 through a contact hole.

[0249] The second gate insulating layer 142 is provided on the active layers A1 and A2 and the second capacitor electrode CE2. The second gate insulating layer 142 has insulating properties. The second gate insulating layer 142 can cover the entire upper surface above the active layers A1 and A2.

[0250] The gate electrode G1 of the first thin film transistor TR1 and the second gate electrode G22 of the second thin film transistor TR2 are provided on the second gate insulating layer 142.

[0251] The interlayer insulating film 160 is provided on the gate electrode G1 of the first thin film transistor TR1 and the second gate electrode G22 of the second thin film transistor TR2. The passivation layer 180 is provided on the interlayer insulating film 160. The interlayer insulating film 160 and the passivation layer 180 protect the thin film transistors TR1 and TR2.

[0252] On the passivation layer 180, a gate line GL, bridge electrodes BR22 and BR23, and the source electrode S2 and drain electrode D2 of the second thin film transistor TR2 are provided.

[0253] The gate line GL is connected to the gate electrode G1 of the first thin film transistor TR1 through a contact hole. Therefore, a scan signal SS can be applied to the gate electrode G1 of the first thin film transistor TR1.

[0254] The second bridge electrode BR22 is provided on the passivation layer 180 and connects the driving power line PL and the active layer A2 of the second thin film transistor TR2. Refer to Figure 20 , one side of the second bridge electrode BR22 is connected to the driving power line PL through a contact hole, and the other side of the second bridge electrode BR22 is connected to the active layer A2 of the second thin film transistor TR2 through a contact hole.

[0255] The other side of the second bridge electrode BR22 connected to the active layer A2 of the second thin film transistor TR2 can be used as the drain electrode D2 of the second thin film transistor TR2. Therefore, a driving voltage Vdd can be applied to the drain electrode D2 of the second thin film transistor TR2.

[0256] The source electrode S2 of the second thin film transistor TR2 is provided on the passivation layer 180 and is connected to the active layer A2 of the second thin film transistor TR2 through a contact hole. In addition, the source electrode S2 of the second thin film transistor TR2 is connected to the second capacitor electrode CE2. As a result, a voltage same as the voltage of the source electrode S2 of the second thin film transistor TR2 can be applied to the second capacitor electrode CE2.

[0257] The third bridge electrode BR23 is provided on the passivation layer 180 and connects the first bridge electrode BR21, the second gate electrode G22 of the second thin film transistor TR2, and the first capacitor electrode CE1 to each other.

[0258] The first bridge electrode BR21 is connected to the drain electrode D1 of the first thin-film transistor TR1, and the third bridge electrode BR23 is connected to the first bridge electrode BR21. As a result of this connection, the data voltage Vdata transmitted to the drain electrode D1 through the first thin-film transistor TR1 can be transmitted to the second gate electrode G22 of the second thin-film transistor TR2 through the first bridge electrode BR21 and the third bridge electrode BR23.

[0259] In addition, the third bridge electrode BR23 is connected to the first capacitor electrode CE1 through a contact hole. As a result, a voltage identical to the voltage of the second gate electrode G22 of the second thin-film transistor TR2 can be applied to the first capacitor electrode CE1 through the third bridge electrode BR23. In addition, a voltage identical to the voltage of the second gate electrode G22 of the second thin-film transistor TR2 can be applied to the first gate electrode G21 of the second thin-film transistor TR2 formed integrally with the first capacitor electrode CE1.

[0260] A planarization layer 190 is disposed on the gate line GL, the bridge electrodes BR22 and BR23, and the source electrode S2 and the drain electrode D2 of the second thin-film transistor TR2. The planarization layer 190 planarizes the upper portions of the first thin-film transistor TR1 and the second thin-film transistor TR2 and protects the first thin-film transistor TR1 and the second thin-film transistor TR2.

[0261] The first electrode 711 of the display element 710 is disposed on the planarization layer 190. The first electrode 711 of the display element 710 can be connected to the source electrode S2 of the second thin-film transistor TR2 through a contact hole formed in the planarization layer 190.

[0262] A bank layer 750 is disposed at the edge of the first electrode 711. The bank layer 750 defines the light-emitting region of the display element 710.

[0263] An organic light-emitting layer 712 is disposed on the first electrode 711, and a second electrode 713 is disposed on the organic light-emitting layer 714. Thus, the display element 710 is completed. Figure 21 The illustrated display element 710 is an organic light-emitting diode OLED. Thus, the display device 1400 according to an embodiment of the present disclosure is an organic light-emitting display device.

[0264] Although Figures 19 to 21 a 2TR1C structure in which the pixel driving circuit PDC has two transistors and one capacitor is described, the present disclosure is not limited thereto. The pixel driving circuit PDC according to another embodiment of the present disclosure may be formed in various structures other than the above structure. The pixel driving circuit PDC may include, for example, three or more thin-film transistors and two or more capacitors.

[0265] The present disclosure is not limited to the above embodiments and drawings, and it is well known to those of ordinary skill in the art that various substitutions, modifications, and changes are possible within the scope of the technical details of the present disclosure.

Claims

1. A thin film transistor, comprising: a first gate electrode; a first gate insulating layer on the first gate electrode; an active layer on the first gate insulating layer; a second gate insulating layer on the active layer; as well as a second gate electrode on the second gate insulating layer, Wherein, the active layer comprises: Channel part; a first connection portion contacting one side of the channel portion; and a second connection portion contacting the other side of the channel portion, Wherein, the channel portion comprises: a first channel portion overlapping the first gate electrode; and a second channel portion overlapping the second gate electrode, Wherein, in a plan view, the first gate electrode and the second gate electrode do not overlap each other.

2. The thin film transistor according to claim 1, in, The first channel portion does not overlap with the second gate electrode; and The second channel portion does not overlap with the first gate electrode.

3. The thin film transistor according to claim 1, in, The first gate electrode and the second gate electrode are spaced apart from each other in a plan view.

4. The thin film transistor according to claim 3, in, The first channel portion and the second channel portion are spaced apart from each other.

5. The thin film transistor according to claim 3, in, In a plan view, a spacing distance between the first gate electrode and the second gate electrode is 0 to 1 μm.

6. The thin film transistor according to claim 3, in, The first channel portion and the second channel portion are spaced apart by a distance of 0 to 1 μm.

7. The thin film transistor according to claim 1, in, The thickness of the first gate insulating layer is 2 to 3 times the thickness of the second gate insulating layer.

8. The thin film transistor according to claim 1, in, A ratio of a width of the first channel portion to a width of the second channel portion is in a range of 8:2 to 2:8, Herein, a direction connecting the first connection portion and the second connection portion in a plan view is a longitudinal direction of the channel portion, and a direction perpendicular to the longitudinal direction of the channel portion is a width direction of the channel portion.

9. The thin film transistor according to claim 8, in, A ratio of a length of the first channel portion to a length of the second channel portion is in a range of 1:2 to 2:

1.

10. The thin film transistor according to claim 8, in, The width of the first channel portion is greater than the width of the second channel portion.

11. The thin film transistor according to claim 10, in, The length of the first channel portion is smaller than the length of the second channel portion.

12. The thin film transistor according to claim 10, in, The length of the first channel portion is greater than the length of the second channel portion.

13. The thin film transistor according to claim 10, in, The first channel portion and the second channel portion have the same length.

14. The thin film transistor according to claim 8, in, The first channel portion and the second channel portion have the same width.

15. The thin film transistor according to claim 8, in, The width of the first channel portion is smaller than the width of the second channel portion.

16. The thin film transistor according to claim 15, in, The length of the first channel portion is greater than the length of the second channel portion.

17. The thin film transistor according to claim 1, in, The active layer includes at least one of the following: IGZO (InGaZnO) based oxide semiconductor material, IZO (InZnO) based oxide semiconductor material, ITZO (InSnZnO) based oxide semiconductor material, FIZO (FeInZnO) based oxide semiconductor material, ZnO based oxide semiconductor material, SIZO (SiInZnO) based oxide semiconductor material, ZnON (zinc oxynitride) based oxide semiconductor material, GZO (GaZnO) based oxide semiconductor material, IGO (InGaO) based oxide semiconductor material, IGZTO (InGaZnSnO) based oxide semiconductor material, GZTO (GaZnSnO) based oxide semiconductor, and IWZO (InWZnO) based oxide semiconductor material.

18. The thin film transistor according to claim 1, in, The active layer comprises: a first oxide semiconductor layer; and a second oxide semiconductor layer on the first oxide semiconductor layer, and The second oxide semiconductor layer is disposed closer to the second gate electrode than the first oxide semiconductor layer, and has a mobility greater than that of the first oxide semiconductor layer.

19. A display device comprising: Pixel driving circuit; as well as display element, connected to the pixel driving circuit, Wherein, the pixel driving circuit comprises a thin film transistor according to any one of claims 1 to 18.

20. The display device according to claim 19, in, The pixel driving circuit includes a driving transistor and a switching transistor, and Wherein, the thin film transistor is the driving transistor.

Images