Display device with thin film transistor and storage capacitor

Abstract

A display device including a thin film transistor and a storage capacitor is provided. The display apparatus may include a display device electrically connected to the thin film transistor. The display device may emit light displaying a specific color. For example, a display device may include a light emitting unit disposed between a first electrode and a second electrode. The thin film transistor may include a plurality of semiconductor patterns. The plurality of semiconductor patterns may be spaced apart in a first direction. The storage capacitor may include sub-capacitors disposed between semiconductor patterns spaced apart in a first direction. Accordingly, in the display device, when driven with a high current, reliability of the thin film transistor may be improved.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10 - 2023 - 0194881, filed on December 28, 2023, which is incorporated herein by reference in its entirety as if fully set forth herein. Technical field

[0003] The present disclosure relates to a display device in which a driving circuit of each pixel region includes a thin - film transistor and a storage capacitor. Background art

[0004] Generally, a display device provides an image to a user. For example, a display device may include a display device such as a liquid crystal, a small LED, a micro - LED, and an OLED. The display device may be controlled by a driving circuit. For example, in a display device, a driving circuit electrically connected to the display device may be provided in each pixel region.

[0005] The driving circuit may provide a driving current corresponding to a data signal to the display device according to a gate signal of a frame. For example, the driving circuit may include a thin - film transistor and a storage capacitor. However, in a display device, heat may be generated due to the operation of the driving circuit. The heat generated by the operation of the driving circuit may be proportional to the driving current generated by the driving circuit. Therefore, in a display device, when the driving current generated by the driving circuit increases, the thin - film transistor of the driving circuit may deteriorate due to the heat generated by the operation of the driving circuit. Therefore, in a display device, when driving at a high current, the reliability of the driving circuit may be reduced. Summary of the invention

[0006] Accordingly, the present disclosure relates to a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the related art.

[0007] An object of the present disclosure is to provide a display device capable of stably driving at a high current.

[0008] Another object of the present disclosure is to provide a display device capable of minimizing or reducing deterioration of a thin - film transistor caused by the operation of a driving circuit.

[0009] Additional advantages, objects, and features of the present disclosure will be partly set forth in the description below, and partly will become apparent to those of ordinary skill in the art upon examination of the following, or may be learned from practice of the present disclosure. The objects and other advantages of the present disclosure may be realized and attained by the structure particularly pointed out in the specification and claims as well as the drawings.

[0010] To achieve these objects and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, a display device including a driving circuit is provided. The driving circuit is electrically connected to a display device. The driving circuit includes a thin film transistor and a storage capacitor. The thin film transistor includes a plurality of sub-transistors connected in parallel. Each sub-transistor includes a semiconductor pattern, a gate electrode, a drain electrode, and a source electrode. The storage capacitor includes a sub-capacitor, and the sub-capacitor is disposed between semiconductor patterns spaced apart in a first direction.

[0011] The semiconductor pattern of each sub-transistor may include the same material as the semiconductor pattern of an adjacent sub-transistor.

[0012] The semiconductor patterns may be arranged side by side in a first direction and a second direction. The second direction may be a direction perpendicular to the first direction. The distance between adjacent semiconductor patterns in the second direction may be the same as the distance between adjacent semiconductor patterns in the first direction.

[0013] The sub-capacitor may have a stacked structure of capacitor electrodes that extend in the second direction.

[0014] The gate electrode, drain electrode, and source electrode of each sub-transistor may extend in the second direction. The gate electrode, drain electrode, and source electrode of each sub-transistor may be spaced apart from the gate electrode, drain electrode, and source electrode of an adjacent sub-transistor in the first direction.

[0015] The drain electrode and source electrode of each sub-transistor may include the same material as the gate electrode of the corresponding sub-transistor.

[0016] The thin film transistor may include a gate connection line, a drain connection line, and a source connection line. The gate connection line, drain connection line, and source connection line may extend in the first direction. The gate electrode of each sub-transistor may be electrically connected to the gate connection line. The drain electrode of each sub-transistor may be electrically connected to the drain connection line. The source electrode of each sub-transistor may be electrically connected to the source connection line.

[0017] The driving circuit and the display device may be supported by a device substrate. A light-shielding pattern may be disposed between the device substrate and the semiconductor pattern of each sub-transistor. The gate connection line may be disposed on the same layer as the light-shielding pattern. The drain connection line and the source connection line may be disposed on a layer different from the gate connection line.

[0018] The semiconductor pattern of each sub-transistor may be disposed between the drain connection line and the source connection line. The gate connection line may extend along between the drain connection line and the semiconductor pattern and between the semiconductor pattern and the source connection line. The sub-capacitor may have a stacked structure of a first capacitor electrode and a second capacitor electrode. The first capacitor electrode may be electrically connected to the gate connection line. The second capacitor electrode may be electrically connected to the source connection line.

[0019] The display device may include a light-emitting unit disposed between a first electrode and a second electrode. The light-emitting unit may include at least one light-emitting material layer.

[0020] In another embodiment, a display device including a device substrate is provided. A first thin-film transistor and a second thin-film transistor are disposed on a pixel region of the device substrate. The second thin-film transistor includes a gate connection line, a drain connection line, a source connection line, and a semiconductor pattern. The first thin-film transistor is electrically connected to the gate connection line of the second thin-film transistor. The source connection line of the second thin-film transistor is electrically connected to the display device. The semiconductor patterns are spaced apart in a first direction. A storage capacitor is disposed between the gate connection line and the source connection line of the second thin-film transistor. The storage capacitor includes a sub-capacitor. The sub-capacitor is disposed between the semiconductor patterns spaced apart in the first direction.

[0021] The semiconductor patterns may be spaced apart in a second direction. The second direction may be a direction perpendicular to the first direction. Each semiconductor pattern and the semiconductor pattern adjacent thereto in the first direction may be staggered in the second direction.

[0022] The second thin-film transistor may include a plurality of gate electrodes, a plurality of drain electrodes, and a plurality of source electrodes. The plurality of gate electrodes may be electrically connected to the gate connection line. The plurality of drain electrodes may be electrically connected to the drain connection line. The plurality of source electrodes may be electrically connected to the source connection line. Each gate electrode may overlap a channel region of at least one semiconductor pattern. Each drain electrode may be electrically connected to a drain region of at least one semiconductor pattern. Each source electrode may be electrically connected to a source region of at least one semiconductor pattern.

[0023] The drain electrode may be disposed on the same layer as the drain connection line. The source electrode may be disposed on the same layer as the source connection line. The gate electrode may be disposed on a different layer from the gate connection line.

[0024] The source connection line may be disposed on a different layer from the gate connection line. The sub-capacitor may have a stacked structure of a first capacitor electrode and a second capacitor electrode. The first capacitor electrode may be disposed on the same layer as the gate connection line. The second capacitor electrode may be disposed on the same layer as the source connection line. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] This application includes drawings to provide a further understanding of the present disclosure. The drawings are incorporated into and constitute a part of this application, showing embodiments of the present disclosure, and are used together with the description to explain the principles of the present disclosure. In the drawings:

[0026] Figure 1 is a diagram schematically showing a display device according to an embodiment of the present disclosure;

[0027] Figure 2 is a diagram showing a circuit of a pixel region in a display device according to an embodiment of the present disclosure;

[0028] Figure 3 is a plan view showing a second thin film transistor and a storage capacitor disposed in a pixel region of a display device according to an embodiment of the present disclosure;

[0029] Figure 4 is Figure 3 an enlarged view of the K region in;

[0030] Figure 5 is along Figure 4 I-I' and II-II' of;

[0031] Figure 6 is along Figure 4 III-III' of;

[0032] Figure 7 is along Figure 4 IV-IV' of;

[0033] Figure 8 is along Figure 4 V-V' of;

[0034] Figures 9 to 12 is a diagram showing a display device according to other embodiments of the present disclosure. Detailed Description

[0035] Hereinafter, through the following detailed description with reference to the accompanying drawings, details related to the above objects, technical configurations, and operational effects of the embodiments of the present disclosure will be clearly understood. The accompanying drawings show some embodiments of the present disclosure. Here, the embodiments of the present disclosure are provided to allow the technical spirit of the present disclosure to be satisfactorily conveyed to those skilled in the art. Therefore, the present disclosure may be embodied in other forms and is not limited to the embodiments described below.

[0036] In addition, throughout the specification and the drawings, the same or extremely similar elements may be denoted by the same reference numerals. For convenience, the lengths and thicknesses of layers and regions may be exaggerated. It should be understood that when a first element is referred to as being "on" a second element, although the first element may be disposed on the second element to be in contact with the second element, a third element may be inserted between the first element and the second element.

[0037] Here, terms such as "first" and "second" may be used to distinguish any one element from another. However, without departing from the technical spirit of the present disclosure, the first element and the second element may be arbitrarily named according to the convenience of those skilled in the art.

[0038] The terms used in the description of the present disclosure are only for describing specific embodiments and are not intended to limit the scope of the present disclosure. For example, unless the context clearly indicates otherwise, an element described in the singular form is intended to include a plurality of elements. Additionally, in the description of the present disclosure, it will be further understood that the terms "comprising" and "including" specify the presence of the stated features, integers, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations.

[0039] Also, unless "directly" is used, the terms "connected" and "coupled" may include that two components are "connected" or "coupled" through one or more other components located between the two components.

[0040] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those of ordinary skill in the art to which the exemplary embodiments belong. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0041] (Embodiment)

[0042] Figure 1 is a diagram schematically showing a display device according to an embodiment of the present disclosure. Figure 2 is a diagram showing a circuit of a pixel region in a display device according to an embodiment of the present disclosure.

[0043] Reference Figure 1 and Figure 2, a display device according to an embodiment of the present disclosure may include a display panel DP. The display panel DP may generate an image provided to a user. For example, the display panel DP may include a plurality of pixel regions PA. Each pixel region PA may be defined by signal wirings GL, DL, PL, RL. For example, each pixel region PA may be surrounded by the signal wirings GL, DL, PL, RL. The signal wirings GL, DL, PL, RL may apply various signals to each pixel region PA. For example, the signal wirings GL, DL, PL, RL may include a gate line GL that sequentially applies a gate signal, a data line DL that applies a data signal, a power voltage supply line PL that provides a power voltage, and a reference voltage supply line RL that provides a reference voltage.

[0044] The gate line GL may be electrically connected to a gate driver GD. The data line DL may be electrically connected to a data driver DD. The power voltage supply line PL and the reference voltage supply line RL may be electrically connected to a power supply unit PU. The gate driver GD and the data driver DD may be controlled by a timing controller TC. For example, the gate driver GD may receive a clock signal, a reset signal, and a start signal from the timing controller TC, and the data driver DD may receive digital video data and a source timing signal from the timing controller TC.

[0045] The display panel DP may include an active area AA in which the pixel regions PA are provided, and a border area BZ provided outside the active area AA. The border area BZ may be provided outside the pixel regions PA. For example, the active area AA may be surrounded by the border area BZ. The gate driver GD, the data driver DD, the power supply unit PU, and the timing controller TC may be provided outside the active area AA. For example, each of the signal wirings GL, DL, PL, RL may include a portion provided on the border area BZ.

[0046] At least one of the gate driver GD, the data driver DD, the power supply unit PU, and the timing controller TC may be provided on the border area BZ. For example, a display device according to an embodiment of the present disclosure may be a gate-in-panel (GIP) type display device in which the gate driver GD is formed on the border area BZ.

[0047] Each pixel region PA can achieve a specific color through signal wirings GL, DL, PL, RL. For example, a driving circuit DC electrically connected to the display device 300 can be provided in each pixel region PA. The driving circuit DC of each pixel region PA can be electrically connected to the signal wirings GL, DL, PL, RL. For example, the driving circuit DC of each pixel region PA can be electrically connected to a gate line GL, a data line DL, a power supply voltage line PL, and a reference voltage line R. The driving circuit DC of each pixel region PA can supply a driving current corresponding to the data signal to the display device 300 of the corresponding pixel region PA according to the gate signal of a frame. For example, the driving circuit DC of each pixel region PA can include a first thin film transistor TR1, a second thin film transistor TR2, a third thin film transistor TR3, and a storage capacitor Cst.

[0048] The first thin film transistor TR1 can transfer the data signal to the second thin film transistor TR2 according to the gate signal. For example, the first thin film transistor TR1 can be used as a switching thin film transistor. The first thin film transistor TR1 can include a first semiconductor pattern, a first gate electrode, a first drain electrode, and a first source electrode. For example, the first gate electrode can be electrically connected to the corresponding gate line GL, and the first drain electrode can be electrically connected to the corresponding data line DL.

[0049] The first semiconductor pattern can include a semiconductor material. For example, the first semiconductor pattern can include amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or an oxide semiconductor such as IGZO. The first semiconductor pattern can include a first drain region, a first channel region, and a first source region. The first channel region can be disposed between the first drain region and the first source region. The resistance of the first drain region and the resistance of the first source region can be less than the resistance of the first channel region. For example, the first drain region and the first source region can include a conductive region of an oxide semiconductor. The first channel region can be an unconductive region of an oxide semiconductor.

[0050] The first gate electrode can be disposed on a part of the first semiconductor pattern. For example, the first gate electrode can overlap with the first channel region of the first semiconductor pattern. The first drain region and the first source region of the first semiconductor pattern can be disposed outside the first gate electrode. The first gate electrode can include a conductive material. For example, the first gate electrode can include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first gate electrode can be spaced apart from the first semiconductor pattern. The first gate electrode can be insulated from the first semiconductor pattern. For example, the first drain region of the first semiconductor pattern can be electrically connected to the first source region of the first semiconductor pattern according to the signal applied to the first gate electrode.

[0051] The first drain electrode may include a conductive material. For example, the first drain electrode may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first drain electrode may include a material different from that of the first gate electrode. For example, the first drain electrode may be disposed on a layer different from the first gate electrode. The first drain electrode may be electrically connected to the first drain region of the first semiconductor pattern. The first drain electrode may be insulated from the first gate electrode.

[0052] The first source electrode may include a conductive material. For example, the first source electrode may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first source electrode may include a material different from that of the first gate electrode. The first source electrode may be disposed on a layer different from the first gate electrode. For example, the first source electrode may be disposed on the same layer as the first drain electrode. The first source electrode may include the same material as the first drain electrode. The first source electrode may be formed by the same process as the first drain electrode. For example, the first source electrode may be formed simultaneously with the first drain electrode. The first source electrode may be electrically connected to the first source region of the first semiconductor pattern. The first source electrode may be insulated from the first gate electrode. The first source electrode may be spaced apart from the first drain electrode.

[0053] Figure 3 is a plan view showing a second thin film transistor and a storage capacitor disposed in a pixel region of a display device according to an embodiment of the present disclosure. Figure 4 is Figure 3 an enlarged view of the K region in Figure 5 is a view taken along Figure 4 I-I' and II-II' of Figure 6 is a view taken along Figure 4 III-III' of Figure 7 is a view taken along Figure 4 IV-IV' of Figure 8 is a view taken along Figure 4 V-V' of

[0054] Referring to Figures 2 to 8 , the second thin film transistor TR2 may generate a driving current corresponding to a data signal. For example, the second thin film transistor TR2 may be used as a driving thin film transistor. The second thin film transistor TR2 may include a plurality of second semiconductor patterns 221, a plurality of second gate electrodes 223, a gate connection line 223c, a plurality of second drain electrodes 225, a drain connection line 225c, a plurality of second source electrodes 227, and a source connection line 227c.

[0055] Each second semiconductor pattern 221 may include a semiconductor material. For example, each second semiconductor pattern 221 may include amorphous silicon (a-Si), polysilicon (poly-Si), or an oxide semiconductor such as IGZO. Each second semiconductor pattern 221 may include the same material as an adjacent second semiconductor pattern 221. Each second semiconductor pattern 221 may be disposed on the same layer as an adjacent second semiconductor pattern 221. Each second semiconductor pattern 221 may be formed by the same process as an adjacent second semiconductor pattern 221. For example, each second semiconductor pattern 221 may be formed simultaneously with an adjacent second semiconductor pattern 221. The second semiconductor patterns 221 may be arranged side by side in a first direction X and a second direction Y perpendicular to the first direction X. For example, each second semiconductor pattern 221 may be spaced apart from a second semiconductor pattern 221 adjacent in the first direction X and a second semiconductor pattern 221 adjacent in the second direction Y. A distance dy between second semiconductor patterns 221 adjacent in the second direction Y may be the same as a distance dx between second semiconductor patterns 221 adjacent in the first direction X.

[0056] Each second semiconductor pattern 221 may include a second drain region, a second channel region, and a second source region. The second channel region may be disposed between the second drain region and the second source region. The second drain region and the second source region may have a resistance smaller than that of the second channel region. For example, the second drain region and the second source region may include a conductive region of an oxide semiconductor. The second channel region may be an unconductive region of the oxide semiconductor.

[0057] Each second gate electrode 223 may be disposed on a part of at least one second semiconductor pattern 221. For example, each second gate electrode 223 may overlap with the second channel region of at least one second semiconductor pattern 221. The second drain region and the second source region of each second semiconductor pattern 221 may be disposed outside the second gate electrode 223. Each second gate electrode 223 may extend in the second direction Y. For example, the second channel regions of second semiconductor patterns 221 arranged side by side in the second direction Y may overlap with one second gate electrode 223. Each second gate electrode 223 may be spaced apart from a second gate electrode 223 adjacent in the first direction X.

[0058] Each second gate electrode 223 may include a conductive material. For example, each second gate electrode 223 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). Each second gate electrode 223 may be spaced apart from the second semiconductor pattern 221. Each second gate electrode 223 may be insulated from the second semiconductor pattern 221. For example, the second channel region of each second semiconductor pattern 221 may have a conductivity corresponding to the voltage applied to one second gate electrode 223.

[0059] The gate connection line 223c may be electrically connected to the first thin film transistor TR1 through the first node N1. For example, the first node N1 may be electrically connected to the first source electrode and the gate connection line 223c. The gate connection line 223c may include a conductive material. For example, the gate connection line 223c may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W).

[0060] Each second gate electrode 223 may be electrically connected to the gate connection line 223c. For example, the data signal transmitted through the first source electrode of the first thin film transistor TR1 may be simultaneously provided to the second gate electrode 223 through the gate connection line 223c. The gate connection line 223c may extend in the first direction X. The gate connection line 223c may include a material different from that of the second gate electrode 223. For example, the gate connection line 223c may be provided on a layer different from that of the second gate electrode 223. Each second gate electrode 223 may include a first end electrically connected to the gate connection line 223c.

[0061] Each second drain electrode 225 may include a conductive material. For example, each second drain electrode 225 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second drain electrode 225 may include the same material as the second gate electrode 223. The second drain electrode 225 may be provided on the same layer as the second gate electrode 223. The second drain electrode 225 may be formed by the same process as the second gate electrode 223. For example, the second drain electrode 225 may be formed simultaneously with the second gate electrode 223.

[0062] Each second drain electrode 225 may be electrically connected to the second drain region of at least one second semiconductor pattern 221. Each second drain electrode 225 may be spaced apart from the second gate electrode 223. Each second drain electrode 225 may be insulated from the second gate electrode 223. Each second drain electrode 225 may extend in the second direction Y. For example, the second drain regions of the second semiconductor patterns 221 arranged side by side in the second direction Y may be electrically connected to one second drain electrode 225. Each second drain electrode 225 may be spaced apart from the second drain electrode 225 adjacent in the first direction X.

[0063] The drain connection line 225c can be electrically connected to the corresponding power supply voltage line PL through the second node N2. The drain connection line 225c can include a conductive material. For example, the drain connection line 225c can include metals such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W).

[0064] Each second drain electrode 225 can be electrically connected to the drain connection line 225c. For example, the power supply voltage provided through the second node N2 can be simultaneously provided to the second drain electrodes 225 through the drain connection line 225c. The drain connection line 225c can extend in the first direction X. The drain connection line 225c can include a material different from that of the gate connection line 223c. The drain connection line 225c can be disposed on a layer different from that of the gate connection line 223c. For example, the drain connection line 225c can be disposed on the same layer as the second drain electrode 225. The drain connection line 225c can include the same material as the second drain electrode 225. The drain connection line 225c can be formed by the same process as the second drain electrode 225. For example, the drain connection line 225c can be formed simultaneously with the second drain electrode 225. Each second drain electrode 225 can be in direct contact with the drain connection line 225c. Each second gate electrode 223 can be spaced apart from the drain connection line 225c. Each second gate electrode 223 can be insulated from the drain connection line 225c.

[0065] Each second source electrode 227 can include a conductive material. For example, each second source electrode 227 can include metals such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second source electrode 227 can include the same material as the second drain electrode 225. The second source electrode 227 can be disposed on the same layer as the second drain electrode 225. The second source electrode 227 can be formed by the same process as the second drain electrode 225. For example, the second source electrode 227 can be formed simultaneously with the second drain electrode 225.

[0066] Each second source electrode 227 can be electrically connected to the second source region of at least one second semiconductor pattern 221. Each second source electrode 227 can be insulated from the second gate electrode 223. Each second source electrode 227 can be spaced apart from the second gate electrode 223 and the second drain electrode 225. Each second source electrode 227 can extend in the second direction Y. For example, the second source regions of the second semiconductor patterns 221 arranged side by side in the second direction Y can be electrically connected to one second source electrode 227. Each second source electrode 227 can be spaced apart from the second source electrodes 227 adjacent in the first direction X.

[0067] Each second semiconductor pattern 221 may form a sub-transistor St together with a second gate electrode 223, a second drain electrode 225, and a second source electrode 227. The second gate electrode 223 overlaps a second channel region of the corresponding second semiconductor pattern 221. The second drain electrode 225 is electrically connected to a second drain region of the corresponding second semiconductor pattern 221. The second source electrode 227 is electrically connected to a second source region of the corresponding second semiconductor pattern 221. For example, the second thin film transistor TR2 may include a plurality of sub-transistors St. The plurality of sub-transistors St may be arranged side by side in a first direction X and a second direction Y. For example, each sub-transistor St may include a second gate electrode 223 different from the sub-transistor St adjacent in the first direction X. The sub-transistors St adjacent in the second direction Y may include the same second drain electrode 225 and the same second source electrode 227.

[0068] The source connection line 227c may be electrically connected to the third node N3. The source connection line 227c may include a conductive material. For example, the source connection line 227c may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W).

[0069] Each second source electrode 227 may be electrically connected to the source connection line 227c. For example, the source connection line 227c may extend in the first direction X. The source connection line 227c may include a material different from that of the gate connection line 223c. The source connection line 227c may be disposed on a layer different from that of the gate connection line 223c. For example, the source connection line 227c may be disposed on the same layer as the second source electrode 227. The source connection line 227c may include the same material as the second source electrode 227. The source connection line 227c may be formed by the same process as the second source electrode 227. For example, the source connection line 227c may be formed simultaneously with the second source electrode 227. Each second source electrode 227 may be in direct contact with the source connection line 227c. Each second gate electrode 223 and each second drain electrode 225 may be spaced apart from the source connection line 227c. Each second gate electrode 223 and each second drain electrode 225 may be insulated from the source connection line 227c. Accordingly, in the display device according to an embodiment of the present disclosure, the plurality of sub-transistors St may be used as a single second thin film transistor TR2. For example, in the display device according to an embodiment of the present disclosure, the second thin film transistor TR2 in each pixel region PA may include a plurality of sub-transistors St connected in parallel through a gate connection line 223c, a drain connection line 225c, and a source connection line 227c of the corresponding pixel region PA.

[0070] The second semiconductor pattern 221 may be disposed between the drain connection line 225c and the source connection line 227c. For example, the gate connection line 223c may extend between the drain connection line 225c and the second semiconductor pattern 221 and between the second semiconductor pattern 221 and the source connection line 227c. In a display device according to an embodiment of the present disclosure, when one of the sub-transistors is not normally driven, one second gate electrode 223, one second drain electrode 225, and one second source electrode 227 may be cut so that the sub-transistor St adjacent to the corresponding sub-transistor St in the second direction Y may not be driven. Therefore, in a display device according to an embodiment of the present disclosure, even if a defect occurs in some sub-transistors St due to a conductive foreign substance or electrostatic short circuit, a driving current may be generated by the second thin film transistor TR2. That is, in a display device according to an embodiment of the present disclosure, the second thin film transistor TR2 may be repaired. Therefore, in a display device according to an embodiment of the present disclosure, the reliability of the second thin film transistor TR2 may be improved.

[0071] The third thin film transistor TR3 may transfer a reference voltage to the storage capacitor Cst according to a gate signal. For example, the third thin film transistor TR3 may be used as a switching thin film transistor. The third thin film transistor TR3 may have the same structure as the first thin film transistor TR1. For example, the third thin film transistor TR3 may include a third semiconductor pattern, a third gate electrode, a third drain electrode, and a third source electrode. The third gate electrode may be electrically connected to the corresponding gate line GL, the third drain electrode may be electrically connected to the corresponding reference voltage supply line RL, and the third source electrode may be electrically connected to the third node N3.

[0072] The third semiconductor pattern may include a semiconductor material. For example, the third semiconductor pattern may include amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or an oxide semiconductor such as IGZO. The third semiconductor pattern may include a third drain region, a third channel region, and a third source region. The third channel region may be disposed between the third drain region and the third source region. The resistance of the third drain region and the resistance of the third source region may be less than the resistance of the third channel region. For example, the third drain region and the third source region may include a conductive region of an oxide semiconductor. The third channel region may be an unconductive region of an oxide semiconductor.

[0073] The third semiconductor pattern may include the same material as the first semiconductor pattern. The third semiconductor pattern may be disposed on the same layer as the first semiconductor pattern. The third semiconductor pattern may be formed by the same process as the first semiconductor pattern. For example, the third semiconductor pattern may be formed simultaneously with the first semiconductor pattern.

[0074] The third gate electrode may be disposed on a part of the third semiconductor pattern. For example, the third gate electrode may overlap with the third channel region of the third semiconductor pattern. The third drain region and the third source region of the third semiconductor pattern may be disposed outside the third gate electrode. The third gate electrode may include a conductive material. For example, the third gate electrode may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The third gate electrode may be spaced apart from the third semiconductor pattern. The third gate electrode may be insulated from the third semiconductor pattern. For example, the third drain region of the third semiconductor pattern may be electrically connected to the third source region of the third semiconductor pattern according to a signal applied to the third gate electrode.

[0075] The third gate electrode may include the same material as the first gate electrode. The third gate electrode may be disposed on the same layer as the first gate electrode. The third gate electrode may be formed by the same process as the first gate electrode. For example, the third gate electrode may be formed simultaneously with the first gate electrode.

[0076] The third drain electrode may include a conductive material. For example, the third drain electrode may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The third drain electrode may include a material different from that of the third gate electrode. For example, the third drain electrode may be disposed on a layer different from that of the third gate electrode. The third drain electrode may be electrically connected to the third drain region of the third semiconductor pattern. The third drain electrode may be insulated from the third gate electrode.

[0077] The third drain electrode may include the same material as the first drain electrode. The third drain electrode may be disposed on the same layer as the first drain electrode. The third drain electrode may be formed by the same process as the first drain electrode. For example, the third drain electrode may be formed simultaneously with the first drain electrode.

[0078] The third source electrode may include a conductive material. For example, the third source electrode may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The third source electrode may include a material different from that of the third gate electrode. The third source electrode may be disposed on a layer different from that of the third gate electrode. For example, the third source electrode may be disposed on the same layer as the third drain electrode. The third source electrode may include the same material as the third drain electrode. The third source electrode may be formed by the same process as the third drain electrode. For example, the third source electrode may be formed simultaneously with the third drain electrode. The third source electrode may be electrically connected to the third source region of the third semiconductor pattern. The third source electrode may be insulated from the third gate electrode. The third source electrode may be spaced apart from the third drain electrode.

[0079] The storage capacitor Cst can hold the signal applied to the first node N1 for one frame. For example, the storage capacitor Cst can be electrically connected to the first node N1 and the third node N3. The storage capacitor Cst can be disposed between the drain connection line 225c and the source connection line 227c. For example, the storage capacitor Cst can include a plurality of sub-capacitors Sc, and the plurality of sub-capacitors Sc are disposed between the second semiconductor patterns 221 spaced apart in the first direction X. Accordingly, in the display device according to an embodiment of the present disclosure, the gap between adjacent sub-transistors St in the first direction X can be sufficiently ensured without increasing the size of each pixel region PA. That is, in the display device according to an embodiment of the present disclosure, the heat generated by the operation of the driving circuit DC in each pixel region PA can be quickly dissipated through the space between the second semiconductor patterns 221 spaced apart in the first direction X. Accordingly, in the display device according to an embodiment of the present disclosure, the deterioration of the second thin film transistor TR2 due to the operation of the driving circuit DC in each pixel region PA can be reduced or minimized. Also, in the display device according to an embodiment of the present disclosure, the high current driving that generates relatively more heat can be stably operated.

[0080] Each sub-capacitor Sc can have a stacked structure of capacitor electrodes 231 and 232. For example, each sub-capacitor Sc can include a first capacitor electrode 231 electrically connected to the gate connection line 223c and a second capacitor electrode 232 electrically connected to the source connection line 227c. The first capacitor electrode 231 and the second capacitor electrode 232 of each sub-capacitor Sc can include a conductive material.

[0081] Each sub-capacitor Sc can be formed by the process of forming the second thin film transistor TR2. For example, the first capacitor electrode 231 can be disposed on the same layer as the gate connection line 223c, and the second capacitor electrode 232 can be disposed on the same layer as the source connection line 227c. The first capacitor electrode 231 can include the same material as the gate connection line 223c, and the second capacitor electrode 232 can include the same material as the source connection line 227c. The first capacitor electrode 231 can be formed by the same process as the gate connection line 223c, and the second capacitor electrode 232 can be formed by the same process as the source connection line 227c. For example, the first capacitor electrode 231 can be formed simultaneously with the gate connection line 223c, and the second capacitor electrode 232 can be formed simultaneously with the source connection line 227c. Accordingly, in the display device according to an embodiment of the present disclosure, the reduction in process efficiency due to the process of forming the storage capacitor Cst can be prevented.

[0082] The first capacitor electrode 231 of each sub-capacitor Sc can be directly connected to the gate connection line 223c. Each sub-capacitor Sc can be surrounded by a second drain electrode 225 and a second source electrode 227. For example, the second capacitor electrodes 232 of some sub-capacitors Sc can be directly connected to the source connection line 227c, and the second capacitor electrodes 232 of the remaining sub-capacitors Sc can be connected to the source connection line 227c through the auxiliary connection line 250.

[0083] The auxiliary connection line 250 can include a conductive material. For example, the auxiliary connection line 250 can include metals such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The auxiliary connection line 250 can be disposed on a layer different from the gate connection line 223c and the source connection line 227c. For example, the auxiliary connection line 250 can include a material different from the gate connection line 223c and the source connection line 227c.

[0084] The sub-capacitors Sc can be individually connected to the gate connection line 223c and the source connection line 227c. Thus, in the display device according to an embodiment of the present disclosure, when a defect occurs in some sub-capacitors Sc, the regions between the corresponding sub-capacitors Sc and the gate connection line 223c and between the corresponding sub-capacitors Sc and the source connection line 227c can be removed so that the corresponding sub-capacitors Sc can be electrically insulated from the gate connection line 223c and the source connection line 227c. For example, in the display device according to an embodiment of the present disclosure, the storage capacitor Cst can be repaired by a process of removing a part of the auxiliary connection line 250 and a part of the second capacitor electrode 232 of the defective sub-capacitor Sc with a laser. That is, in the display device according to an embodiment of the present disclosure, even if a defect occurs in some sub-capacitors Sc due to conductive foreign matter or electrostatic short circuit, the voltage applied to the first node N1 through the storage capacitor Cst can be maintained for one frame. Therefore, in the display device according to an embodiment of the present disclosure, the reliability of the driving circuit DC in each pixel region PA can be improved.

[0085] The driving circuit DC of each pixel region PA and the display device 300 can be supported by the device substrate 100. For example, the driving circuit DC of each pixel region PA and the display device 300 can be disposed on the device substrate 100. The device substrate 100 can include an insulating material. For example, the device substrate 100 can include glass or plastic.

[0086] A plurality of insulating layers 110, 120, 130, 140, 150, and 160 for preventing unnecessary electrical connections may be provided on the device substrate 100. For example, a buffer insulating layer 110, a gate insulating layer 120, an interlayer insulating layer 130, a device passivation layer 140, a planarization layer 150, and a dam insulating layer 160 may be provided on the device substrate 100.

[0087] The buffer insulating layer 110 may be provided close to the device substrate 100. The buffer insulating layer 110 may prevent contamination caused by the device substrate 100 during the formation of the first semiconductor pattern, the second semiconductor pattern 221, and the third semiconductor pattern in each pixel region PA. For example, the upper surfaces of the first semiconductor pattern, the second semiconductor pattern 221, and the third semiconductor pattern of the device substrate 100 facing each pixel region PA may be completely covered by the buffer insulating layer 110. The first semiconductor pattern, the second semiconductor pattern 221, and the third semiconductor pattern in each pixel region PA may be provided on the buffer insulating layer 110. The buffer insulating layer 110 may include an insulating material. For example, the buffer insulating layer 110 may include inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx). The buffer insulating layer 110 may include a multilayer structure. For example, the buffer insulating layer 110 may have a stacked structure of an inorganic insulating layer made of silicon oxide (SiOx) and an inorganic insulating layer made of silicon nitride (SiNx).

[0088] A light-shielding pattern 105 may be provided between the device substrate 100 and the buffer insulating layer 110 of each pixel region PA. The light-shielding pattern 105 in each pixel region PA may include a material capable of absorbing or blocking light. For example, the light-shielding pattern 105 in each pixel region PA may include metals such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). Light traveling through the device substrate 100 in the direction of the second semiconductor pattern 221 in each pixel region PA may be blocked by one of the light-shielding patterns 105 in the corresponding pixel region PA. Therefore, in the display device according to an embodiment of the present disclosure, characteristic changes of the second thin film transistor TR2 in each pixel region PA due to external light may be prevented.

[0089] The first capacitor electrode 231 of each sub-capacitor Sc in each pixel region PA may be disposed between the device substrate 100 and the buffer insulating layer 110. For example, the light-shielding pattern 105 of each pixel region PA may be disposed on the same layer as the gate connection line 223c and the first capacitor electrode 231 of the corresponding pixel region PA. The light-shielding pattern 105, the gate connection line 223c, and the first capacitor electrode 231 of each pixel region PA may be covered by the buffer insulating layer 110. For example, the light-shielding pattern 105, the gate connection line 223c, and the first capacitor electrode 231 of each pixel region PA may be in direct contact with the upper surface of the device substrate 100. The light-shielding pattern 105 of each pixel region PA may include the same material as the gate connection line 223c and the first capacitor electrode 231 of the corresponding pixel region PA. The light-shielding pattern 105 of each pixel region PA may be formed by the same process as the gate connection line 223c and the first capacitor electrode 231 of the corresponding pixel region PA. For example, the light-shielding pattern 105 of each pixel region PA may be formed simultaneously with the gate connection line 223c and the first capacitor electrode 231 of the corresponding pixel region PA.

[0090] Each light-shielding pattern 105 may extend in the second direction Y. Each light-shielding pattern 105 may be spaced apart from the light-shielding pattern 105 adjacent in the first direction X. For example, the second semiconductor pattern 221 arranged side by side in the second direction in each pixel region PA may overlap with one light-shielding pattern 105 in the corresponding pixel region PA. A specific voltage may be applied to each light-shielding pattern 105. For example, each light-shielding pattern 105 in each pixel region PA may be electrically connected to the source connection line 227c. Accordingly, in the display device according to an embodiment of the present disclosure, a change in characteristics of the second thin film transistor TR2 in each pixel region PA due to external light can be effectively prevented. The light-shielding pattern 105 of each pixel region PA may be spaced apart from the gate connection line 223c and the first capacitor electrode 231 of the corresponding pixel region PA. For example, each light-shielding pattern 105 in each pixel region PA may be disposed between the first capacitor electrodes 231 of the corresponding pixel region PA. The light-shielding pattern 105 and the first capacitor electrode 231 of each pixel region PA may be alternately disposed in the first direction X.

[0091] The gate insulating layer 120 may be disposed on the buffer insulating layer 110. The first gate electrode of each pixel region PA may be insulated from the first semiconductor pattern of the corresponding pixel region PA through the gate insulating layer 120. The second gate electrode 223 of each pixel region PA may be insulated from the second semiconductor pattern 221 of the corresponding pixel region PA through the gate insulating layer 120. The third gate electrode of each pixel region PA may be insulated from the third semiconductor pattern of the corresponding pixel region PA through the gate insulating layer 120. For example, the gate insulating layer 120 may cover the first semiconductor pattern, the second semiconductor pattern 221, and the third semiconductor pattern of each pixel region PA. The first gate electrode, the second gate electrode 223, the second drain electrode 225, the second source electrode 227, and the third gate electrode of each pixel region PA may be disposed on the gate insulating layer 120. The gate insulating layer 120 may include an insulating material. For example, the gate insulating layer 120 may include an inorganic insulating material.

[0092] The interlayer insulating layer 130 may be disposed on the gate insulating layer 120. The interlayer insulating layer 130 may include an insulating material. For example, the interlayer insulating layer 130 may be an inorganic insulating material.

[0093] The drain connection line 225c and the source connection line 227c of each pixel region PA can be disposed on the same layer as the second gate electrode 223, the second drain electrode 225, and the second source electrode 227 of the corresponding pixel region PA. For example, the drain connection line 225c and the source connection line 227c of each pixel region PA can be disposed between the gate insulating layer 120 and the interlayer insulating layer 130 of the corresponding pixel region PA. The interlayer insulating layer 130 can cover the drain connection line 225c and the source connection line 227c of each pixel region PA. The first drain electrode, the first source electrode, the third drain electrode, and the third source electrode of each pixel region PA can be disposed on a layer different from the second drain electrode 225 and the second source electrode 227 of the corresponding pixel region PA. For example, the first drain electrode, the first source electrode, the third drain electrode, and the third source electrode of each pixel region PA can be disposed on the interlayer insulating layer 130. The interlayer insulating layer 130 can cover the first gate electrode, the second gate electrode 223, the second drain electrode 225, the second source electrode 227, and the third gate electrode of each pixel region PA. The first drain electrode and the first source electrode of each pixel region PA can be insulated from the first gate electrode of the corresponding pixel region PA through the gate insulating layer 120 and the interlayer insulating layer 130. The third drain electrode and the third source electrode of each pixel region PA can be insulated from the third gate electrode of the corresponding pixel region PA through the gate insulating layer 120 and the interlayer insulating layer 130. Each second drain electrode 225 can penetrate the gate insulating layer 120 to directly contact the second drain region of the corresponding second semiconductor pattern 221. Each second source electrode 227 can penetrate the gate insulating layer 120 to directly contact the second source region of the corresponding second semiconductor pattern 221.

[0094] The auxiliary connection line 250 of each pixel region PA can be disposed on the same layer as the first drain electrode, the first source electrode, the third drain electrode, and the third source electrode of the corresponding pixel region PA. For example, the auxiliary connection line 250 of each pixel region PA can be disposed on the interlayer insulating layer 130. The auxiliary connection line 250 of each pixel region PA can include the same material as the first drain electrode, the first source electrode, the third drain electrode, and the third source electrode of the corresponding pixel region PA. The auxiliary connection line 250 of each pixel region PA can be formed by the same process as the first drain electrode, the first source electrode, the third drain electrode, and the third source electrode of the corresponding pixel region PA. For example, the auxiliary connection line 250 of each pixel region PA can be formed simultaneously with the first drain electrode, the first source electrode, the third drain electrode, and the third source electrode of the corresponding pixel region PA. The auxiliary connection line 250 of each pixel region PA can be in direct contact with the source connection line 227c of the corresponding pixel region PA and the second capacitor electrode 232 of some sub-capacitors Sc.

[0095] The device passivation layer 140 may be disposed on the interlayer insulating layer 130. The device passivation layer 140 may prevent the driving circuit DC in each pixel region PA from being damaged due to external impact and moisture. For example, the driving circuit DC of each pixel region PA may be covered by the device passivation layer 140. The device passivation layer 140 may cover the first drain electrode, the first source electrode, the third drain electrode, and the third source electrode of each pixel region PA. The auxiliary connection line 250 of each pixel region PA may be covered by the device passivation layer 140. The device passivation layer 140 may include an insulating material. For example, the device passivation layer 140 may be an inorganic insulating layer made of an inorganic insulating material.

[0096] The planarization layer 150 may be disposed on the device passivation layer 140. The planarization layer 150 may remove the thickness difference caused by the driving circuit DC of each pixel region PA. For example, the upper surface of the planarization layer 150 opposite to the device substrate 100 may be a flat surface. The upper surface of the planarization layer 150 may be parallel to the upper surface of the device substrate 100. The planarization layer 150 may include an insulating material. The planarization layer 150 may include a material different from that of the device passivation layer 140. The planarization layer 150 may include a material having relatively high fluidity. For example, the planarization layer 150 may include an organic insulating material.

[0097] The display device 300 of each pixel region PA may be disposed on the planarization layer 150. The display device 300 of each pixel region PA may emit light of a specific color for display. For example, the display device 300 of each pixel region PA may include a first electrode 310, a light-emitting unit 320, and a second electrode 330, which are sequentially stacked on the planarization layer 150 of the corresponding pixel region PA.

[0098] The first electrode 310 may include a conductive material. The first electrode 310 may include a material having a high reflectivity. For example, the first electrode 310 may include a metal such as aluminum (Al) or silver (Ag). The first electrode 310 may have a multilayer structure. For example, the first electrode 310 may have a structure in which a reflective electrode made of a metal is disposed between transparent electrodes made of a transparent conductive material (such as ITO and IZO).

[0099] The light-emitting unit 320 may generate light having a brightness corresponding to the voltage difference between the first electrode 310 and the second electrode 330. For example, the light-emitting unit 320 may include a light-emitting material layer (EML). The light-emitting material layer may include a light-emitting material. The light-emitting material may include an organic material, an inorganic material, or a hybrid material. For example, the display device according to an embodiment of the present disclosure may be an organic light-emitting display device including an organic light-emitting material.

[0100] Multiple light-emitting material layers EML may be provided in the light-emitting unit 320. For example, the light-emitting unit 320 may include a plurality of light-emitting stacks and at least one charge generation layer between the light-emitting stacks, and the light-emitting stack has at least one light-emitting material layer. The charge generation layer may supply holes or electrons to adjacent light-emitting stacks. Thus, in the display device according to an embodiment of the present disclosure, each light-emitting stack may emit light. The light emitted from each light-emitting stack may display the same color. Thus, in the display device according to an embodiment of the present disclosure, color reproduction may be improved.

[0101] The light-emitting unit 320 may include at least one functional layer. The functional layer may be one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). Thus, in the display device according to an embodiment of the present disclosure, the efficiency of the light-emitting unit 320 may be improved.

[0102] The second electrode 330 may include a conductive material. The second electrode 330 may include a material different from that of the first electrode 310. The transmittance of the second electrode 330 may be higher than that of the first electrode 310. For example, the second electrode 330 may be a transparent electrode made of a transparent conductive material such as ITO and IZO, or a semi-transparent electrode formed by a metal such as Ag and Mg thinly. Thus, in the display device according to an embodiment of the present disclosure, the light generated by the light-emitting unit 320 may be emitted to the outside through the second electrode 330.

[0103] The display device 300 in each pixel region PA may be electrically connected to a second thin film transistor TR2 of a driving circuit DC corresponding to the pixel region PA. The first electrode 310 in each pixel region PA may be electrically connected to a third node N3 corresponding to the pixel region PA. The first electrode 310 in each pixel region PA may include a portion overlapping with a source connection line 227c corresponding to the pixel region PA. For example, the first electrode 310 in each pixel region PA may penetrate the planarization layer 150 and be in direct contact with the source connection line 227c corresponding to the pixel region PA. The first electrode 310 in each pixel region PA may include a region directly contacting the upper surface of the planarization layer 150. For example, the light-emitting unit 320 and the second electrode 330 in each pixel region PA may be stacked on a portion of the corresponding first electrode 310 that is in direct contact with the upper surface of the planarization layer 150.

[0104] The bank insulating layer 160 may be provided on the planarization layer 150. The bank insulating layer 160 may include an insulating material. For example, the bank insulating layer 160 may include an organic insulating material. The bank insulating layer 160 may include a material different from that of the planarization layer 150.

[0105] The partition insulating layer 160 may define a light-emitting region in each pixel region PA. The first electrode 310 of each pixel region PA may be partially exposed by the partition insulating layer 160. For example, the edge of the first electrode 310 of each pixel region PA may be covered by the partition insulating layer 160. Accordingly, in the display device according to an embodiment of the present disclosure, the first electrode 310 of each pixel region PA may be insulated from the first electrode 310 of an adjacent pixel region PA through the partition insulating layer 160.

[0106] The portion of the first electrode 310 in each pixel region PA exposed by the partition insulating layer 160 may overlap with the light-emitting region of the corresponding pixel region PA. The portion of the first electrode 310 in each pixel region PA overlapping with the light-emitting region of the corresponding pixel region PA may be in direct contact with the upper surface of the planarization layer 150. That is, in the display device according to an embodiment of the present disclosure, the light-emitting unit 320 and the second electrode 330 of each pixel region PA may be stacked on the light-emitting region of the corresponding pixel region PA defined by the partition insulating layer 160. Accordingly, in the display device according to an embodiment of the present disclosure, luminance deviation according to the light generation position emitted from each pixel region PA may be prevented.

[0107] The voltage applied to the second electrode 330 of each pixel region PA may be the same as the voltage applied to the second electrode 330 of an adjacent pixel region PA. For example, the second electrode 330 of each pixel region PA may be electrically connected to the second electrode 330 of an adjacent pixel region PA. The second electrode 330 of each pixel region PA may include the same material as the second electrode 330 of an adjacent pixel region PA. The second electrode 330 of each pixel region PA may be formed through the same process as the second electrode 330 of an adjacent pixel region PA. For example, the second electrode 330 of each pixel region PA may be formed simultaneously with the second electrode 330 of an adjacent pixel region PA. The second electrode 330 of each pixel region PA may be in direct contact with the second electrode 330 of an adjacent pixel region PA. For example, the second electrode 330 of each pixel region PA may extend onto the partition insulating layer 160. Accordingly, in the display device according to an embodiment of the present disclosure, the process of forming the second electrode 330 in each pixel region PA may be simplified. Also, in the display device according to an embodiment of the present disclosure, the luminance of the light emitted from the light-emitting unit 320 of each pixel region PA may be adjusted by a data signal applied to the driving circuit DC of the corresponding pixel region PA.

[0108] The image implemented by the pixel region PA may include various colors. The light emitted from the display device 300 of each pixel region PA may display a color different from the light emitted from the display device 300 of an adjacent pixel region PA. For example, each pixel region PA may include one of a red pixel region where the light emitted from the display device 300 displays red, a blue pixel region where the light emitted from the display device 300 displays blue, and a green pixel region where the light emitted from the display device 300 displays green. Some light-emitting units 320 of each pixel region PA may be spaced apart from the light-emitting units 320 of an adjacent pixel region PA. For example, the light-emitting material layer (EML) of each pixel region PA may be spaced apart from the light-emitting material layer (EML) of an adjacent pixel region PA. The light-emitting unit 320 of each pixel region PA may include an end portion located on the bank insulating layer 160.

[0109] The encapsulation structure 400 may be disposed on the display device 300 of each pixel region PA. The encapsulation structure 400 may prevent the display device 300 from being damaged due to external moisture and impact. The encapsulation structure 400 may have a multi-layer structure. For example, the encapsulation structure 400 may have a stacked structure of a first encapsulation layer 410, a second encapsulation layer 420, and a third encapsulation layer 430. The first encapsulation layer 410, the second encapsulation layer 420, and the third encapsulation layer 430 may include an insulating material. The second encapsulation layer 420 may include a material different from that of the first encapsulation layer 410 and the third encapsulation layer 430. For example, the first encapsulation layer 410 and the third encapsulation layer 430 may include an inorganic insulating material, and the second encapsulation layer 420 may include an organic insulating material. Accordingly, in the display device according to an embodiment of the present disclosure, the display device 300 can be effectively prevented from being damaged due to external moisture and impact. The thickness difference caused by the display device 300 of each pixel region PA may be removed by the second encapsulation layer 420. The thickness of the second encapsulation layer 420 may be greater than the thickness of the first encapsulation layer 410 and the thickness of the third encapsulation layer 430. For example, the upper surface of the encapsulation structure 400 opposite to the device substrate 100 may be a flat surface. The upper surface of the encapsulation structure 400 may be parallel to the upper surface of the device substrate 100.

[0110] Therefore, a display device according to an embodiment of the present disclosure may include a display device 300 and a driving circuit DC electrically connected to the display device 300 in each pixel region PA. The second thin film transistor TR2 used as a driving thin film transistor in the driving circuit DC may be composed of a plurality of sub-transistors St arranged side by side in a first direction X and a second direction Y. The storage capacitor Cst of the driving circuit DC may include a plurality of sub-capacitors Sc disposed between the sub-transistors St spaced apart in the first direction X. Therefore, in the display device according to an embodiment of the present disclosure, without increasing the overall size, deterioration and / or damage of the second thin film transistor TR2 in the corresponding pixel region PA caused by heat generated by the operation of the driving circuit DC in each pixel region PA can be prevented. Therefore, in the display device according to an embodiment of the present disclosure, the reliability of the driving circuit DC can be improved when driving with a high current.

[0111] Moreover, in the display device according to an embodiment of the present disclosure, the process of separating a part of the second thin film transistor TR2 and / or a part of the storage capacitor Cst in each pixel region PA can be simplified. That is, in the display device according to an embodiment of the present disclosure, even if a part of the second thin film transistor TR2 and / or the storage capacitor Cst in each pixel region PA is partially damaged due to conductive foreign matter or electrostatic short circuit, the driving circuit DC of the corresponding pixel region PA can be normally driven. Therefore, in the display device according to an embodiment of the present disclosure, the efficiency and reliability of the driving circuit DC in each pixel region PA can be improved.

[0112] The display device according to an embodiment of the present disclosure is described as the driving circuit DC of each pixel region PA being composed of a first thin film transistor TR1, a second thin film transistor TR2, a third thin film transistor TR3, and a storage capacitor Cst. However, in a display device according to another embodiment of the present disclosure, the driving circuit DC of each pixel region PA may include a driving thin film transistor and at least one switching thin film transistor. For example, in a display device according to another embodiment of the present disclosure, the driving circuit DC of each pixel region PA may not include the third thin film transistor TR3. Therefore, in a display device according to another embodiment of the present disclosure, the degree of freedom in configuring the driving circuit DC in each pixel region PA can be improved.

[0113] In a display device according to an embodiment of the present disclosure, the positions and electrical connections of the first drain electrode, the first source electrode, the second drain electrode 225, the second source electrode 227, the third drain electrode, and the third source electrode in each pixel region PA may vary according to the configuration of the corresponding driving circuit DC and / or the types of the corresponding thin film transistors TR1, TR2, and TR3. For example, in a display device according to another embodiment of the present disclosure, the second gate connection line 223c of each pixel region PA may be electrically connected to the first drain electrode of the corresponding pixel region PA through the first node N1 of the corresponding pixel region PA. Therefore, in a display device according to another embodiment of the present disclosure, the degree of freedom in the configuration of each driving circuit DC and the types of the corresponding thin film transistors TR1, TR2, and TR3 can be improved.

[0114] A display device according to an embodiment of the present disclosure is described such that the second drain electrode 225 and the second source electrode 227 of each pixel region PA may be provided on the same layer as the second gate electrode 223 of the corresponding pixel region PA. However, in a display device according to another embodiment of the present disclosure, the second drain electrode 225 and the second source electrode 227 of each pixel region PA may be provided on the same layer as the first drain electrode, the first source electrode, the third drain electrode, and the third source electrode of the corresponding pixel region PA. For example, in a display device according to another embodiment of the present disclosure, the second drain electrode 225 and the second source electrode 227 of each pixel region PA may be provided between the interlayer insulating layer 130 and the device passivation layer 140 of the corresponding pixel region PA. Therefore, in a display device according to another embodiment of the present disclosure, the degree of freedom in the configuration of the second thin film transistor TR2 in each pixel region PA can be improved.

[0115] In a display device according to an embodiment of the present disclosure, the second drain region of each second semiconductor pattern 221 in each pixel region PA may be electrically connected to the corresponding second drain electrode 225 through a plurality of contact holes, and the second source region of each second semiconductor pattern 221 may be electrically connected to the corresponding second source electrode 227 through a plurality of contact holes. Therefore, in a display device according to an embodiment of the present disclosure, the electrical connection between the second drain region of each second semiconductor pattern 221 and the corresponding second drain electrode 225 and the electrical connection between the second source region of each second semiconductor pattern 221 and the corresponding second source electrode 227 can be stably maintained. That is, in a display device according to an embodiment of the present disclosure, the sub-transistor St in each pixel region PA can be stably driven. Therefore, in a display device according to an embodiment of the present disclosure, the efficiency and reliability of the driving circuit DC in each pixel region PA can be improved.

[0116] A display device according to another embodiment of the present disclosure may include a color filter disposed on a path of light emitted from a display device 300 in each pixel region PA. For example, in a display device according to another embodiment of the present disclosure, the color filter may be disposed on a packaging structure 400. Light passing through the color filter in each pixel region PA may display the same color as the light emitted from the display device 300 in the corresponding pixel region PA. Accordingly, in a display device according to another embodiment of the present disclosure, color reproduction may be improved.

[0117] A display device according to an embodiment of the present disclosure has been described as light emitted from a display device 300 in each pixel region PA may display a different color from light emitted from a display device 300 in an adjacent pixel region PA. However, in a display device according to another embodiment of the present disclosure, light emitted from a display device 300 in each pixel region PA may display the same color as light emitted from a display device 300 in an adjacent pixel region PA. For example, in a display device according to another embodiment of the present disclosure, the display device 300 in each pixel region PA may emit white light. That is, in a display device according to another embodiment of the present disclosure, an image having various colors may be realized by a color filter disposed on the pixel region PA. Accordingly, in a display device according to another embodiment of the present disclosure, the light emitting unit 320 in each pixel region PA may have the same stacked structure as the light emitting unit 320 in an adjacent pixel region PA. The light emitting unit 320 in each pixel region PA may be formed by the same process as the light emitting unit 320 in an adjacent pixel region PA. For example, the light emitting unit 320 in each pixel region PA may be formed simultaneously with the light emitting unit 320 in an adjacent pixel region PA. Accordingly, in a display device according to another embodiment of the present disclosure, the process of forming the light emitting unit 320 in each pixel region PA may be simplified.

[0118] A display device according to an embodiment of the present disclosure has been described as the display device 300 in each pixel region PA may be a self-emitting device in which at least one light emitting material layer (EML) is disposed between a first electrode 310 and a second electrode 330. However, in a display device according to another embodiment of the present disclosure, the display device 300 in each pixel region PA may have various configurations. For example, in a display device according to another embodiment of the present disclosure, the display device 300 in each pixel region PA may be a small LED or a micro LED using a PN junction. Accordingly, in a display device according to another embodiment of the present disclosure, the degree of freedom of the display device 300 in each pixel region PA may be improved.

[0119] A display device according to an embodiment of the present disclosure has been described such that the second semiconductor patterns 221 in each pixel region PA may be spaced apart from each other. However, in a display device according to another embodiment of the present disclosure, the second semiconductor patterns 221 in each pixel region PA may have various shapes. For example, in a display device according to another embodiment of the present disclosure, as Figure 9 shown, each second semiconductor pattern 221 in each pixel region may extend in the second direction Y. Each second semiconductor pattern 221 in each pixel region PA may be spaced apart from the second semiconductor pattern 221 of the corresponding pixel region PA adjacent in the first direction X. Each sub-capacitor Sc in each pixel region may be disposed between the second semiconductor patterns 221 spaced apart in the first direction X. For example, the second semiconductor pattern 221 and the sub-capacitor Sc of each pixel region may extend in parallel in the second direction. Therefore, in a display device according to another embodiment of the present disclosure, the degree of freedom in the shape of each second semiconductor pattern 221 may be improved.

[0120] A display device according to an embodiment of the present disclosure has been described such that the arrangement of the second semiconductor patterns 221 in each pixel region PA may have a matrix shape. However, in a display device according to another embodiment of the present disclosure, the second semiconductor patterns 221 in each pixel region PA may be arranged in various shapes. For example, in a display device according to another embodiment of the present disclosure, as Figure 10 shown, each second semiconductor pattern 221 in each pixel region PA and the second semiconductor pattern 221 adjacent in the second direction Y may be alternately disposed in the first direction X. Therefore, in a display device according to another embodiment of the present disclosure, the distance between the second semiconductor patterns 221 in each pixel region PA may be increased. That is, in a display device according to another embodiment of the present disclosure, the heat generated by the operation of the driving circuit in each pixel region may be dissipated more quickly. Therefore, in a display device according to another embodiment of the present disclosure, when driving with a high current, the reliability of the driving circuit in each pixel region PA may be effectively improved.

[0121] A display device according to an embodiment of the present disclosure has been described such that the drain connection line 225c and the source connection line 227c of each pixel region PA may have a single-layer structure. However, in a display device according to another embodiment of the present disclosure, the drain connection line 225c and the source connection line 227c of each pixel region PA may have a multi-layer structure. For example, in a display device according to another embodiment of the present disclosure, as Figure 11 and Figure 12As shown, the drain connection line 225c of each pixel region PA may have a stacked structure of a first drain connection layer 225a and a second drain connection layer 225b, and the source connection line 227c of each pixel region PA may have a stacked structure of a first source connection layer 227a and a second source connection layer 227b.

[0122] The first source connection layer 227a may be disposed on the same layer as the first drain connection layer 225a. For example, the first drain connection layer 225a and the first source connection layer 227a may be disposed between the gate insulating layer 120 and the interlayer insulating layer 130. The second source connection layer 227b may be disposed on the same layer as the second drain connection layer 225b. The second drain connection layer 225b may be disposed on the same layer as the auxiliary connection line 250. For example, the second drain connection layer 225b and the second source connection layer 227b may include the same material as the auxiliary connection line 250. The second drain connection layer 225b and the second source connection layer 227b may be formed by the same process as the auxiliary connection line 250. For example, the second drain connection layer 225b and the second source connection layer 227b may be formed simultaneously with the auxiliary connection line 250. The auxiliary connection line 250 may be in direct contact with the second source connection layer 227b.

[0123] The second drain connection layer 225b may be electrically connected to the first drain connection layer 225a. For example, the first drain connection layer 225a and the second drain connection layer 225b may extend parallel to each other in the first direction X. The second source connection layer 227b may be electrically connected to the first source connection layer 227a. For example, the first source connection layer 227a and the second source connection layer 227b may extend parallel to each other in the first direction X. Accordingly, in a display device according to another embodiment of the present disclosure, the resistance of the drain connection line 225c and the resistance of the source connection line 227c in each pixel region may be reduced. That is, in a display device according to another embodiment of the present disclosure, signal delay according to the position of each second semiconductor pattern 221 in each pixel region may be reduced or prevented. Accordingly, in a display device according to another embodiment of the present disclosure, the operation characteristics of the second thin film transistor in each pixel region may be improved. Also, in a display device according to another embodiment of the present disclosure, the efficiency and reliability of the driving circuit in each pixel region may be effectively increased.

[0124] As a result, a display device according to an embodiment of the present disclosure may include a display device electrically connected to a driving circuit, the driving circuit may include a thin film transistor and a storage capacitor, the thin film transistor may include a plurality of semiconductor patterns spaced apart in a first direction, and the storage capacitor may include a sub-capacitor disposed between the semiconductor patterns spaced apart in the first direction. Accordingly, in the display device according to an embodiment of the present disclosure, each semiconductor pattern may be sufficiently spaced apart from an adjacent semiconductor pattern. That is, in the display device according to an embodiment of the present disclosure, heat generated by the operation of the driving circuit may be rapidly dissipated through the space between the semiconductor patterns spaced apart in the first direction. Accordingly, in the display device according to an embodiment of the present disclosure, the efficiency and reliability of the driving circuit when driving with a high current may be improved. Also, in the display device according to an embodiment of the present disclosure, low power driving may be achieved by improving the efficiency of the driving circuit, and power consumption may be reduced.

Claims

1. A display device, comprising: A driving circuit, the driving circuit comprising a thin film transistor and a storage capacitor; as well as a display device, the display device being electrically connected to the drive circuit, Wherein, the thin film transistor includes a plurality of sub-transistors connected in parallel, Each sub-transistor includes a semiconductor pattern, a gate electrode, a drain electrode and a source electrode. The plurality of sub-transistors are arranged in a first direction. The storage capacitor includes sub-capacitors disposed between the plurality of sub-transistors spaced apart from each other.

2. The display device according to claim 1, wherein: The semiconductor pattern of each sub-transistor is spaced apart from the semiconductor pattern of an adjacent sub-transistor in the first direction, The sub-capacitors are disposed between semiconductor patterns spaced apart along the first direction.

3. The display device according to claim 1, wherein: The sub-capacitor includes a first capacitor electrode and a second capacitor electrode extending in a second direction perpendicular to the first direction.

4. The display device according to claim 3, wherein: Each of the sub-transistors includes a plurality of semiconductor patterns spaced apart from each other in the second direction, The plurality of semiconductor patterns of each sub-transistor have a plurality of drain regions connected to each other through drain electrodes of corresponding sub-transistors and a plurality of source regions connected to each other through source electrodes of corresponding sub-transistors.

5. The display device according to claim 3, wherein: The semiconductor pattern of each sub-transistor extends in the second direction.

6. The display device according to claim 3, wherein: The gate electrode, the drain electrode and the source electrode of each sub-transistor extend in the second direction.

7. The display device according to claim 6, wherein: The thin film transistor further includes a gate connection line, a drain connection line, and a source connection line extending in the first direction. wherein the gate electrodes of the plurality of sub-transistors are electrically connected to the gate connection line, wherein the drain electrodes of the plurality of sub-transistors are electrically connected to the drain connection line, Wherein, source electrodes of the plurality of sub-transistors are electrically connected to the source connection line.

8. The display device according to claim 7, further comprising: A device substrate, the device substrate supporting the driving circuit and the display device; as well as a light shielding pattern, the light shielding pattern being disposed between the device substrate and the semiconductor pattern of each sub-transistor, Wherein, the gate connection line is arranged on the same layer as the light shielding pattern, Wherein, the drain connection line and the source connection line are arranged on a layer different from that of the gate connection line.

9. The display device according to claim 7, wherein: The semiconductor patterns of the plurality of sub-transistors are disposed between the drain connection line and the source connection line in the second direction.

10. The display device according to claim 9, wherein: The gate connection line extends between the drain connection line and the semiconductor patterns of the plurality of sub-transistors and between the semiconductor patterns of the plurality of sub-transistors and the source connection line.

11. The display device according to claim 7, wherein: The first capacitor electrode is electrically connected to the gate connection line, and the second capacitor electrode is electrically connected to the source connection line.

12. The display device according to claim 11, wherein: The first capacitor electrode is provided on the same layer as the gate connection line, The second capacitor electrode is arranged on the same layer as the source connection line.

13. The display device according to claim 8, wherein: The light shielding patterns and the sub-capacitors are alternately arranged in the first direction.

14. A display device comprising: A thin film transistor, wherein the thin film transistor is disposed on a pixel region of a device substrate, and the thin film transistor comprises a gate connection line, a drain connection line, and a source connection line; a display device, the display device receiving a driving current from the thin film transistor; as well as a storage capacitor connected between the gate connection line and the source connection line of the thin film transistor, The thin film transistor includes a plurality of semiconductor patterns spaced apart in a first direction, wherein the plurality of semiconductor patterns are disposed between the drain connection lines and the source connection lines spaced apart in a second direction perpendicular to the first direction, The storage capacitor is disposed between semiconductor patterns spaced apart along the first direction.

15. The display device according to claim 14, wherein: The plurality of semiconductor patterns are also spaced apart in the second direction.

16. The display device according to claim 15, wherein: in, Each semiconductor pattern is arranged in a staggered manner in the second direction with a semiconductor pattern adjacent to the first direction.

17. The display device according to claim 14, wherein: The thin film transistor includes a plurality of gate electrodes electrically connected to the gate connection line, a plurality of drain electrodes electrically connected to the drain connection line, and a plurality of source electrodes electrically connected to the source connection line. wherein each gate electrode overlaps with a channel region in at least one semiconductor pattern, wherein each drain electrode is electrically connected to a drain region in at least one semiconductor pattern, Each source electrode is electrically connected to a source region in at least one semiconductor pattern.

18. The display device according to claim 17, wherein: The drain electrode is provided on the same layer as the drain connection line, Wherein, the source electrode is arranged on the same layer as the source connection line, Wherein, the gate electrode is arranged on a layer different from the gate connection line.

19. The display device according to claim 14, wherein: The storage capacitor includes a first capacitor electrode electrically connected to the gate connection line and a second capacitor electrode electrically connected to the source connection line.

20. The display device according to claim 19, wherein The source connection line is arranged on a layer different from the gate connection line, wherein the first capacitor electrode is disposed on the same layer as the gate connection line, The second capacitor electrode is arranged on the same layer as the source connection line.

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