TBC solar cell with improved UV attenuation, preparation method thereof, and battery assembly

Abstract

The present invention belongs to the technical field of solar cells, and specifically relates to a TBC solar cell with improved UV attenuation, a preparation method thereof, and a solar cell assembly. During light injection, the difference in light radiation intensity between the back and front sides is controlled within the aforementioned range, thereby greatly reducing the front side irradiation intensity. By strictly controlling the front side light radiation intensity within a relatively low range, the release of hydrogen in the front side passivation film to the crystalline silicon surface and substrate during light injection is reduced, thereby reducing the hydrogen passivation level of the front side and reducing the content of silicon-hydrogen bonds at the interface. At the same time, a light radiation intensity far greater than that of the front side is provided, thereby increasing light injection into the back side irradiation and facilitating rapid hydrogen passivation of the back side. Thus, by limiting the front side light radiation intensity within a relatively low range, it is beneficial to reduce the uncontrollable heat impact caused by high light radiation, and reduce the release of hydrogen in the front side passivation film to the crystalline silicon surface and substrate during light injection, thereby reducing the UV attenuation of the cell.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cells, and in particular relates to a TBC solar cell with improved UV attenuation, a preparation method thereof, and a cell assembly. Background Art

[0002] With the development of the photovoltaic industry, the conversion efficiency of crystalline silicon solar cells has continued to improve, gradually approaching its theoretical limit. To further increase the light-receiving area of the cell, high-efficiency cells are undergoing a trend from double-sided contact to back-contact (BC). Removing the front electrode from obstruction can improve short-circuit current (Isc) by 2-3%. Based on surface passivation technology, BC cells can be further divided into Tunneling Oxide Passivated Contact (TOPCon) cells, Heterojunction Junction (HJT) cells, and HPBC cells using hybrid passivation technologies (such as Al-BSF, PERC, TOPCon, and HJT). Of these, TBC cells offer the highest cost-effectiveness and the greatest potential for industrialization.

[0003] Unlike traditional bifacial TOPCon cells, TBC cells lack an emitter on the front side, have a lower surface doping concentration, similar to the silicon wafer substrate, and are passivated using aluminum oxide and silicon nitride. Therefore, TBC cells rely much more heavily on aluminum oxide chemical passivation than traditional bifacial TOPCon cells, and their efficiency degradation from ultraviolet radiation (UV) is also much greater than that of bifacial TOPCon cells.

[0004] The existing TBC technology approach does not specifically address this issue. The front-side passivation film and light injection process still use the double-sided TOPCon process. This process fully hydrogen-passivates the front surface of the cell, saturating the dangling bonds on the crystalline silicon surface with hydrogen atoms to achieve excellent open-circuit voltage (Voc). However, this process forms a large number of silicon-hydrogen bonds on the crystalline silicon surface. UV radiation can break some of these bonds, reducing the effectiveness of the surface chemical passivation. Furthermore, due to the low front-side doping concentration of the TBC and the weak field passivation effect, the surface recombination rate increases significantly, resulting in severe UV attenuation.

[0005] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or public known technology. Summary of the Invention

[0006] The purpose of the present invention is to solve the problem that the surface chemical passivation effect of the existing TBC battery is reduced and the UV attenuation is serious due to ultraviolet radiation, thereby reducing the battery conversion efficiency.

[0007] To achieve the above objectives, in a first aspect, the present invention provides a method for preparing a TBC solar cell with improved UV attenuation, comprising:

[0008] A silicon wafer is prepared with a pyramid velvet surface on the front and an N region, a channel region and a P region arranged alternately on the back;

[0009] Prepare a passivation anti-reflection layer on both the front and back sides of the silicon wafer;

[0010] Screen printing gate lines on the back side of the silicon wafer and sintering the gate lines;

[0011] Light is injected into the sintered silicon wafer; during the light injection, the ratio of the irradiation intensity on the front side to the back side of the silicon wafer is lower than 0.002.

[0012] Optionally, during sintering, the radiation intensity on the front side of the silicon wafer is less than or equal to 0.1 sun.

[0013] Optionally, during light injection, the irradiation intensity on the front side of the silicon wafer is less than or equal to 0.1 sun.

[0014] Optionally, during sintering, the ratio of the radiation intensity on the front side to the back side of the silicon wafer is lower than 0.002.

[0015] Optionally, during sintering, the back side of the silicon wafer is heated by LED auxiliary heating, and the front side of the silicon wafer is heated by electric heating wire or infrared heating.

[0016] Optionally, during light injection, the back side of the silicon wafer is heated by LED auxiliary heating, and the front side of the silicon wafer is heated by electric heating wire or infrared heating.

[0017] Optionally, the sintering temperature is 600-800°C; and / or the light injection temperature is 300-700°C.

[0018] Optionally, the passivation anti-reflection layer includes a passivation layer and an anti-reflection layer, and the passivation layer is closer to the silicon wafer than the anti-reflection layer.

[0019] Optionally, the passivation layer is an aluminum oxide film layer with a thickness of 3-20 nm.

[0020] Optionally, the anti-reflection layer includes multiple layers of silicon nitride film layers, and the refractive index of the multiple layers of silicon nitride film layers decreases from the side close to the silicon wafer to the side away from the silicon wafer; wherein, the one or more layers of silicon nitride film layers close to the silicon wafer together constitute a UV absorption layer, and the refractive index of the UV absorption layer ranges from 2.3 to 2.7, and the total thickness is 2 to 20 nm.

[0021] Optionally, a hydrogen barrier layer is further provided between the anti-reflection layer and the passivation layer, and the thickness of the hydrogen barrier layer is 1-10 nm.

[0022] Optionally, the preparation of a silicon wafer having a pyramid velvet surface on the front side and an N region, a channel region, and a P region arranged alternately on the back side includes:

[0023] providing a polishing substrate;

[0024] Sequentially forming a first tunneling silicon oxide layer, a first doped polysilicon layer, and a first element-doped silicon oxide layer on the back side of the substrate;

[0025] Patterning the first tunneling silicon oxide layer, the first doped polysilicon layer, and the first element-doped silicon oxide layer to form a first opening region; the first opening region corresponds to the N region and the channel region of the final battery structure;

[0026] Sequentially forming a second tunneling silicon oxide layer, a second doped polysilicon layer, and a second element-doped silicon oxide layer on the back side of the substrate;

[0027] Patterning a predetermined area on the back side of the substrate, wherein the patterned area corresponds to the P region and the channel region of the final battery structure, wherein the overlapping portion of the patterned area and the first opening area is the channel region;

[0028] The first doped element silicon oxide layer and the second doped element silicon oxide layer, the first doped polysilicon layer and the second doped polysilicon layer and the first tunneling oxide layer and the second tunneling oxide layer on the front side and the side surrounding plating area of the substrate are removed, and the front side of the substrate is subjected to texturing and cleaning; at the same time, the second doped element oxide layer, the second doped polysilicon layer and the second tunneling oxide layer in the P area and the channel area on the back side of the silicon wafer are removed, and finally the first doped element silicon oxide layer in the entire back area is removed, thereby obtaining a silicon wafer with a pyramid velvet surface on the front side and an N area, a channel area and a P area arranged alternately on the back side.

[0029] In a second aspect, an embodiment of the present invention further provides a TBC solar cell with improved UV attenuation, which is prepared using the preparation method described in the first aspect.

[0030] In a third aspect, an embodiment of the present invention further provides a battery assembly, comprising the TBC solar cell with improved UV attenuation as described in the second aspect.

[0031] The embodiments of the present invention have at least the following beneficial effects:

[0032] The embodiments of the present invention provide a TBC solar cell with improved UV attenuation and a preparation method thereof. During light injection, the light radiation intensity difference between the back and front sides of the silicon wafer is controlled so that the ratio of the front to back irradiation intensity is lower than 0.002. Since hydrogen passivation is achieved by high-intensity light injection on the back side of the silicon wafer during light injection, but high-intensity light injection on the front side will inevitably lead to excessive migration and release of hydrogen in layers such as the passivation film and the substrate, which may cause UV attenuation of the battery. Therefore, the present invention controls the light radiation intensity difference between the back and front sides within the above range, greatly reducing the front irradiation intensity. By strictly controlling the light radiation intensity on the front side within a lower range, the release of hydrogen in the front passivation film layer to the crystalline silicon surface and substrate during light injection is reduced, the hydrogen passivation level on the front side is reduced, and the interface silicon-hydrogen bond content is reduced. At the same time, it provides remote The light radiation intensity is greater than that on the front side, and the light injection to the back side is increased, which is beneficial to the rapid hydrogen passivation of the back side. In addition, due to the high irradiation intensity, high-power light irradiation equipment is often used, and the vacuum environment and other characteristics in the battery preparation process make it difficult for heat to be conducted, resulting in high light irradiation bringing uncontrollable heat affecting the front and back of the battery. Especially when the front side of the battery needs to suppress the release of hydrogen in the front passivation film to the crystalline silicon surface and substrate during light injection, the impact of high-intensity irradiation will increase significantly, exacerbating the UV attenuation of the battery. Therefore, by limiting the front light irradiation intensity to a lower range, it is beneficial to reduce the uncontrollable heat impact brought by high light irradiation, reduce the release of hydrogen in the front passivation film to the crystalline silicon surface and substrate during light injection, reduce the UV attenuation of the battery, and thus improve the battery conversion efficiency loss under UV irradiation.

[0033] Furthermore, by increasing the thickness of the passivation layer, reducing the amount of hydrogen released from the passivation film, and adding silicon oxide or silicon oxynitride with better thermal stability between aluminum oxide and silicon nitride, the hydrogen barrier capacity of the film is improved. The refractive index of the silicon nitride film is above 2.3, and the ultraviolet light transmission is reduced by the high refractive index anti-reflection layer. Multi-angle optimization is carried out to reduce the impact of UV on the passivation functional film layer on the surface of the solar cell, further improving the loss of battery conversion efficiency under UV irradiation. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1 This is a flow chart of a method for preparing a TBC solar cell with improved UV attenuation provided by an embodiment of the present invention;

[0036] Figure 21 is a schematic diagram of a specific process of step S100 in a method for preparing a TBC solar cell with improved UV attenuation provided by an embodiment of the present invention;

[0037] Figure 3 This is a process structure diagram corresponding to step S101 in a method for preparing a TBC solar cell with improved UV attenuation provided by an embodiment of the present invention;

[0038] Figure 4 This is a process structure diagram corresponding to step S102 in a method for preparing a TBC solar cell with improved UV attenuation provided by an embodiment of the present invention;

[0039] Figure 5 This is a process structure diagram corresponding to step S103 in a method for preparing a TBC solar cell with improved UV attenuation provided by an embodiment of the present invention;

[0040] Figure 6 This is a process structure diagram corresponding to step S104 in a method for preparing a TBC solar cell with improved UV attenuation provided by an embodiment of the present invention;

[0041] Figure 7 This is a process structure diagram corresponding to step S105 in a method for preparing a TBC solar cell with improved UV attenuation provided by an embodiment of the present invention;

[0042] Figure 8 This is a process structure diagram corresponding to step S106 in a method for preparing a TBC solar cell with improved UV attenuation provided by an embodiment of the present invention;

[0043] Figure 9 This is a process structure diagram corresponding to step S200 in a method for preparing a TBC solar cell with improved UV attenuation provided by an embodiment of the present invention;

[0044] Figure 10 Schematic diagram of the structure of a TBC solar cell with improved UV attenuation provided by an embodiment of the present invention.

[0045] Description of the drawings: 1-substrate; 2-first tunneling silicon oxide layer; 3-first doped polysilicon layer; 4-first element-doped silicon oxide layer; 5-first opening region; 5a-N region; 6-second tunneling silicon oxide layer; 7-second doped polysilicon layer; 8-second element-doped silicon oxide layer; 9-second opening region; 9a-P region; 10-channel region; 11-pyramid velvet surface; 12-passivation anti-reflection layer; 13-gate line. DETAILED DESCRIPTION

[0046] The technical solutions of the present invention are described clearly and completely below with reference to the embodiments. It is obvious that the embodiments described are only a portion of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are also within the scope of protection of the present invention.

[0047] Those skilled in the art will understand that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art in the art to which this invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and, unless specifically defined as such, will not be interpreted in an idealized or overly formal sense.

[0048] It should be further understood that the wording "comprising" used in the description of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. The wording "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0049] The first aspect, such as Figure 1 As shown, an embodiment of the present invention provides a method for preparing a TBC solar cell with improved UV attenuation, comprising the following steps:

[0050] S100 , preparing a silicon wafer having a pyramid velvet surface 11 on the front side and an N region 5 a , a channel region 10 and a P region 9 a arranged alternately on the back side.

[0051] It should be noted that the silicon wafer in step S100 is a semi-finished product of a solar cell (see Figure 8 ), the silicon wafer has completed the preparation of the N region 5a, channel region 10, and P region 9a of the solar cell. Because different solar cell structures may have certain differences, this embodiment does not specifically limit the specific cell structure.

[0052] Alternatively, as Figure 2 As shown, the specific method for preparing the silicon wafer in step S100 includes:

[0053] S101, provide a polished silicon wafer, refer to Figure 3 .

[0054] Specifically, the silicon wafer is polished by alkaline solution to obtain a polished silicon wafer. The silicon wafer has a front side and a back side. The front side refers to the light-receiving side where the solar cell works normally, and the back side is the opposite side of the light-receiving side. Figure 2The upward surface of the silicon wafer is the front surface, and the downward surface is the back surface. In the embodiments of the present invention, the inner surface is usually closer to the silicon wafer, and the outer surface is farther away from the silicon wafer. The silicon wafer can be N-type or P-type. This embodiment uses N-type as an example for description.

[0055] S102, sequentially forming a first tunneling silicon oxide layer 2, a first doped polysilicon layer 3 and a first element-doped silicon oxide layer 4 on the back side of the substrate 1, see Figure 4 .

[0056] Specifically, the first tunneling silicon oxide layer 2 is currently formed using methods such as thermal oxidation (including dry oxygen oxidation and wet oxygen oxidation), chemical vapor deposition (CVD) (including plasma-enhanced chemical vapor deposition (PECVD) and low-pressure chemical vapor deposition (LPCVD)), and room-temperature wet oxidation. This embodiment uses dry oxygen thermal oxidation as an example. The oxidation temperature ranges from 550°C to 650°C to form the first tunneling silicon oxide layer 2, with a thickness of 1-2 nm. Alternatively, the first intrinsic polysilicon layer can be deposited using LPCVD at a temperature range of 550°C to a thickness of 50-500 nm. Alternatively, the first intrinsic polysilicon layer can be doped by high-temperature diffusion to form the first doped polysilicon layer 3, with a diffusion temperature range of 800°C to 1050°C.

[0057] Optionally, the high temperature diffusion includes a high temperature oxidation step to transform the outermost side of the first doped polysilicon layer 3 into a first doped element silicon oxide layer 4 with a thickness ranging from 50 to 150 nm and a high temperature oxidation temperature ranging from 950 to 1050°C.

[0058] Optionally, the first doping element is boron, the first doped polysilicon layer 3 is boron-doped polysilicon, forming the semiconductor film layer of the N region 5a, and the first doped silicon oxide layer 4 is a borosilicate glass (BSG) layer. Optionally, the thickness of the BSG layer is 50-150 nm.

[0059] S103, the first tunneling silicon oxide layer 2, the first doped polysilicon layer 3 and the first element-doped silicon oxide layer 4 are patterned to form a first opening area 5; the first opening area 5 corresponds to the N area 5a and the channel area 10 of the final battery structure. The overlapping portion of the first opening area 5 and the second opening area 9 in S105 is the channel area 10, for details, see Figure 5 .

[0060] Specifically, laser delamination combined with wet etching is used to etch an opening 5 on the backside of the silicon wafer (the first opening 5 exposes the backside of the silicon wafer). This etching removes the first element-doped silicon oxide layer 4, the first doped polysilicon layer 3, and the first tunneling silicon oxide layer 2 within the first opening 5. Optionally, the laser wavelength range is 300-1100 nm, the scanning speed range is 10-100 m / s, and the frequency range is 100 kHz-100 MHz. The wet etching method utilizes a mixture of an alkaline solution and a SiO2 protective additive.

[0061] S104, sequentially preparing a second tunneling silicon oxide layer 6, a second doped polysilicon layer 7, and a second element-doped silicon oxide layer 8 on the back side of the silicon wafer. Figure 6 shown.

[0062] Specifically, the second tunneling silicon oxide layer 6 is currently formed using methods such as thermal oxidation (including dry oxygen oxidation and wet oxygen oxidation), chemical vapor deposition (CVD) (including plasma chemical vapor deposition (PECVD) and low-pressure chemical vapor deposition (LPCVD)), and room-temperature wet oxidation. Optionally, dry oxygen thermal oxidation is used at a temperature range of 550-650°C to form the second tunneling silicon oxide layer 6, with a thickness of 1-2nm. Optionally, LPCVD is used to deposit a second intrinsic polysilicon layer at a temperature range of 550-650°C, with a thickness range of 50-300nm. Optionally, the second intrinsic polysilicon layer is doped by high-temperature diffusion to form the second doped polysilicon layer 7, with a diffusion temperature range of 750-950°C.

[0063] Optionally, the high temperature diffusion includes a high temperature oxidation step to transform the outermost side of the second doped polysilicon layer 7 into a second doped element silicon oxide layer 8 with a thickness ranging from 20 to 100 nm and a high temperature oxidation temperature ranging from 850 to 950°C.

[0064] Optionally, the second doping element is phosphorus, the second doped polysilicon layer 7 is phosphorus-doped polysilicon, to form the semiconductor film layer of the P region 9a, and the second doped silicon oxide layer 8 is a phosphosilicate glass (PSG) layer. Optionally, the thickness of the PSG layer is 20-100 nm.

[0065] It should be noted that if the first doped polysilicon layer 3 and the second doped polysilicon layer 7 are formed by low-temperature deposition of amorphous silicon (e.g., PECVD), high-temperature annealing is required after step S104 to convert the deposited amorphous silicon layers into the first doped polysilicon layer 3 and the second doped polysilicon layer 7, respectively, and crystallize them. The temperature range of the high-temperature annealing is 900-1000°C.

[0066] S105, patterning the second opening area 9 on the back side of the substrate 1, the second opening area 9 corresponds to the P area 9a and the channel area 10 of the final battery structure, wherein the overlapping portion of the second opening area 9 and the first opening area 5 is the channel area 10, for details, see Figure 7 .

[0067] Specifically, the second doped element oxide layer in the patterned area is modified to be easily etched by alkaline solution. Optionally, the patterning method is laser film opening. Optionally, the laser wavelength range is: 300-1100nm, the scanning speed range is: 10-100m / s, and the frequency range is: 100kHz-100MHz.

[0068] S106, remove the first doped element silicon oxide layer 4 and the second doped element silicon oxide layer 8, the first doped polysilicon layer 3 and the second doped polysilicon layer 7 and the first tunneling oxide layer and the second tunneling oxide layer on the front side and the side surrounding plating area of the substrate 1, and perform texturing and cleaning on the front side of the substrate 1; at the same time, remove the second doped element oxide layer, the second doped polysilicon layer 7 and the second tunneling oxide layer in the P area 9a and the channel area 10 on the back side of the silicon wafer, and finally remove the first doped element silicon oxide layer 4 in the entire back area.

[0069] Specifically, if Figure 8 As shown, all film layers on the front and side plating areas of the silicon wafer are removed through three consecutive wet processes, wherein the first wet process can remove all film layers such as the first doped element silicon oxide layer 4, the second doped element silicon oxide layer 8, the first doped polysilicon layer 3, the second doped polysilicon layer 7 and the first tunneling oxide layer, the second tunneling oxide layer on the front and side plating areas of the silicon wafer by acid solution, wherein the acid solution is a mixed solution containing hydrofluoric acid, nitric acid and sulfuric acid.

[0070] Optionally, the first wet process is performed in a chain wet process equipment with the front side of the silicon wafer facing downward to perform the above process. The second wet process can be performed by texturing the silicon wafer using a mixed solution containing an alkali solution, a texturing additive, and a SiO2 protective additive. While forming a pyramid texture 11 on the front side, the second doped element oxide layer, the second doped polysilicon layer 7, and the second tunnel oxide layer in the P region 9a and the channel region 10 on the back side of the silicon wafer are removed. The crystalline silicon in the channel region is etched to a depth of 1-5 μm. The channel region can be polished or formed into a pyramid texture. The third wet process is performed by removing the first doped element silicon oxide layer 4 from all areas of the back side using hydrofluoric acid.

[0071] Optionally, the second wet process and the third wet process are both carried out in a tank-type wet process equipment.

[0072] Optionally, RCA cleaning is performed after the second wet process and the third wet process to improve the second-generation cleanliness of the silicon wafer surface.

[0073] S200, such as Figure 9As shown, a passivation anti-reflection layer is prepared on both the front and back sides of the silicon wafer.

[0074] Optionally, the passivation anti-reflection layer 12 includes a passivation layer and an anti-reflection layer, and the passivation layer is closer to the silicon wafer than the anti-reflection layer.

[0075] Optionally, the passivation layer is an aluminum oxide film layer having a thickness of 3 to 20 nm. Optionally, the aluminum oxide film layer on the front side of the silicon wafer has a thickness of 5 to 8 nm, which is slightly higher than the conventional thickness range (the conventional thickness is generally about 4 nm).

[0076] This embodiment increases the thickness of the aluminum oxide film layer to enhance the hydrogen blocking capability of the film layer, thereby reducing the release of hydrogen from the front anti-reflection layer to the crystalline silicon surface and substrate, lowering the hydrogen passivation level on the front side, and reducing the silicon-hydrogen bond content at the interface, which is beneficial to reducing UV attenuation of the battery.

[0077] Optionally, the aluminum oxide film layer is deposited by ALD (Atomic Layer Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition), which is beneficial for improving the hydrogen barrier capability of the passivation film.

[0078] Optionally, the anti-reflection layer in this embodiment includes a multilayer silicon nitride film layer, and the refractive index of the multilayer silicon nitride film layer decreases from the side close to the silicon wafer to the side away from the silicon wafer, that is, the refractive index of the silicon nitride film layer close to the silicon wafer (inner layer) is larger, while the refractive index of the silicon nitride film layer away from the silicon wafer (outer layer) is smaller.

[0079] The one or more silicon nitride layers (part of the anti-reflection layer) located near the silicon wafer together form the UV absorbing layer. The UV absorbing layer has a refractive index ranging from 2.3 to 2.7 and a total thickness of 2 to 20 nm. For example, the anti-reflection layer may include five silicon nitride layers, with the UV absorbing layer comprising the two closest to the silicon wafer. These two layers have relatively high refractive indices, both within the range of 2.3 to 2.7, with the innermost layer having the highest refractive index, for example, 2.6. Another silicon nitride layer in the UV absorbing layer has a refractive index of 2.4, while the refractive indices of the remaining three outermost layers are all less than 2.3, decreasing in order.

[0080] Optionally, the total thickness of the UV absorption layer in the anti-reflection layer is in the range of 5-15nm, that is, the use of a high-refractive-index and high-thickness silicon nitride film layer on the front side is beneficial to reducing the transmission of ultraviolet light, thereby further reducing the impact of front-side irradiation, and further reducing the rate of ultraviolet damage to the silicon-hydrogen bonds at the crystalline silicon interface, which is beneficial to further reduce the UV attenuation of the battery.

[0081] Optionally, a hydrogen barrier layer is further provided between the anti-reflection layer and the passivation layer, and the thickness of the hydrogen barrier layer is 1 to 10 nm. Optionally, the hydrogen barrier layer is a silicon oxide layer or a silicon oxynitride film layer. Optionally, the thickness of the hydrogen barrier layer is 2 to 5 nm. The above-mentioned film layers can be prepared by deposition and other methods, which are not specifically limited here. It should be noted that if the hydrogen barrier layer is a silicon oxide layer, it can be prepared between the passivation layer and the silicon wafer. If the hydrogen barrier layer is a silicon oxynitride layer, considering the preparation efficiency and cost, it is generally prepared between the passivation layer and the anti-reflection layer, so that it can be prepared using the same equipment as the anti-reflection layer.

[0082] This embodiment increases the hydrogen resistance of the film layer by adding silicon oxide or silicon oxynitride with better stability between the aluminum oxide film layer and the silicon nitride film layer. It also increases the thickness of the aluminum oxide film layer, thereby increasing the difficulty of hydrogen migration, reducing the release of hydrogen in the front passivation film to the crystalline silicon surface and substrate, reducing the hydrogen passivation level on the front side, and reducing the content of silicon-hydrogen bonds at the interface, which helps to further reduce the UV attenuation of the battery.

[0083] S300, screen printing the gate lines on the back side of the silicon wafer and sintering.

[0084] Specifically, a gate electrode is prepared on the back of a silicon wafer by screen printing and solidified by high-temperature sintering, with the sintering temperature generally being 600-800°C.

[0085] S400: Light is injected into the sintered silicon wafer. During light injection, the ratio of the irradiation intensity on the front side to the back side of the silicon wafer is less than 0.002. The irradiation intensity ratio on the front side to the back side of the silicon wafer can be selected from 0.002, 0.0018, 0.0016, 0.0014, 0.0018, 0.0013, 0.001, 0.0008, 0.0006, 0.0004, etc.

[0086] Optionally, the light injection temperature is 300-700°C.

[0087] Optionally, after step S400 , the method further includes: testing and sorting; the purpose of the testing and sorting is to select batteries that meet electrical requirements.

[0088] An embodiment of the present invention provides a method for preparing a TBC solar cell with improved UV attenuation. During light injection, the light radiation intensity difference between the back and front sides of the silicon wafer is controlled so that the ratio of the front-to-back radiation intensity is less than 0.002. Since hydrogen passivation is achieved on the back side of the silicon wafer through high-intensity light injection during light injection, high-intensity light injection on the front side inevitably leads to excessive migration and release of hydrogen in layers such as the passivation film and the substrate, which can cause UV attenuation of the cell. Therefore, the present invention controls the light radiation intensity difference between the back and front sides within the aforementioned range, significantly reducing the front-side radiation intensity. By strictly controlling the front-side radiation intensity to a lower range, the release of hydrogen from the front-side passivation film to the crystalline silicon surface and substrate during light injection is reduced, thereby lowering the hydrogen passivation level on the front side and reducing the interfacial silicon-hydrogen bond content. Simultaneously, a light radiation intensity significantly greater than that on the front side is provided, thereby increasing light injection on the back side and facilitating rapid hydrogen passivation on the back side. Thus, by limiting the front-side radiation intensity to a lower range, the release of hydrogen from the front-side passivation film to the crystalline silicon surface and substrate during light injection is reduced, thereby reducing UV attenuation of the cell. In addition, by increasing the refractive index of the innermost silicon nitride film layer on the front side, the transmittance of ultraviolet rays during front irradiation is further reduced.

[0089] Optionally, in step S300, the radiation intensity on the front side of the silicon wafer during sintering is less than or equal to 0.1 sun.

[0090] Specifically, during sintering, light of a certain irradiation intensity will be generated more or less while being heated at high temperature. If the intensity of the light generated is too high, the hydrogen passivation level on the front side during the sintering process will increase, and the possibility of UV attenuation of the battery will increase. By limiting the front irradiation intensity during the sintering process to less than or equal to 0.1 sun, the release of hydrogen in the front passivation film to the crystalline silicon surface and substrate can be effectively inhibited, thereby reducing the hydrogen passivation level on the front side, reducing the content of silicon-hydrogen bonds at the interface, and reducing UV attenuation of the battery.

[0091] Optionally, in step S400 , the irradiation intensity on the front side of the silicon wafer during light injection is less than or equal to 0.1 sun.

[0092] Specifically, when light is injected, the front irradiation intensity is less than or equal to 0.1 sun, which can effectively inhibit the release of hydrogen in the front passivation film to the crystalline silicon surface and substrate, reduce the hydrogen passivation level on the front, and reduce the interface silicon-hydrogen bond content, thereby reducing the UV attenuation of the battery.

[0093] Optionally, in step S300 , the ratio of the radiation intensity on the front side to the back side of the silicon wafer during sintering is lower than 0.002.

[0094] Specifically, by controlling the difference in light radiation intensity between the back and front sides during sintering, the ratio of the front to back irradiation intensity is made lower than 0.002. In this way, the back side is controlled to have a certain high light irradiation intensity during sintering, which can achieve pre-passivation of hydrogen on the back side during the sintering process to a certain extent, thereby improving the hydrogen passivation efficiency. At the same time, the light radiation intensity of the front side during sintering is controlled to be within a lower range. The effect can be referred to the light intensity control during light injection, so as to further control the influence of light intensity on the front side of the battery during sintering, thereby further reducing the UV attenuation of the battery.

[0095] Optionally, in step S300, during sintering, the back side of the silicon wafer is heated by LED auxiliary heating, and the front side of the silicon wafer is heated by electric heating wire or infrared heating.

[0096] Optionally, in step S400, during light injection, the back side of the silicon wafer is heated by LED auxiliary heating, and the front side of the silicon wafer is heated by electric heating wire or infrared heating.

[0097] In this embodiment, by adopting different irradiation heating methods for the front and back sides of the battery during sintering and light injection, it is beneficial to achieve highly different irradiation intensity conditions for the front and back sides, thereby helping to reduce UV attenuation of the battery.

[0098] In a second aspect, an embodiment of the present invention further provides a TBC solar cell with improved UV attenuation, which is prepared using the preparation method of the above embodiment.

[0099] Specifically, the specific structure of the TBC solar cell prepared by steps S101 to S106 and S200 to S400 is as follows: Figure 10 As shown, including:

[0100] Substrate 1; the backside of substrate 1 is spaced apart with a P region 9a, a channel region 10, and an N region 5a to facilitate the subsequent formation of the PN junction of the solar cell. The sides and front of substrate 1 are textured to form a pyramid texture 11. A passivation anti-reflection layer 12 is applied to the front, back, and sides of the entire silicon wafer. Gate lines 13 are formed on the passivation anti-reflection layer 12 located on the N region 5a and P region 9a to form the positive and negative electrodes of the solar cell.

[0101] It should be noted that the detailed description of the specific structure of the TBC solar cell can refer to the contents of the aforementioned embodiments and will not be repeated here.

[0102] The TBC solar cell provided by the embodiment of the present invention greatly reduces the irradiation intensity of the front side of the cell by controlling the difference in light radiation intensity between the back side and the front side. By strictly controlling the light radiation intensity of the front side within a lower range, the release of hydrogen in the front passivation film to the crystalline silicon surface and substrate during light injection is reduced, the hydrogen passivation level of the front side is reduced, and the content of interfacial silicon-hydrogen bonds is reduced. At the same time, a light radiation intensity much greater than that of the front side is provided, which increases the light injection to the back side and is beneficial to the rapid hydrogen passivation of the back side. Therefore, by limiting the light radiation intensity of the front side within a lower range, the release of hydrogen in the front passivation film to the crystalline silicon surface and substrate during light injection is reduced, thereby reducing the UV attenuation of the cell.

[0103] In a third aspect, an embodiment of the present invention provides a battery assembly, comprising the TBC solar cell in the aforementioned embodiment.

[0104] The method for preparing the TBC solar cell in the embodiment of the present invention may further include other conventional required steps, which can be selected according to actual needs and will not be described in detail here.

[0105] The embodiments of the present invention are described in detail below, which are exemplary and only used to explain the present invention, and are not to be construed as limiting the present invention.

[0106] Example 1

[0107] A method for preparing a TBC solar cell with improved UV attenuation comprises the following steps:

[0108] S100 , preparing a silicon wafer having a pyramid velvet surface 11 on the front side and an N region 5 a , a channel region 10 and a P region 9 a arranged alternately on the back side.

[0109] At S200, aluminum oxide, silicon oxynitride, and multiple silicon nitride layers are deposited on both the front and back sides of the silicon wafer. The aluminum oxide layer is 6 nm thick, the silicon oxynitride layer is 3 nm thick, and the innermost silicon nitride layer (closest to the aluminum oxide layer) is 10 nm thick and has a refractive index of 2.4.

[0110] S300: Screen-printing gate lines on the back of the silicon wafer and sintering. During sintering, the ratio of the irradiance intensity on the front to back of the silicon wafer is 0.0017. During light injection, the irradiance intensity on the front of the silicon wafer is 0.1 sun, and the irradiance intensity on the back of the silicon wafer is 60 sun.

[0111] S400: Light is injected into the sintered silicon wafer. During light injection, the ratio of the irradiance intensity on the front and back sides of the silicon wafer is 0.0017. The irradiance intensity on the front side of the silicon wafer is 0.1 sun, and the irradiance intensity on the back side of the silicon wafer is 60 sun. The light source is located above the wafer, and the front side of the silicon wafer faces downward, away from the light source.

[0112] The TBC solar cell prepared by the above method has a cell conversion efficiency of 26.25%, and its attenuation rate for UV60 is 1.14%. The attenuation rate is tested by using IV to measure the cell conversion efficiency before and after UV attenuation, i.e., attenuation rate = (efficiency before attenuation - efficiency after attenuation) / efficiency before attenuation.

[0113] Example 2

[0114] The method of Example 1 is referred to, except that in step S300, the ratio of the irradiation intensity on the front and back sides of the silicon wafer during sintering is 0.01, the irradiation intensity on the front side of the silicon wafer during light injection is 0.1 sun, and the irradiation intensity on the back side of the silicon wafer during light injection is 10 sun.

[0115] The TBC solar cell prepared by the above method has a cell conversion efficiency of 26.08% and an attenuation rate of 1.10% for UV60.

[0116] Example 3

[0117] The method of Example 1 is referred to, except that in step S300, the irradiation intensity on the front side of the silicon wafer during sintering is 0.3 sun, and other conditions are the same as those of Example 1.

[0118] The TBC solar cell prepared by the above method has a cell conversion efficiency of 26.23% and an attenuation rate of 1.32% for UV60.

[0119] Example 4

[0120] The method of Example 1 is referred to, except that in step S400, the irradiation intensity on the front side of the silicon wafer during light injection is 0.5 sun, and other conditions are the same as those of Example 1.

[0121] The TBC solar cell prepared by the above method has an efficiency of 26.26% before attenuation, and its attenuation rate for UV60 is 1.56%.

[0122] Example 5

[0123] The method of Example 1 is referred to, except that in step S300, the thickness of the aluminum oxide film layer is 4 nm. The TBC solar cell prepared by the method of Example 5 has an efficiency before attenuation of 26.19% and an attenuation rate of 1.48% for UV60.

[0124] Example 6

[0125] The method of Example 1 was used, except that in step S300, no hydrogen barrier layer was prepared between the passivation layer and the anti-reflection layer. The TBC solar cell prepared by the method of Example 6 had an efficiency of 26.26% before attenuation and an attenuation rate of 1.66% for UV60.

[0126] Example 7

[0127] The method of Example 1 is referred to, except that in step S300, the thickness of the innermost silicon nitride film layer on the front side of the silicon wafer is 15 nm and the refractive index is 2.2. The TBC solar cell with improved UV attenuation prepared by the method of Example 7 has an efficiency before attenuation of 26.24% and an attenuation rate for UV60 of 1.51%.

[0128] Comparative Example 1

[0129] The method of Example 1 was used, except that in step S400, the ratio of the irradiation intensity on the front and back sides of the silicon wafer during light injection was 10, corresponding to a front irradiation intensity of 10 sun and a back irradiation intensity of 1 sun. The TBC solar cell with improved UV attenuation prepared by the method of Comparative Example 1 had an efficiency of 26.28% before attenuation and a UV60 attenuation rate of 2.57%.

[0130] Test Case

[0131] The TBC solar cells with improved UV attenuation obtained in the above examples and comparative examples were subjected to performance tests, and the results are shown in Table 1.

[0132] Table 1 Comparison of performance test results of various embodiments and comparative examples

[0133]

[0134] The above results show that, compared to the comparative example, the embodiment scheme of the present invention can greatly reduce the front irradiation intensity. By strictly controlling the front light radiation intensity within a lower range, the release of hydrogen in the front passivation film to the crystalline silicon surface and substrate during light injection is reduced, thereby reducing the hydrogen passivation level on the front side, reducing the content of interfacial silicon-hydrogen bonds, and thus reducing the UV attenuation of the battery. Furthermore, according to Examples 1 and 2 to 7, it can be seen that the preferred specific preparation method and specific battery structure scheme of the present invention are adopted. By limiting the front light radiation intensity within a lower range, the release of hydrogen in the front passivation film to the crystalline silicon surface and substrate during light injection is reduced. At the same time, strong light injection on the back side can ensure that the battery efficiency is not affected.

[0135] In the description of the present invention, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0136] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0137] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal connections between two components. A person of ordinary skill in the art can understand the specific meanings of the above terms in the present invention based on the specific circumstances. In the description of this specification, specific features, structures, materials, or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0138] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a TBC solar cell with improved UV attenuation, characterized in that: include: A silicon wafer is prepared with a pyramid velvet surface on the front and an N region, a channel region and a P region arranged alternately on the back; Prepare a passivation anti-reflection layer on both the front and back sides of the silicon wafer; Screen printing gate lines on the back side of the silicon wafer and sintering the gate lines; Light is injected into the sintered silicon wafer; during the light injection, the ratio of the irradiation intensity on the front side to the back side of the silicon wafer is lower than 0.002; during the light injection, the irradiation intensity on the front side of the silicon wafer is less than or equal to 0.1 sun.

2. The method for preparing a TBC solar cell according to claim 1, wherein: During sintering, the radiation intensity on the front side of the silicon wafer is less than or equal to 0.1 sun.

3. The method for preparing a TBC solar cell according to claim 2, wherein: During sintering, the ratio of the radiation intensity on the front side to the back side of the silicon wafer is lower than 0.

002.

4. The method for preparing a TBC solar cell according to claim 3, wherein: During sintering, the back of the silicon wafer is heated by LED auxiliary heating, and the front of the silicon wafer is heated by electric heating wire or infrared heating.

5. The method for preparing a TBC solar cell according to claim 1, wherein: During light injection, the back side of the silicon wafer is heated by LED auxiliary means, and the front side of the silicon wafer is heated by electric heating wire or infrared means.

6. The method for preparing a TBC solar cell according to claim 1, wherein: The sintering temperature is 600-800°C; and / or the light injection temperature is 300-700°C.

7. The method for preparing a TBC solar cell according to claim 1, wherein: The passivation anti-reflection layer includes a passivation layer and an anti-reflection layer, and the passivation layer is closer to the silicon wafer than the anti-reflection layer.

8. The method for preparing a TBC solar cell according to claim 7, wherein: The passivation layer is an aluminum oxide film layer with a thickness of 3-20 nm.

9. The method for preparing a TBC solar cell according to claim 7, wherein: The anti-reflection layer includes multiple silicon nitride film layers, and the refractive index of the multiple silicon nitride film layers decreases from the side close to the silicon wafer to the side away from the silicon wafer; wherein, the one or more silicon nitride film layers close to the silicon wafer together constitute a UV absorption layer, and the refractive index of the UV absorption layer ranges from 2.3 to 2.7, and the total thickness is 2 to 20 nm.

10. The method for preparing a TBC solar cell according to any one of claims 7 to 9, characterized in that: A hydrogen barrier layer is further provided between the anti-reflection layer and the passivation layer, and the thickness of the hydrogen barrier layer is 1-10 nm.

11. The method for preparing a TBC solar cell according to any one of claims 1 to 9, characterized in that: The method for preparing a silicon wafer having a pyramid velvet surface on the front side and an N region, a channel region, and a P region arranged alternately on the back side includes: providing a polishing substrate; Sequentially forming a first tunneling silicon oxide layer, a first doped polysilicon layer, and a first element-doped silicon oxide layer on the back side of the substrate; Patterning the first tunneling silicon oxide layer, the first doped polysilicon layer, and the first element-doped silicon oxide layer to form a first opening region; the first opening region corresponds to the N region and the channel region of the final battery structure; Sequentially forming a second tunneling silicon oxide layer, a second doped polysilicon layer, and a second element-doped silicon oxide layer on the back side of the substrate; Patterning a second opening region on the back side of the substrate, wherein the second opening region corresponds to the P region and the channel region of the final battery structure, wherein the overlapping portion of the second opening region and the first opening region is the channel region; The first doped element silicon oxide layer and the second doped element silicon oxide layer, the first doped polysilicon layer and the second doped polysilicon layer and the first tunneling oxide layer and the second tunneling oxide layer on the front side and the side surrounding plating area of the substrate are removed, and the front side of the substrate is subjected to texturing and cleaning; at the same time, the second doped element oxide layer, the second doped polysilicon layer and the second tunneling oxide layer in the P area and the channel area on the back side of the silicon wafer are removed, and finally the first doped element silicon oxide layer in the entire back area is removed, thereby obtaining a silicon wafer with a pyramid velvet surface on the front side and an N area, a channel area and a P area arranged alternately on the back side.

12. A TBC solar cell with improved UV attenuation, characterized in that: The method is described in any one of claims 1 to 11.

13. A battery assembly, characterized in that: Comprising the TBC solar cell as claimed in claim 12.

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